udb 0.1.16 → 0.1.18

data/.data/spec/std/isa/csr/misa.yaml

@@ -27,9 +27,6 @@ fields:
     location: 0
     description: |
       Indicates support for the `A` (atomic) extension.
-
-      [when,"MUTABLE_MISA_A == true"]
-      Writing 0 to this field will cause all atomic instructions to raise an `IllegalInstruction` exception.
     type(): |
       return (implemented?(ExtensionName::A) && MUTABLE_MISA_A) ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value(): |
@@ -41,9 +38,6 @@ fields:
     location: 1
     description: |
       Indicates support for the `B` (bitmanip) extension.
-
-      [when,"MUTABLE_MISA_B == true"]
-      Writing 0 to this field will cause all bitmanip instructions to raise an `IllegalInstruction` exception.
     type(): |
       return (implemented?(ExtensionName::B) && MUTABLE_MISA_B) ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value(): |
@@ -109,25 +103,6 @@ fields:
 
       # fall-through; write the intended value
       return csr_value.F;
-  G:
-    location: 6
-    description: |
-      Indicates support for all of the following extensions: `I`, `A`, `M`, `F`, `D`.
-    type(): |
-      if ((implemented?(ExtensionName::A) && MUTABLE_MISA_A) ||
-          (implemented?(ExtensionName::M) && MUTABLE_MISA_M) ||
-          (implemented?(ExtensionName::F) && MUTABLE_MISA_F) ||
-          (implemented?(ExtensionName::D) && MUTABLE_MISA_D)) {
-        return CsrFieldType::ROH;
-      } else {
-        return CsrFieldType::RO;
-      }
-    reset_value(): |
-      return (
-        implemented?(ExtensionName::A) &&
-        implemented?(ExtensionName::M) &&
-        implemented?(ExtensionName::F) &&
-        implemented?(ExtensionName::D)) ? 1 : 0;
   H:
     location: 7
     description: |
@@ -157,7 +132,9 @@ fields:
       Indicates support for the `M` (integer multiply/divide) extension.
 
       [when,"MUTABLE_MISA_M == true"]
-      Writing 0 to this field will cause all attempts to execute an integer multiply or divide instruction to raise an `IllegalInstruction` exception.
+      Writing 0 to this field will cause all attempts to execute an integer divide or
+      remainder instruction to raise an `IllegalInstruction` exception. The multiply
+      instructions are provided by `Zmmul` and are unaffected.
     type(): |
       return (implemented?(ExtensionName::M) && MUTABLE_MISA_M) ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value(): |
@@ -229,18 +206,25 @@ fields:
     definedBy:
       extension:
         name: Zvl32b
+  X:
+    location: 23
+    description: |
+      The `X` bit will be set if there are any non-standard extensions.
+    type: RO
+    reset_value(): |
+      return NON_STANDARD_EXTENSION_IMPLEMENTED ? 1 : 0;
 sw_read(): |
   return (
     (CSR[misa].MXL `<< (xlen() - 2)) |
+    (CSR[misa].X `<< 23) |
     (CSR[misa].V `<< 21) |
     (CSR[misa].U `<< 20) |
     (CSR[misa].S `<< 18) |
     (CSR[misa].Q `<< 16) |
     (CSR[misa].M `<< 12) |
-    (CSR[misa].I `<< 7) |
-    (CSR[misa].H `<< 6) |
-    ((CSR[misa].A & CSR[misa].M & CSR[misa].F & CSR[misa].D) `<< 5) | # 'G'
-    (CSR[misa].F `<< 4) |
+    (CSR[misa].I `<< 8) |
+    (CSR[misa].H `<< 7) |
+    (CSR[misa].F `<< 5) |
     (CSR[misa].D `<< 3) |
     (CSR[misa].C `<< 2) |
     (CSR[misa].B `<< 1) |

data/.data/spec/std/isa/csr/mseccfg.yaml

@@ -22,4 +22,30 @@ definedBy:
           - name: Smmpm
           - name: Zicfilp
           - name: Smepmp
-fields: {}
+fields:
+  USEED:
+    location: 8
+    description: |
+      Controls access to the `seed` CSR from U-mode.
+    definedBy:
+      extension:
+        allOf:
+          - name: Zkr
+          - name: U
+    type(): |
+      return USEED_READ_ONLY_ZERO ? CsrFieldType::RO : CsrFieldType::RW;
+    reset_value(): |
+      return USEED_READ_ONLY_ZERO ? 0 : UNDEFINED_LEGAL;
+  SSEED:
+    location: 9
+    description: |
+      Controls access to the `seed` CSR from S-mode and VS-mode.
+    definedBy:
+      extension:
+        allOf:
+          - name: Zkr
+          - name: S
+    type(): |
+      return SSEED_READ_ONLY_ZERO ? CsrFieldType::RO : CsrFieldType::RW;
+    reset_value(): |
+      return SSEED_READ_ONLY_ZERO ? 0 : UNDEFINED_LEGAL;

data/.data/spec/std/isa/csr/mstatus.yaml

@@ -40,9 +40,9 @@ fields:
       # this is read-only if FS and VS are both read-only
       # otherwise, it is read-only with hardware update
 
-      if (implemented?(ExtensionName::F) && (HW_MSTATUS_FS_DIRTY_UPDATE != "never")) {
+      if (implemented?(ExtensionName::F)) {
         return CsrFieldType::ROH;
-      } else if (implemented?(ExtensionName::V) && (HW_MSTATUS_VS_DIRTY_UPDATE != "never")) {
+      } else if (implemented?(ExtensionName::V)) {
         return CsrFieldType::ROH;
       } else {
         return CsrFieldType::RO;
@@ -607,7 +607,10 @@ fields:
       extension:
         name: S
     reset_value(): |
-      return (CSR[misa].S == 1'b1) ? UNDEFINED_LEGAL : 0;
+      if (CSR[misa].S == 1'b1) {
+        return UNDEFINED_LEGAL;
+      }
+      return 0;
   MIE:
     location: 3
     long_name: M-mode Interrupt Enable
@@ -644,4 +647,7 @@ fields:
       extension:
         name: S
     reset_value(): |
-      return (CSR[misa].S == 1'b1) ? UNDEFINED_LEGAL : 0;
+      if (CSR[misa].S == 1'b1) {
+        return UNDEFINED_LEGAL;
+      }
+      return 0;

data/.data/spec/std/isa/csr/schema.adoc

@@ -53,7 +53,7 @@ Privilege Mode::
 |===
 | *key*         | priv_mode
 | *value type*  | one of ["M", "S", "U", or "VS"]
-| *description* | The least-privilege mode that can access this CSR
+| *description* | The least-privilege mode that can access this CSR. For an indirect CSR, this also identifies the target indirect CSR address space.
 |===
 
 Length::
@@ -72,12 +72,12 @@ Indirect::
 | *key*         | indirect
 | *value type*  | Boolean
 | *default*     | false
-| *description* | Whether or not the CSR is accessible through the indirect CSRs of the `Smcdrind`/`Sscdrind` extensions.
+| *description* | Whether or not the CSR is accessible through the indirect CSRs of the `Smcsrind`/`Sscsrind` extensions.
 |===
 
 Address::
 
-[IMPORTANT] `address` is a required key *unless* the CSR is only accessible through the indirect registers of the `Smcsrind`/`Sscrind` extensions, in which case `indirect_address` is required. Both `address` and `indirect_address` may be specified when a CSR is accessible directly and indirectly.
+[IMPORTANT] `address` is a required key *unless* the CSR is only accessible through the indirect registers of the `Smcsrind`/`Sscsrind` extensions, in which case `indirect_address` is required. Both `address` and `indirect_address` may be specified when a CSR is accessible directly and indirectly.
 
 |===
 | *key*         | address
@@ -88,7 +88,13 @@ Address::
 |===
 | *key*         | indirect_address
 | *value type*  | Integer
-| *description* | Indirect sddress of the CSR, as given to the indirect CSRs of the `Smcsrind`/`Sscdrind` extensions
+| *description* | Indirect address of the CSR, as given to the indirect CSRs of the `Smcsrind`/`Sscsrind` extensions
+|===
+
+|===
+| *key*         | indirect_slot
+| *value type*  | Integer between 1-6
+| *description* | Indirect window slot of the CSR, corresponding to its appearance in *ireg<slot>
 |===
 
 Virtual Address::

data/.data/spec/std/isa/csr/scontext.yaml

@@ -18,10 +18,14 @@ description: |
   with a hypervisor that does not swap `scontext`.
 
 definedBy:
-  extension:
-    allOf:
-      - name: Sdtrig
-      - name: S
+  allOf:
+    - extension:
+        name: Sdtrig
+    - extension:
+        name: S
+    - param:
+        name: SCONTEXT_IMPLEMENTED
+        equal: true
 fields:
   DATA:
     location: 31-0

data/.data/spec/std/isa/csr/senvcfg.yaml

@@ -88,17 +88,12 @@ fields:
     description: |
       *Cache Block Invalidate instruction Enable*
 
-      This field has restricted values based on the value of `menvcfg.CBIE`.
-      When an invalid value is written, it is ignored and the field remains unchanged.
+      The legal values of this field do not depend on `menvcfg.CBIE`.
+      When the reserved value `10` is written, it is ignored and the field remains unchanged.
 
-      [separator="!",%autowidth,cols=",.>"]
-      !===
-      ! [.rotate]#`menvcfg.CBIE`# ! Valid values of `senvcfg.CBIE`
-
-      ! 00 ! 00
-      ! 01 ! 00, 01
-      ! 11 ! 00, 01, 11
-      !===
+      Execution of `cbo.inval` in U-mode is enabled only if it is also enabled in S-mode
+      by `menvcfg.CBIE`. If `menvcfg.CBIE` is `01`, an enabled `cbo.inval` performs a
+      flush operation in U-mode even if `senvcfg.CBIE` is `11`.
 
       Controls execution of the cache block invalidate instruction, `cbo.inval`,
       in U-mode
@@ -120,9 +115,8 @@ fields:
     sw_write(csr_value): |
       if (csr_value.CBIE == 0 || csr_value.CBIE == 1 || csr_value.CBIE == 3) {
         return csr_value.CBIE;
-      } else {
-        return UNDEFINED_LEGAL_DETERMINISTIC;
       }
+      return CSR[senvcfg].CBIE;
     reset_value: UNDEFINED_LEGAL
   UKTE:
     location: 8

data/.data/spec/std/isa/csr/sstateen0.yaml

@@ -9,7 +9,7 @@ name: sstateen0
 long_name: Supervisor State Enable 0 Register
 address: 0x10C
 priv_mode: S
-length: MXLEN
+length: 64
 writable: true
 description: |
   Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,

data/.data/spec/std/isa/csr/sstateen1.yaml

@@ -9,7 +9,7 @@ name: sstateen1
 long_name: Supervisor State Enable 1 Register
 address: 0x10D
 priv_mode: S
-length: MXLEN
+length: 64
 writable: true
 description: |
   Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
@@ -61,8 +61,7 @@ definedBy:
 
 fields:
   DATA:
-    location_rv64: 63-0
-    location_rv32: 31-0
+    location: 31-0
     description: Data value
     type: RW
     sw_write(csr_value): |

data/.data/spec/std/isa/csr/sstateen2.yaml

@@ -9,7 +9,7 @@ name: sstateen2
 long_name: Supervisor State Enable 2 Register
 address: 0x10E
 priv_mode: S
-length: MXLEN
+length: 64
 writable: true
 description: |
   Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
@@ -61,8 +61,7 @@ definedBy:
 
 fields:
   DATA:
-    location_rv64: 63-0
-    location_rv32: 31-0
+    location: 31-0
     description: Data value
     type: RW
     sw_write(csr_value): |

data/.data/spec/std/isa/csr/sstateen3.yaml

@@ -9,7 +9,7 @@ name: sstateen3
 long_name: Supervisor State Enable 3 Register
 address: 0x10F
 priv_mode: S
-length: MXLEN
+length: 64
 writable: true
 description: |
   Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
@@ -61,8 +61,7 @@ definedBy:
 
 fields:
   DATA:
-    location_rv64: 63-0
-    location_rv32: 31-0
+    location: 31-0
     description: Data value
     type: RW
     sw_write(csr_value): |

data/.data/spec/std/isa/csr/tcontrol.yaml

@@ -0,0 +1,41 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: "csr_schema.json#"
+kind: csr
+name: tcontrol
+long_name: Trigger Control
+address: 0x7A5
+priv_mode: M
+length: XLEN
+writable: true
+description: |
+  This optional register is only accessible in M-mode and Debug Mode and provides
+  various control bits related to triggers.
+definedBy:
+  allOf:
+    - extension:
+        name: Sdtrig
+    - param:
+        name: TCONTROL_IMPLEMENTED
+        equal: true
+fields:
+  MPTE:
+    location: 7
+    description: |
+      M-mode previous trigger enable field.
+      MPTE and MTE provide one solution to a problem regarding triggers with action=0
+      firing in M-mode trap handlers.
+      When any trap into M-mode is taken, MPTE is set to the value of MTE.
+    type: RW-H
+    reset_value: 0
+  MTE:
+    location: 3
+    description: |
+      M-mode trigger enable field.
+      0 (disabled):: Triggers with action=0 do not match/fire while the hart is in M-mode.
+      1 (enabled):: Triggers do match/fire while the hart is in M-mode.
+      When any trap into M-mode is taken, MTE is set to 0. When `mret` is executed, MTE is
+      set to the value of MPTE.
+    type: RW-H
+    reset_value: 0

data/.data/spec/std/isa/csr/tdata2.yaml

@@ -21,8 +21,12 @@ description: |
   If XLEN is less than DXLEN, writes to this register are sign-extended.
 
 definedBy:
-  extension:
-    name: Sdtrig
+  allOf:
+    - extension:
+        name: Sdtrig
+    - param:
+        name: TDATA2_IMPLEMENTED
+        equal: true
 fields:
   DATA:
     location_rv32: 31-0

data/.data/spec/std/isa/csr/tdata3.yaml

@@ -21,8 +21,12 @@ description: |
   If XLEN is less than DXLEN, writes to this register are sign-extended.
 
 definedBy:
-  extension:
-    name: Sdtrig
+  allOf:
+    - extension:
+        name: Sdtrig
+    - param:
+        name: TDATA3_IMPLEMENTED
+        equal: true
 fields:
   DATA:
     location_rv32: 31-0

data/.data/spec/std/isa/csr/tinfo.yaml

@@ -0,0 +1,44 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: "csr_schema.json#"
+kind: csr
+name: tinfo
+long_name: Trigger Info
+address: 0x7A4
+priv_mode: M
+length: XLEN
+writable: true
+description: |
+  This register provides access to the trigger selected by `tselect`.
+  The reset values listed here apply to every underlying trigger.
+
+  This register is optional if no triggers are implemented, or if `type` is not writable
+  and `version` would be 0. In this case the debugger can read the only supported type
+  from `tdata1`.
+
+  Writing this read/write CSR has no effect.
+definedBy:
+  extension:
+    name: Sdtrig
+fields:
+  VERSION:
+    location: 31-24
+    description: |
+      Contains the version of the Sdtrig extension implemented.
+
+      0 (0):: Supports triggers as described in this spec at commit 5a5c078, made on
+      February 2, 2023.
+
+      1 (1):: Supports triggers as described in the ratified version 1.0 of this document.
+    type: RO
+    reset_value: UNDEFINED_LEGAL
+  TYPES:
+    location: 15-0
+    description: |
+      One bit for each possible `type` enumerated in `tdata1`. Bit N corresponds to type N.
+      If the bit is set, then that type is supported by the currently selected trigger.
+
+      If the currently selected trigger doesn't exist, this field contains 1.
+    type: RO
+    reset_value: UNDEFINED_LEGAL

data/.data/spec/std/isa/ext/Sdext.yaml

@@ -6,9 +6,65 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Sdext
-long_name: Debug
+long_name: External debug support
 description: |
-  Hart-visible portion of the debug spec.
+  Sdext is the hart-visible portion of the RISC-V Debug Specification. It
+  defines Debug Mode, the `dret` instruction, and the `dcsr`, `dpc`,
+  `dscratch0`, and `dscratch1` CSRs that allow an external debugger (via the
+  Debug Module) to halt, inspect, and resume a hart.
+
+  *Debug Mode*
+
+  Debug Mode is a special processor mode used only when a hart is halted for
+  external debugging. While in Debug Mode:
+
+  * All operations are executed with machine-mode privilege, except that
+    `mstatus.MPRV` is ignored unless `dcsr.MPRVEN` is set.
+  * Interrupts (including NMI) are not taken.
+  * Exceptions do not update any registers (including `mcause`, `mepc`, and
+    `mtval`); the hart instead returns to the Debug Module's park loop.
+  * Triggers do not fire.
+  * Counters and `time` may be stopped, as controlled by `dcsr.STOPCOUNT` and
+    `dcsr.STOPTIME`.
+  * The debug CSRs (`dcsr`, `dpc`, `dscratch0`, `dscratch1`) are accessible.
+    Accessing them outside of Debug Mode raises an Illegal Instruction
+    exception.
+
+  *Halting*
+
+  A hart enters Debug Mode (halts) in response to a halt request from the
+  debugger, a halt-on-reset request, an `ebreak` executed in a mode whose
+  `dcsr.EBREAK*` bit is set, a trigger with `action`=1, completion of a
+  single step, membership in a halt group, or (with Smdbltrp and
+  `dcsr.CETRIG`=1) a critical error. On entry:
+
+  . `dcsr.CAUSE` (and, where applicable, `dcsr.EXTCAUSE`) records why Debug
+    Mode was entered.
+  . `dcsr.PRV` and `dcsr.V` record the privilege and virtualization mode the
+    hart was in.
+  . `dpc` records the virtual address of the next instruction that would have
+    executed.
+  . If Zicfilp is implemented, `dcsr.PELP` records the current `ELP` state and
+    `ELP` is set to `NO_LP_EXPECTED`.
+
+  *Resuming*
+
+  The debugger resumes the hart by having it execute `dret` from Debug Mode.
+  On resume, the PC is set to `dpc`, the privilege and virtualization mode
+  are restored from `dcsr.PRV` and `dcsr.V`, `mstatus.MPRV` (and, with
+  Smdbltrp/Ssdbltrp, the double-trap bits) are cleared when returning to a
+  less-privileged mode, `ELP` is restored from `dcsr.PELP` when Zicfilp is
+  implemented, and the hart leaves Debug Mode. A debugger may write `dcsr`
+  and `dpc` before resuming to change where and in what mode execution
+  continues.
+
+  *Single step*
+
+  When `dcsr.STEP` is set and the hart resumes, it executes exactly one
+  instruction and then re-enters Debug Mode with `dcsr.CAUSE` = 4 (step). If
+  that instruction takes an exception, the hart enters Debug Mode
+  immediately after the PC is updated to the trap handler. `dcsr.STEPIE`
+  controls whether interrupts may be taken while single stepping.
 type: privileged
 versions:
   - version: "1.0.0"

data/.data/spec/std/isa/ext/Sm.yaml

@@ -62,8 +62,8 @@ versions:
         `pc` to `__x__tval`.
       - Specified relaxed constraints for implicit reads of non-idempotent regions.
   - version: "1.13.0"
-    state: frozen
-    ratification_date: 2023-12
+    state: ratified
+    ratification_date: 2024-10
     changes:
       - Redefined `misa`.MXL to be read-only, making MXLEN a constant.
       - Defined the `misa`.B field to reflect that the B extension has been

data/.data/spec/std/isa/ext/Smcdeleg.yaml

@@ -38,3 +38,10 @@ versions:
         company: Ventana Microsystems
       - name: John Hauser
         email: jh.riscv@jhauser.us
+requirements:
+  extension:
+    allOf:
+      - name: Ssccfg
+        version: ~> 1.0
+      - name: Sscsrind
+        version: ~> 1.0

data/.data/spec/std/isa/ext/Smctr.yaml

@@ -51,7 +51,7 @@ requirements:
   extension:
     allOf:
       - name: S
-        version: ~> 1.13 # The latest ratified version of S when Sscntr was ratified
+        version: ~> 1.13 # The latest ratified version of S when Ssctr was ratified
       - name: Smcsrind
         version: ~> 1.0
       - name: Ssctr

data/.data/spec/std/isa/ext/Smmpm.yaml

@@ -14,3 +14,11 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2024-10
+requirements:
+  allOf:
+    - param:
+        name: MXLEN
+        equal: 64
+    - extension:
+        name: Sm
+        version: ">= 1.12"

data/.data/spec/std/isa/ext/Smnpm.yaml

@@ -15,3 +15,22 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2024-10
+requirements:
+  allOf:
+    - extension:
+        name: U
+    - if:
+        extension:
+          name: S
+      then:
+        param:
+          name: SXLEN
+          includes: 64
+    - if:
+        not:
+          extension:
+            name: S
+      then:
+        param:
+          name: UXLEN
+          includes: 64

data/.data/spec/std/isa/ext/Smpmpdeleg.yaml

@@ -0,0 +1,33 @@
+# Copyright (c) Shanghai Jiao Tong University
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Smpmpdeleg
+type: privileged
+long_name: Machine PMP Delegation to SPMP
+description: |
+  The Smpmpdeleg extension provides the mpmpdeleg CSR, which controls how many
+  PMP entries are delegated to SPMP.
+
+  The mpmpdeleg CSR contains a pmpnum field in bits [6:0]. Let max_pmp be the
+  implementation's total number of PMP entries. Entries 0 through pmpnum-1
+  remain as PMP entries, while entries pmpnum through max_pmp-1 are delegated
+  to SPMP.
+
+  When pmpnum = 0, all entries are delegated to SPMP.
+  When pmpnum = max_pmp, no entries are delegated to SPMP.
+
+  Writes to SPMP CSRs are ignored when no entries are delegated to SPMP.
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: 2026-08
+    url: "https://github.com/riscv/riscv-spmp/tree/v1.0"
+requirements:
+  extension:
+    allOf:
+      - name: S
+      - name: Smcsrind

data/.data/spec/std/isa/ext/Ssccfg.yaml

@@ -14,3 +14,10 @@ versions:
     state: ratified
     ratification_date: 2024-03
     url: https://docs.google.com/document/d/1s-GeH5XpHBLzbQZucA8DPA7vvF7Xvf_nrPbrU2YLBcE/edit#heading=h.yyrgtolcaczx
+requirements:
+  extension:
+    allOf:
+      - name: Smcdeleg
+        version: ~> 1.0
+      - name: Sscsrind
+        version: ~> 1.0

data/.data/spec/std/isa/ext/Ssctr.yaml

@@ -18,6 +18,6 @@ requirements:
   extension:
     allOf:
       - name: S
-        version: ~> 1.13 # The latest ratified version of S when Sscntr was ratified
+        version: ~> 1.13 # The latest ratified version of S when Ssctr was ratified
       - name: Sscsrind
         version: ~> 1.0

data/.data/spec/std/isa/ext/Ssnpm.yaml

@@ -15,3 +15,11 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2024-10
+requirements:
+  allOf:
+    - extension:
+        name: S
+        version: ">= 1.12"
+    - param:
+        name: UXLEN
+        includes: 64