udb 0.1.16 → 0.1.18

data/.data/spec/std/isa/ext/Sspmp.yaml

@@ -0,0 +1,44 @@
+# Copyright (c) Shanghai Jiao Tong University
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Sspmp
+type: privileged
+long_name: Supervisor Physical Memory Protection
+description: |
+  The Sspmp extension defines a Supervisor-level Physical Memory Protection (SPMP)
+  mechanism that allows S-mode software to configure memory protection regions.
+
+  SPMP entries are accessed indirectly via the Sscsrind/Smcsrind extension.
+  The siselect CSR selects the SPMP entry (0x100-0x13F), and sireg/sireg2 access
+  the corresponding spmpaddr/spmpcfg values.
+
+  SPMP provides memory protection for S-mode and U-mode accesses when satp.MODE
+  is Bare. It does not apply when virtual memory translation is active.
+
+  Key behaviors:
+
+  * SPMP entries are delegated from PMP entries via the mpmpdeleg CSR.
+  * Each SPMP entry has address (spmpaddr) and configuration (spmpcfg) registers
+  * spmpcfg includes R, W, X permissions, address matching mode (A), lock bit (L),
+    U-mode bit (U), and SHARED bit
+  * Out-of-bounds siselect values read as 0 and writes are ignored
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: 2026-08
+    url: "https://github.com/riscv/riscv-spmp/tree/v1.0"
+requirements:
+  allOf:
+    - extension:
+        name: Sscsrind
+    - anyOf:
+      - not:
+          extension:
+            name: Sm
+            version: "~> 1.13"
+      - extension:
+          name: Smpmpdeleg

data/.data/spec/std/isa/ext/Sspmpen.yaml

@@ -0,0 +1,30 @@
+# Copyright (c) Shanghai Jiao Tong University
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Sspmpen
+type: privileged
+long_name: SPMP Enable Register
+description: |
+  The Sspmpen extension adds the spmpen CSR, which provides per-entry enable bits
+  for SPMP regions.
+
+  Each bit spmpen[i] controls whether SPMP entry i is active. An entry is active
+  only when both spmpen[i] is set and spmpcfg[i].A != 0 (address matching mode
+  is not OFF).
+
+  When spmpcfg[i].L (lock bit) is set, spmpen[i] becomes read-only.
+
+  The spmpen CSR is a WARL register. Bits beyond the number of implemented SPMP
+  entries are read-only zero.
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: 2026-08
+    url: "https://github.com/riscv/riscv-spmp/tree/v1.0"
+requirements:
+  extension:
+    name: Sspmp

data/.data/spec/std/isa/ext/Ssstrict.yaml

@@ -43,9 +43,9 @@ versions:
 requirements:
   allOf:
     - param:
-        name: TRAP_ON_UNIMPLEMENTED_INSTRUCTION
+        name: TRAP_ON_RESERVED_INSTRUCTION
         equal: true
-        reason: Ssstrict requires unimplemented opcodes to trap
+        reason: Ssstrict requires unimplemented opcodes in the standard or reserved encoding spaces to trap
     - param:
         name: TRAP_ON_UNIMPLEMENTED_CSR
         equal: true

data/.data/spec/std/isa/ext/Sv32.yaml

@@ -6,8 +6,8 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Sv32
-long_name: 32-bit virtual address translation (3 level)
-description: 32-bit virtual address translation (3 level)
+long_name: 32-bit virtual address translation (2 level)
+description: 32-bit virtual address translation (2 level)
 type: privileged
 versions:
   - version: "1.0"

data/.data/spec/std/isa/ext/Svpbmt.yaml

@@ -8,8 +8,8 @@ kind: extension
 name: Svpbmt
 long_name: Page-based memory types
 description: |
-  This extension mandates that the `satp` mode Bare must
-  be supported.
+  This extension specifies page-based memory types, adding the PBMT field
+  to page-table entries to control memory type, cacheability, and ordering attributes.
 type: privileged
 versions:
   - version: "1.0.0"

data/.data/spec/std/isa/ext/Zaamo.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zaamo
-long_name: Load-acquire/Store-release atomic instructions
+long_name: Atomic Memory Operations
 type: unprivileged
 versions:
   - version: "1.0.0"

data/.data/spec/std/isa/ext/Zbc.yaml

@@ -17,6 +17,10 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2021-06
+    requirements:
+      extension:
+        name: Zbkc
+        version: "~> 1.0.0"
     repositories:
       - url: https://github.com/riscv/riscv-bitmanip
         branch: main

data/.data/spec/std/isa/ext/Zvabd.yaml

@@ -12,9 +12,13 @@ description: |
   vectors of integers, including widening absolute-difference-and-accumulate
   variants. These operations are widely used in image registration, object
   recognition, motion estimation, and loop filters for video workloads.
+
+  The single-width instructions support SEW = 8, 16, and 32, and also support
+  SEW = 64 when Zve64x is implemented. The widening accumulate instructions
+  support SEW = 8 and 16.
 type: unprivileged
 versions:
-  - version: "0.7.0"
+  - version: "0.9.0"
     state: frozen
 requirements:
   extension:

data/.data/spec/std/isa/ext/Zvfbdota32f.yaml

@@ -0,0 +1,23 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Zvfbdota32f
+long_name: FP32 batched dot-product extension
+type: unprivileged
+rvi_jira_issue: https://riscv.atlassian.net/browse/RVS-3925
+requirements:
+  extension:
+    name: Zve32f
+    version: "= 1.0.0"
+versions:
+  - version: "0.7.0"
+    state: development
+    repositories:
+      - url: https://github.com/riscv/riscv-isa-manual.git
+        branch: zvbdot
+description: |
+  `Zvfbdota32f` is a member of the `Zvbdota` family of batched
+  dot-product extensions. It provides FP32 batched dot-product capability for
+  vector floating-point computation.

data/.data/spec/std/isa/ext/Zvfbfa.yaml

@@ -0,0 +1,24 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+$schema: "ext_schema.json#"
+kind: extension
+name: Zvfbfa
+long_name: Vector Extension for Additional BF16 Computation
+type: unprivileged
+description: |
+ The Zvfbfa extension adds more complete BF16 vector compute support.
+ Zvfbfa is compatible with, but does not require, Zvfbfwma and Zvfbfmin.
+versions:
+ - version: "0.8.0"
+   # date: 2026-06-08
+   # commit: f15df74e95e56ad5fabdc9edcf0f1c907d29040a
+   state: development
+   repositories:
+     - url: https://github.com/riscv/riscv-isa-manual
+       branch: zvfbfa
+requirements:
+ extension:
+   allOf:
+     - name: Zve32f
+     - name: Zfbfmin

data/.data/spec/std/isa/ext/Zvfofp4min.yaml

@@ -0,0 +1,21 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+$schema: "ext_schema.json#"
+kind: extension
+name: Zvfofp4min
+long_name: Vector OFP4 Conversion Extension
+type: unprivileged
+description: |
+ The Zvfofp4min extension provides basic vector conversion support for
+ the OFP4 E2M1 format.
+versions:
+ - version: "0.1.0"
+   state: development
+   # commit: e1e20a75c9a9fa797519fcc11ee997c7a7be4503
+   repositories:
+     - url: https://github.com/aswaterman/riscv-misc
+       branch: main
+requirements:
+ extension:
+   name: Zve32f

data/.data/spec/std/isa/ext/Zvfofp8min.yaml

@@ -0,0 +1,20 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+$schema: "ext_schema.json#"
+kind: extension
+name: Zvfofp8min
+long_name: Vector OFP8 Conversion Extension
+description: |
+ The Zvfofp8min extension provides basic vector conversion support for the
+ 8-bit floating-point formats OFP8 E4M3 and OFP8 E5M2.
+type: unprivileged
+versions:
+ - version: "0.9.0"
+   state: development
+   repositories:
+     - url: https://github.com/riscv/riscv-isa-manual
+       branch: zvfofp8min
+requirements:
+ extension:
+   name: Zve32f

data/.data/spec/std/isa/ext/Zvzip.yaml

@@ -0,0 +1,24 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Zvzip
+long_name: Vector Extension for Reordering Structured Data
+type: unprivileged
+versions:
+  - version: "0.3.0"
+    state: development
+    repositories:
+      - url: https://github.com/ptomsich/riscv-isa-manual.git
+        branch: zvzip
+requirements:
+  extension:
+    name: Zve32x
+description: |
+  The `Zvzip` extension provides vector instructions for reordering structured
+  data in vector registers: interleaving and deinterleaving element sequences,
+  and pairwise transposition of elements from two vector register groups.
+  These operations support packing and unpacking structured data and
+  transposing small matrices.

data/.data/spec/std/isa/inst/B/andn.yaml

@@ -32,8 +32,4 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = X[xs1] & ~X[xs2];

data/.data/spec/std/isa/inst/B/orn.yaml

@@ -31,8 +31,4 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = X[xs1] | ~X[xs2];

data/.data/spec/std/isa/inst/B/rev8.yaml

@@ -45,10 +45,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg input = X[xs1];
   XReg output = 0;
 

data/.data/spec/std/isa/inst/B/rol.yaml

@@ -31,10 +31,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg shamt = (xlen() == 32) ? X[xs2][4:0] : X[xs2][5:0];
 
   X[xd] = (X[xs1] << shamt) | (X[xs1] >> (xlen() - shamt));

data/.data/spec/std/isa/inst/B/rolw.yaml

@@ -34,10 +34,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg xs1_word = X[xs1][31:0];
   XReg shamt = X[xs2][4:0];
 

data/.data/spec/std/isa/inst/B/ror.yaml

@@ -31,10 +31,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg shamt = (xlen() == 32) ? X[xs2][4:0] : X[xs2][5:0];
 
   X[xd] = (X[xs1] >> shamt) | (X[xs1] << (xlen() - shamt));

data/.data/spec/std/isa/inst/B/rori.yaml

@@ -42,10 +42,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg shamt = (xlen() == 32) ? shamt[4:0] : shamt[5:0];
 
   X[xd] = (X[xs1] >> shamt) | (X[xs1] << (xlen() - shamt));

data/.data/spec/std/isa/inst/B/roriw.yaml

@@ -35,10 +35,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg xs1_word = X[xs1][31:0];
 
   XReg unextended_result = (xs1_word >> shamt) | (xs1_word << (32 - shamt));

data/.data/spec/std/isa/inst/B/rorw.yaml

@@ -35,10 +35,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg xs1_word = X[xs1][31:0];
   XReg shamt = X[xs2][4:0];
 

data/.data/spec/std/isa/inst/B/xnor.yaml

@@ -31,8 +31,4 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = ~(X[xs1] ^ X[xs2]);

data/.data/spec/std/isa/inst/C/c.addi.yaml

@@ -33,8 +33,8 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   X[xd] = X[xd] + $signed(imm);

data/.data/spec/std/isa/inst/C/c.addi16sp.yaml

@@ -30,8 +30,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   X[2] = X[2] + $signed(imm);

data/.data/spec/std/isa/inst/C/c.addi4spn.yaml

@@ -31,8 +31,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   X[creg2reg(xd)] = X[2] + imm;

data/.data/spec/std/isa/inst/C/c.addiw.yaml

@@ -34,8 +34,8 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   X[xd] = sext((X[xd] + sext(imm, 6)), 32);

data/.data/spec/std/isa/inst/C/c.beqz.yaml

@@ -29,8 +29,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
   if (X[creg2reg(xs1)] == 0) {
     jump($pc + $signed(imm));

data/.data/spec/std/isa/inst/C/c.bnez.yaml

@@ -8,8 +8,8 @@ kind: instruction
 name: c.bnez
 long_name: Branch if NOT Equal Zero
 description: |
-  C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register xs1' is NOT zero.
-  It expands to `beq` `xs1, x0, offset`.
+  C.BNEZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BNEZ takes the branch if the value in register xs1' is NOT zero.
+  It expands to `bne` `xs1, x0, offset`.
 definedBy:
   extension:
     name: Zca
@@ -29,8 +29,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
   if (X[creg2reg(xs1)] != 0) {
     jump($pc + $signed(imm));

data/.data/spec/std/isa/inst/C/c.ebreak.yaml

@@ -32,8 +32,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
   if (TRAP_ON_EBREAK) {
     raise_precise(ExceptionCode::Breakpoint, mode(), $pc);

data/.data/spec/std/isa/inst/C/c.j.yaml

@@ -27,8 +27,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   jump($pc + $signed(imm));

data/.data/spec/std/isa/inst/C/c.jal.yaml

@@ -29,8 +29,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg return_addr = $pc + 2;

data/.data/spec/std/isa/inst/C/c.jalr.yaml

@@ -26,8 +26,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
   XReg addr = X[xs1];
   XReg returnaddr;

data/.data/spec/std/isa/inst/C/c.jr.yaml

@@ -26,8 +26,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   jump(X[xs1]);

data/.data/spec/std/isa/inst/C/c.ld.yaml

@@ -50,8 +50,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   if (xlen() == 32) {

data/.data/spec/std/isa/inst/C/c.ldsp.yaml

@@ -49,8 +49,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[2] + imm;

data/.data/spec/std/isa/inst/C/c.li.yaml

@@ -30,8 +30,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   X[xd] = $signed(imm);

data/.data/spec/std/isa/inst/C/c.lui.yaml

@@ -33,8 +33,8 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   X[xd] = $signed(imm);

data/.data/spec/std/isa/inst/C/c.lw.yaml

@@ -32,8 +32,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[creg2reg(xs1)] + imm;

data/.data/spec/std/isa/inst/C/c.lwsp.yaml

@@ -32,8 +32,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[2] + imm;

data/.data/spec/std/isa/inst/C/c.mv.yaml

@@ -30,8 +30,8 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   X[xd] = X[xs2];

data/.data/spec/std/isa/inst/C/c.nop.yaml

@@ -32,6 +32,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }

data/.data/spec/std/isa/inst/C/c.sd.yaml

@@ -49,8 +49,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[creg2reg(xs1)] + imm;