udb 0.1.16 → 0.1.18
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.data/cfgs/example_rv64_with_overlay.yaml +157 -2
- data/.data/cfgs/mc100-32-full-example.yaml +6 -0
- data/.data/cfgs/profile/RVA23S64.yaml +1 -1
- data/.data/cfgs/profile/RVA23p1S64.yaml +217 -0
- data/.data/cfgs/profile/RVB23S64.yaml +1 -1
- data/.data/cfgs/profile/RVB23p1S64.yaml +179 -0
- data/.data/cfgs/qc_iu.yaml +14 -0
- data/.data/cfgs/rv32-riscv-tests.yaml +143 -0
- data/.data/cfgs/rv32-vector.yaml +144 -1
- data/.data/cfgs/rv64-riscv-tests.yaml +143 -0
- data/.data/cfgs/rv64-vector.yaml +145 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mva01s.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mvsa01.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pop.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popret.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popretz.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.push.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pushfp.yaml +2 -2
- data/.data/spec/schemas/README.adoc +4 -1
- data/.data/spec/schemas/csr_schema.json +2 -2
- data/.data/spec/schemas/schema_defs.json +4 -1
- data/.data/spec/std/isa/csr/H/hgeie.yaml +38 -0
- data/.data/spec/std/isa/csr/H/hgeip.yaml +33 -0
- data/.data/spec/std/isa/csr/H/hideleg.yaml +120 -0
- data/.data/spec/std/isa/csr/H/hie.yaml +74 -0
- data/.data/spec/std/isa/csr/H/hip.yaml +88 -0
- data/.data/spec/std/isa/csr/H/hvip.yaml +46 -0
- data/.data/spec/std/isa/csr/H/vsie.yaml +86 -0
- data/.data/spec/std/isa/csr/H/vsip.yaml +98 -0
- data/.data/spec/std/isa/csr/H/vsscratch.yaml +29 -0
- data/.data/spec/std/isa/csr/I/mcounteren.layout +7 -0
- data/.data/spec/std/isa/csr/I/mcounteren.yaml +7 -0
- data/.data/spec/std/isa/csr/I/pmpaddr0.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr1.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr10.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr11.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr12.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr13.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr14.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr15.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr16.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr17.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr18.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr19.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr2.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr20.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr21.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr22.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr23.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr24.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr25.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr26.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr27.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr28.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr29.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr3.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr30.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr31.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr32.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr33.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr34.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr35.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr36.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr37.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr38.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr39.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr4.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr40.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr41.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr42.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr43.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr44.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr45.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr46.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr47.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr48.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr49.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr5.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr50.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr51.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr52.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr53.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr54.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr55.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr56.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr57.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr58.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr59.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr6.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr60.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr61.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr62.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr63.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr7.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr8.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr9.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddrN.layout +7 -7
- data/.data/spec/std/isa/csr/Smcdeleg/scountinhibit.layout +111 -0
- data/.data/spec/std/isa/csr/Smcdeleg/scountinhibit.yaml +840 -0
- data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml +2 -0
- data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml +2 -0
- data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml +2 -0
- data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml +2 -0
- data/.data/spec/std/isa/csr/Smcsrind/mireg.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg2.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg3.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg4.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg5.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg6.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg2.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg3.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg4.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg5.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg6.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg2.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg3.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg4.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg5.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg6.yaml +2 -2
- data/.data/spec/std/isa/csr/Smctr/sctrctl.yaml +1 -1
- data/.data/spec/std/isa/csr/Smctr/sctrdepth.yaml +43 -0
- data/.data/spec/std/isa/csr/Smctr/sctrstatus.yaml +37 -0
- data/.data/spec/std/isa/csr/Smctr/vsctrctl.yaml +3 -1
- data/.data/spec/std/isa/csr/Sscofpmf/scountovf.layout +7 -0
- data/.data/spec/std/isa/csr/Sscofpmf/scountovf.yaml +7 -0
- data/.data/spec/std/isa/csr/Sstc/stimecmp.yaml +42 -0
- data/.data/spec/std/isa/csr/Sstc/stimecmph.yaml +43 -0
- data/.data/spec/std/isa/csr/Sstc/vstimecmp.yaml +45 -0
- data/.data/spec/std/isa/csr/Sstc/vstimecmph.yaml +46 -0
- data/.data/spec/std/isa/csr/V/vcsr.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vl.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vlenb.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vstart.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vtype.yaml +20 -1
- data/.data/spec/std/isa/csr/V/vxrm.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vxsat.yaml +1 -1
- data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.layout +1 -15
- data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.yaml +29 -267
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounterN.layout +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounterNh.layout +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent10.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent10h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent11.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent11h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent12.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent12h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent13.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent13h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent14.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent14h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent15.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent15h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent16.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent16h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent17.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent17h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent18.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent18h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent19.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent19h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent20.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent20h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent21.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent21h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent22.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent22h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent23.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent23h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent24.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent24h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent25.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent25h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent26.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent26h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent27.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent27h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent28.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent28h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent29.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent29h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent3.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent30.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent30h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent31.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent31h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent3h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent4.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent4h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent5.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent5h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent6.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent6h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent7.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent7h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent8.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent8h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent9.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent9h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmeventN.layout +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmeventNh.layout +4 -4
- data/.data/spec/std/isa/csr/Zkr/seed.yaml +75 -0
- data/.data/spec/std/isa/csr/hcontext.yaml +4 -4
- data/.data/spec/std/isa/csr/mcontext.yaml +4 -4
- data/.data/spec/std/isa/csr/mcycle.yaml +2 -0
- data/.data/spec/std/isa/csr/mcycleh.yaml +2 -0
- data/.data/spec/std/isa/csr/medeleg.yaml +72 -36
- data/.data/spec/std/isa/csr/menvcfg.yaml +12 -1
- data/.data/spec/std/isa/csr/menvcfgh.yaml +12 -0
- data/.data/spec/std/isa/csr/mideleg.yaml +37 -12
- data/.data/spec/std/isa/csr/mie.yaml +12 -6
- data/.data/spec/std/isa/csr/minstret.yaml +2 -0
- data/.data/spec/std/isa/csr/minstreth.yaml +2 -0
- data/.data/spec/std/isa/csr/mip.yaml +15 -7
- data/.data/spec/std/isa/csr/misa.yaml +14 -30
- data/.data/spec/std/isa/csr/mseccfg.yaml +27 -1
- data/.data/spec/std/isa/csr/mstatus.yaml +10 -4
- data/.data/spec/std/isa/csr/schema.adoc +10 -4
- data/.data/spec/std/isa/csr/scontext.yaml +8 -4
- data/.data/spec/std/isa/csr/senvcfg.yaml +6 -12
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- data/.data/spec/std/isa/inst/Zabha/amoand.h.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amomax.b.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amomax.b.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amomax.h.rl.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amomaxu.b.rl.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amomaxu.h.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amomaxu.h.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amomin.b.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amomin.b.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amomin.h.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amomin.h.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amominu.b.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amominu.b.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amominu.h.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amominu.h.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoor.b.aq.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amoor.b.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoor.b.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amoor.h.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoor.h.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoswap.b.aq.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amoswap.b.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoswap.b.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amoswap.h.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoswap.h.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amoxor.b.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoxor.b.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amoxor.h.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoxor.h.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zalrsc/lr.d.rl.yaml +0 -6
- data/.data/spec/std/isa/inst/Zalrsc/lr.d.yaml +0 -6
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- data/.data/spec/std/isa/inst/Zalrsc/lr.w.aqrl.yaml +1 -11
- data/.data/spec/std/isa/inst/Zalrsc/lr.w.rl.yaml +1 -11
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- data/.data/spec/std/isa/inst/Zalrsc/sc.d.aqrl.yaml +4 -10
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- data/.data/spec/std/isa/inst/Zba/sh1add.yaml +0 -4
- data/.data/spec/std/isa/inst/Zba/sh2add.uw.yaml +0 -4
- data/.data/spec/std/isa/inst/Zba/sh2add.yaml +0 -4
- data/.data/spec/std/isa/inst/Zba/sh3add.uw.yaml +0 -4
- data/.data/spec/std/isa/inst/Zba/sh3add.yaml +0 -4
- data/.data/spec/std/isa/inst/Zba/slli.uw.yaml +0 -4
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- data/.data/spec/std/isa/inst/Zbb/clzw.yaml +0 -4
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- data/.data/spec/std/isa/inst/Zbb/cpopw.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/ctz.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/ctzw.yaml +0 -4
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- data/.data/spec/std/isa/inst/Zbb/maxu.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/min.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/minu.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/orc.b.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/sext.b.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/sext.h.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/zext.h.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbc/clmulr.yaml +0 -4
- data/.data/spec/std/isa/inst/{B → Zbkc}/clmul.yaml +1 -7
- data/.data/spec/std/isa/inst/{B → Zbkc}/clmulh.yaml +1 -7
- data/.data/spec/std/isa/inst/Zbs/bclr.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbs/bclri.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbs/bext.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbs/bexti.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbs/binv.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbs/binvi.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbs/bset.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbs/bseti.yaml +0 -4
- data/.data/spec/std/isa/inst/Zcb/c.lbu.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcb/c.lh.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcb/c.lhu.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcb/c.mul.yaml +2 -6
- data/.data/spec/std/isa/inst/Zcb/c.not.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcb/c.sb.yaml +2 -2
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- data/.data/spec/std/isa/inst/Zcb/c.zext.w.yaml +2 -6
- data/.data/spec/std/isa/inst/Zcd/c.fld.yaml +3 -3
- data/.data/spec/std/isa/inst/Zcd/c.fldsp.yaml +4 -4
- data/.data/spec/std/isa/inst/Zcd/c.fsd.yaml +3 -3
- data/.data/spec/std/isa/inst/Zcd/c.fsdsp.yaml +4 -4
- data/.data/spec/std/isa/inst/Zcf/c.flw.yaml +3 -3
- data/.data/spec/std/isa/inst/Zcf/c.flwsp.yaml +4 -4
- data/.data/spec/std/isa/inst/Zcf/c.fsw.yaml +3 -3
- data/.data/spec/std/isa/inst/Zcf/c.fswsp.yaml +4 -4
- data/.data/spec/std/isa/inst/Zcmp/cm.mva01s.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcmp/cm.mvsa01.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcmp/cm.pop.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcmp/cm.popret.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcmp/cm.popretz.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcmp/cm.push.yaml +2 -2
- data/.data/spec/std/isa/inst/Zfh/fcvt.h.s.yaml +28 -20
- data/.data/spec/std/isa/inst/Zfh/fcvt.s.h.yaml +35 -20
- data/.data/spec/std/isa/inst/Zicbom/cbo.clean.yaml +2 -2
- data/.data/spec/std/isa/inst/Zicbom/cbo.flush.yaml +2 -2
- data/.data/spec/std/isa/inst/Zicbom/cbo.inval.yaml +2 -2
- data/.data/spec/std/isa/inst/Zicboz/cbo.zero.yaml +2 -2
- data/.data/spec/std/isa/inst/Zvabd/vabd.vv.yaml +3 -3
- data/.data/spec/std/isa/inst/Zvabd/vabd.vx.yaml +69 -0
- data/.data/spec/std/isa/inst/Zvabd/vabdu.vv.yaml +3 -3
- data/.data/spec/std/isa/inst/Zvabd/{vabs.v.yaml → vabdu.vx.yaml} +17 -11
- data/.data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml +1 -1
- data/.data/spec/std/isa/inst/Zvabd/vwabda.vx.yaml +73 -0
- data/.data/spec/std/isa/inst/Zvabd/vwabdau.vv.yaml +1 -1
- data/.data/spec/std/isa/inst/Zvabd/vwabdau.vx.yaml +74 -0
- data/.data/spec/std/isa/inst/Zvfbdota32f/vfbdota.vv.yaml +68 -0
- data/.data/spec/std/isa/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml +3 -1
- data/.data/spec/std/isa/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml +3 -1
- data/.data/spec/std/isa/inst/Zvfofp4min/vfext.vf2.yaml +35 -0
- data/.data/spec/std/isa/inst/Zvfofp8min/vfncvt.f.f.q.yaml +31 -0
- data/.data/spec/std/isa/inst/Zvfofp8min/vfncvt.sat.f.f.q.yaml +32 -0
- data/.data/spec/std/isa/inst/Zvfofp8min/vfncvtbf16.sat.f.f.w.yaml +32 -0
- data/.data/spec/std/isa/inst/Zvzip/vpaire.vv.yaml +36 -0
- data/.data/spec/std/isa/inst/Zvzip/vpairo.vv.yaml +37 -0
- data/.data/spec/std/isa/inst/Zvzip/vunzipe.v.yaml +33 -0
- data/.data/spec/std/isa/inst/Zvzip/vunzipo.v.yaml +33 -0
- data/.data/spec/std/isa/inst/Zvzip/vzip.vv.yaml +37 -0
- data/.data/spec/std/isa/isa/builtin_functions.idl +54 -1
- data/.data/spec/std/isa/isa/globals.isa +117 -5
- data/.data/spec/std/isa/isa/util.idl +1 -0
- data/.data/spec/std/isa/param/COUNTINHIBIT_EN.yaml +2 -10
- data/.data/spec/std/isa/param/HCONTEXT_IMPLEMENTED.yaml +29 -0
- data/.data/spec/std/isa/param/HCOUNTENABLE_EN.yaml +2 -5
- data/.data/spec/std/isa/param/HPM_COUNTER10_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER11_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER12_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER13_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER14_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER15_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER16_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER17_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER18_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER19_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER20_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER21_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER22_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER23_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER24_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER25_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER26_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER27_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER28_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER29_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER30_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER31_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER3_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER4_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER5_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER6_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER7_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER8_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER9_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTERN_WIDTH.layout +27 -0
- data/.data/spec/std/isa/param/HW_MSTATUS_FS_DIRTY_UPDATE.yaml +2 -4
- data/.data/spec/std/isa/param/HW_MSTATUS_VS_DIRTY_UPDATE.yaml +2 -4
- data/.data/spec/std/isa/param/LRSC_FAIL_ON_NON_EXACT_LRSC.yaml +1 -1
- data/.data/spec/std/isa/param/LRSC_FAIL_ON_VA_SYNONYM.yaml +1 -1
- data/.data/spec/std/isa/param/LRSC_MISALIGNED_BEHAVIOR.yaml +4 -4
- data/.data/spec/std/isa/param/LRSC_RESERVATION_STRATEGY.yaml +1 -1
- data/.data/spec/std/isa/param/{MCONTEXT_AVAILABLE.yaml → MCONTEXT_IMPLEMENTED.yaml} +3 -3
- data/.data/spec/std/isa/param/MCOUNTENABLE_EN.yaml +2 -5
- data/.data/spec/std/isa/param/MEDELEG_DELEGATABLE.yaml +121 -0
- data/.data/spec/std/isa/param/MEI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/MIDELEG_DELEGATABLE.yaml +177 -0
- data/.data/spec/std/isa/param/MSI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/MSTATUS_FS_LEGAL_VALUES.yaml +8 -15
- data/.data/spec/std/isa/param/MSTATUS_VS_LEGAL_VALUES.yaml +7 -15
- data/.data/spec/std/isa/param/MTI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/MTVAL_WIDTH.yaml +17 -5
- data/.data/spec/std/isa/param/MUTABLE_MISA_A.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_B.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_C.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_D.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_F.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_M.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_Q.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_U.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_V.yaml +1 -1
- data/.data/spec/std/isa/param/{HCONTEXT_AVAILABLE.yaml → NON_STANDARD_EXTENSION_IMPLEMENTED.yaml} +5 -7
- data/.data/spec/std/isa/param/NUM_EXTERNAL_GUEST_INTERRUPTS.yaml +1 -1
- data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml +1 -1
- data/.data/spec/std/isa/param/REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
- data/.data/spec/std/isa/param/REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
- data/.data/spec/std/isa/param/REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
- data/.data/spec/std/isa/param/SCONTEXT_IMPLEMENTED.yaml +18 -0
- data/.data/spec/std/isa/param/SCOUNTENABLE_EN.yaml +2 -6
- data/.data/spec/std/isa/param/SCTRDEPTH_DEPTH_LEGAL_VALUES.yaml +27 -0
- data/.data/spec/std/isa/param/SDTRIG_BREAKPOINT_REENTRANCY.yaml +45 -0
- data/.data/spec/std/isa/param/SDTRIG_ETRIGGER_SUPPORTED_EXCEPTIONS.yaml +37 -0
- data/.data/spec/std/isa/param/SDTRIG_ETRIGGER_SUPPORTED_TRIGGERS.yaml +25 -0
- data/.data/spec/std/isa/param/SDTRIG_ICOUNT_COUNT_HARDWIRED_1.yaml +23 -0
- data/.data/spec/std/isa/param/SDTRIG_ICOUNT_SELF_WRITE_SETS_PENDING.yaml +23 -0
- data/.data/spec/std/isa/param/SDTRIG_ICOUNT_SUPPORTED_TRIGGERS.yaml +25 -0
- data/.data/spec/std/isa/param/SDTRIG_ITRIGGER_SUPPORTED_INTERRUPTS.yaml +37 -0
- data/.data/spec/std/isa/param/SDTRIG_ITRIGGER_SUPPORTED_TRIGGERS.yaml +25 -0
- data/.data/spec/std/isa/param/SDTRIG_MAX_CHAIN_LENGTH.yaml +33 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_EXECUTE_WRITABLE.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_LOAD_WRITABLE.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_MASKMAX6.yaml +26 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_MATCH_LEGAL_VALUES.yaml +41 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_SELECT_WRITABLE.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_SIZE_LEGAL_VALUES.yaml +38 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_STORE_WRITABLE.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_SUPPORTED_TRIGGERS.yaml +25 -0
- data/.data/spec/std/isa/param/SDTRIG_M_WRITABLE.yaml +17 -0
- data/.data/spec/std/isa/param/SDTRIG_NUM_TRIGGERS.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_S_WRITABLE.yaml +19 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_MHSELECT_MCONTEXT_MATCH.yaml +24 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_MHSELECT_VMID_MATCH.yaml +23 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_MHVALUE_LEN.yaml +26 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_SSELECT_ASID_MATCH.yaml +23 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_SSELECT_SCONTEXT_MATCH.yaml +26 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_SVALUE_LEN.yaml +26 -0
- data/.data/spec/std/isa/param/SDTRIG_U_WRITABLE.yaml +19 -0
- data/.data/spec/std/isa/param/SDTRIG_VS_WRITABLE.yaml +19 -0
- data/.data/spec/std/isa/param/SDTRIG_VU_WRITABLE.yaml +19 -0
- data/.data/spec/std/isa/param/SEI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/SSEED_READ_ONLY_ZERO.yaml +28 -0
- data/.data/spec/std/isa/param/SSI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/STI_INTR_IMPL.yaml +33 -0
- data/.data/spec/std/isa/param/STVAL_WIDTH.yaml +81 -0
- data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SMMPM.yaml +40 -0
- data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SMNPM.yaml +42 -0
- data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SSNPM.yaml +42 -0
- data/.data/spec/std/isa/param/TCONTROL_IMPLEMENTED.yaml +16 -0
- data/.data/spec/std/isa/param/TDATA2_IMPLEMENTED.yaml +26 -0
- data/.data/spec/std/isa/param/TDATA3_IMPLEMENTED.yaml +29 -0
- data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_S.yaml +1 -1
- data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_U.yaml +1 -1
- data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_VS.yaml +1 -1
- data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml +1 -1
- data/.data/spec/std/isa/param/USEED_READ_ONLY_ZERO.yaml +28 -0
- data/.data/spec/std/isa/param/WFI_FINITE.yaml +20 -0
- data/.data/spec/std/isa/param/WFI_U_MODE.yaml +20 -0
- data/.data/spec/std/isa/profile/RVA23p1S64.yaml +37 -0
- data/.data/spec/std/isa/profile/RVB23p1S64.yaml +39 -0
- data/.data/spec/std/isa/profile_family/RVA.yaml +3 -1
- data/.data/spec/std/isa/profile_family/RVB.yaml +3 -1
- data/.data/spec/std/isa/profile_release/RVA23p1.yaml +30 -0
- data/.data/spec/std/isa/profile_release/RVB23p1.yaml +30 -0
- data/lib/udb/Z3_VERSION +1 -1
- data/lib/udb/log.rb +16 -0
- data/lib/udb/obj/csr.rb +38 -45
- data/lib/udb/obj/database_obj.rb +1 -1
- data/lib/udb/obj/exception_code.rb +3 -3
- data/lib/udb/version.rb +1 -1
- metadata +139 -13
- data/.data/spec/std/isa/param/PMLEN.yaml +0 -20
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@@ -0,0 +1,177 @@
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# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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# SPDX-License-Identifier: BSD-3-Clause-Clear
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# yaml-language-server: $schema=../../../schemas/param_schema.json
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$schema: param_schema.json#
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kind: parameter
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name: MIDELEG_DELEGATABLE
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description: |
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Indicates which interrupts can be delegated via `mideleg`.
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12
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Entry _i_ corresponds to `mideleg` bit _i_, which uses the same bit layout as `mip`.
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13
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When an entry is true, the corresponding interrupt can be delegated: the `mideleg` bit is writable,
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except for bits that are always delegated, which are read-only one.
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When an entry is false, the corresponding `mideleg` bit is read-only zero.
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+
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17
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An unimplemented interrupt cannot be delegated, i.e., if `STI_INTR_IMPL` is false,
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`MIDELEG_DELEGATABLE[5]` must be false.
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When the H extension is implemented, VSSI, VSTI, and VSEI are always delegated to HS-mode,
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so `MIDELEG_DELEGATABLE[2]`, `[6]`, and `[10]` must be true.
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SGEI is also always delegated when any guest external interrupts are implemented
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(`NUM_EXTERNAL_GUEST_INTERRUPTS` is nonzero), so `MIDELEG_DELEGATABLE[12]` must then be true;
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otherwise it must be false.
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When H is not implemented, all four must be false.
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long_name: Interrupts that can be delegated through mideleg
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schema:
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type: array
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items:
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type: boolean
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maxItems: 64
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minItems: 64
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definedBy:
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extension:
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name: S
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requirements:
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allOf:
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# Reserved interrupt codes (0, 4, 8, 14, 15) cannot be delegated
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- param:
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allOf:
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- name: MIDELEG_DELEGATABLE
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index: 0
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equal: false
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- name: MIDELEG_DELEGATABLE
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index: 4
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equal: false
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- name: MIDELEG_DELEGATABLE
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index: 8
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equal: false
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- name: MIDELEG_DELEGATABLE
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index: 14
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equal: false
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- name: MIDELEG_DELEGATABLE
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index: 15
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55
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equal: false
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56
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# An unimplemented interrupt cannot be delegated
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57
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+
- if:
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param:
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59
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name: MIDELEG_DELEGATABLE
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60
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index: 1
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61
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equal: true
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62
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then:
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param:
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64
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name: SSI_INTR_IMPL
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equal: true
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66
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- if:
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67
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param:
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68
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name: MIDELEG_DELEGATABLE
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69
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index: 3
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70
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equal: true
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71
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+
then:
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72
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param:
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73
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name: MSI_INTR_IMPL
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equal: true
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75
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- if:
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param:
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name: MIDELEG_DELEGATABLE
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index: 5
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equal: true
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80
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then:
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param:
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82
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name: STI_INTR_IMPL
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equal: true
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- if:
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param:
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name: MIDELEG_DELEGATABLE
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index: 7
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equal: true
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then:
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param:
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91
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name: MTI_INTR_IMPL
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92
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equal: true
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93
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- if:
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94
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param:
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95
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name: MIDELEG_DELEGATABLE
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96
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index: 9
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97
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equal: true
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98
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then:
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99
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param:
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100
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+
name: SEI_INTR_IMPL
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101
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equal: true
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102
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+
- if:
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103
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param:
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104
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name: MIDELEG_DELEGATABLE
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105
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index: 11
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106
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equal: true
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107
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+
then:
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108
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param:
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109
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+
name: MEI_INTR_IMPL
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110
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equal: true
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111
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# LCOFI (bit 13) is defined by Sscofpmf
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112
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- if:
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113
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not:
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114
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+
extension:
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115
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name: Sscofpmf
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116
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then:
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117
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param:
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118
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+
name: MIDELEG_DELEGATABLE
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119
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+
index: 13
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120
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+
equal: false
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121
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+
# VSSI, VSTI, and VSEI are always delegated to HS-mode when H is implemented
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122
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- if:
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123
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extension:
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124
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name: H
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125
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then:
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allOf:
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127
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# VSSI, VSTI, and VSEI are always delegated to HS-mode when H is implemented
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128
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- param:
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129
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allOf:
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130
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+
- name: MIDELEG_DELEGATABLE
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131
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+
index: 2
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132
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equal: true
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133
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- name: MIDELEG_DELEGATABLE
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134
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+
index: 6
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135
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equal: true
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136
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+
- name: MIDELEG_DELEGATABLE
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137
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+
index: 10
|
|
138
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+
equal: true
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139
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+
# SGEI is always delegated to HS-mode when any guest external interrupts are implemented (GEILEN nonzero)
|
|
140
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+
- if:
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141
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+
not:
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142
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+
param:
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143
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+
name: NUM_EXTERNAL_GUEST_INTERRUPTS
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144
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+
equal: 0
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145
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then:
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146
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param:
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147
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name: MIDELEG_DELEGATABLE
|
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148
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+
index: 12
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149
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equal: true
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150
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+
- if:
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151
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param:
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152
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+
name: NUM_EXTERNAL_GUEST_INTERRUPTS
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153
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equal: 0
|
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154
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then:
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155
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param:
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156
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name: MIDELEG_DELEGATABLE
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157
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index: 12
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158
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equal: false
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- if:
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not:
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extension:
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name: H
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then:
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param:
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165
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allOf:
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- name: MIDELEG_DELEGATABLE
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167
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index: 2
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168
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equal: false
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169
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- name: MIDELEG_DELEGATABLE
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170
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index: 6
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171
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equal: false
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172
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- name: MIDELEG_DELEGATABLE
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173
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index: 10
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174
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equal: false
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175
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- name: MIDELEG_DELEGATABLE
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176
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index: 12
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177
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equal: false
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@@ -0,0 +1,28 @@
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1
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# Copyright (c) David_Harris@hmc.edu 13 July 2026
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2
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# SPDX-License-Identifier: BSD-3-Clause-Clear
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3
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+
|
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4
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# yaml-language-server: $schema=../../../schemas/param_schema.json
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5
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6
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$schema: param_schema.json#
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7
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kind: parameter
|
|
8
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name: MSI_INTR_IMPL
|
|
9
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description: |
|
|
10
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+
Whether or not machine-level software interrupts are implemented.
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|
11
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+
|
|
12
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+
Possible values:
|
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13
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+
|
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14
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true::
|
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15
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Machine-level software interrupts are implemented.
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16
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`mie.MSIE` is writable, and `mideleg.MSI` is writable if `MIDELEG_DELEGATABLE[3]` is true.
|
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17
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+
|
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18
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false::
|
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19
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Machine-level software interrupts are not implemented.
|
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20
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`mie.MSIE` and `mideleg.MSI` are read-only zero.
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21
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+
long_name: Machine-level software interrupts are implemented
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22
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schema:
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23
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type: boolean
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24
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definedBy:
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25
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extension:
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26
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allOf:
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27
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+
- name: Zicsr
|
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28
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- name: Sm
|
|
@@ -6,32 +6,25 @@
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|
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6
6
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$schema: param_schema.json#
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7
7
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kind: parameter
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8
8
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name: MSTATUS_FS_LEGAL_VALUES
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9
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-
description:
|
|
10
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-
|
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11
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-
"
|
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12
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-
long_name: TODO
|
|
9
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description: The set of values that mstatus.FS supports.
|
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10
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long_name: mstatus.FS legal values
|
|
13
11
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schema:
|
|
14
12
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type: array
|
|
15
13
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items:
|
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16
14
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type: integer
|
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17
15
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enum:
|
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18
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-
- 0
|
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19
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-
- 1
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20
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-
- 2
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21
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-
- 3
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16
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+
- 0 # Off
|
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17
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+
- 1 # Initial
|
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18
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- 2 # Clean
|
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19
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+
- 3 # Dirty
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22
20
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maxItems: 4
|
|
23
21
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minItems: 1
|
|
24
22
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uniqueItems: true
|
|
25
23
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requirements:
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|
26
24
|
idl(): |
|
|
27
|
-
implemented?(ExtensionName::F)
|
|
28
|
-
(HW_MSTATUS_FS_DIRTY_UPDATE == "precise" ||
|
|
29
|
-
HW_MSTATUS_FS_DIRTY_UPDATE == "imprecise")
|
|
30
|
-
->
|
|
25
|
+
implemented?(ExtensionName::F) ->
|
|
31
26
|
$array_includes?(MSTATUS_FS_LEGAL_VALUES, 3);
|
|
32
|
-
reason:
|
|
33
|
-
If there is a hardware update to mstatus.FS, then the Dirty state must be
|
|
34
|
-
supported
|
|
27
|
+
reason: If F extension is implemented, then the Dirty state must be supported
|
|
35
28
|
definedBy:
|
|
36
29
|
extension:
|
|
37
30
|
allOf:
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|
@@ -7,34 +7,26 @@ $schema: param_schema.json#
|
|
|
7
7
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kind: parameter
|
|
8
8
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name: MSTATUS_VS_LEGAL_VALUES
|
|
9
9
|
description: The set of values that mstatus.VS will accept from a software write.
|
|
10
|
-
long_name:
|
|
10
|
+
long_name: mstatus.VS legal values
|
|
11
11
|
schema:
|
|
12
12
|
type: array
|
|
13
13
|
items:
|
|
14
14
|
type: integer
|
|
15
15
|
enum:
|
|
16
|
-
- 0
|
|
17
|
-
- 1
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|
18
|
-
- 2
|
|
19
|
-
- 3
|
|
16
|
+
- 0 # Off
|
|
17
|
+
- 1 # Initial
|
|
18
|
+
- 2 # Clean
|
|
19
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+
- 3 # Dirty
|
|
20
20
|
minItems: 1
|
|
21
21
|
maxItems: 4
|
|
22
22
|
uniqueItems: true
|
|
23
23
|
requirements:
|
|
24
24
|
idl(): |
|
|
25
|
-
# [RULE] If the v registers are implemented, the VS field shall not be read-only zero.
|
|
26
|
-
implemented?(ExtensionName::V)
|
|
27
|
-
-> $array_size(MSTATUS_VS_LEGAL_VALUES) > 1;
|
|
28
|
-
|
|
29
25
|
# [RULE] If there is a hardware update to mstatus.VS, then the Dirty state must be supported
|
|
30
|
-
implemented?(ExtensionName::V)
|
|
31
|
-
|
|
32
|
-
-> $array_includes?(MSTATUS_VS_LEGAL_VALUES, 0) &&
|
|
33
|
-
$array_includes?(MSTATUS_VS_LEGAL_VALUES, 3);
|
|
26
|
+
implemented?(ExtensionName::V)
|
|
27
|
+
-> $array_includes?(MSTATUS_VS_LEGAL_VALUES, 3);
|
|
34
28
|
|
|
35
29
|
reason: |
|
|
36
|
-
If V is supported, both Off (0) and Dirty (3) must be supported
|
|
37
|
-
|
|
38
30
|
If there is a hardware update to mstatus.VS, then the Dirty state must be supported
|
|
39
31
|
definedBy:
|
|
40
32
|
extension:
|
|
@@ -0,0 +1,28 @@
|
|
|
1
|
+
# Copyright (c) David_Harris@hmc.edu 13 July 2026
|
|
2
|
+
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
+
|
|
4
|
+
# yaml-language-server: $schema=../../../schemas/param_schema.json
|
|
5
|
+
|
|
6
|
+
$schema: param_schema.json#
|
|
7
|
+
kind: parameter
|
|
8
|
+
name: MTI_INTR_IMPL
|
|
9
|
+
description: |
|
|
10
|
+
Whether or not machine-level timer interrupts are implemented.
|
|
11
|
+
|
|
12
|
+
Possible values:
|
|
13
|
+
|
|
14
|
+
true::
|
|
15
|
+
Machine-level timer interrupts are implemented.
|
|
16
|
+
`mie.MTIE` and `mtimecmp` are writable, and `mideleg.MTI` is writable if `MIDELEG_DELEGATABLE[7]` is true.
|
|
17
|
+
|
|
18
|
+
false::
|
|
19
|
+
Machine-level timer interrupts are not implemented.
|
|
20
|
+
`mie.MTIE` and `mideleg.MTI` are read-only zero. `mtimecmp` is optional and may be read-only zero.
|
|
21
|
+
long_name: Machine-level timer interrupts are implemented
|
|
22
|
+
schema:
|
|
23
|
+
type: boolean
|
|
24
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+
definedBy:
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+
extension:
|
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+
allOf:
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- name: Zicsr
|
|
28
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+
- name: Sm
|
|
@@ -29,7 +29,7 @@ requirements:
|
|
|
29
29
|
|
|
30
30
|
# in RV32, MTVAL must be able to hold a physical address if M-mode takes an exception
|
|
31
31
|
# that reports an address
|
|
32
|
-
# Since
|
|
32
|
+
# Since physical address width can be larger than 32 with Sv32, need to downsize MTVAL in that case
|
|
33
33
|
(
|
|
34
34
|
MXLEN == 32 &&
|
|
35
35
|
PHYS_ADDR_WIDTH > 32 &&
|
|
@@ -42,11 +42,15 @@ requirements:
|
|
|
42
42
|
REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED ||
|
|
43
43
|
REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT ||
|
|
44
44
|
REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT ||
|
|
45
|
-
REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT
|
|
45
|
+
REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT ||
|
|
46
|
+
REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT ||
|
|
47
|
+
REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT ||
|
|
48
|
+
REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT
|
|
46
49
|
)
|
|
47
50
|
) -> (MTVAL_WIDTH == 32);
|
|
48
51
|
|
|
49
|
-
# TODO: uncomment when we have support for parameter comparison
|
|
52
|
+
# TODO: uncomment when we have support for parameter/function comparison
|
|
53
|
+
# on the RHS of a constraint.
|
|
50
54
|
# (
|
|
51
55
|
# (
|
|
52
56
|
# MXLEN == 64 ||
|
|
@@ -64,10 +68,15 @@ requirements:
|
|
|
64
68
|
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED ||
|
|
65
69
|
# REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT ||
|
|
66
70
|
# REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT ||
|
|
67
|
-
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT
|
|
71
|
+
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT ||
|
|
72
|
+
# REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT ||
|
|
73
|
+
# REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT ||
|
|
74
|
+
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT
|
|
68
75
|
# )
|
|
69
76
|
# ) -> (MTVAL_WIDTH >= PHYS_ADDR_WIDTH);
|
|
70
77
|
|
|
78
|
+
# TODO: uncomment when we have support for parameter/function comparison
|
|
79
|
+
# on the RHS of a constraint.
|
|
71
80
|
# (
|
|
72
81
|
# implemented?(ExtensionName::S) &&
|
|
73
82
|
# (
|
|
@@ -79,7 +88,10 @@ requirements:
|
|
|
79
88
|
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED ||
|
|
80
89
|
# REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT ||
|
|
81
90
|
# REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT ||
|
|
82
|
-
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT
|
|
91
|
+
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT ||
|
|
92
|
+
# REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT ||
|
|
93
|
+
# REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT ||
|
|
94
|
+
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT
|
|
83
95
|
# )
|
|
84
96
|
# ) -> (MTVAL_WIDTH >= max_va_size());
|
|
85
97
|
|
data/.data/spec/std/isa/param/{HCONTEXT_AVAILABLE.yaml → NON_STANDARD_EXTENSION_IMPLEMENTED.yaml}
RENAMED
|
@@ -5,15 +5,13 @@
|
|
|
5
5
|
|
|
6
6
|
$schema: param_schema.json#
|
|
7
7
|
kind: parameter
|
|
8
|
-
name:
|
|
8
|
+
name: NON_STANDARD_EXTENSION_IMPLEMENTED
|
|
9
9
|
description: |
|
|
10
|
-
|
|
11
|
-
|
|
10
|
+
If any non-standard extensions are implemented, this parameter must be true.
|
|
11
|
+
This parameter is used as the reset value for `misa.X`.
|
|
12
|
+
long_name: Non-standard extensions implemented
|
|
12
13
|
schema:
|
|
13
14
|
type: boolean
|
|
14
15
|
definedBy:
|
|
15
16
|
extension:
|
|
16
|
-
name:
|
|
17
|
-
requirements:
|
|
18
|
-
idl(): HCONTEXT_AVAILABLE -> MCONTEXT_AVAILABLE;
|
|
19
|
-
reason: HCONTEXT cannot exist without MCONTEXT
|
|
17
|
+
name: Sm
|
|
@@ -22,7 +22,7 @@ description: |
|
|
|
22
22
|
An implemented entry may still be read-only zero (but will never cause an exception).
|
|
23
23
|
The number of entries that are actually usable is given by
|
|
24
24
|
NUM_USABLE_PMP_ENTRIES.
|
|
25
|
-
long_name:
|
|
25
|
+
long_name: number of implemented PMP entries
|
|
26
26
|
schema:
|
|
27
27
|
type: integer
|
|
28
28
|
enum: [0, 16, 64]
|
|
@@ -7,7 +7,7 @@ $schema: param_schema.json#
|
|
|
7
7
|
kind: parameter
|
|
8
8
|
name: REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK
|
|
9
9
|
description: |
|
|
10
|
-
When true, `mtval` is written with the
|
|
10
|
+
When true, `mtval` is written with the landing pad fault cause (code=2) when a SoftwareCheck exception is raised into M-mode due to a landing pad error.
|
|
11
11
|
|
|
12
12
|
When false, `mtval` is written with 0.
|
|
13
13
|
long_name: TODO
|
|
@@ -7,7 +7,7 @@ $schema: param_schema.json#
|
|
|
7
7
|
kind: parameter
|
|
8
8
|
name: REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK
|
|
9
9
|
description: |
|
|
10
|
-
When true, `stval` is written with the
|
|
10
|
+
When true, `stval` is written with the landing pad fault cause (code=2) when a SoftwareCheck exception is raised into S-mode due to a landing pad error.
|
|
11
11
|
|
|
12
12
|
When false, `stval` is written with 0.
|
|
13
13
|
long_name: TODO
|
|
@@ -7,7 +7,7 @@ $schema: param_schema.json#
|
|
|
7
7
|
kind: parameter
|
|
8
8
|
name: REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK
|
|
9
9
|
description: |
|
|
10
|
-
When true, `vstval` is written with the
|
|
10
|
+
When true, `vstval` is written with the landing pad fault cause (code=2) when a SoftwareCheck exception is raised into VS-mode due to a landing pad error.
|
|
11
11
|
|
|
12
12
|
When false, `vstval` is written with 0.
|
|
13
13
|
long_name: TODO
|
|
@@ -0,0 +1,18 @@
|
|
|
1
|
+
# Copyright (C) 2026 Harvey Mudd College
|
|
2
|
+
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
+
|
|
4
|
+
# yaml-language-server: $schema=../../../schemas/param_schema.json
|
|
5
|
+
|
|
6
|
+
$schema: param_schema.json#
|
|
7
|
+
kind: parameter
|
|
8
|
+
name: SCONTEXT_IMPLEMENTED
|
|
9
|
+
description: |
|
|
10
|
+
Specifies if the scontext CSR is implemented
|
|
11
|
+
long_name: scontext CSR is implemented
|
|
12
|
+
schema:
|
|
13
|
+
type: boolean
|
|
14
|
+
definedBy:
|
|
15
|
+
extension:
|
|
16
|
+
allOf:
|
|
17
|
+
- name: Sdtrig
|
|
18
|
+
- name: S
|
|
@@ -9,9 +9,8 @@ name: SCOUNTENABLE_EN
|
|
|
9
9
|
description: |
|
|
10
10
|
Indicates which counters can delegated via `scounteren`
|
|
11
11
|
|
|
12
|
-
|
|
13
|
-
|
|
14
|
-
SCOUNTENABLE_EN[3] to true.
|
|
12
|
+
`SCOUNTENABLE_EN[n]` controls whether `scounteren.HPM<n>` is writable. It does not
|
|
13
|
+
depend on whether `hpmcounter<n>`/`mhpmcounter<n>` is read-only zero.
|
|
15
14
|
|
|
16
15
|
SCOUNTENABLE_EN[0:2] must all be false if `Zicntr` is not implemented.
|
|
17
16
|
SCOUNTENABLE_EN[3:31] must all be false if `Zihpm` is not implemented.
|
|
@@ -29,14 +28,11 @@ requirements:
|
|
|
29
28
|
}
|
|
30
29
|
for (U32 i = 3; i < 32; i++) {
|
|
31
30
|
!implemented?(ExtensionName::Zihpm) -> !SCOUNTENABLE_EN[i];
|
|
32
|
-
(!HPM_COUNTER_EN[i]) -> !SCOUNTENABLE_EN[i];
|
|
33
31
|
}
|
|
34
32
|
reason: |
|
|
35
33
|
Counters 0-2 are defined by Zicntr
|
|
36
34
|
|
|
37
35
|
Counters 3..31 are defined by Zihpm
|
|
38
|
-
|
|
39
|
-
When mhpmcounter[i] does not exist, it cannot be enabled.
|
|
40
36
|
definedBy:
|
|
41
37
|
extension:
|
|
42
38
|
name: S
|
|
@@ -0,0 +1,27 @@
|
|
|
1
|
+
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
2
|
+
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
+
|
|
4
|
+
# yaml-language-server: $schema=../../../schemas/param_schema.json
|
|
5
|
+
|
|
6
|
+
$schema: param_schema.json#
|
|
7
|
+
kind: parameter
|
|
8
|
+
name: SCTRDEPTH_DEPTH_LEGAL_VALUES
|
|
9
|
+
description: |
|
|
10
|
+
The set of supported actual depths for the Control Transfer Records (CTR) buffer.
|
|
11
|
+
long_name: Supported CTR buffer depths
|
|
12
|
+
schema:
|
|
13
|
+
type: array
|
|
14
|
+
items:
|
|
15
|
+
type: integer
|
|
16
|
+
enum:
|
|
17
|
+
- 16
|
|
18
|
+
- 32
|
|
19
|
+
- 64
|
|
20
|
+
- 128
|
|
21
|
+
- 256
|
|
22
|
+
maxItems: 5
|
|
23
|
+
minItems: 1
|
|
24
|
+
uniqueItems: true
|
|
25
|
+
definedBy:
|
|
26
|
+
extension:
|
|
27
|
+
name: Smctr
|
|
@@ -0,0 +1,45 @@
|
|
|
1
|
+
# Copyright (C) 2026 Harvey Mudd College
|
|
2
|
+
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
+
|
|
4
|
+
# yaml-language-server: $schema=../../../schemas/param_schema.json
|
|
5
|
+
|
|
6
|
+
$schema: param_schema.json#
|
|
7
|
+
kind: parameter
|
|
8
|
+
name: SDTRIG_BREAKPOINT_REENTRANCY
|
|
9
|
+
description: |
|
|
10
|
+
How the hart prevents triggers with action=0 (breakpoint exception) from re-firing
|
|
11
|
+
inside their own handler (Debug spec 1.0, Sdtrig "Native Triggers").
|
|
12
|
+
|
|
13
|
+
* No_reentrancy_support: no specific support for reentrancy.
|
|
14
|
+
* Use_interrupt_enables: triggers with action=0 do not match or fire in M-mode while
|
|
15
|
+
mstatus.MIE is 0 (and likewise S/VS-mode with sstatus.SIE / vsstatus.SIE when delegated).
|
|
16
|
+
* Use_tcontrol: tcontrol.mte and tcontrol.mpte are implemented, and medeleg[3] is hard-wired to 0.
|
|
17
|
+
long_name: Breakpoint reentrancy mechanism
|
|
18
|
+
schema:
|
|
19
|
+
type: string
|
|
20
|
+
enum:
|
|
21
|
+
- No_reentrancy_support
|
|
22
|
+
- Use_interrupt_enables
|
|
23
|
+
- Use_tcontrol
|
|
24
|
+
requirements:
|
|
25
|
+
if:
|
|
26
|
+
param:
|
|
27
|
+
name: SDTRIG_BREAKPOINT_REENTRANCY
|
|
28
|
+
equal: Use_tcontrol
|
|
29
|
+
then:
|
|
30
|
+
allOf:
|
|
31
|
+
- param:
|
|
32
|
+
name: TCONTROL_IMPLEMENTED
|
|
33
|
+
equal: true
|
|
34
|
+
reason: The Use_tcontrol mechanism requires the tcontrol CSR.
|
|
35
|
+
- if:
|
|
36
|
+
extension:
|
|
37
|
+
name: S
|
|
38
|
+
then:
|
|
39
|
+
param:
|
|
40
|
+
name: MEDELEG_DELEGATABLE
|
|
41
|
+
index: 3
|
|
42
|
+
equal: false
|
|
43
|
+
definedBy:
|
|
44
|
+
extension:
|
|
45
|
+
name: Sdtrig
|