axi_tdl 0.0.19 → 0.1.7

data/lib/tdl/class_hdl/hdl_struct.rb

@@ -158,7 +158,7 @@ module ClassHDL
 
         def [](a)
             if dimension
-                return TdlSpace::ArrayChain.new(self,[a])
+                return TdlSpace::ArrayChain.create(obj:self,lchain:[a],belong_to_module: belong_to_module)
             else  
                 raise TdlError.new "#{@name} dimenson is nil "
             end
@@ -171,7 +171,7 @@ module ClassHDL
                 self.define_singleton_method(e.name) do 
                     # RedefOpertor.with_normal_operators do
                     ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
-                        TdlSpace::ArrayChain.new("#{@name}.#{e.to_s}".to_nq)
+                        TdlSpace::ArrayChain.create(obj:"#{@name}.#{e.to_s}".to_nq, belong_to_module: self.belong_to_module)
                     end
                 end
             end

data/lib/tdl/elements/Reset.rb

@@ -5,7 +5,7 @@ class Reset < SignalElm
     attr_reader :name,:active
     attr_accessor :id,:ghost,:port,:dsize
 
-    def initialize(name:"system_rst",active:"LOW",port:false,dsize:1)
+    def initialize(name:"system_rst",active:"LOW",port:false,dsize:1, belong_to_module: nil)
         name_legal?(name)
         # @id = GlobalParam.CurrTdlModule.BindEleClassVars.Reset.id
         @dsize = dsize
@@ -15,14 +15,10 @@ class Reset < SignalElm
         if @active.eql?("low") && @active.eql?("high")
             raise TdlError.new("RESET ACTIVE PARA #{@active} ERROR")
         end
-        # if @port
-        #     GlobalParam.CurrTdlModule.BindEleClassVars.Reset.ports << self if @id != 0
-        # else
-        #     GlobalParam.CurrTdlModule.BindEleClassVars.Reset.inst_stack << method(:inst).to_proc
-        # end
-        # if @id == 2
-        #     raise TdlError.new("____________")
-        # end
+        @belong_to_module = belong_to_module
+        unless @belong_to_module 
+            raise TdlError.new("Reset<#{name}> dnot have belong_to_module")
+        end
     end
 
     # def signal

data/lib/tdl/elements/clock.rb

@@ -5,7 +5,7 @@ class Clock < SignalElm
     attr_reader :name
     attr_accessor :id,:ghost,:port,:dsize,:freqM,:jitter
 
-    def initialize(name:"system_clock",freqM:100.0,port:false,dsize:1,jitter: 0.01)
+    def initialize(name:"system_clock",freqM:100.0,port:false,dsize:1,jitter: 0.01, belong_to_module: nil)
         name_legal?(name)
         # @id = GlobalParam.CurrTdlModule.BindEleClassVars.Clock.id
         @name = name
@@ -13,14 +13,10 @@ class Clock < SignalElm
         @port = port
         @dsize = dsize
         @jitter = jitter
-        # if @port
-        #     GlobalParam.CurrTdlModule.BindEleClassVars.Clock.ports << self if @id != 0
-        # else
-        #     GlobalParam.CurrTdlModule.BindEleClassVars.Clock.inst_stack << method(:inst).to_proc
-        # end
-        # if @id == 0
-        #     raise TdlError.new(" ID ")
-        # end
+        @belong_to_module = belong_to_module
+        unless @belong_to_module 
+            raise TdlError.new("Clock<#{name}> dnot have belong_to_module")
+        end
     end
 
     # def port_length

data/lib/tdl/elements/data_inf.rb

@@ -567,23 +567,6 @@ end
 
 class DataInf_C ## signals in interface
 
-    # def valid
-    #     RedefOpertor.with_normal_operators do 
-    #         # raise TdlError.new("\nARRAY Don't have 'valid'") unless @dimension.empty?
-    #         # NqString.new(signal.concat ".valid") 
-    #         if @dimension.empty?
-    #             NqString.new(signal.concat ".valid") 
-    #         else 
-    #             unless @_array_chain_hash_
-    #                 rel = generate_inf_to_signals('valid',width=1)
-    #                 @_array_chain_hash_ = {}
-    #                 @_array_chain_hash_['valid'] = rel
-    #             end
-    #             TdlSpace::ArrayChain.new(@_array_chain_hash_['valid'],[])
-    #         end
-    #     end
-    # end
-
     define_arraychain_tail_method('valid')
     define_arraychain_tail_method('ready',width=1,rv=true)
     define_arraychain_tail_method('vld_rdy')

data/lib/tdl/elements/logic.rb

@@ -21,7 +21,7 @@ class Logic < SignalElm
     # attr_reader :dsize
     attr_accessor :name,:dsize,:id,:ghost,:type
     attr_reader :dimension,:port
-    def initialize(name:"tmp",dsize:1,port: false,default: nil,msb_high: true,dimension: [],type: "logic")
+    def initialize(name:"tmp",dsize:1,port: false,default: nil,msb_high: true,dimension: [],type: "logic",belong_to_module: nil)
         @name   = name
         # @id = GlobalParam.CurrTdlModule.BindEleClassVars.Logic.id
         @dsize = dsize
@@ -37,31 +37,12 @@ class Logic < SignalElm
             yield
         end
 
-        # if @port && (@port != :origin)
-        #     GlobalParam.CurrTdlModule.BindEleClassVars.Logic.ports << self if @id != 0
-        # else
-        #     # @@inst_stack << method(:inst).to_proc
-        #     GlobalParam.CurrTdlModule.BindEleClassVars.Logic.inst_stack << lambda{ inst() }
-        # end
-        # define_method(:signal) do |h,l|
-        #     if h
-        #         hh = h
-        #     else
-        #         hh = dsize-1
-        #     end
-        #
-        #     if l
-        #         ll = l
-        #     else
-        #         l = 0
-        #     end
-        #
-        #     if dsize == 1
-        #         "#{name}_id#{@id}"
-        #     else
-        #         "#{name}_id#{@id}[#{hh}:#{ll}]"
-        #     end
-        # end
+        @belong_to_module = belong_to_module
+
+        unless @belong_to_module
+            raise TdlError.new("Logic<#{@name}> be not belong_to_module")
+        end
+
     end
 
     def copy(name:@name.to_s,dsize:@dsize,port:@port,default:@default,msb_high:@msb_high,dimension:@dimension,type:@type,belong_to_module:@belong_to_module)
@@ -98,12 +79,9 @@ class Logic < SignalElm
             b.slaver = true
         end
 
-        # RedefOpertor.with_normal_operators do
-        #     TdlSpace::ArrayChain.new(self,a,b)
-        # end
-        # end
+        
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
-            TdlSpace::ArrayChain.new(self,a,b)
+            TdlSpace::ArrayChain.create(obj: self,lchain: a, end_slice: b, belong_to_module: belong_to_module)
         end
     end
 

data/lib/tdl/elements/mail_box.rb

@@ -4,11 +4,16 @@ class MailBox < BaseElm
     # include AlwaysBlock
     # include RedefOpertor
     attr_accessor :ghost
-    def initialize(name:'mbox',depth:100)
+    def initialize(name:'mbox',depth:100, belong_to_module: nil )
         @name = name
 
         @depth = depth
 
+        @belong_to_module = belong_to_module
+        unless @belong_to_module 
+            raise TdlError.new("Clock<#{name}> dnot have belong_to_module")
+        end
+
     end
 
     def signal

data/lib/tdl/elements/originclass.rb

@@ -8,8 +8,9 @@ module TdlSpace
     end
 
     class ArrayChain
-        attr_reader :obj,:chain,:end_slice
-        def initialize(obj="tmp",lchain=[],end_slice=false)
+        attr_reader :obj,:chain,:end_slice,:belong_to_module
+        def initialize(obj="tmp",lchain=[],end_slice=false,belong_to_module=nil)
+            @belong_to_module=belong_to_module
             @obj = obj
             if !end_slice
                 if lchain.is_a? Array
@@ -25,48 +26,19 @@ module TdlSpace
             else
                 raise TdlError.new("数组下标类型出错")
             end
+
+            unless @belong_to_module
+                raise TdlError.new "ArrayChain<#{obj.to_s}> 必须添加 belong_to_module"
+            end
         end
 
-        # def [](a,b=false)
-        #     if a.is_a? ClassHDL::OpertorChain
-        #         a.slaver = true
-        #     end
-    
-        #     if b.is_a? ClassHDL::OpertorChain
-        #         b.slaver = true
-        #     end
-
-        #     if @end_slice
-        #         raise TdlError.new("数组下标已经被用片选[#{@end_slice[0]},#{@end_slice[1]}]终结")
-        #     end
-        #     RedefOpertor.with_normal_operators do
-        #         unless b 
-        #             ArrayChain.new(obj,chain+[a])
-        #         else 
-        #             # ArrayChain.new(&obj,chain,[a,b])
-        #             @end_slice = [a,b]
-        #             self
-        #         end
-        #     end
-        # end
-
-        # def to_s
-        #     RedefOpertor.with_normal_operators do
-        #         str = ""
-        #         chain.each do |e|
-        #             unless e.is_a? ArrayChainSignalMethod
-        #                 str += "[#{e.to_s}]"
-        #             else 
-        #                 str += ".#{e.name.to_s}"
-        #             end
-        #         end
-        #         if @end_slice
-        #             str += "[#{@end_slice[0]}:#{@end_slice[1]}]"
-        #         end
-
-        #         "#{obj.to_s}#{str}".to_nq
-        #     end
-        # end
+        def self.create(obj: "tmp",lchain: [],end_slice: false,belong_to_module: nil)
+            ArrayChain.new(obj, lchain, end_slice, belong_to_module)
+        end
+
+        def root_ref(&block)
+            "#{belong_to_module.root_ref(&block)}.#{to_s}".to_nq
+        end
 
         def inspect
             self.to_s
@@ -86,9 +58,7 @@ module TdlSpace
             end
             ## 判断 obj是否响应方法
             if @obj.respond_to?(method) && !method.to_s.eql?("inst_name")
-                # ArrayChain.new(@obj.to_s,lchain=@chain + [ArrayChainSignalMethod.new(method)])
-                # ArrayChain.new(@obj.to_s,lchain=@chain.dup.concat([ArrayChainSignalMethod.new(method)]))
-                ArrayChain.new(@obj,lchain=@chain.dup.concat([ArrayChainSignalMethod.new(method)]))
+                ArrayChain.create(obj: @obj,lchain:@chain.dup.concat([ArrayChainSignalMethod.new(method)]) ,belong_to_module: belong_to_module)
             else 
             
                 # raise TdlError.new("ArrayChain 没有末尾方法 #{method} #{arg}")
@@ -212,7 +182,7 @@ class BaseElm < AxiTdl::SdlModuleActiveBaseElm
                             
                             @_array_chain_hash_[name.to_s] = rel
                         end
-                        TdlSpace::ArrayChain.new(@_array_chain_hash_[name.to_s],[])
+                        TdlSpace::ArrayChain.create(obj: @_array_chain_hash_[name.to_s],lchain:[],belong_to_module: self.belong_to_module)
                     end
                 end
             end
@@ -484,7 +454,7 @@ class InfElm
 
         return signal if @dimension.empty?
         
-        TdlSpace::ArrayChain.new(self,a,b)
+        TdlSpace::ArrayChain.create(obj: self,lchain: a, end_slice: b, belong_to_module: belong_to_module)
     end
 
     def self.same_name_socket(way,mix,inf_array,base_new_inf=nil,belong_to_module=nil)

data/lib/tdl/elements/parameter.rb

@@ -6,7 +6,7 @@ class Parameter < BaseElm
     include BaseModule
     attr_accessor :name,:value,:id,:ghost,:type,:vcs_string
 
-    def initialize(name: "P",value:100,local:false,port:false,show:true,type:nil)
+    def initialize(name: "P",value:100,local:false,port:false,show:true,type:nil,belong_to_module: nil)
         @name = name
         @local = local
         # @id = GlobalParam.CurrTdlModule.BindEleClassVars.Parameter.id
@@ -14,11 +14,10 @@ class Parameter < BaseElm
         @show = show
         @value = value
         @type = type
-        # if @port
-        #     GlobalParam.CurrTdlModule.BindEleClassVars.Parameter.ports << self
-        # else
-        #     GlobalParam.CurrTdlModule.BindEleClassVars.Parameter.inst_stack << method(:inst)
-        # end
+        @belong_to_module = belong_to_module
+        unless @belong_to_module 
+            raise TdlError.new("Parameter<#{name}> dnot have belong_to_module")
+        end
     end
 
     def inst

data/lib/tdl/examples/11_test_unit/dve.tcl

@@ -12,128 +12,8 @@ gui_set_time_units 1ps
 ## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
 ## ==== [add_signal] ===== ##
 
-## -------------- sub_md0_logic -------------------------
-set _wave_session_group_sub_md0_logic sub_md0_logic
-# set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name -seed sub_md0_logic]
-if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_logic"]} {
-    set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name]
-}
-set Group2_sub_md0_logic "$_wave_session_group_sub_md0_logic"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_sub_md0_logic" {  {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.cnt}  }
-## ============== sub_md0_logic =========================
-        
-
-## -------------- sub_md0_interface -------------------------
-set _wave_session_group_sub_md0_interface sub_md0_interface
-# set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name -seed sub_md0_interface]
-if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_interface"]} {
-    set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name]
-}
-set Group2_sub_md0_interface "$_wave_session_group_sub_md0_interface"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_sub_md0_interface" {  {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.axis_in}  }
-## ============== sub_md0_interface =========================
-        
-
-## -------------- sub_md0_default -------------------------
-set _wave_session_group_sub_md0_default sub_md0_default
-# set _wave_session_group_sub_md0_default [gui_sg_generate_new_name -seed sub_md0_default]
-if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_default"]} {
-    set _wave_session_group_sub_md0_default [gui_sg_generate_new_name]
-}
-set Group2_sub_md0_default "$_wave_session_group_sub_md0_default"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_sub_md0_default" {  }
-## ============== sub_md0_default =========================
-        
-
-## -------------- sub_md0_default.inter_tf -------------------------
-## set _wave_session_group_sub_md0_default_inter_tf Group1
-## set _wave_session_group_sub_md0_default_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md0_default ]
 
-set _wave_session_group_sub_md0_default_inter_tf $_wave_session_group_sub_md0_default|
-append _wave_session_group_sub_md0_default_inter_tf inter_tf
-set sub_md0_default|inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
-
-# set Group2_sub_md0_default_inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_sub_md0_default_inter_tf" {  {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.inter_tf}  }  
-## ============== sub_md0_default.inter_tf =========================
-        
-
-## -------------- sub_md1_default -------------------------
-set _wave_session_group_sub_md1_default sub_md1_default
-# set _wave_session_group_sub_md1_default [gui_sg_generate_new_name -seed sub_md1_default]
-if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_default"]} {
-    set _wave_session_group_sub_md1_default [gui_sg_generate_new_name]
-}
-set Group2_sub_md1_default "$_wave_session_group_sub_md1_default"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_sub_md1_default" {  {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.cnt}  {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.axis_out}  {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.enable}  }
-## ============== sub_md1_default =========================
-        
-
-## -------------- sub_md1_inner -------------------------
-set _wave_session_group_sub_md1_inner sub_md1_inner
-# set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name -seed sub_md1_inner]
-if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_inner"]} {
-    set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name]
-}
-set Group2_sub_md1_inner "$_wave_session_group_sub_md1_inner"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner" {  }
-## ============== sub_md1_inner =========================
-        
 
-## -------------- sub_md1_inner.inter_tf -------------------------
-## set _wave_session_group_sub_md1_inner_inter_tf Group1
-## set _wave_session_group_sub_md1_inner_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md1_inner ]
-
-set _wave_session_group_sub_md1_inner_inter_tf $_wave_session_group_sub_md1_inner|
-append _wave_session_group_sub_md1_inner_inter_tf inter_tf
-set sub_md1_inner|inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
-
-# set Group2_sub_md1_inner_inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner_inter_tf" {  {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.inter_tf}  }  
-## ============== sub_md1_inner.inter_tf =========================
-        
-
-## -------------- exp_test_unit_default -------------------------
-set _wave_session_group_exp_test_unit_default exp_test_unit_default
-# set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name -seed exp_test_unit_default]
-if {[gui_sg_is_group -name "$_wave_session_group_exp_test_unit_default"]} {
-    set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name]
-}
-set Group2_exp_test_unit_default "$_wave_session_group_exp_test_unit_default"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default" {  }
-## ============== exp_test_unit_default =========================
-        
-
-## -------------- exp_test_unit_default.axis_data_inf -------------------------
-## set _wave_session_group_exp_test_unit_default_axis_data_inf Group1
-## set _wave_session_group_exp_test_unit_default_axis_data_inf [gui_sg_generate_new_name -seed axis_data_inf -parent $_wave_session_group_exp_test_unit_default ]
-
-set _wave_session_group_exp_test_unit_default_axis_data_inf $_wave_session_group_exp_test_unit_default|
-append _wave_session_group_exp_test_unit_default_axis_data_inf axis_data_inf
-set exp_test_unit_default|axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
-
-# set Group2_exp_test_unit_default_axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default_axis_data_inf" {  {Sim:tb_exp_test_unit.rtl_top.axis_data_inf}  }  
-## ============== exp_test_unit_default.axis_data_inf =========================
-        
 
 ## 创建波形窗口
 if {![info exists useOldWindow]} { 
@@ -162,33 +42,9 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
 ## gui_list_add_group -id ${Wave.3}  -after ${Group2} [list ${Group2|tx_inf}]
 ## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
 ## === [add_signal_wave] === ##
-## -------------- Group2_sub_md0_logic -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_logic}]
-## ============== Group2_sub_md0_logic =========================
-## -------------- Group2_sub_md0_interface -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_interface}]
-## ============== Group2_sub_md0_interface =========================
-## -------------- Group2_sub_md0_default -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_default}]
-## ============== Group2_sub_md0_default =========================
-## -------------- sub_md0_default|inter_tf -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md0_default|inter_tf}]
-## ============== sub_md0_default|inter_tf =========================
-## -------------- Group2_sub_md1_default -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_default}]
-## ============== Group2_sub_md1_default =========================
-## -------------- Group2_sub_md1_inner -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_inner}]
-## ============== Group2_sub_md1_inner =========================
-## -------------- sub_md1_inner|inter_tf -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md1_inner|inter_tf}]
-## ============== sub_md1_inner|inter_tf =========================
-## -------------- Group2_exp_test_unit_default -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_exp_test_unit_default}]
-## ============== Group2_exp_test_unit_default =========================
-## -------------- exp_test_unit_default|axis_data_inf -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${exp_test_unit_default|axis_data_inf}]
-## ============== exp_test_unit_default|axis_data_inf =========================
+
+
+
 
 gui_seek_criteria -id ${Wave.3} {Any Edge}
 
@@ -205,12 +61,9 @@ gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linka
 gui_list_set_filter -id ${Wave.3} -text {*}
 ##gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2}  -position in
 ## === [add_bar] === ##
-gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md0_logic}  -position in
-gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md0_interface}  -position in
-gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md0_default}  -position in
-gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md1_default}  -position in
-gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md1_inner}  -position in
-gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_exp_test_unit_default}  -position in
+
+
+
 
 gui_marker_move -id ${Wave.3} {C1} 560248001
 gui_view_scroll -id ${Wave.3} -vertical -set 35