axi_tdl 0.0.19 → 0.1.7

data/lib/tdl/rebuild_ele/ele_base.rb

@@ -128,7 +128,7 @@ module TdlSpace
                 define_method(tdl_key) do 
                     rel = self.instance_variable_get("@_#{tdl_key}_")
                     unless rel 
-                        "#{inst_name}.#{hdl_key}".to_nq
+                        TdlSpace::ArrayChain.create(obj: "#{inst_name}.#{hdl_key}".to_nq, belong_to_module: belong_to_module)
                     else 
                         rel 
                     end
@@ -152,9 +152,9 @@ module TdlSpace
                 define_method('clock') do 
                     rel = self.instance_variable_get("@_#{tdl_key}_")
                     if !dimension || dimension.empty?
-                        rel || TdlSpace::ArrayChain.new("#{self.inst_name}.#{hdl_key}")
+                        rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
                     else  
-                        rel || TdlSpace::ArrayChain.new("#{self.inst_name}[0].#{hdl_key}")
+                        rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}[0].#{hdl_key}", belong_to_module: belong_to_module)
                     end
                 end
 
@@ -171,7 +171,7 @@ module TdlSpace
              self.class_exec(tdl_key) do |tdl_key|
                 define_method('reset') do 
                     rel = self.instance_variable_get("@_#{tdl_key}_")
-                    rel || TdlSpace::ArrayChain.new("#{self.inst_name}.#{hdl_key}")
+                    rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
                 end
 
                 define_method("reset=") do |arg|
@@ -200,7 +200,7 @@ module TdlSpace
             self.class_exec(tdl_key) do |tdl_key|
                 define_method(tdl_key) do 
                     rel = self.instance_variable_get("@_#{tdl_key}_") || default_value
-                    rel || TdlSpace::ArrayChain.new("#{self.inst_name}.#{hdl_key}")
+                    rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
                 end
 
                 define_method("#{tdl_key}=") do |arg|
@@ -215,7 +215,7 @@ module TdlSpace
                 _io_map(e,e,nil,'sdata',nil)
                 self.class_exec(e) do |e|
                     define_method(e) do 
-                        TdlSpace::ArrayChain.new("#{self.inst_name}.#{e}")
+                        TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{e}", belong_to_module: belong_to_module)
                     end
                 end
             end
@@ -225,7 +225,7 @@ module TdlSpace
             _io_map(name,name,nil,'pdata',dimension)
             self.class_exec(name) do |e|
                 define_method(e) do 
-                    TdlSpace::ArrayChain.new("#{self.inst_name}.#{e}")
+                    TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{e}", belong_to_module: belong_to_module)
                 end
             end
         end
@@ -374,7 +374,7 @@ module TdlSpace
                     e.slaver = true
                 end 
             end
-            TdlSpace::ArrayChain.new(self,a)
+            TdlSpace::ArrayChain.create(obj: self,lchain: a, belong_to_module: belong_to_module)
         end
 
         def instance(exp_len: nil)
@@ -432,11 +432,16 @@ module TdlSpace
                 vv = rel || v[1]
                 # vv = self.send(k) || v[1]
                 ## 不例化 FreqM，FreqM只是为了SDL兼容
-                if vv && k.to_s != 'freqM'
+                # if vv && k.to_s != 'freqM'
+                if vv 
                     if vv.instance_of?(String)
                         str << ".#{v[0]}(\"#{vv}\")"
                     else
-                        str << ".#{v[0]}(#{vv})"
+                        if k.to_s == 'freqM'
+                            str << ".#{v[0]}(#{(respond_to?(:clock) && self.clock.is_a?(Clock) && self.clock.freqM ) || vv})"
+                        else 
+                            str << ".#{v[0]}(#{vv})"
+                        end
                     end
                 end
             end

data/lib/tdl/sdlmodule/sdlmodule.rb

@@ -74,7 +74,7 @@ class SdlModule
             if e.is_a? String 
                 next 
             end
-            tmp = e.new(name:"#{head}_NC")
+            tmp = e.new(name:"#{head}_NC",belong_to_module: self)
             tmp.belong_to_module = self
             tmp.ghost = true
             instance_variable_set("@#{head}_NC",tmp)
@@ -127,16 +127,6 @@ class SdlModule
         @@allmodule << self
         @module_name = name
         @real_sv_path = File.join(@out_sv_path,"#{@module_name}.sv") if @out_sv_path
-        # @port_clocks = []
-        # @port_resets = []
-        # @port_params = []
-        # @port_logics = []
-        # @port_datainfs = []
-        # @port_datainf_c_s = []
-        # @port_videoinfs = []
-        # @port_axisinfs = []
-        # @port_axi4infs = []
-        # @port_axilinfs = []
 
         @port_clocks        = Hash.new
         @port_resets        = Hash.new
@@ -164,52 +154,16 @@ class SdlModule
             # self.instance_variable_set("#{head_str}_NC",tmp)
         end
         create_ghost
-        # @super_modules = []
-        # @Logic_collect = []
-        # @Logic_inst = []
-        # @Logic_draw = []
-        #
-        # @Clock_collect = []
-        # @Clock_inst = []
-        # @Clock_draw = []
-        #
-        # @Reset_collect = []
-        # @Reset_inst = []
-        # @Reset_draw = []
-        #
-        # @Parameter_collect = []
-        # @Parameter_inst = []
-        # @Parameter_draw = []
-        #
-        # @DataInf_collect = []
-        # @DataInf_inst = []
-        # @DataInf_draw = []
-        #
-        # @DataInf_C_collect = []
-        # @DataInf_C_inst = []
-        # @DataInf_C_draw = []
-        #
-        # @AxiStream_collect = []
-        # @AxiStream_inst = []
-        # @AxiStream_draw = []
-        #
-        # @AxiLite_collect = []
-        # @AxiLite_inst = []
-        # @AxiLite_draw = []
-        #
-        # @VideoInf_collect = []
-        # @VideoInf_inst = []
-        # @VideoInf_draw = []
-        #
-        # @Axi4_collect = []
-        # @Axi4_inst = []
-        # @Axi4_draw = []
+
         if block_given?
             yield(self)
         end
 
         @instanced_and_parent_module ||= Hash.new
         @instance_and_children_module ||= Hash.new
+
+        ## 记录当前模块被例化的 具体对象
+        @instances =[]
     end
 
     public
@@ -473,3 +427,115 @@ class SdlModule
         end
     end
 end
+
+class SdlModule 
+
+    ## 获取信号的绝对路径
+    def path_refs(&block)
+        collects = []
+        if self != TopModule.current.techbench
+            @instances.each do |it|
+                it.origin.parents_inst_tree do |tree|
+                    ll = ["$root"]
+                    rt = tree.reverse
+                    rt.each_index do |index|
+                        if rt[index].respond_to? :module_name
+                            ll << rt[index].module_name 
+                        else 
+                            ll << rt[index].inst_name
+                        end
+                    end
+                    # ll << it.inst_name
+                    new_name = ll.join('.').to_nq
+                    if block_given?
+                        if yield(new_name)
+                            collects << new_name
+                        end 
+                    else
+                        collects << new_name
+                    end
+                end
+            end
+        else
+            collects = ["$root.#{self.module_name}".to_nq]
+        end
+        collects
+    end
+
+    ## 定义获取 信号的绝对路径
+    def root_ref(&block)
+        ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
+            rels = path_refs(&block)
+            if block_given?
+                sst = "block given"
+            else
+                sst = "no block"
+            end
+
+            if rels.size == 1
+                rels[0]
+            elsif rels.size == 0
+                raise TdlError.new "#{module_name} Cant find root ref {#{sst}}"
+            else
+                raise TdlError.new "#{module_name} Find multi root refs {#{sst}} \n#{rels.join("\n")}\n"
+            end
+        end
+    end
+
+end
+
+## 迭代 本模块及本模块的子模块
+class SdlModule 
+
+    def all_ref_sdlmodules(&block) 
+        sdlms = instance_and_children_module.values.uniq
+        sdlms = sdlms.map do |e|
+            if e.instance_and_children_module.any? 
+                e.all_ref_sdlmodules(&block)
+            else 
+                e 
+            end
+        end
+        sdlms = sdlms.unshift(self)
+        sdlms = sdlms.flatten
+        sdlms.map(&block)
+    end
+
+end
+
+### 有时候 sdlmodule 引用的是 HDL文件，为了能够 正常引用到 需要特殊处理
+class SdlModule
+    def contain_hdl(*hdl_names)
+        __contain_hdl__(false,*hdl_names)
+    end
+
+    def __contain_hdl__(recreate,*hdl_names)
+        hdl_names = hdl_names.map do |e| 
+
+            if e.include?("/") || e.include?("\\")
+                e 
+            else  
+                
+                ee = find_first_hdl_path(e)
+                if recreate && !ee 
+                    raise TdlError.new("Cant find #{e} in tdl_paths")
+                end
+                ee || e
+            end
+        end 
+        unless recreate
+            @__contain_hdl__ ||= []
+            @__contain_hdl__ += hdl_names
+        else 
+            @__contain_hdl__ = hdl_names
+        end
+        @__contain_hdl__.uniq!
+        @__contain_hdl__
+    end
+
+    def require_hdl(*hdl_path)
+        hdl_path.each do |hp|
+            __require_hdl__(hp,self)
+        end
+    end
+end

data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb

@@ -88,7 +88,7 @@ module TdlSpace
                 dimension = []
             end
             name = to_inp(name)
-            belong_to_module.Def.logic(name: name,dsize: @chain.last || 1,dimension: dimension,type: @type || 'logic')
+            rel = belong_to_module.Def.logic(name: name,dsize: @chain.last || 1,dimension: dimension,type: @type || 'logic')
         end
 
         def wire 

data/lib/tdl/sdlmodule/sdlmodule_draw.rb

@@ -52,19 +52,19 @@ class SdlModule
         pre_inst_stack_call
         @out_sv_path ||= '..\..\tdl\test_sdlmodule'
         if File.exist?(File.join(@out_sv_path,"#{module_name}.sv")) 
-            old_str = File.open(File.join(@out_sv_path,"#{module_name}.sv")).read.gsub(/\/\*.*?\*\//m,"").gsub(/\/\/.*/,"").sub(/^`timescale .*/,"").strip
+            old_str = File.open(File.join(@out_sv_path,"#{module_name}.sv")).read.sub(/\/\*.*?\*\//m,"").gsub(/\/\/.*/,"").sub(/^`timescale .*/,"").strip
         
 
             head_str,body_str = build_module_verb(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
             new_str = head_str+body_str
-            if body_str.gsub(/\/\*.*?\*\//m,"").gsub(/\/\/.*/,"").strip != old_str
+            if body_str.gsub(/\/\/.*/,"").strip != old_str
                 File.open(File.join(@out_sv_path,"#{module_name}.sv"),"w") do |f|
                     f.print new_str
                 end
             end 
         else
             File.open(File.join(@out_sv_path,"#{module_name}.sv"),"w") do |f|
-                f.print build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
+                f.print build_module_verb(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code).join("")
             end
         end 
     end

data/lib/tdl/sdlmodule/sdlmodule_instance.rb

@@ -448,6 +448,9 @@ class SdlModule
         # @ports = (@port_clocks + @port_resets + @port_logics + @port_datainfs + @port_datainf_c_s + @port_videoinfs + @port_axisinfs + @port_axi4infs + @port_axilinfs)
         @instance_cnt ||= 0
         inst_p = SdlInst.new(origin:self,name:name)
+     
+        @instances ||= []
+        @instances << inst_p
 
         @port_params.each do |k,v|
             inst_p.inst_param_hash[k.to_s] = nil

data/lib/tdl/sdlmodule/sdlmodule_port_define.rb

@@ -65,7 +65,7 @@ class SdlModule
         if value.is_a? Float
             type = :real
         end
-        tmp = Parameter.new(name:name.to_s,value:value,port:true,type:type,show:show)
+        tmp = Parameter.new(name:name.to_s,value:value,port:true,type:type,show:show, belong_to_module: self)
         add_to_new_module("@port_params",tmp)
         add_method_to_itgt(name,tmp)
         tmp
@@ -87,7 +87,7 @@ class SdlModule
         #     tmp
         # end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
-            tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension)
+            tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension, belong_to_module: self)
             add_to_new_module("@port_logics",tmp)
             add_method_to_itgt(name,tmp)
             tmp
@@ -109,7 +109,7 @@ class SdlModule
         #     tmp
         # end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
-            tmp = Logic.new(name:name,dsize:dsize,port:"output",dimension:dimension,type: 'logic')
+            tmp = Logic.new(name:name,dsize:dsize,port:"output",dimension:dimension,type: 'logic', belong_to_module: self)
             add_to_new_module("@port_logics",tmp)
 
             if block_given?
@@ -136,7 +136,7 @@ class SdlModule
         #     tmp
         # end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
-            tmp = Logic.new(name:name,dsize:dsize,port:"inout",dimension:dimension,type: '' )
+            tmp = Logic.new(name:name,dsize:dsize,port:"inout",dimension:dimension,type: '' , belong_to_module: self)
             add_to_new_module("@port_logics",tmp)
 
             if block_given?
@@ -150,7 +150,7 @@ class SdlModule
     def Clock(name,freqM:100,port: :input,pin:[],iostd:[],dsize:1,pin_prop:nil)
         port_name_chk(name)
         pin,iostd = parse_pin_prop(pin_prop) if pin_prop
-        a = Clock.new(name:name,freqM:freqM,port:port,dsize:dsize)
+        a = Clock.new(name:name,freqM:freqM,port:port,dsize:dsize, belong_to_module: self)
         add_to_new_module("@port_clocks",a)
 
         if block_given?
@@ -164,7 +164,7 @@ class SdlModule
     def Reset(name,port: :input,active:"low",pin:[],iostd:[],dsize:1,pin_prop:nil)
         port_name_chk(name)
         pin,iostd = parse_pin_prop(pin_prop) if pin_prop
-        a = Reset.new(name:name,active:active.to_s.downcase,port:port,dsize:dsize)
+        a = Reset.new(name:name,active:active.to_s.downcase,port:port,dsize:dsize, belong_to_module: self)
         add_to_new_module("@port_resets",a)
         # define_method(name){ a }
         add_method_to_itgt(name,a)

data/lib/tdl/sdlmodule/sdlmodule_varible.rb

@@ -13,25 +13,25 @@ class DefXp
     end
 
     def logic(name:"tmp",dsize:1,port:false,default:nil,msb_high:true,dimension:[],type:"logic",&block)
-        lg = Logic.new(name:name,dsize:dsize,port:port,default:default,msb_high:msb_high,dimension:dimension,type:type)
+        lg = Logic.new(name:name,dsize:dsize,port:port,default:default,msb_high:msb_high,dimension:dimension,type:type, belong_to_module: @sdlmodule)
         var_common(lg,&block)
         add_method_to_itgt(name,lg)
     end
 
     def clock(name:"",freqM:100,dsize:1,&block)
-        a = Clock.new(name:name,freqM:freqM,dsize:dsize)
+        a = Clock.new(name:name,freqM:freqM,dsize:dsize, belong_to_module: @sdlmodule)
         var_common(a,&block)
         add_method_to_itgt(name,a)
     end
 
     def reset(name:"",active:"low",dsize:1,&block)
-        a = Reset.new(name:name,active:active,dsize:dsize)
+        a = Reset.new(name:name,active:active,dsize:dsize, belong_to_module: @sdlmodule)
         var_common(a,&block)
         add_method_to_itgt(name,a)
     end
 
     def parameter(name:"P",value:100,local:false,type:nil,&block)
-        a = Parameter.new(name:name,value:value,local:local,port:false,show:true,type:type)
+        a = Parameter.new(name:name,value:value,local:local,port:false,show:true,type:type, belong_to_module: @sdlmodule)
         var_common(a,&block)
         add_method_to_itgt(name,a)
     end
@@ -77,12 +77,12 @@ class DefXp
     # end
 
     def mailbox(name:'mbox',depth:100,&block)
-        a = MailBox.new(name:name,depth:depth)
+        a = MailBox.new(name:name,depth:depth, belong_to_module: @sdlmodule)
         var_common(a,&block)
     end
 
     def debuglogic(name:"tmp",dsize:1,port:false,default:nil,msb_high:true,dimension:[],type:"logic",&block)
-        lg = DebugLogic.new(name:name,dsize:dsize,port:port,default:default,msb_high:msb_high,dimension:dimension,type:type)
+        lg = DebugLogic.new(name:name,dsize:dsize,port:port,default:default,msb_high:msb_high,dimension:dimension,type:type, belong_to_module: @sdlmodule)
         var_common(lg,&block)
         add_method_to_itgt(name,lg)
     end

data/lib/tdl/sdlmodule/test_unit_module.rb

@@ -43,6 +43,8 @@ class SdlModule
     end
 
     def gen_dev_wave_tcl ## 返回一个[]
+        return ['','',''] unless TopModule.sim
+
         dve_tcl_hash = {}
         track_signals_hash.each do |flag, base_ele_bhash|
             base_elms = []
@@ -50,6 +52,7 @@ class SdlModule
             intf_elms_name = []
             base_ele_bhash.each do |ele, sub_filter_block|
                 _ref_paths = ele.path_refs(&@__track_filter_block__)
+                _ref_paths.uniq!
 
                 if sub_filter_block
                     _ref_paths = _ref_paths.select do |e| 
@@ -143,6 +146,8 @@ class SdlModule
 
                 sub_hash.each do |ele, sub_filter_block|
                     _root_refs = ele.path_refs(&filter_block)
+                    _root_refs.uniq!
+                    
                     if sub_filter_block 
                         _root_refs.select! do |e| sub_filter_block.call(e) end
                     end    
@@ -210,6 +215,7 @@ class TestUnitModule < SdlModule ##TestUnitModule 是在编译完 TopModule TB
             to_down_pass    <= 1.b0
             initial_exec("wait(from_up_pass)")
             initial_exec("$root.#{TopModule.current.techbench.module_name}.test_unit_region = \"#{module_name}\"")
+            initial_exec("$display(\"--------------- Current test_unit <%0s> --------------------\", \"#{module_name}\")")
             block.call ## collect __root_ref_eles__ at here
             to_down_pass    <= 1.b1
         end
@@ -325,6 +331,12 @@ class TopModule
     def _exec_add_test_unit
         @_test_unit_collect_ ||= []
         args = @_test_unit_collect_
+        ## 例化需要的itgt test unit
+        # ItegrationVerb.test_unit_inst
+        ItegrationVerb.test_unit_inst do |name|
+            args.include? name.to_s
+        end
+
         self.techbench.instance_exec(args) do |args|
             index = 0
             last_index = 0