axi_tdl 0.0.19 → 0.1.7

data/lib/public_atom_module/pipe_reg.v

@@ -0,0 +1,93 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.0
+creaded: 2015/7/9 9:20:55
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module pipe_reg #(
+	parameter		DSIZE	= 8
+)(
+	input				clock			,
+	input				rst_n           ,
+	input				wr_en           ,
+	input [DSIZE-1:0]	indata          ,
+	input				low_empty       ,
+	output				valid           ,
+	output				curr_empty      ,
+	output				sum_empty       ,
+	output[DSIZE-1:0]	outdata         ,
+	output				high_reload 
+);
+
+/*
+table  
+higher_vld(wr_en)   curr_valid  low_empty :  next_valid   next_data  curr_empty sum_empty
+     1                  1           1     :      1           U           0        curr_empty | low_empty  
+     1                  1           0     :      1           K           0        curr_empty | low_empty
+     1                  0           1     :      1           U           0        curr_empty | low_empty
+     1                  0           0     :      1           U           0        curr_empty | low_empty
+     0                  1           1     :      0           C           1        curr_empty | low_empty
+     0                  1           0     :      1           K           0        curr_empty | low_empty
+     0                  0           1     :      0           C           1        curr_empty | low_empty
+     0                  0           0     :      0           C           1        curr_empty | low_empty
+*/
+
+reg					data_vld;
+reg[DSIZE-1:0]		data_reg;  
+reg					reload_reg;
+
+always@(posedge clock/*,negedge rst_n*/)
+	if(~rst_n)	data_vld	<= 1'b0;
+	else 
+		case({wr_en,data_vld,low_empty})
+		3'b111,
+		3'b110,
+		3'b101,
+		3'b100,
+		3'b010:	data_vld	<= 1'b1;
+		default:data_vld	<= 1'b0;
+		endcase
+
+always@(posedge clock/*,negedge rst_n*/)
+	if(~rst_n)	reload_reg	<= 1'b0;
+	else 
+		case({wr_en,data_vld,low_empty})
+		3'b111:	reload_reg	<= 1'b1;
+		3'b110:	reload_reg	<= 1'b0;
+		3'b101:	reload_reg	<= 1'b1;
+		3'b100:	reload_reg	<= 1'b1;
+		3'b011:	reload_reg	<= 1'b1;
+		3'b010: reload_reg	<= 1'b0;
+		3'b001:	reload_reg	<= 1'b1;
+		3'b000:	reload_reg	<= 1'b1;
+		default:reload_reg	<= 1'b0;
+		endcase
+
+always@(posedge clock/*,negedge rst_n*/)
+	if(~rst_n)	data_reg	<= {DSIZE{1'b0}};
+	else 
+		case({wr_en,data_vld,low_empty})
+		3'b111:	data_reg	<= indata;
+		3'b110:	data_reg	<= data_reg;
+		3'b101:	data_reg	<= indata;
+		3'b100:	data_reg	<= indata;
+		3'b011:	data_reg	<= {DSIZE{1'b0}};
+		3'b010: data_reg	<= data_reg;
+		3'b001:	data_reg	<= {DSIZE{1'b0}};
+		3'b000:	data_reg	<= {DSIZE{1'b0}};
+		default:data_reg	<= {DSIZE{1'b0}};
+		endcase
+
+assign	curr_empty	= !data_vld;
+assign	outdata		= data_reg;
+assign	valid		= data_vld;
+assign	sum_empty	= curr_empty | low_empty;
+assign	high_reload	= reload_reg;
+
+endmodule
+	

data/lib/public_atom_module/pipe_reg_2write_ports.v

@@ -0,0 +1,84 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.0
+creaded: 2015/7/9 9:20:55
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module pipe_reg_2write_port #(
+	parameter		DSIZE	= 8
+)(
+	input				clock			,
+	input				rst_n           ,
+	input				wr_en0          ,
+	input [DSIZE-1:0]	indata0         ,
+	input				wr_en1          ,
+	input [DSIZE-1:0]	indata1         ,
+	input				low_empty       ,
+	output				valid           ,
+	output				curr_empty      ,
+	output				sum_empty       ,
+	output[DSIZE-1:0]	outdata          
+);
+
+wire[DSIZE-1:0]		indata;
+wire				wr_en;
+
+assign indata	= wr_en0? indata0 : (wr_en1? indata0 :{DSIZE{1'b0}});
+assign wr_en	= wr_en0 | wr_en1;
+
+/*
+table  
+higher_vld(wr_en)   curr_valid  low_empty :  next_valid   next_data  curr_empty sum_empty
+     1                  1           1     :      1           U           0        curr_empty | low_empty  
+     1                  1           0     :      1           K           0        curr_empty | low_empty
+     1                  0           1     :      1           U           0        curr_empty | low_empty
+     1                  0           0     :      1           U           0        curr_empty | low_empty
+     0                  1           1     :      0           C           1        curr_empty | low_empty
+     0                  1           0     :      1           K           0        curr_empty | low_empty
+     0                  0           1     :      0           C           1        curr_empty | low_empty
+     0                  0           0     :      0           C           1        curr_empty | low_empty
+*/
+
+reg					data_vld;
+reg[DSIZE-1:0]		data_reg;
+
+always@(posedge clock/*,negedge rst_n*/)
+	if(~rst_n)	data_vld	<= 1'b0;
+	else 
+		case({wr_en,data_vld,low_empty})
+		3'b111,
+		3'b110,
+		3'b101,
+		3'b100,
+		3'b010:	data_vld	<= 1'b1;
+		default:data_vld	<= 1'b0;
+		endcase
+
+always@(posedge clock/*,negedge rst_n*/)
+	if(~rst_n)	data_reg	<= {DSIZE{1'b0}};
+	else 
+		case({wr_en,data_vld,low_empty})
+		3'b111:	data_reg	<= indata;
+		3'b110:	data_reg	<= data_reg;
+		3'b101:	data_reg	<= indata;
+		3'b100:	data_reg	<= indata;
+		3'b011:	data_reg	<= {DSIZE{1'b0}};
+		3'b010: data_reg	<= data_reg;
+		3'b001:	data_reg	<= {DSIZE{1'b0}};
+		3'b000:	data_reg	<= {DSIZE{1'b0}};
+		default:data_reg	<= {DSIZE{1'b0}};
+		endcase
+
+
+assign	curr_empty	= !data_vld;
+assign	outdata		= data_reg;
+assign	valid		= data_vld;
+assign	sum_empty	= curr_empty | low_empty;
+
+endmodule
+	

data/lib/public_atom_module/sim/clock_rst_verb.sv

@@ -0,0 +1,54 @@
+/**********************************************
+______________________________________________
+_______  ___   ___          ___   __   _    _
+_______ |     |   | |\  /| |___  |  \  |   /_\
+_______ |___  |___| | \/ | |___  |__/  |  /   \
+_______________________________________________
+descript:
+author : Young
+Version: VERB.0.0
+	create a module for it
+creaded: 2015/10/16 10:50:52
+madified:
+***********************************************/
+`timescale 1ns/1ps
+(* data_inf = "true" *)
+module clock_rst_verb #(
+	parameter bit		ACTIVE			= 1,
+	parameter longint	PERIOD_CNT		= 0,
+	parameter			RST_HOLD		= 5,
+	parameter real		FreqM			= 100
+)(
+	output			clock,
+	output			rst_x
+);
+
+bit clk_pause = 1;
+bit	clock_reg;
+bit	rst_reg;
+
+longint ccnt = 0;
+
+initial begin
+	clk_pause	= 1;
+	clock_reg	= 0;
+	rst_reg		= ACTIVE;
+	#(1000/FreqM*2);
+	clk_pause	= 0;
+	repeat(RST_HOLD)
+		@(posedge clock_reg);
+	rst_reg		= ~rst_reg;
+end
+
+always #(1000/FreqM/2) begin
+	if(clk_pause == 0 && (PERIOD_CNT==0 || ccnt < PERIOD_CNT))
+		clock_reg	= ~clock_reg;
+end
+
+always@(posedge clock)
+	ccnt	<= ccnt + 1;
+
+assign	clock	= clock_reg;
+assign	rst_x	= rst_reg;
+
+endmodule

data/lib/public_atom_module/sim/clock_rst_verc.sv

@@ -0,0 +1,69 @@
+/**********************************************
+______________________________________________
+_______  ___   ___          ___   __   _    _
+_______ |     |   | |\  /| |___  |  \  |   /_\
+_______ |___  |___| | \/ | |___  |__/  |  /   \
+_______________________________________________
+descript:
+author : Young
+Version: VERB.0.0
+	create a module for it
+Version: VERC.0.0 ###### Tue Oct 13 14:44:58 CST 2020
+    add restart
+creaded: 2015/10/16 10:50:52
+madified:
+***********************************************/
+`timescale 1ns/1ps
+(* data_inf = "true" *)
+module clock_rst_verc #(
+	parameter bit		ACTIVE			= 1,
+	parameter longint	PERIOD_CNT		= 0,
+	parameter			RST_HOLD		= 5,
+	parameter real		FreqM			= 100
+)(
+    input           reboot,
+	output			clock,
+	output			rst_x
+);
+
+bit clk_pause = 1;
+bit	clock_reg;
+bit	rst_reg;
+
+longint ccnt = 0;
+
+initial begin
+	clk_pause	= 1;
+	clock_reg	= 0;
+	rst_reg		= ACTIVE;
+	#(1000/FreqM*2);
+	clk_pause	= 0;
+	repeat(RST_HOLD)
+		@(posedge clock_reg);
+	rst_reg		= ~rst_reg;
+end
+
+
+always@(posedge reboot) begin 
+    clk_pause	= 1;
+	clock_reg	= 0;
+	rst_reg		= ACTIVE;
+	#(1000/FreqM*2);
+	clk_pause	= 0;
+	repeat(RST_HOLD)
+		@(posedge clock_reg);
+	rst_reg		= ~rst_reg;
+end 
+
+always #(1000/FreqM/2) begin
+	if(clk_pause == 0 && (PERIOD_CNT==0 || ccnt < PERIOD_CNT))
+		clock_reg	= ~clock_reg;
+end
+
+always@(posedge clock)
+	ccnt	<= ccnt + 1;
+
+assign	clock	= clock_reg;
+assign	rst_x	= rst_reg;
+
+endmodule

data/lib/public_atom_module/sim/latency_long_tb.sv

@@ -0,0 +1,49 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.0
+creaded: 2015/12/1 14:28:31
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module latency_long_tb;
+
+bit		clock = 0;
+bit		rst_n = 0;
+
+always #5 clock	= ~clock;
+
+initial begin
+	repeat(10)	@(posedge clock);
+	rst_n	= 1;
+end
+
+bit		d;
+
+initial begin
+	d = 0   ;
+	wait(rst_n);
+	repeat(20) @(posedge clock);
+	d = 1;
+	repeat(1) @(posedge clock);
+	d = 0;
+end
+
+latency_long #(
+	.LAT		(5		)
+)latency_long_inst(
+	.clock 		(clock		),
+	.rst_n	    (rst_n      ),
+	.d          (d          ),
+	.q          (           )
+);
+
+
+endmodule
+
+
+
+

data/lib/public_atom_module/sim/latency_long_tb.sv.bak

@@ -0,0 +1,49 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.0
+creaded: 2015/12/1 14:28:31
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module latency_long_tb;
+
+bit		clock = 0;
+bit		rst_n = 0;
+
+always #5 clock	= ~clock;
+
+initial begin
+	repeat(10)	@(posedge clock);
+	rst_n	= 1;
+end
+
+bit		d;
+
+initial begin
+	d = 0   ;
+	wait(rst_n);
+	repeat(20) @(posedge clock);
+	d = 1;
+	repeat(10) @(posedge clock);
+	d = 0;
+end
+
+latency_long #(
+	.LAT		(5		)
+)latency_long_inst(
+	.clock 		(clock		),
+	.rst_n	    (rst_n      ),
+	.d          (d          ),
+	.q          (           )
+);
+
+
+endmodule
+
+
+
+

data/lib/public_atom_module/sim_system_pkg.sv

@@ -0,0 +1,4 @@
+package SystemPkg;
+    parameter SIM = "ON";
+
+endpackage

data/lib/public_atom_module/synth_system_pkg.sv

@@ -0,0 +1,4 @@
+package SystemPkg;
+    parameter SIM = "OFF";
+
+endpackage

data/lib/tdl/Logic/logic_edge.rb

@@ -1,7 +1,7 @@
 
 
 class Logic     ## EDGE METHOD
-    def raising(cnt:1,clock:nil,reset:nil)
+    def raising(cnt:1,clock:nil,reset: 1.b1 )
 
         # if cnt==1 && clock == nil && reset==nil && @raising_record
         #     return @raising_record

data/lib/tdl/auto_script/import_hdl.rb

@@ -1,6 +1,6 @@
-
-def require_hdl(hdl_path)
-    basename = File.basename(hdl_path,".sv")
+$__contain_hdl__ = []
+def __require_hdl__(hdl_path,current_sdlm=nil)
+    basename = File.basename(hdl_path,".*")
     unless SdlModule.exist_module? basename
         ## 检测是不是全路径, 或当前路径查得到
         if File.exist? hdl_path
@@ -13,6 +13,25 @@ def require_hdl(hdl_path)
                 end
 
                 AutoGenSdl.new(rel,File.join(__dir__,"tmp")).auto_rb
+
+                ## 如果是 在非 sdlmodule 内引用需要添加contain_hdl
+                # if !(current_sdlm.is_a?(SdlModule))
+                #     if TopModule.current
+                #         TopModule.current.contain_hdl(rel)
+                #     else
+                #         unless  $__contain_hdl__.include? rel
+                #             $__contain_hdl__ << rel
+                #         end
+                #     end
+                # end
+                if current_sdlm 
+                    current_sdlm.contain_hdl(rel)
+                else 
+                    unless  $__contain_hdl__.include? rel
+                        $__contain_hdl__ << rel
+                    end
+                end
+                
             else 
                 raise TdlError.new("path<#{hdl_path}> error!!!")
             end
@@ -21,6 +40,18 @@ def require_hdl(hdl_path)
     end
 end
 
+def TopModule.contain_hdl(*hdl_paths)
+    hdl_paths.each do |hdl_path|
+        rel = find_first_hdl_path(hdl_path)
+        unless rel 
+            return nil 
+        end
+        unless  $__contain_hdl__.include? rel
+            $__contain_hdl__ << rel
+        end
+    end
+end
+
 unless File.exist? File.join(__dir__,'tmp')  
     Dir.mkdir File.join(__dir__,'tmp')
 end
@@ -28,8 +59,12 @@ end
 def find_first_hdl_path(basename)
     $__tdl_paths__.each do |e|
         if File.exist? File.join(e,basename)
-            return File.join(e,basename)
+            return File.expand_path(File.join(e,basename))
         end
     end
     return nil
 end
+
+def require_hdl(hdl_path)
+    __require_hdl__(hdl_path,nil)
+end