axi_tdl 0.0.19 → 0.1.7
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/Rakefile +7 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
- data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
- data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +10 -10
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +2 -1
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +2 -1
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +9 -9
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +5 -5
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +9 -9
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +50 -0
- data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/common/test_write_mem.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +13 -13
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
- data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
- data/lib/axi/platform_ip/long_fifo_verb.sv +1 -1
- data/lib/axi/platform_ip/wide_fifo.sv +1 -1
- data/lib/axi/platform_ip/xilinx_fifo_verb.sv +1 -1
- data/lib/axi/platform_ip/xilinx_fifo_verc.sv +2 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +2 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
- data/lib/axi_tdl.rb +31 -1
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/public_atom_module/CheckPClock.sv +53 -0
- data/lib/public_atom_module/LICENSE.md +674 -0
- data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
- data/lib/public_atom_module/bits_decode.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
- data/lib/public_atom_module/broaden.v +43 -0
- data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
- data/lib/public_atom_module/ceiling.v +39 -0
- data/lib/public_atom_module/ceiling_A1.v +42 -0
- data/lib/public_atom_module/clock_rst.sv +64 -0
- data/lib/public_atom_module/cross_clk_sync.v +37 -0
- data/lib/public_atom_module/edge_generator.v +50 -0
- data/lib/public_atom_module/flooring.v +36 -0
- data/lib/public_atom_module/latch_data.v +30 -0
- data/lib/public_atom_module/latency.v +48 -0
- data/lib/public_atom_module/latency_dynamic.v +83 -0
- data/lib/public_atom_module/latency_long.v +84 -0
- data/lib/public_atom_module/latency_verb.v +52 -0
- data/lib/public_atom_module/once_event.sv +65 -0
- data/lib/public_atom_module/pipe_reg.v +93 -0
- data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
- data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
- data/lib/public_atom_module/sim/clock_rst_verc.sv +69 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
- data/lib/public_atom_module/sim_system_pkg.sv +4 -0
- data/lib/public_atom_module/synth_system_pkg.sv +4 -0
- data/lib/tdl/Logic/logic_edge.rb +1 -1
- data/lib/tdl/auto_script/import_hdl.rb +39 -4
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +47 -10
- data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
- data/lib/tdl/class_hdl/hdl_always_ff.rb +2 -2
- data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
- data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
- data/lib/tdl/class_hdl/hdl_function.rb +4 -4
- data/lib/tdl/class_hdl/hdl_generate.rb +4 -1
- data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
- data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
- data/lib/tdl/class_hdl/hdl_package.rb +45 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
- data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
- data/lib/tdl/elements/Reset.rb +5 -9
- data/lib/tdl/elements/clock.rb +5 -9
- data/lib/tdl/elements/data_inf.rb +0 -17
- data/lib/tdl/elements/logic.rb +9 -31
- data/lib/tdl/elements/mail_box.rb +6 -1
- data/lib/tdl/elements/originclass.rb +17 -47
- data/lib/tdl/elements/parameter.rb +5 -6
- data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +2 -2
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +9 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +2 -2
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +2 -2
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +41 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +2 -1
- data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +7 -7
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +2 -2
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +8 -8
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +9 -9
- data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
- data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
- data/lib/tdl/examples/8_top_module/dve.tcl +155 -2
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +29 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +7 -26
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +28 -0
- data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +13 -0
- data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +35 -0
- data/lib/tdl/examples/9_itegration/dve.tcl +155 -2
- data/lib/tdl/examples/9_itegration/tb_test_top.sv +2 -2
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -1
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +38 -0
- data/lib/tdl/examples/9_itegration/test_top.sv +4 -4
- data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +40 -0
- data/lib/tdl/examples/9_itegration/top.rb +1 -0
- data/lib/tdl/exlib/axis_verify.rb +4 -3
- data/lib/tdl/exlib/constraints_verb.rb +1 -0
- data/lib/tdl/exlib/itegration_verb.rb +212 -169
- data/lib/tdl/rebuild_ele/ele_base.rb +15 -10
- data/lib/tdl/sdlmodule/sdlmodule.rb +117 -51
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +3 -3
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
- data/lib/tdl/sdlmodule/test_unit_module.rb +12 -0
- data/lib/tdl/sdlmodule/top_module.rb +13 -10
- data/lib/tdl/tdl.rb +1 -11
- data/lib/tdl/tdlerror/tdlerror.rb +1 -1
- metadata +46 -5
- data/CODE_OF_CONDUCT.md +0 -74
- data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
@@ -3,6 +3,7 @@ require_hdl 'data_c_sim_master_model.sv'
|
|
3
3
|
TdlBuild.axis_sim_master_model(__dir__) do
|
4
4
|
parameter.LOOP "TRUE"
|
5
5
|
parameter.RAM_DEPTH 10000
|
6
|
+
input - 'enable'
|
6
7
|
input - 'load_trigger'
|
7
8
|
input[32] - 'total_length'
|
8
9
|
input[512*8] - 'mem_file' # {axis_tvalid, axis_tuser, axis_tkeep, axis_tlast, axis_tdata}
|
@@ -13,6 +14,7 @@ TdlBuild.axis_sim_master_model(__dir__) do
|
|
13
14
|
data_c_sim_master_model.data_c_sim_master_model_inst do |h| #(
|
14
15
|
h.param.LOOP param.LOOP
|
15
16
|
h.param.RAM_DEPTH param.RAM_DEPTH
|
17
|
+
h.input.enable enable
|
16
18
|
h.input.load_trigger load_trigger
|
17
19
|
h.input[32].total_length total_length
|
18
20
|
h.input[512*8].mem_file mem_file
|
@@ -0,0 +1,46 @@
|
|
1
|
+
/**********************************************
|
2
|
+
_______________________________________
|
3
|
+
___________ Cook Darwin __________
|
4
|
+
_______________________________________
|
5
|
+
descript:
|
6
|
+
author : Cook.Darwin
|
7
|
+
Version: VERA.0.0
|
8
|
+
created: 2021-04-16 17:01:07 +0800
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
|
13
|
+
module axis_sim_master_model #(
|
14
|
+
parameter LOOP = "TRUE",
|
15
|
+
parameter RAM_DEPTH = 10000
|
16
|
+
)(
|
17
|
+
input enable,
|
18
|
+
input load_trigger,
|
19
|
+
input [31:0] total_length,
|
20
|
+
input [4095:0] mem_file,
|
21
|
+
axi_stream_inf.master out_inf
|
22
|
+
);
|
23
|
+
|
24
|
+
//==========================================================================
|
25
|
+
//-------- define ----------------------------------------------------------
|
26
|
+
|
27
|
+
data_inf_c #(.DSIZE(out_inf.DSIZE + out_inf.KSIZE + out_inf.USIZE + 1),.FreqM(1.0)) out_inf_dc (.clock(out_inf.aclk),.rst_n(out_inf.aresetn)) ;
|
28
|
+
//==========================================================================
|
29
|
+
//-------- instance --------------------------------------------------------
|
30
|
+
data_c_sim_master_model #(
|
31
|
+
.LOOP (LOOP ),
|
32
|
+
.RAM_DEPTH (RAM_DEPTH )
|
33
|
+
)data_c_sim_master_model_inst(
|
34
|
+
/* input */.enable (enable ),
|
35
|
+
/* input */.load_trigger (load_trigger ),
|
36
|
+
/* input */.total_length (total_length ),
|
37
|
+
/* input */.mem_file (mem_file ),
|
38
|
+
/* data_inf_c.master */.out_inf (out_inf_dc )
|
39
|
+
);
|
40
|
+
//==========================================================================
|
41
|
+
//-------- expression ------------------------------------------------------
|
42
|
+
assign out_inf.axis_tvalid = out_inf_dc.valid;
|
43
|
+
assign out_inf_dc.ready = out_inf.axis_tready;
|
44
|
+
assign {>>{out_inf.axis_tuser,out_inf.axis_tkeep,out_inf.axis_tlast,out_inf.axis_tdata}} = out_inf_dc.data;
|
45
|
+
|
46
|
+
endmodule
|
@@ -0,0 +1,62 @@
|
|
1
|
+
/**********************************************
|
2
|
+
_______________________________________
|
3
|
+
___________ Cook Darwin __________
|
4
|
+
_______________________________________
|
5
|
+
descript:
|
6
|
+
author : Cook.Darwin
|
7
|
+
Version: VERA.0.0
|
8
|
+
created: 2021-04-16 17:01:06 +0800
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
|
13
|
+
module axis_split_channel_verb (
|
14
|
+
input [15:0] split_len,
|
15
|
+
axi_stream_inf.slaver origin_inf,
|
16
|
+
axi_stream_inf.master first_inf,
|
17
|
+
axi_stream_inf.master end_inf
|
18
|
+
);
|
19
|
+
|
20
|
+
//==========================================================================
|
21
|
+
//-------- define ----------------------------------------------------------
|
22
|
+
logic clock;
|
23
|
+
logic rst_n;
|
24
|
+
logic [16-1:0] insert_seed ;
|
25
|
+
logic [16-1:0] next_split_len ;
|
26
|
+
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_insert (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
27
|
+
//==========================================================================
|
28
|
+
//-------- instance --------------------------------------------------------
|
29
|
+
axis_insert_copy axis_insert_copy_inst(
|
30
|
+
/* input */.insert_seed (insert_seed ),
|
31
|
+
/* input */.insert_len (8'd1 ),
|
32
|
+
/* axi_stream_inf.slaver */.in_inf (origin_inf ),
|
33
|
+
/* axi_stream_inf.master */.out_inf (origin_inf_insert )
|
34
|
+
);
|
35
|
+
common_fifo #(
|
36
|
+
.DEPTH (4 ),
|
37
|
+
.DSIZE (16 )
|
38
|
+
)common_fifo_head_bytesx_inst(
|
39
|
+
/* input */.clock (clock ),
|
40
|
+
/* input */.rst_n (rst_n ),
|
41
|
+
/* input */.wdata (split_len ),
|
42
|
+
/* input */.wr_en ((origin_inf.axis_tcnt == '0) && origin_inf.axis_tvalid && origin_inf.axis_tready ),
|
43
|
+
/* output */.rdata (next_split_len ),
|
44
|
+
/* input */.rd_en (origin_inf_insert.axis_tvalid && origin_inf_insert.axis_tready && origin_inf_insert.axis_tlast ),
|
45
|
+
/* output */.count (/*unused */ ),
|
46
|
+
/* output */.empty (/*unused */ ),
|
47
|
+
/* output */.full (/*unused */ )
|
48
|
+
);
|
49
|
+
axi_stream_split_channel axi_stream_split_channel_inst(
|
50
|
+
/* input */.split_len (next_split_len ),
|
51
|
+
/* axi_stream_inf.slaver */.origin_inf (origin_inf_insert ),
|
52
|
+
/* axi_stream_inf.master */.first_inf (first_inf ),
|
53
|
+
/* axi_stream_inf.master */.end_inf (end_inf )
|
54
|
+
);
|
55
|
+
//==========================================================================
|
56
|
+
//-------- expression ------------------------------------------------------
|
57
|
+
assign clock = origin_inf.aclk;
|
58
|
+
assign rst_n = origin_inf.aresetn;
|
59
|
+
|
60
|
+
assign insert_seed = split_len-1'b1;
|
61
|
+
|
62
|
+
endmodule
|
@@ -0,0 +1,50 @@
|
|
1
|
+
/**********************************************
|
2
|
+
_______________________________________
|
3
|
+
___________ Cook Darwin __________
|
4
|
+
_______________________________________
|
5
|
+
descript:
|
6
|
+
author : Cook.Darwin
|
7
|
+
Version: VERA.0.0
|
8
|
+
creaded:
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
(* axi_stream = "true" *)
|
13
|
+
module axis_width_convert_verb #(
|
14
|
+
parameter IDSIZE = 8,
|
15
|
+
parameter ODSIZE = 16
|
16
|
+
)(
|
17
|
+
axi_stream_inf.slaver in_axis,
|
18
|
+
axi_stream_inf.master out_axis
|
19
|
+
);
|
20
|
+
|
21
|
+
generate
|
22
|
+
if(IDSIZE == ODSIZE)
|
23
|
+
axis_direct_A1 #(
|
24
|
+
.IDSIZE (in_axis.DSIZE),
|
25
|
+
.ODSIZE (out_axis.DSIZE)
|
26
|
+
)axis_direct_A1_inst(
|
27
|
+
/* axi_stream_inf.slaver */ .slaver (in_axis ),
|
28
|
+
/* axi_stream_inf.master */ .master (out_axis )
|
29
|
+
);
|
30
|
+
else
|
31
|
+
width_convert_verb #(
|
32
|
+
.ISIZE (IDSIZE ),
|
33
|
+
.OSIZE (ODSIZE )
|
34
|
+
)width_convert_verb_inst(
|
35
|
+
/* input */ .clock (in_axis.aclk ),
|
36
|
+
/* input */ .rst_n (in_axis.aresetn ),
|
37
|
+
/* input [ISIZE-1:0] */ .wr_data (in_axis.axis_tdata ),
|
38
|
+
/* input */ .wr_vld (in_axis.axis_tvalid ),
|
39
|
+
/* output logic */ .wr_ready (in_axis.axis_tready ),
|
40
|
+
/* input */ .wr_last (in_axis.axis_tlast ),
|
41
|
+
/* input */ .wr_align_last (1'b0), //can be leave 1'b0
|
42
|
+
/* output logic[OSIZE-1:0] */ .rd_data (out_axis.axis_tdata ),
|
43
|
+
/* output logic */ .rd_vld (out_axis.axis_tvalid ),
|
44
|
+
/* input */ .rd_ready (out_axis.axis_tready ),
|
45
|
+
/* output */ .rd_last (out_axis.axis_tlast )
|
46
|
+
);
|
47
|
+
|
48
|
+
endgenerate
|
49
|
+
|
50
|
+
endmodule
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
5
5
|
descript:
|
6
6
|
author : Cook.Darwin
|
7
7
|
Version: VERA.0.0
|
8
|
-
created:
|
8
|
+
created: 2021-04-16 17:01:05 +0800
|
9
9
|
madified:
|
10
10
|
***********************************************/
|
11
11
|
`timescale 1ns/1ps
|
@@ -23,8 +23,8 @@ module data_c_pipe_sync_seam #(
|
|
23
23
|
//==========================================================================
|
24
24
|
//-------- define ----------------------------------------------------------
|
25
25
|
|
26
|
-
data_inf_c #(.DSIZE(in_inf.DSIZE)) in_inf_array[LAT-1:0] (.clock(in_inf.clock),.rst_n(in_inf.rst_n)) ;
|
27
|
-
data_inf_c #(.DSIZE(out_inf.DSIZE)) out_inf_array[LAT-1:0] (.clock(out_inf.clock),.rst_n(out_inf.rst_n)) ;
|
26
|
+
data_inf_c #(.DSIZE(in_inf.DSIZE),.FreqM(in_inf.FreqM)) in_inf_array[LAT-1:0] (.clock(in_inf.clock),.rst_n(in_inf.rst_n)) ;
|
27
|
+
data_inf_c #(.DSIZE(out_inf.DSIZE),.FreqM(out_inf.FreqM)) out_inf_array[LAT-1:0] (.clock(out_inf.clock),.rst_n(out_inf.rst_n)) ;
|
28
28
|
//==========================================================================
|
29
29
|
//-------- instance --------------------------------------------------------
|
30
30
|
|
@@ -48,22 +48,22 @@ for(genvar KK0=0;KK0 < LAT;KK0++)begin
|
|
48
48
|
endgenerate
|
49
49
|
//-------- CLOCKs Total 2 ----------------------
|
50
50
|
//--->> CheckClock <<----------------
|
51
|
-
logic
|
52
|
-
integer
|
53
|
-
ClockSameDomain
|
51
|
+
logic cc_done_9,cc_same_9;
|
52
|
+
integer cc_afreq_9,cc_bfreq_9;
|
53
|
+
ClockSameDomain CheckPClock_inst_9(
|
54
54
|
/* input */ .aclk (in_inf.clock ),
|
55
55
|
/* input */ .bclk (out_inf.clock ),
|
56
|
-
/* output logic */ .done (
|
57
|
-
/* output logic */ .same (
|
58
|
-
/* output integer */ .aFreqK (
|
59
|
-
/* output integer */ .bFreqK (
|
56
|
+
/* output logic */ .done (cc_done_9),
|
57
|
+
/* output logic */ .same (cc_same_9),
|
58
|
+
/* output integer */ .aFreqK (cc_afreq_9),
|
59
|
+
/* output integer */ .bFreqK (cc_bfreq_9)
|
60
60
|
);
|
61
61
|
|
62
62
|
initial begin
|
63
|
-
wait(
|
64
|
-
assert(
|
63
|
+
wait(cc_done_9);
|
64
|
+
assert(cc_same_9)
|
65
65
|
else begin
|
66
|
-
$error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/
|
66
|
+
$error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
|
67
67
|
repeat(10)begin
|
68
68
|
@(posedge in_inf.clock);
|
69
69
|
end
|
@@ -13,6 +13,7 @@ module data_c_sim_master_model #(
|
|
13
13
|
parameter LOOP = "TRUE",
|
14
14
|
parameter RAM_DEPTH = 10000
|
15
15
|
)(
|
16
|
+
input enable,
|
16
17
|
input load_trigger,
|
17
18
|
input [31:0] total_length,
|
18
19
|
input[512*8-1:0] mem_file,
|
@@ -46,24 +47,26 @@ end
|
|
46
47
|
always@(posedge out_inf.clock) begin
|
47
48
|
if(~out_inf.rst_n) index <= 0;
|
48
49
|
else begin
|
49
|
-
if(
|
50
|
-
if(
|
51
|
-
if(
|
52
|
-
|
50
|
+
if(enable)begin
|
51
|
+
if(out_inf.ready) begin
|
52
|
+
if(index >= total_length_lock-1)begin
|
53
|
+
if(LOOP == "TRUE" || LOOP == "ON")begin
|
54
|
+
index <= 0;
|
55
|
+
end else begin
|
56
|
+
index <= total_length_lock-1;
|
57
|
+
disable_coe <= 1'b1;
|
58
|
+
end
|
53
59
|
end else begin
|
54
|
-
index
|
55
|
-
disable_coe <= 1'b1;
|
60
|
+
index <= index + 1;
|
56
61
|
end
|
57
62
|
end else begin
|
58
|
-
index <= index
|
63
|
+
index <= index;
|
59
64
|
end
|
60
|
-
end
|
61
|
-
index <= index;
|
62
|
-
end
|
65
|
+
end
|
63
66
|
end
|
64
67
|
end
|
65
68
|
|
66
69
|
assign out_inf.data = BRAM[index][out_inf.DSIZE-1:0];
|
67
|
-
assign out_inf.valid = BRAM[index][out_inf.DSIZE] && ~disable_coe;
|
70
|
+
assign out_inf.valid = BRAM[index][out_inf.DSIZE] && ~disable_coe && enable;
|
68
71
|
|
69
72
|
endmodule
|
@@ -53,7 +53,7 @@ localparam DIV = ((DSIZE>=37) && (DSIZE<=72)) ? 512 :
|
|
53
53
|
((DSIZE>=5 ) && (DSIZE<=9 )) ? 4096 :
|
54
54
|
((DSIZE>=1 ) && (DSIZE<=4 )) ? 8192 : 8192;
|
55
55
|
|
56
|
-
localparam KNUM = DEPTH/DIV;
|
56
|
+
localparam KNUM = DEPTH/DIV + (DEPTH/DIV == 0);
|
57
57
|
|
58
58
|
// FIFO_DUALCLOCK_MACRO: Dual Clock First-In, First-Out (FIFO) RAM Buffer
|
59
59
|
// Artix-7
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
5
5
|
descript:
|
6
6
|
author : Cook.Darwin
|
7
7
|
Version: VERA.0.0
|
8
|
-
created:
|
8
|
+
created: 2021-04-03 14:03:23 +0800
|
9
9
|
madified:
|
10
10
|
***********************************************/
|
11
11
|
`timescale 1ns/1ps
|
@@ -36,113 +36,114 @@ logic_sim_model #(
|
|
36
36
|
.DSIZE (16 ),
|
37
37
|
.RAM_DEPTH (8 )
|
38
38
|
)split_len_sim_model_inst(
|
39
|
-
/* input */.next_at_negedge_of (origin_inf.axis_tvalid && origin_inf.axis_tready && origin_inf.axis_tlast
|
40
|
-
/* input */.next_at_posedge_of (1'b0
|
41
|
-
/* input */.load_trigger (1'b0
|
42
|
-
/* input */.total_length (8
|
43
|
-
/* input */.mem_file ("/
|
44
|
-
/* output */.data (split_len
|
39
|
+
/* input */.next_at_negedge_of (origin_inf.axis_tvalid && origin_inf.axis_tready && origin_inf.axis_tlast ),
|
40
|
+
/* input */.next_at_posedge_of (1'b0 ),
|
41
|
+
/* input */.load_trigger (1'b0 ),
|
42
|
+
/* input */.total_length (8 ),
|
43
|
+
/* input */.mem_file ("/home/wmy367/work/gem/axi_tdl/lib/tdl/auto_script/tmp/split_len_R674.coe" ),
|
44
|
+
/* output */.data (split_len )
|
45
45
|
);
|
46
46
|
axis_sim_master_model #(
|
47
47
|
.LOOP ("TRUE" ),
|
48
48
|
.RAM_DEPTH (246 )
|
49
49
|
)sim_model_inst_origin_inf(
|
50
|
-
/* input */.
|
51
|
-
/* input */.
|
52
|
-
/* input */.
|
53
|
-
/*
|
50
|
+
/* input */.enable (1'b1 ),
|
51
|
+
/* input */.load_trigger (1'b0 ),
|
52
|
+
/* input */.total_length (246 ),
|
53
|
+
/* input */.mem_file ("/home/wmy367/work/gem/axi_tdl/lib/tdl/auto_script/tmp/coe_origin_inf_R1699.coe" ),
|
54
|
+
/* axi_stream_inf.master */.out_inf (origin_inf )
|
54
55
|
);
|
55
56
|
axis_sim_verify_by_coe #(
|
56
57
|
.RAM_DEPTH (21 ),
|
57
58
|
.VERIFY_KEEP ("OFF" ),
|
58
59
|
.VERIFY_USER ("OFF" )
|
59
60
|
)axis_sim_verify_by_coe_inst_first_inf(
|
60
|
-
/* input */.load_trigger (1'b0
|
61
|
-
/* input */.total_length (21
|
62
|
-
/* input */.mem_file ("/
|
63
|
-
/* axi_stream_inf.mirror */.mirror_inf (first_inf
|
61
|
+
/* input */.load_trigger (1'b0 ),
|
62
|
+
/* input */.total_length (21 ),
|
63
|
+
/* input */.mem_file ("/home/wmy367/work/gem/axi_tdl/lib/tdl/auto_script/tmp/first_inf_R1282.coe" ),
|
64
|
+
/* axi_stream_inf.mirror */.mirror_inf (first_inf )
|
64
65
|
);
|
65
66
|
axis_sim_verify_by_coe #(
|
66
67
|
.RAM_DEPTH (113 ),
|
67
68
|
.VERIFY_KEEP ("OFF" ),
|
68
69
|
.VERIFY_USER ("OFF" )
|
69
70
|
)axis_sim_verify_by_coe_inst_end_inf(
|
70
|
-
/* input */.load_trigger (1'b0
|
71
|
-
/* input */.total_length (113
|
72
|
-
/* input */.mem_file ("/
|
73
|
-
/* axi_stream_inf.mirror */.mirror_inf (end_inf
|
71
|
+
/* input */.load_trigger (1'b0 ),
|
72
|
+
/* input */.total_length (113 ),
|
73
|
+
/* input */.mem_file ("/home/wmy367/work/gem/axi_tdl/lib/tdl/auto_script/tmp/end_inf_R1315.coe" ),
|
74
|
+
/* axi_stream_inf.mirror */.mirror_inf (end_inf )
|
74
75
|
);
|
75
76
|
//==========================================================================
|
76
77
|
//-------- expression ------------------------------------------------------
|
77
78
|
initial begin
|
78
|
-
|
79
|
-
|
80
|
-
|
79
|
+
clock = 1'b0;
|
80
|
+
#(100ns);
|
81
|
+
forever begin #(5.0ns);clock = ~clock;end;
|
81
82
|
end
|
82
83
|
|
83
84
|
initial begin
|
84
|
-
|
85
|
-
|
86
|
-
|
85
|
+
rst_n = 1'b0;
|
86
|
+
#(200ns);
|
87
|
+
rst_n = ~rst_n;
|
87
88
|
end
|
88
89
|
|
89
90
|
initial begin
|
90
|
-
|
91
|
-
|
92
|
-
|
93
|
-
|
91
|
+
first_inf_rdy_percetage_index = 0;
|
92
|
+
first_inf_rdy_percetage[0] = 50;
|
93
|
+
first_inf_rdy_percetage[1] = 100;
|
94
|
+
first_inf_rdy_percetage[2] = 30;
|
94
95
|
end
|
95
96
|
|
96
97
|
always@(posedge clock) begin
|
97
98
|
if(first_inf.axis_tvalid && first_inf.axis_tready && first_inf.axis_tlast)begin
|
98
|
-
if(
|
99
|
-
|
99
|
+
if(first_inf_rdy_percetage_index>=(3-1))begin
|
100
|
+
first_inf_rdy_percetage_index <= 0;
|
100
101
|
end
|
101
102
|
else begin
|
102
|
-
|
103
|
+
first_inf_rdy_percetage_index <= (first_inf_rdy_percetage_index+1'b1);
|
103
104
|
end
|
104
105
|
end
|
105
106
|
else begin
|
106
|
-
|
107
|
+
first_inf_rdy_percetage_index <= first_inf_rdy_percetage_index;
|
107
108
|
end
|
108
109
|
end
|
109
110
|
|
110
111
|
always@(posedge clock) begin
|
111
112
|
if(~rst_n)begin
|
112
|
-
|
113
|
+
first_inf.axis_tready <= 1'b0;
|
113
114
|
end
|
114
115
|
else begin
|
115
|
-
|
116
|
+
first_inf.axis_tready <= ($urandom_range(0,99) <= first_inf_rdy_percetage[first_inf_rdy_percetage_index]);
|
116
117
|
end
|
117
118
|
end
|
118
119
|
|
119
120
|
initial begin
|
120
|
-
|
121
|
-
|
122
|
-
|
123
|
-
|
121
|
+
end_inf_rdy_percetage_index = 0;
|
122
|
+
end_inf_rdy_percetage[0] = 100;
|
123
|
+
end_inf_rdy_percetage[1] = 50;
|
124
|
+
end_inf_rdy_percetage[2] = 100;
|
124
125
|
end
|
125
126
|
|
126
127
|
always@(posedge clock) begin
|
127
128
|
if(end_inf.axis_tvalid && end_inf.axis_tready && end_inf.axis_tlast)begin
|
128
|
-
if(
|
129
|
-
|
129
|
+
if(end_inf_rdy_percetage_index>=(3-1))begin
|
130
|
+
end_inf_rdy_percetage_index <= 0;
|
130
131
|
end
|
131
132
|
else begin
|
132
|
-
|
133
|
+
end_inf_rdy_percetage_index <= (end_inf_rdy_percetage_index+1'b1);
|
133
134
|
end
|
134
135
|
end
|
135
136
|
else begin
|
136
|
-
|
137
|
+
end_inf_rdy_percetage_index <= end_inf_rdy_percetage_index;
|
137
138
|
end
|
138
139
|
end
|
139
140
|
|
140
141
|
always@(posedge clock) begin
|
141
142
|
if(~rst_n)begin
|
142
|
-
|
143
|
+
end_inf.axis_tready <= 1'b0;
|
143
144
|
end
|
144
145
|
else begin
|
145
|
-
|
146
|
+
end_inf.axis_tready <= ($urandom_range(0,99) <= end_inf_rdy_percetage[end_inf_rdy_percetage_index]);
|
146
147
|
end
|
147
148
|
end
|
148
149
|
|