axi_tdl 0.0.19 → 0.1.7

data/lib/tdl/sdlmodule/top_module.rb

@@ -154,17 +154,16 @@ endmodule\n"
         end
 
         ## 生成 itgt下的子模块文件
-        # gen_children_modules
-        @_itgt_collect_.each do |itgt|
-            itgt.gen_children_modules()
-        end
+        # @_itgt_collect_.each do |itgt|
+        #     itgt.gen_children_modules()
+        # end
 
-        if implicit_itgt_collect
-            ## 执行 itegration_verb 里面的silence
-            implicit_itgt_collect.each do |itgt|
-                itgt.gen_children_modules()
-            end
-        end
+        # if implicit_itgt_collect
+        #     ## 执行 itegration_verb 里面的silence
+        #     implicit_itgt_collect.each do |itgt|
+        #         itgt.gen_children_modules()
+        #     end
+        # end
 
     end
 
@@ -341,6 +340,7 @@ endmodule\n"
     end
 
     define_global("sim",nil)
+    define_global("itgt_implicit_reject",nil)
 
 end
 ## 添加 itegration verb
@@ -438,6 +438,9 @@ class TopModule
                 SdlModule.gen_dev_wave_tcl File.join(sdlm.vcs_path,"dve.tcl")
             end
             sdlm.create_xdc
+
+            ## 全局contain_hdl 引入到 TopModule
+            sdlm.contain_hdl(*$__contain_hdl__)
         else 
             sdlm.origin_sv = true 
         end

data/lib/tdl/tdl.rb

@@ -138,7 +138,7 @@ require_relative "./exlib/logic_verify.rb"
 $argvs_hash = {}
 $argvs_hash = Parser.parse($TdlARGV || ARGV) 
 TopModule.sim = $argvs_hash[:sim]
-
+TopModule.itgt_implicit_reject = $argvs_hash[:itgt_implicit_reject]
 class Tdl
 
     def self.comment(c="-",info="_____")
@@ -271,16 +271,6 @@ class Tdl
         puts(pagination("SUMMARY"))
         puts "#{TopModule.sim ? 'SIM' : 'SYNTH'} RUN SPEND #{Time.now - $__start_time__} sec @ TIME : #{Time.now}"
 
-        ## ----------- 
-        # TopModule.current.ref_modules.uniq.each do |e| 
-        #     unless  e.is_a? ClassHDL::ClearSdlModule
-        #         puts "#{e.real_sv_path}: #{e.module_name}"
-        #     end
-        # end
-        ## ===========
-        # File.open("/home/myw357/work/FPGA/mammo_tcp_20210315/tmp.tcl", "w") do |f|
-        #     f.puts SdlModule.call_module('test_mac_1g_verb').gen_dev_wave_tcl
-        # end
     end
 
 end

data/lib/tdl/tdlerror/tdlerror.rb

@@ -4,6 +4,6 @@ class TdlError < ScriptError
         head_str0 = String.new("\n+_____________________________________________+\n")
         head_str1 = "\n|----------------TDL ERROR--------------------|\n"
         end_str0  = "\n+================TDL ERROR====================+\n"
-        super(head_str0.concat(head_str1).concat(arge.to_s[0,255]+end_str0))
+        super(head_str0.concat(head_str1).concat(arge.to_s[0,255]).concat(end_str0))
     end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: axi_tdl
 version: !ruby/object:Gem::Version
-  version: 0.0.19
+  version: 0.1.7
 platform: ruby
 authors:
 - Cook.Darwin
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2021-03-20 00:00:00.000000000 Z
+date: 2021-05-04 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rake
@@ -64,7 +64,6 @@ files:
 - ".github/workflows/ruby.yml"
 - ".gitignore"
 - ".travis.yml"
-- CODE_OF_CONDUCT.md
 - Gemfile
 - LICENSE
 - README.EN.md
@@ -209,6 +208,7 @@ files:
 - lib/axi/AXI_stream/axi_stream_partition_A1.sv
 - lib/axi/AXI_stream/axi_stream_planer.sv
 - lib/axi/AXI_stream/axi_stream_split_channel.rb
+- lib/axi/AXI_stream/axi_stream_split_channel.sv
 - lib/axi/AXI_stream/axi_streams_combin.sv
 - lib/axi/AXI_stream/axi_streams_combin_A1.sv
 - lib/axi/AXI_stream/axi_streams_scaler.sv
@@ -230,8 +230,10 @@ files:
 - lib/axi/AXI_stream/axis_head_cut.sv
 - lib/axi/AXI_stream/axis_head_cut_verb.sv
 - lib/axi/AXI_stream/axis_head_cut_verc.rb
+- lib/axi/AXI_stream/axis_head_cut_verc.sv
 - lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv
 - lib/axi/AXI_stream/axis_insert_copy.rb
+- lib/axi/AXI_stream/axis_insert_copy.sv
 - lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv
 - lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv
 - lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv
@@ -240,18 +242,20 @@ files:
 - lib/axi/AXI_stream/axis_length_split.sv
 - lib/axi/AXI_stream/axis_length_split_with_addr.sv
 - lib/axi/AXI_stream/axis_length_split_with_user.sv
-- lib/axi/AXI_stream/axis_length_split_writh_user.sv
 - lib/axi/AXI_stream/axis_link_trigger.sv
 - lib/axi/AXI_stream/axis_master_empty.sv
 - lib/axi/AXI_stream/axis_mirror_to_master.sv
 - lib/axi/AXI_stream/axis_mirrors.sv
 - lib/axi/AXI_stream/axis_orthogonal.sv
 - lib/axi/AXI_stream/axis_pipe_sync_seam.rb
+- lib/axi/AXI_stream/axis_pipe_sync_seam.sv
 - lib/axi/AXI_stream/axis_ram_buffer.sv
 - lib/axi/AXI_stream/axis_rom_contect.rb
 - lib/axi/AXI_stream/axis_rom_contect.sv
 - lib/axi/AXI_stream/axis_rom_contect_sim.rb
+- lib/axi/AXI_stream/axis_rom_contect_sim.sv
 - lib/axi/AXI_stream/axis_sim_master_model.rb
+- lib/axi/AXI_stream/axis_sim_master_model.sv
 - lib/axi/AXI_stream/axis_sim_slaver_model.rb
 - lib/axi/AXI_stream/axis_sim_verify_by_coe.sv
 - lib/axi/AXI_stream/axis_slaver_empty.sv
@@ -259,6 +263,7 @@ files:
 - lib/axi/AXI_stream/axis_slaver_pipe_A1.sv
 - lib/axi/AXI_stream/axis_slaver_vector_empty.sv
 - lib/axi/AXI_stream/axis_split_channel_verb.rb
+- lib/axi/AXI_stream/axis_split_channel_verb.sv
 - lib/axi/AXI_stream/axis_to_axi4_or_lite.rb
 - lib/axi/AXI_stream/axis_to_axi4_or_lite.sv
 - lib/axi/AXI_stream/axis_to_data_inf.sv
@@ -281,6 +286,7 @@ files:
 - lib/axi/AXI_stream/data_width/axis_width_combin.sv
 - lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv
 - lib/axi/AXI_stream/data_width/axis_width_convert.sv
+- lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv
 - lib/axi/AXI_stream/data_width/axis_width_destruct.sv
 - lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv
 - lib/axi/AXI_stream/ex_status/axis_ex_status.sv
@@ -547,6 +553,34 @@ files:
 - lib/axi/video_interface/video_interface.sv
 - lib/axi_tdl.rb
 - lib/axi_tdl/version.rb
+- lib/public_atom_module/CheckPClock.sv
+- lib/public_atom_module/LICENSE.md
+- lib/public_atom_module/altera_xilinx_always_block_sw.rb
+- lib/public_atom_module/bits_decode.sv
+- lib/public_atom_module/bits_decode_verb.sv
+- lib/public_atom_module/bits_decode_verb_sdl.rb
+- lib/public_atom_module/broaden.v
+- lib/public_atom_module/broaden_and_cross_clk.v
+- lib/public_atom_module/ceiling.v
+- lib/public_atom_module/ceiling_A1.v
+- lib/public_atom_module/clock_rst.sv
+- lib/public_atom_module/cross_clk_sync.v
+- lib/public_atom_module/edge_generator.v
+- lib/public_atom_module/flooring.v
+- lib/public_atom_module/latch_data.v
+- lib/public_atom_module/latency.v
+- lib/public_atom_module/latency_dynamic.v
+- lib/public_atom_module/latency_long.v
+- lib/public_atom_module/latency_verb.v
+- lib/public_atom_module/once_event.sv
+- lib/public_atom_module/pipe_reg.v
+- lib/public_atom_module/pipe_reg_2write_ports.v
+- lib/public_atom_module/sim/clock_rst_verb.sv
+- lib/public_atom_module/sim/clock_rst_verc.sv
+- lib/public_atom_module/sim/latency_long_tb.sv
+- lib/public_atom_module/sim/latency_long_tb.sv.bak
+- lib/public_atom_module/sim_system_pkg.sv
+- lib/public_atom_module/synth_system_pkg.sv
 - lib/spec/spec_helper.rb
 - lib/tdl/LICENSE
 - lib/tdl/Logic/Logic.tar.gz
@@ -1120,11 +1154,13 @@ files:
 - lib/tdl/examples/11_test_unit/exp_test_unit.rb
 - lib/tdl/examples/11_test_unit/exp_test_unit.sv
 - lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc
+- lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv
 - lib/tdl/examples/11_test_unit/modules/sub_md0.rb
 - lib/tdl/examples/11_test_unit/modules/sub_md0.sv
 - lib/tdl/examples/11_test_unit/modules/sub_md1.rb
 - lib/tdl/examples/11_test_unit/modules/sub_md1.sv
 - lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv
+- lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv
 - lib/tdl/examples/11_test_unit/tu0.sv
 - lib/tdl/examples/11_test_unit/tu1.sv
 - lib/tdl/examples/1_define_module/example1.rb
@@ -1196,22 +1232,27 @@ files:
 - lib/tdl/examples/8_top_module/example.rb
 - lib/tdl/examples/8_top_module/pins.yml
 - lib/tdl/examples/8_top_module/tb_test_top.sv
+- lib/tdl/examples/8_top_module/tb_test_top_sim.sv
 - lib/tdl/examples/8_top_module/test_top.sv
 - lib/tdl/examples/8_top_module/test_top_constraints.xdc
+- lib/tdl/examples/8_top_module/test_top_sim.sv
 - lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv
 - lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb
 - lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb
 - lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb
 - lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb
 - lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv
+- lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv
 - lib/tdl/examples/9_itegration/dve.tcl
 - lib/tdl/examples/9_itegration/pins.yml
 - lib/tdl/examples/9_itegration/tb_test_top.sv
 - lib/tdl/examples/9_itegration/tb_test_tttop.sv
+- lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv
 - lib/tdl/examples/9_itegration/test_top.sv
 - lib/tdl/examples/9_itegration/test_top_constraints.xdc
 - lib/tdl/examples/9_itegration/test_tttop.sv
 - lib/tdl/examples/9_itegration/test_tttop_constraints.xdc
+- lib/tdl/examples/9_itegration/test_tttop_sim.sv
 - lib/tdl/examples/9_itegration/top.rb
 - lib/tdl/examples/readme.md
 - lib/tdl/exlib/axis_eth_ex.rb
@@ -1290,7 +1331,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.0.3
+rubygems_version: 3.0.3.1
 signing_key: 
 specification_version: 4
 summary: Axi 是一个轻量级的AXI4库. Tdl 是一种硬件构造语言

data/CODE_OF_CONDUCT.md

@@ -1,74 +0,0 @@
-# Contributor Covenant Code of Conduct
-
-## Our Pledge
-
-In the interest of fostering an open and welcoming environment, we as
-contributors and maintainers pledge to making participation in our project and
-our community a harassment-free experience for everyone, regardless of age, body
-size, disability, ethnicity, gender identity and expression, level of experience,
-nationality, personal appearance, race, religion, or sexual identity and
-orientation.
-
-## Our Standards
-
-Examples of behavior that contributes to creating a positive environment
-include:
-
-* Using welcoming and inclusive language
-* Being respectful of differing viewpoints and experiences
-* Gracefully accepting constructive criticism
-* Focusing on what is best for the community
-* Showing empathy towards other community members
-
-Examples of unacceptable behavior by participants include:
-
-* The use of sexualized language or imagery and unwelcome sexual attention or
-advances
-* Trolling, insulting/derogatory comments, and personal or political attacks
-* Public or private harassment
-* Publishing others' private information, such as a physical or electronic
-  address, without explicit permission
-* Other conduct which could reasonably be considered inappropriate in a
-  professional setting
-
-## Our Responsibilities
-
-Project maintainers are responsible for clarifying the standards of acceptable
-behavior and are expected to take appropriate and fair corrective action in
-response to any instances of unacceptable behavior.
-
-Project maintainers have the right and responsibility to remove, edit, or
-reject comments, commits, code, wiki edits, issues, and other contributions
-that are not aligned to this Code of Conduct, or to ban temporarily or
-permanently any contributor for other behaviors that they deem inappropriate,
-threatening, offensive, or harmful.
-
-## Scope
-
-This Code of Conduct applies both within project spaces and in public spaces
-when an individual is representing the project or its community. Examples of
-representing a project or community include using an official project e-mail
-address, posting via an official social media account, or acting as an appointed
-representative at an online or offline event. Representation of a project may be
-further defined and clarified by project maintainers.
-
-## Enforcement
-
-Instances of abusive, harassing, or otherwise unacceptable behavior may be
-reported by contacting the project team at cook_darwin@hotmail.com. All
-complaints will be reviewed and investigated and will result in a response that
-is deemed necessary and appropriate to the circumstances. The project team is
-obligated to maintain confidentiality with regard to the reporter of an incident.
-Further details of specific enforcement policies may be posted separately.
-
-Project maintainers who do not follow or enforce the Code of Conduct in good
-faith may face temporary or permanent repercussions as determined by other
-members of the project's leadership.
-
-## Attribution
-
-This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4,
-available at [http://contributor-covenant.org/version/1/4][version]
-
-[homepage]: http://contributor-covenant.org
-[version]: http://contributor-covenant.org/version/1/4/

data/lib/axi/AXI_stream/axis_length_split_writh_user.sv

@@ -1,87 +0,0 @@
-/**********************************************
-______________   ______________
-______________ X ______________
-______________  ______________
-
-descript:
-author : Cook.Darwin
-Version: VERA.0.X 2018/1/25 
-    use axis_user to detect last
-creaded: 2017/5/19 
-madified:
-***********************************************/
-`timescale 1ns/1ps
-(* axi_stream = "true" *)
-module axis_length_split_with_user (
-    input [31:0]           length,      ////[0] mean 0 len
-    (* up_stream = "true" *)
-    axi_stream_inf.slaver  axis_in,
-    (* down_stream = "true" *)
-    axi_stream_inf.master  axis_out
-);
-
-wire    clock,rst_n,clken;
-
-assign  clock   = axis_in.aclk;
-assign  rst_n   = axis_in.aresetn;
-assign  clken   = axis_in.aclken;
-
-axi_stream_inf #(.DSIZE(axis_in.DSIZE)) axis_pre (.aclk(clock),.aresetn(rst_n),.aclken(clken));
-
-
-logic [31:0]        cnt;
-
-always@(posedge clock,negedge rst_n)
-    if(~rst_n)  cnt     <= '0;
-    else begin
-        if(axis_in.axis_tvalid  && axis_in.axis_tready && axis_in.axis_tlast)
-                cnt     <= '0;
-        else if(axis_in.axis_tvalid  && axis_in.axis_tready && (cnt >= (length-1)))
-                cnt     <= '0;
-        else if(axis_in.axis_tvalid  && axis_in.axis_tready)
-                cnt     <= cnt + 1'b1;
-        else    cnt     <= cnt;
-    end
-
-logic   new_last;
-
-always@(posedge clock,negedge rst_n)
-    if(~rst_n)  new_last    <= 1'b0;
-    else begin
-        if(axis_in.axis_tvalid  && axis_in.axis_tready && (new_last||axis_in.axis_tlast))
-                new_last    <= 1'b0;
-        else if(axis_in.axis_tvalid  && axis_in.axis_tready && cnt==(length-2))
-                new_last    <= 1'b1;
-        else    new_last    <= new_last;
-    end
-
-// logic   mark_tail;
-//
-// always@(posedge clock,negedge rst_n)
-//     if(~rst_n)  mark_tail   <= 1'b0;
-//     else begin
-//         if(axis_in.axis_tvalid  && axis_in.axis_tready && axis_in.axis_tlast)
-//                 mark_tail   <= 1'b0;
-//         else if(axis_in.axis_tvalid  && axis_in.axis_tready && axis_in.axis_tcnt==(length-1))
-//                 mark_tail   <= 1'b1;
-//         else    mark_tail   <= mark_tail;
-//     end
-
-assign axis_pre.axis_tvalid = axis_in.axis_tvalid;
-assign axis_pre.axis_tdata  = axis_in.axis_tdata;
-assign axis_pre.axis_tlast  = new_last || axis_in.axis_tlast;
-assign axis_pre.axis_tkeep  = axis_in.axis_tkeep;
-// assign axis_pre.axis_tuser  = axis_in.axis_tuser;
-assign axis_pre.axis_tuser  = axis_in.axis_tlast;
-assign axis_in.axis_tready  = axis_pre.axis_tready;
-
-axis_connect_pipe axis_connect_pipe_inst(
-/*  axi_stream_inf.slaver  */  .axis_in     (axis_pre   ),
-/*  axi_stream_inf.master  */  .axis_out    (axis_out   )
-);
-
-int out_cnt;
-
-assign out_cnt = axis_out.axis_tcnt;
-
-endmodule