axi_tdl 0.0.19 → 0.1.7

data/lib/axi/AXI_stream/axis_head_cut_verc.sv

@@ -0,0 +1,242 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERC.0.0
+created: XXXX.XX.XX
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module axis_head_cut_verc #(
+    parameter  BYTE_BITS = 8,
+    parameter  DX        = (origin_inf.DSIZE / BYTE_BITS)
+)(
+    input [9:0]             bytes,
+    axi_stream_inf.slaver   origin_inf,
+    axi_stream_inf.master   out_inf
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+logic  clock;
+logic  rst_n;
+logic [18-1:0]  origin_sync_info[3-1:0] ;
+logic [18-1:0]  origin_sync_info_out[3-1:0] ;
+logic [10-1:0]  bytes_Q ;
+logic [10-1:0]  bytes_QQ ;
+logic [4-1:0]  bytes_x ;
+logic [4-1:0]  bytes_x_Q ;
+logic [4-1:0]  bytes_x_tmp ;
+logic [4-1:0]  bytes_x_sub_nDx ;
+logic [4-1:0]  bytes_x_sub_nDx_tmp ;
+logic [2-1:0]  route_addr ;
+logic [2-1:0]  route_addr_tmp ;
+logic fifo_wr_en;
+logic [4-1:0]  int_cut_len ;
+logic [4-1:0]  shift_sel_pre ;
+logic fifo_wr_en_lat;
+logic [4-1:0]  shift_sel ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_post (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) sub_origin_inf [2:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_cut_mix (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss_E0 (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss_E0_CH (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(out_inf.DSIZE),.FreqM(out_inf.FreqM),.USIZE(1)) out_inf_branchR655 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+axis_pipe_sync_seam #(
+    .LAT   (3  ),
+    .DSIZE (18 )
+)axis_pipe_sync_seam_inst(
+/* input                 */.in_datas  (origin_sync_info     ),
+/* output                */.out_datas (origin_sync_info_out ),
+/* axi_stream_inf.slaver */.in_inf    (origin_inf           ),
+/* axi_stream_inf.master */.out_inf   (origin_inf_post      )
+);
+axi_stream_interconnect_S2M #(
+    .NUM   (3 )
+)axi_stream_interconnect_S2M_inst(
+/* input                 */.addr (route_addr      ),
+/* axi_stream_inf.slaver */.s00  (origin_inf_post ),
+/* axi_stream_inf.master */.m00  (sub_origin_inf  )
+);
+common_fifo #(
+    .DEPTH (4 ),
+    .DSIZE (4 )
+)common_fifo_head_bytesx_inst(
+/* input  */.clock (clock                                                                                            ),
+/* input  */.rst_n (rst_n                                                                                            ),
+/* input  */.wdata (bytes_x                                                                                          ),
+/* input  */.wr_en (fifo_wr_en && (bytes_x!= '0)                                                                     ),
+/* output */.rdata (int_cut_len                                                                                      ),
+/* input  */.rd_en ((sub_origin_inf[1].axis_tvalid && sub_origin_inf[1].axis_tready && sub_origin_inf[1].axis_tlast) ),
+/* output */.count (/*unused */                                                                                      ),
+/* output */.empty (/*unused */                                                                                      ),
+/* output */.full  (/*unused */                                                                                      )
+);
+axis_head_cut_verb axis_head_cut_verb_inst(
+/* input                 */.length   ({12'd0,int_cut_len} ),
+/* axi_stream_inf.slaver */.axis_in  (sub_origin_inf[1]   ),
+/* axi_stream_inf.master */.axis_out (origin_inf_ss       )
+);
+axis_append_A1 #(
+    .MODE            ("END"         ),
+    .DSIZE           (out_inf.DSIZE ),
+    .HEAD_FIELD_LEN  (1             ),
+    .HEAD_FIELD_NAME ("HEAD Filed"  ),
+    .END_FIELD_LEN   (1             ),
+    .END_FIELD_NAME  ("END Filed"   )
+)axis_append_A1_inst(
+/* input                 */.enable     (1'b1               ),
+/* input                 */.head_value (/*unused */        ),
+/* input                 */.end_value  ('0                 ),
+/* axi_stream_inf.slaver */.origin_in  (origin_inf_cut_mix ),
+/* axi_stream_inf.master */.append_out (origin_inf_ss_E0   )
+);
+common_fifo #(
+    .DEPTH (4 ),
+    .DSIZE (4 )
+)common_fifo_head_nDx_inst(
+/* input  */.clock (clock                                                                                       ),
+/* input  */.rst_n (rst_n                                                                                       ),
+/* input  */.wdata (shift_sel_pre                                                                               ),
+/* input  */.wr_en (fifo_wr_en_lat                                                                              ),
+/* output */.rdata (shift_sel                                                                                   ),
+/* input  */.rd_en (origin_inf_ss_E0.axis_tvalid && origin_inf_ss_E0.axis_tready && origin_inf_ss_E0.axis_tlast ),
+/* output */.count (/*unused */                                                                                 ),
+/* output */.empty (/*unused */                                                                                 ),
+/* output */.full  (/*unused */                                                                                 )
+);
+axis_connect_pipe_right_shift_verb #(
+    .SHIFT_BYTE_BIT (BYTE_BITS ),
+    .SNUM           (DX        )
+)axis_connect_pipe_right_shift_verb_inst(
+/* input                 */.shift_sel (shift_sel           ),
+/* axi_stream_inf.slaver */.axis_in   (origin_inf_ss_E0    ),
+/* axi_stream_inf.master */.axis_out  (origin_inf_ss_E0_CH )
+);
+axis_head_cut_verb last_cut_inst(
+/* input                 */.length   (16'd1               ),
+/* axi_stream_inf.slaver */.axis_in  (origin_inf_ss_E0_CH ),
+/* axi_stream_inf.master */.axis_out (out_inf_branchR655  )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+
+axi_stream_inf #(.DSIZE(out_inf.DSIZE))  sub_out_inf[2-1:0](.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1));
+
+
+axis_direct  axis_direct_out_inf_inst0 (
+/*  axi_stream_inf.slaver*/ .slaver (sub_origin_inf[0]),
+/*  axi_stream_inf.master*/ .master (sub_out_inf[0])
+);
+
+axis_direct  axis_direct_out_inf_inst1 (
+/*  axi_stream_inf.slaver*/ .slaver (out_inf_branchR655),
+/*  axi_stream_inf.master*/ .master (sub_out_inf[1])
+);
+
+
+axi_stream_inf #(.DSIZE(origin_inf_cut_mix.DSIZE))  sub_origin_inf_cut_mix[2-1:0](.aclk(origin_inf_cut_mix.aclk),.aresetn(origin_inf_cut_mix.aresetn),.aclken(1'b1));
+
+
+axis_direct  axis_direct_origin_inf_cut_mix_inst0 (
+/*  axi_stream_inf.slaver*/ .slaver (origin_inf_ss),
+/*  axi_stream_inf.master*/ .master (sub_origin_inf_cut_mix[0])
+);
+
+axis_direct  axis_direct_origin_inf_cut_mix_inst1 (
+/*  axi_stream_inf.slaver*/ .slaver (sub_origin_inf[2]),
+/*  axi_stream_inf.master*/ .master (sub_origin_inf_cut_mix[1])
+);
+initial begin
+    assert(DX<17)else begin
+        $error("param.DX<%0d> !< 17",DX);
+        $stop;
+    end
+end
+
+assign clock = origin_inf.aclk;
+assign rst_n = origin_inf.aresetn;
+
+always_comb begin 
+    bytes_x_tmp = '0;
+    for(integer gvar_cc_1=0;gvar_cc_1<10;gvar_cc_1=gvar_cc_1+1)begin
+        if(bytes<DX*(10-gvar_cc_1))begin
+            bytes_x_tmp = (10-1)-gvar_cc_1;
+        end
+    end
+end
+
+assign origin_sync_info[0] = {bytes_x_tmp,bytes_x_tmp,bytes};
+assign {bytes_x,bytes_Q} = {origin_sync_info_out[0][13:10],origin_sync_info_out[0][9:0]};
+assign bytes_x_sub_nDx_tmp = bytes_Q-(bytes_x*DX);
+assign origin_sync_info[1] = {bytes_x_sub_nDx_tmp,bytes_x,bytes_Q};
+assign {bytes_x_sub_nDx,bytes_x_Q,bytes_QQ} = {origin_sync_info_out[1][17:14],origin_sync_info_out[1][13:10],origin_sync_info_out[1][9:0]};
+assign origin_sync_info[2] = {10'd0,route_addr_tmp};
+assign route_addr = origin_sync_info_out[2][1:0];
+
+always_comb begin 
+    if(bytes_QQ=='0)begin
+        route_addr_tmp = 2'd0;
+    end
+    else if(bytes_x_Q=='0)begin
+        route_addr_tmp = 2'd2;
+    end
+    else if(bytes_x_sub_nDx=='0)begin
+        route_addr_tmp = 2'd1;
+    end
+    else begin
+        route_addr_tmp = 2'd1;
+    end
+end
+
+always_ff@(posedge clock,negedge rst_n) begin 
+    if(~rst_n)begin
+        fifo_wr_en <= 1'b0;
+    end
+    else begin
+        fifo_wr_en <= (origin_inf.axis_tcnt=='0&&origin_inf.axis_tvalid && origin_inf.axis_tready);
+    end
+end
+
+assign shift_sel_pre = DX-bytes_x_sub_nDx;
+
+
+//----->> fifo_wr_en LAST DELAY <<------------------
+latency #(
+    .LAT    (2),
+    .DSIZE  (1)
+)fifo_wr_en_lat2_inst(
+    clock,
+    rst_n,
+    fifo_wr_en,
+    fifo_wr_en_lat
+);
+//-----<< fifo_wr_en LAST DELAY >>------------------
+
+
+axi_stream_interconnect_M2S_A1 #(
+//axi_stream_interconnect_M2S_noaddr #(
+    .NUM        (2)
+ //   .DSIZE      (out_inf.DSIZE)
+)out_inf_M2S_noaddr_inst(
+/*  axi_stream_inf.slaver */ .s00      (sub_out_inf ), //[NUM-1:0],
+/*  axi_stream_inf.master */ .m00      (out_inf) //
+);
+
+
+axi_stream_interconnect_M2S_A1 #(
+//axi_stream_interconnect_M2S_noaddr #(
+    .NUM        (2)
+ //   .DSIZE      (origin_inf.DSIZE)
+)origin_inf_cut_mix_M2S_noaddr_inst(
+/*  axi_stream_inf.slaver */ .s00      (sub_origin_inf_cut_mix ), //[NUM-1:0],
+/*  axi_stream_inf.master */ .m00      (origin_inf_cut_mix) //
+);
+
+endmodule

data/lib/axi/AXI_stream/axis_insert_copy.sv

@@ -0,0 +1,79 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: 2021-04-16 17:01:06 +0800
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module axis_insert_copy (
+    input [15:0]            insert_seed,
+    input [7:0]             insert_len,
+    axi_stream_inf.slaver   in_inf,
+    axi_stream_inf.master   out_inf
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+logic  clock;
+logic  rst_n;
+logic insert_tri;
+axi_stream_inf #(.DSIZE(in_inf.DSIZE),.FreqM(in_inf.FreqM),.USIZE(1)) in_inf_valve (.aclk(in_inf.aclk),.aresetn(in_inf.aresetn),.aclken(1'b1)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+axis_connect_pipe axis_connect_pipe_inst(
+/* axi_stream_inf.slaver */.axis_in  (in_inf_valve ),
+/* axi_stream_inf.master */.axis_out (out_inf      )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+assign clock = in_inf.aclk;
+assign rst_n = in_inf.aresetn;
+
+assign in_inf_valve.axis_tdata = in_inf.axis_tdata;
+assign in_inf_valve.axis_tvalid = in_inf.axis_tvalid|insert_tri;
+assign in_inf_valve.axis_tuser = in_inf.axis_tuser;
+assign in_inf_valve.axis_tkeep = in_inf.axis_tkeep;
+assign in_inf.axis_tready = in_inf_valve.axis_tready&~insert_tri;
+assign in_inf_valve.axis_tlast = in_inf.axis_tlast&~insert_tri;
+
+always_ff@(posedge clock,negedge rst_n) begin 
+    if(~rst_n)begin
+        insert_tri <= 1'b0;
+    end
+    else begin
+        if(insert_seed=='0)begin
+            if(in_inf.axis_tvalid && in_inf.axis_tready && in_inf.axis_tlast)begin
+                insert_tri <= 1'b1;
+            end
+            else if(in_inf_valve.axis_tvalid && in_inf_valve.axis_tready)begin
+                insert_tri <= (in_inf_valve.axis_tcnt<(insert_len-1'b1));
+            end
+            else if(in_inf_valve.axis_tcnt=='0&&~(in_inf.axis_tvalid && in_inf.axis_tready))begin
+                insert_tri <= 1'b1;
+            end
+            else begin
+                insert_tri <= insert_tri;
+            end
+        end
+        else begin
+            if(in_inf_valve.axis_tvalid && in_inf_valve.axis_tready)begin
+                if(in_inf_valve.axis_tcnt>=(insert_seed-1'b1) &&(in_inf_valve.axis_tcnt<((insert_seed+insert_len)-1'b1))&&~in_inf.axis_tlast)begin
+                    insert_tri <= 1'b1;
+                end
+                else begin
+                    insert_tri <= 1'b0;
+                end
+            end
+            else begin
+                insert_tri <= insert_tri;
+            end
+        end
+    end
+end
+
+endmodule

data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv

@@ -0,0 +1,48 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: 2021-04-16 17:01:05 +0800
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module axis_pipe_sync_seam #(
+    parameter  LAT   = 4,
+    parameter  DSIZE = 32
+)(
+    input [DSIZE-1:0]       in_datas  [LAT-1:0],
+    output [DSIZE-1:0]      out_datas [LAT-1:0],
+    axi_stream_inf.slaver   in_inf,
+    axi_stream_inf.master   out_inf
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+
+data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE),.FreqM(1.0)) data_in_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
+data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE),.FreqM(data_in_inf.FreqM)) data_out_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+data_c_pipe_sync_seam #(
+    .LAT   (LAT   ),
+    .DSIZE (DSIZE )
+)data_c_pipe_sync_seam_inst(
+/* input             */.in_datas  (in_datas     ),
+/* output            */.out_datas (out_datas    ),
+/* data_inf_c.slaver */.in_inf    (data_in_inf  ),
+/* data_inf_c.master */.out_inf   (data_out_inf )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+assign data_in_inf.data = {>>{in_inf.axis_tuser,in_inf.axis_tkeep,in_inf.axis_tlast,in_inf.axis_tdata}};
+assign data_in_inf.valid = in_inf.axis_tvalid;
+assign in_inf.axis_tready = data_in_inf.ready;
+assign {out_inf.axis_tuser,out_inf.axis_tkeep,out_inf.axis_tlast,out_inf.axis_tdata} = data_out_inf.data;
+assign out_inf.axis_tvalid = data_out_inf.valid;
+assign data_out_inf.ready = out_inf.axis_tready;
+
+endmodule

data/lib/axi/AXI_stream/axis_rom_contect_sim.sv

@@ -0,0 +1,113 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: 2021-04-16 17:01:02 +0800
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module axis_rom_contect_sim #(
+    parameter  FNUM = 8,
+    parameter  STEP = 1
+)(
+    input [FNUM-1:0]        load_files,
+    input [4095:0]          init_files        [FNUM-1:0],
+    axi_stream_inf.slaver   a_axis_zip,
+    axi_stream_inf.slaver   b_axis_zip,
+    axi_stream_inf.master   a_rom_contect_inf,
+    axi_stream_inf.master   b_rom_contect_inf
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+
+axi_stream_inf #(.DSIZE((a_axis_zip.DSIZE / 2)),.FreqM(a_axis_zip.FreqM),.USIZE(1)) a_axis_unzip (.aclk(a_axis_zip.aclk),.aresetn(a_axis_zip.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE((b_axis_zip.DSIZE / 2)),.FreqM(b_axis_zip.FreqM),.USIZE(1)) b_axis_unzip (.aclk(b_axis_zip.aclk),.aresetn(b_axis_zip.aresetn),.aclken(1'b1)) ;
+cm_ram_inf #(.DSIZE(a_rom_contect_inf.DSIZE),.RSIZE(a_axis_zip.DSIZE),.MSIZE(1)) xram_inf();
+axi_stream_inf #(.DSIZE(a_rom_contect_inf.DSIZE+(a_axis_zip.DSIZE / 2)),.FreqM(a_rom_contect_inf.FreqM),.USIZE(1)) a_rom_contect_inf_pre (.aclk(a_rom_contect_inf.aclk),.aresetn(a_rom_contect_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(b_rom_contect_inf.DSIZE+(b_axis_zip.DSIZE / 2)),.FreqM(b_rom_contect_inf.FreqM),.USIZE(1)) b_rom_contect_inf_pre (.aclk(b_rom_contect_inf.aclk),.aresetn(b_rom_contect_inf.aresetn),.aclken(1'b1)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+axis_uncompress_A1 #(
+    .ASIZE ((a_axis_zip.DSIZE / 2) ),
+    .LSIZE ((a_axis_zip.DSIZE / 2) ),
+    .STEP  (STEP                   )
+)axis_uncompress_A1_ainst(
+/* axi_stream_inf.slaver */.axis_zip   (a_axis_zip   ),
+/* axi_stream_inf.master */.axis_unzip (a_axis_unzip )
+);
+axis_uncompress_A1 #(
+    .ASIZE ((a_axis_zip.DSIZE / 2) ),
+    .LSIZE ((a_axis_zip.DSIZE / 2) ),
+    .STEP  (STEP                   )
+)axis_uncompress_A1_binst(
+/* axi_stream_inf.slaver */.axis_zip   (b_axis_zip   ),
+/* axi_stream_inf.master */.axis_unzip (b_axis_unzip )
+);
+common_ram_sim_wrapper #(
+    .FNUM (FNUM )
+)common_ram_wrapper_sim_inst(
+/* input             */.load_files (load_files ),
+/* input             */.init_files (init_files ),
+/* cm_ram_inf.slaver */.ram_inf    (xram_inf   )
+);
+axi_stream_planer #(
+    .LAT   (3                       ),
+    .DSIZE (a_rom_contect_inf.DSIZE ),
+    .HEAD  ("FALSE"                 )
+)axi_stream_planer_ainst(
+/* input                 */.reset     (~a_axis_zip.aresetn   ),
+/* input                 */.pack_data (xram_inf.doa          ),
+/* axi_stream_inf.slaver */.axis_in   (a_axis_unzip          ),
+/* axi_stream_inf.master */.axis_out  (a_rom_contect_inf_pre )
+);
+axi_stream_planer #(
+    .LAT   (3                       ),
+    .DSIZE (b_rom_contect_inf.DSIZE ),
+    .HEAD  ("FALSE"                 )
+)axi_stream_planer_binst(
+/* input                 */.reset     (~b_axis_zip.aresetn   ),
+/* input                 */.pack_data (xram_inf.dob          ),
+/* axi_stream_inf.slaver */.axis_in   (b_axis_unzip          ),
+/* axi_stream_inf.master */.axis_out  (b_rom_contect_inf_pre )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+initial begin
+    assert(a_axis_zip.DSIZE==b_axis_zip.DSIZE)else begin
+        $error("a_axis_zip.DSIZE<%0d> must equal b_axis_zip.DSIZE<%0d>",a_axis_zip.DSIZE,b_axis_zip.DSIZE);
+        $stop;
+    end
+    assert(a_rom_contect_inf.DSIZE==b_rom_contect_inf.DSIZE)else begin
+        $error("a_rom_contect_inf.DSIZE<%0d>==b_rom_contect_inf.DSIZE<%0d>",a_rom_contect_inf.DSIZE,b_rom_contect_inf.DSIZE);
+        $stop;
+    end
+end
+
+assign xram_inf.addra = a_axis_unzip.axis_tdata;
+assign xram_inf.dia = '0;
+assign xram_inf.wea = '0;
+assign xram_inf.ena = 1'b1;
+assign xram_inf.clka = a_axis_zip.aclk;
+assign xram_inf.rsta = ~a_axis_zip.aresetn;
+assign xram_inf.addrb = b_axis_unzip.axis_tdata;
+assign xram_inf.dib = '0;
+assign xram_inf.web = '0;
+assign xram_inf.enb = 1'b1;
+assign xram_inf.clkb = b_axis_zip.aclk;
+assign xram_inf.rstb = ~b_axis_zip.aresetn;
+
+assign a_rom_contect_inf.axis_tdata = a_rom_contect_inf_pre.axis_tdata[a_rom_contect_inf.DSIZE-1:0];
+assign a_rom_contect_inf.axis_tvalid = a_rom_contect_inf_pre.axis_tvalid;
+assign a_rom_contect_inf.axis_tlast = a_rom_contect_inf_pre.axis_tlast;
+assign a_rom_contect_inf_pre.axis_tready = a_rom_contect_inf.axis_tready;
+assign b_rom_contect_inf.axis_tdata = b_rom_contect_inf_pre.axis_tdata[b_rom_contect_inf.DSIZE-1:0];
+assign b_rom_contect_inf.axis_tvalid = b_rom_contect_inf_pre.axis_tvalid;
+assign b_rom_contect_inf.axis_tlast = b_rom_contect_inf_pre.axis_tlast;
+assign b_rom_contect_inf_pre.axis_tready = b_rom_contect_inf.axis_tready;
+
+endmodule