axi_tdl 0.0.19 → 0.1.7

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Files changed (146) hide show
  1. checksums.yaml +4 -4
  2. data/Rakefile +7 -0
  3. data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
  4. data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
  5. data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
  6. data/lib/axi/AXI4/axi4_dpram_cache.sv +10 -10
  7. data/lib/axi/AXI4/axi4_rd_burst_track.sv +2 -1
  8. data/lib/axi/AXI4/axi4_wr_burst_track.sv +2 -1
  9. data/lib/axi/AXI4/axis_to_axi4_wr.sv +9 -9
  10. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
  11. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +5 -5
  12. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
  13. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +9 -9
  14. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
  15. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
  16. data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
  17. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
  18. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  19. data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
  20. data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
  21. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  22. data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +50 -0
  23. data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
  24. data/lib/axi/common/common_ram_wrapper.sv +1 -1
  25. data/lib/axi/common/test_write_mem.sv +1 -1
  26. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +13 -13
  27. data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
  28. data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
  29. data/lib/axi/platform_ip/long_fifo_verb.sv +1 -1
  30. data/lib/axi/platform_ip/wide_fifo.sv +1 -1
  31. data/lib/axi/platform_ip/xilinx_fifo_verb.sv +1 -1
  32. data/lib/axi/platform_ip/xilinx_fifo_verc.sv +2 -1
  33. data/lib/axi/techbench/tb_axi_stream_split_channel.rb +2 -1
  34. data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
  35. data/lib/axi_tdl.rb +31 -1
  36. data/lib/axi_tdl/version.rb +1 -1
  37. data/lib/public_atom_module/CheckPClock.sv +53 -0
  38. data/lib/public_atom_module/LICENSE.md +674 -0
  39. data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
  40. data/lib/public_atom_module/bits_decode.sv +71 -0
  41. data/lib/public_atom_module/bits_decode_verb.sv +71 -0
  42. data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
  43. data/lib/public_atom_module/broaden.v +43 -0
  44. data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
  45. data/lib/public_atom_module/ceiling.v +39 -0
  46. data/lib/public_atom_module/ceiling_A1.v +42 -0
  47. data/lib/public_atom_module/clock_rst.sv +64 -0
  48. data/lib/public_atom_module/cross_clk_sync.v +37 -0
  49. data/lib/public_atom_module/edge_generator.v +50 -0
  50. data/lib/public_atom_module/flooring.v +36 -0
  51. data/lib/public_atom_module/latch_data.v +30 -0
  52. data/lib/public_atom_module/latency.v +48 -0
  53. data/lib/public_atom_module/latency_dynamic.v +83 -0
  54. data/lib/public_atom_module/latency_long.v +84 -0
  55. data/lib/public_atom_module/latency_verb.v +52 -0
  56. data/lib/public_atom_module/once_event.sv +65 -0
  57. data/lib/public_atom_module/pipe_reg.v +93 -0
  58. data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
  59. data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
  60. data/lib/public_atom_module/sim/clock_rst_verc.sv +69 -0
  61. data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
  62. data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
  63. data/lib/public_atom_module/sim_system_pkg.sv +4 -0
  64. data/lib/public_atom_module/synth_system_pkg.sv +4 -0
  65. data/lib/tdl/Logic/logic_edge.rb +1 -1
  66. data/lib/tdl/auto_script/import_hdl.rb +39 -4
  67. data/lib/tdl/axi4/axi4_interconnect_verb.rb +47 -10
  68. data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
  69. data/lib/tdl/class_hdl/hdl_always_ff.rb +2 -2
  70. data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
  71. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
  72. data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
  73. data/lib/tdl/class_hdl/hdl_function.rb +4 -4
  74. data/lib/tdl/class_hdl/hdl_generate.rb +4 -1
  75. data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
  76. data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
  77. data/lib/tdl/class_hdl/hdl_package.rb +45 -0
  78. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
  79. data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
  80. data/lib/tdl/elements/Reset.rb +5 -9
  81. data/lib/tdl/elements/clock.rb +5 -9
  82. data/lib/tdl/elements/data_inf.rb +0 -17
  83. data/lib/tdl/elements/logic.rb +9 -31
  84. data/lib/tdl/elements/mail_box.rb +6 -1
  85. data/lib/tdl/elements/originclass.rb +17 -47
  86. data/lib/tdl/elements/parameter.rb +5 -6
  87. data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
  88. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +2 -2
  89. data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +9 -0
  90. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +2 -2
  91. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +2 -2
  92. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
  93. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +41 -0
  94. data/lib/tdl/examples/11_test_unit/tu0.sv +2 -1
  95. data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
  96. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +3 -3
  97. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +3 -3
  98. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +3 -3
  99. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
  100. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +3 -3
  101. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +3 -3
  102. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
  103. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
  104. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +2 -2
  105. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +7 -7
  106. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
  107. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  108. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +2 -2
  109. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
  110. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +8 -8
  111. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +9 -9
  112. data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
  113. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
  114. data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
  115. data/lib/tdl/examples/8_top_module/dve.tcl +155 -2
  116. data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
  117. data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +29 -0
  118. data/lib/tdl/examples/8_top_module/test_top.sv +7 -26
  119. data/lib/tdl/examples/8_top_module/test_top_sim.sv +28 -0
  120. data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +13 -0
  121. data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +35 -0
  122. data/lib/tdl/examples/9_itegration/dve.tcl +155 -2
  123. data/lib/tdl/examples/9_itegration/tb_test_top.sv +2 -2
  124. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -1
  125. data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +38 -0
  126. data/lib/tdl/examples/9_itegration/test_top.sv +4 -4
  127. data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
  128. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +40 -0
  129. data/lib/tdl/examples/9_itegration/top.rb +1 -0
  130. data/lib/tdl/exlib/axis_verify.rb +4 -3
  131. data/lib/tdl/exlib/constraints_verb.rb +1 -0
  132. data/lib/tdl/exlib/itegration_verb.rb +212 -169
  133. data/lib/tdl/rebuild_ele/ele_base.rb +15 -10
  134. data/lib/tdl/sdlmodule/sdlmodule.rb +117 -51
  135. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
  136. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +3 -3
  137. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
  138. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
  139. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
  140. data/lib/tdl/sdlmodule/test_unit_module.rb +12 -0
  141. data/lib/tdl/sdlmodule/top_module.rb +13 -10
  142. data/lib/tdl/tdl.rb +1 -11
  143. data/lib/tdl/tdlerror/tdlerror.rb +1 -1
  144. metadata +46 -5
  145. data/CODE_OF_CONDUCT.md +0 -74
  146. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
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  Version: VERA.0.0
8
- created: xxxx.xx.xx
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+ created: 2021-03-20 20:34:51 +0800
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  madified:
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  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -23,7 +23,7 @@ test_top rtl_top(
23
23
  //==========================================================================
24
24
  //-------- expression ------------------------------------------------------
25
25
  initial begin
26
- forever begin #(33ns);gl_clk = ~gl_clk;end;
26
+ forever begin #(33ns);gl_clk = ~gl_clk;end;
27
27
  end
28
28
 
29
29
  endmodule
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
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  Version: VERA.0.0
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- created: 2021-03-20 12:10:28 +0800
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+ created: 2021-04-03 13:47:04 +0800
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  madified:
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  ***********************************************/
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  `timescale 1ns/1ps
@@ -0,0 +1,38 @@
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+ /**********************************************
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+ _______________________________________
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+ ___________ Cook Darwin __________
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+ _______________________________________
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+ descript:
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+ author : Cook.Darwin
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+ Version: VERA.0.0
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+ created: 2021-04-03 14:05:10 +0800
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+ madified:
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+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+
13
+ module tb_test_tttop_sim();
14
+ //==========================================================================
15
+ //-------- define ----------------------------------------------------------
16
+ logic gl_clk;
17
+ string test_unit_region;
18
+ logic unit_pass_u;
19
+ logic unit_pass_d;
20
+
21
+ //==========================================================================
22
+ //-------- instance --------------------------------------------------------
23
+ test_tttop_sim rtl_top(
24
+ /* input clock */.global_sys_clk (gl_clk )
25
+ );
26
+ test_clock_bb test_unit_0(
27
+ /* input */.from_up_pass (unit_pass_u ),
28
+ /* output */.to_down_pass (unit_pass_d )
29
+ );
30
+ //==========================================================================
31
+ //-------- expression ------------------------------------------------------
32
+ initial begin
33
+ forever begin #(33ns);gl_clk = ~gl_clk;end;
34
+ end
35
+
36
+ assign unit_pass_u = 1'b1;
37
+
38
+ endmodule
@@ -5,7 +5,7 @@ _______________________________________
5
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  descript:
6
6
  author : Cook.Darwin
7
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  Version: VERA.0.0
8
- created: xxxx.xx.xx
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+ created: 2021-03-20 20:34:51 +0800
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9
  madified:
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  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -33,8 +33,8 @@ a_test_md a_test_md_inst(
33
33
  );
34
34
  //==========================================================================
35
35
  //-------- expression ------------------------------------------------------
36
- assign x_origin_inf.axis_tvalid = 1'b0;
37
- assign x_origin_inf.axis_tdata = '0;
38
- assign x_origin_inf.axis_tlast = 1'b0;
36
+ assign x_origin_inf.axis_tvalid = 1'b0;
37
+ assign x_origin_inf.axis_tdata = '0;
38
+ assign x_origin_inf.axis_tlast = 1'b0;
39
39
 
40
40
  endmodule
@@ -1,40 +1,9 @@
1
- /**********************************************
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- _______________________________________
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- ___________ Cook Darwin __________
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- _______________________________________
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- descript:
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- author : Cook.Darwin
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- Version: VERA.0.0
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- created: xxxx.xx.xx
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- madified:
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- ***********************************************/
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- `timescale 1ns/1ps
12
-
13
- module test_tttop (
14
- input global_sys_clk
15
- );
16
-
17
- //==========================================================================
18
- //-------- define ----------------------------------------------------------
19
- logic clock_100M;
20
- logic rstn_100M;
21
- axi_stream_inf #(.DSIZE(16),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
22
- //==========================================================================
23
- //-------- instance --------------------------------------------------------
24
- simple_clock simple_clock_inst(
25
- /* input clock */.sys_clk (global_sys_clk ),
26
- /* output clock */.clock (clock_100M ),
27
- /* output reset */.rst_n (rstn_100M )
28
- );
29
- a_test_md a_test_md_inst(
30
- /* input clock */.clock (clock_100M ),
31
- /* input reset */.rst (~rstn_100M ),
32
- /* axi_stream_inf.master */.origin_inf (x_origin_inf )
33
- );
34
- //==========================================================================
35
- //-------- expression ------------------------------------------------------
36
- assign x_origin_inf.axis_tvalid = 1'b0;
37
- assign x_origin_inf.axis_tdata = '0;
38
- assign x_origin_inf.axis_tlast = 1'b0;
39
1
 
2
+ `timescale 1ns/1ps
3
+ module test_tttop();
4
+ initial begin
5
+ #(1us);
6
+ $warning("Check TopModule.sim,please!!!");
7
+ $stop;
8
+ end
40
9
  endmodule
@@ -0,0 +1,40 @@
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+ /**********************************************
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+ _______________________________________
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+ ___________ Cook Darwin __________
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+ _______________________________________
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+ descript:
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+ author : Cook.Darwin
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+ Version: VERA.0.0
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+ created: 2021-05-04 20:03:49 +0800
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+ madified:
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+ ***********************************************/
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+ `timescale 1ns/1ps
12
+
13
+ module test_tttop_sim (
14
+ input global_sys_clk
15
+ );
16
+
17
+ //==========================================================================
18
+ //-------- define ----------------------------------------------------------
19
+ logic clock_100M;
20
+ logic rstn_100M;
21
+ axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
22
+ //==========================================================================
23
+ //-------- instance --------------------------------------------------------
24
+ simple_clock simple_clock_inst(
25
+ /* input clock */.sys_clk (global_sys_clk ),
26
+ /* output clock */.clock (clock_100M ),
27
+ /* output reset */.rst_n (rstn_100M )
28
+ );
29
+ a_test_md a_test_md_inst(
30
+ /* input clock */.clock (clock_100M ),
31
+ /* input reset */.rst (~rstn_100M ),
32
+ /* axi_stream_inf.master */.origin_inf (x_origin_inf )
33
+ );
34
+ //==========================================================================
35
+ //-------- expression ------------------------------------------------------
36
+ assign x_origin_inf.axis_tvalid = 1'b0;
37
+ assign x_origin_inf.axis_tdata = '0;
38
+ assign x_origin_inf.axis_tlast = 1'b0;
39
+
40
+ endmodule
@@ -8,4 +8,5 @@ TopModule.test_tttop(__dir__) do
8
8
  add_itegration('ClockManage',pins_map: :CM)
9
9
  add_itegration('ABlock')
10
10
 
11
+ add_test_unit('test_clock_bb')
11
12
  end
@@ -128,9 +128,9 @@ end
128
128
 
129
129
  class AxiStream
130
130
 
131
- def to_simple_sim_master_coe(length: [10,200], gap_len: [0,10], data: [ (0...100) ] , vld_perc: [50, 100], loop_coe: true)
131
+ def to_simple_sim_master_coe(enable: 1.b1, length: [10,200], gap_len: [0,10], data: [ (0...100) ] , vld_perc: [50, 100], loop_coe: true)
132
132
  # raise TdlError.new "file cant be empty" unless file
133
- file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{globle_random_name_flag}.coe")
133
+ file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","coe_#{self.name}_#{globle_random_name_flag}.coe")
134
134
  _sps = nil
135
135
  ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
136
136
  require_sdl 'axis_sim_master_model.rb'
@@ -144,11 +144,12 @@ class AxiStream
144
144
  _sps
145
145
  end
146
146
 
147
- @belong_to_module.instance_exec(self,file,loop_coe) do |_self,file,loop_coe|
147
+ @belong_to_module.instance_exec(self,file,loop_coe,enable) do |_self,file,loop_coe,_enable|
148
148
 
149
149
  Instance(:axis_sim_master_model,"sim_model_inst_#{_self.name}") do |h|
150
150
  h.param.LOOP (loop_coe ? "TRUE" : "FALSE")
151
151
  h.param.RAM_DEPTH File.open(File.expand_path(file)).readlines.size
152
+ h.input.enable _enable
152
153
  h.input.load_trigger 1.b0
153
154
  h.input[32].total_length h.param.RAM_DEPTH
154
155
  h.input[512*8].mem_file File.expand_path(file) # {axis_tvalid, axis_tuser, axis_tkeep, axis_tlast, axis_tdata}
@@ -41,6 +41,7 @@ class ConstraintsVerb
41
41
  pulltype = ([pulltype] * pin_name.size ) unless pulltype.is_a? Array
42
42
  drive = ([drive] * pin_name.size ) unless drive.is_a? Array
43
43
 
44
+ pin_name = ((pin_name.is_a?(Array) && pin_name) || [pin_name] )
44
45
  pin_name.each_index do |index|
45
46
  @package_pin_and_IOSTANDARD << [port_name[index],pin_name[index].to_s.upcase,iostandard[index].to_s.upcase,pulltype[index].to_s,drive[index].to_s]
46
47
 
@@ -354,25 +354,25 @@ class ItegrationVerb
354
354
  _names_pool_inst()
355
355
  # @itgt_links = ItgtLinks.new(self)
356
356
  ## 为child module 生成方法
357
- init_children_modules()
357
+ # init_children_modules()
358
358
  # init_children_modules_post()
359
359
  end
360
360
 
361
- def init_children_modules
362
- blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_hash_") || {}
363
- blocks_hash_post = self.class.instance_variable_get("@_sdl_eval_blocks_post_hash_") || {}
364
- dir_hash = self.class.instance_variable_get("@_sdl_eval_dir_hash_")
361
+ # def init_children_modules
362
+ # blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_hash_") || {}
363
+ # blocks_hash_post = self.class.instance_variable_get("@_sdl_eval_blocks_post_hash_") || {}
364
+ # dir_hash = self.class.instance_variable_get("@_sdl_eval_dir_hash_")
365
365
 
366
- blocks_hash = blocks_hash.merge blocks_hash_post
366
+ # blocks_hash = blocks_hash.merge blocks_hash_post
367
367
 
368
- blocks_hash.keys.each do |key|
368
+ # blocks_hash.keys.each do |key|
369
369
 
370
- sdlm = SdlModule.new(name:self.class.to_s + "_#{@nickname}#{key}",out_sv_path:dir_hash[key])
371
- define_singleton_method(key) do
372
- sdlm
373
- end
374
- end
375
- end
370
+ # sdlm = SdlModule.new(name:self.class.to_s + "_#{@nickname}#{key}",out_sv_path:dir_hash[key])
371
+ # define_singleton_method(key) do
372
+ # sdlm
373
+ # end
374
+ # end
375
+ # end
376
376
 
377
377
  # def init_children_modules_post
378
378
  # blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_post_hash_")
@@ -387,20 +387,20 @@ class ItegrationVerb
387
387
  # end
388
388
  # end
389
389
 
390
- def gen_children_modules
391
- blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_hash_") || {}
392
- blocks_hash_post = self.class.instance_variable_get("@_sdl_eval_blocks_post_hash_") || {}
393
- blocks_hash = blocks_hash.merge blocks_hash_post
394
- blocks_hash.keys.each do |key|
395
- self.send(key).gen_sv_module()
396
- end
397
- end
390
+ # def gen_children_modules
391
+ # blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_hash_") || {}
392
+ # blocks_hash_post = self.class.instance_variable_get("@_sdl_eval_blocks_post_hash_") || {}
393
+ # blocks_hash = blocks_hash.merge blocks_hash_post
394
+ # blocks_hash.keys.each do |key|
395
+ # self.send(key).gen_sv_module()
396
+ # end
397
+ # end
398
398
 
399
399
  # define_singleton_method(:inst) do
400
400
  def inst
401
401
  # 先生成子模块
402
402
  ## 执行 生成 sdl module
403
- inst_child_module()
403
+ # inst_child_module()
404
404
 
405
405
  blocks = self.class.instance_variable_get("@_inst_blocks_")
406
406
  ItegrationVerb.curr_itgt_push(self)
@@ -422,7 +422,7 @@ class ItegrationVerb
422
422
  end
423
423
 
424
424
  ## 执行 生成 sdl module
425
- inst_child_module_post()
425
+ # inst_child_module_post()
426
426
 
427
427
  ## 执行top module techbench eval
428
428
  tb_inst()
@@ -431,7 +431,8 @@ class ItegrationVerb
431
431
  ## 执行 约束
432
432
  inst_constraints()
433
433
  ## 执行单元测试
434
- test_unit_inst()
434
+ ## 改到 运行 top_module _exec_add_test_unit 那边执行
435
+ # test_unit_inst()
435
436
  end
436
437
 
437
438
  def tb_inst
@@ -464,8 +465,11 @@ class ItegrationVerb
464
465
  return if blocks.empty?
465
466
  ItegrationVerb.curr_itgt_push self
466
467
 
467
- return unless TopModule.sim
468
-
468
+ unless TopModule.sim
469
+ ItegrationVerb.curr_itgt_pop
470
+ return
471
+ end
472
+
469
473
  blocks.each do |b|
470
474
  # @top_module.techbench.instance_exec(self,&b.clone)
471
475
  sdlm = TestUnitModule.new(name: b[0],out_sv_path: b[1])
@@ -486,62 +490,94 @@ class ItegrationVerb
486
490
 
487
491
  end
488
492
 
489
- def inst_child_module
490
- blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_hash_")
491
- return unless blocks_hash
492
- ItegrationVerb.curr_itgt_push self
493
- $_implicit_curr_itgt_.with_none_itgt do
494
- blocks_hash.keys.each do |key|
495
- sdlm = self.send(key)
496
-
497
-
498
- blocks = blocks_hash[key]
499
- if blocks.length == 1
500
- block = blocks[0]
501
- sdlm.instance_exec(self,&block)
502
- elsif blocks.length > 1
503
- # block = Proc.new do
504
- blocks.each do |b|
505
- # b.call
506
- sdlm.instance_exec(self,&b)
507
- end
508
- # end
509
- else
510
- ;
511
- end
512
- end
513
- end
514
- ItegrationVerb.curr_itgt_pop
515
- end
493
+ def self.test_unit_inst(&filter_block)
494
+ # blocks = self.instance_variable_get("@_inst_test_unit_blocks_")
495
+ # blocks = instance_variable_get("@_inst_test_unit_blocks_") || []
496
+ blocks = @@_inst_test_unit_blocks_ || []
497
+ return unless blocks
498
+ return if blocks.empty?
499
+ return unless TopModule.sim
516
500
 
517
- def inst_child_module_post
518
- blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_post_hash_")
519
- return unless blocks_hash
520
- ItegrationVerb.curr_itgt_push self
521
- $_implicit_curr_itgt_.with_none_itgt do
522
- blocks_hash.keys.each do |key|
523
- sdlm = self.send(key)
524
- # $_implicit_curr_itgt_ = self
501
+ ItegrationVerb.curr_itgt_push nil
525
502
 
526
- blocks = blocks_hash[key]
527
- if blocks.length == 1
528
- block = blocks[0]
529
- sdlm.instance_exec(self,&block)
530
- elsif blocks.length > 1
531
- # block = Proc.new do
532
- blocks.each do |b|
533
- # b.call
534
- sdlm.instance_exec(self,&b)
535
- end
536
- # end
537
- else
538
- next
503
+ blocks.each do |b|
504
+ # @top_module.techbench.instance_exec(self,&b.clone)
505
+ if !(block_given?) || filter_block.call(b[0])
506
+ sdlm = TestUnitModule.new(name: b[0],out_sv_path: b[1])
507
+ $_implicit_curr_itgt_.with_none_itgt do
508
+ sdlm.input - "from_up_pass"
509
+ sdlm.output.logic - "to_down_pass"
510
+ end
511
+ sdlm.instance_exec(nil,&b[2])
512
+
513
+ if b[1] && File.exist?(b[1])
514
+ sdlm.gen_sv_module
515
+ else
516
+ sdlm.origin_sv = true
539
517
  end
540
518
  end
541
519
  end
520
+
542
521
  ItegrationVerb.curr_itgt_pop
522
+
543
523
  end
544
524
 
525
+ # def inst_child_module
526
+ # blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_hash_")
527
+ # return unless blocks_hash
528
+ # ItegrationVerb.curr_itgt_push self
529
+ # $_implicit_curr_itgt_.with_none_itgt do
530
+ # blocks_hash.keys.each do |key|
531
+ # sdlm = self.send(key)
532
+
533
+
534
+ # blocks = blocks_hash[key]
535
+ # if blocks.length == 1
536
+ # block = blocks[0]
537
+ # sdlm.instance_exec(self,&block)
538
+ # elsif blocks.length > 1
539
+ # # block = Proc.new do
540
+ # blocks.each do |b|
541
+ # # b.call
542
+ # sdlm.instance_exec(self,&b)
543
+ # end
544
+ # # end
545
+ # else
546
+ # ;
547
+ # end
548
+ # end
549
+ # end
550
+ # ItegrationVerb.curr_itgt_pop
551
+ # end
552
+
553
+ # def inst_child_module_post
554
+ # blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_post_hash_")
555
+ # return unless blocks_hash
556
+ # ItegrationVerb.curr_itgt_push self
557
+ # $_implicit_curr_itgt_.with_none_itgt do
558
+ # blocks_hash.keys.each do |key|
559
+ # sdlm = self.send(key)
560
+ # # $_implicit_curr_itgt_ = self
561
+
562
+ # blocks = blocks_hash[key]
563
+ # if blocks.length == 1
564
+ # block = blocks[0]
565
+ # sdlm.instance_exec(self,&block)
566
+ # elsif blocks.length > 1
567
+ # # block = Proc.new do
568
+ # blocks.each do |b|
569
+ # # b.call
570
+ # sdlm.instance_exec(self,&b)
571
+ # end
572
+ # # end
573
+ # else
574
+ # next
575
+ # end
576
+ # end
577
+ # end
578
+ # ItegrationVerb.curr_itgt_pop
579
+ # end
580
+
545
581
  def self.inherited(subclass)
546
582
  unless @@child.include? subclass
547
583
  @@child << subclass
@@ -589,7 +625,7 @@ class ItegrationVerb
589
625
  public
590
626
  def check_same_method(name)
591
627
  if respond_to? name.to_s
592
- raise TdlError.new("Itegration can't Redefine method #{name}")
628
+ raise TdlError.new("Itegration `#{to_s}` can't Redefine method #{name}")
593
629
  end
594
630
  end
595
631
 
@@ -635,39 +671,42 @@ class ItegrationVerb
635
671
  end
636
672
  end
637
673
  ## 先从 已经加入的隐性itgt搜索
638
- @top_module.implicit_itgt_collect.each do |i|
639
- explort_attrs = i.class.get_itgt_var('itegration_explort_collect')
640
- if ((explort_attrs & container_attrs).sort == container_attrs.sort && i.flag_match(flag_attrs))
641
- # puts "Itgt Good"
642
- mark = true
643
- unless self.respond_to? e
644
- define_singleton_method(e) do
645
- ## 如果从其他模块调用则出发 dynac_active
646
- ItegrationVerbAgent.new(i)
674
+ ## 去除隐性引入
675
+ unless TopModule.itgt_implicit_reject
676
+ @top_module.implicit_itgt_collect.each do |i|
677
+ explort_attrs = i.class.get_itgt_var('itegration_explort_collect')
678
+ if ((explort_attrs & container_attrs).sort == container_attrs.sort && i.flag_match(flag_attrs))
679
+ # puts "Itgt Good"
680
+ mark = true
681
+ unless self.respond_to? e
682
+ define_singleton_method(e) do
683
+ ## 如果从其他模块调用则出发 dynac_active
684
+ ItegrationVerbAgent.new(i)
685
+ end
686
+ i.link_eval
687
+ i.child_inst_itgt << self
647
688
  end
648
- i.link_eval
649
- i.child_inst_itgt << self
689
+ break
650
690
  end
651
- break
652
691
  end
653
- end
654
- next if mark ## 找到了 就处理下一个Link
655
- ## 如果没有找到 再从 ItegrationVerb children里面找到比加入
656
- @@child.each do |c|
657
- explort_attrs = c.get_itgt_var('itegration_explort_collect')
658
- # puts explort_attrs
659
- if ((explort_attrs & container_attrs).sort == container_attrs.sort && c.flag_match(flag_attrs))
660
- # puts "Child Good"
661
- isp = @top_module.add_itegration(c.to_s,nickname:'implicit',implicit:true)
662
- @top_module.implicit_itgt_collect << isp
663
- ## 如果是隐性添加,先不要加入pin_map
664
- define_singleton_method(e) do
665
- ItegrationVerbAgent.new(isp)
692
+ next if mark ## 找到了 就处理下一个Link
693
+ ## 如果没有找到 再从 ItegrationVerb children里面找到比加入
694
+ @@child.each do |c|
695
+ explort_attrs = c.get_itgt_var('itegration_explort_collect')
696
+ # puts explort_attrs
697
+ if ((explort_attrs & container_attrs).sort == container_attrs.sort && c.flag_match(flag_attrs))
698
+ # puts "Child Good"
699
+ isp = @top_module.add_itegration(c.to_s,nickname:'implicit',implicit:true)
700
+ @top_module.implicit_itgt_collect << isp
701
+ ## 如果是隐性添加,先不要加入pin_map
702
+ define_singleton_method(e) do
703
+ ItegrationVerbAgent.new(isp)
704
+ end
705
+ isp.link_eval
706
+ isp.child_inst_itgt << self
707
+ mark = true
708
+ break
666
709
  end
667
- isp.link_eval
668
- isp.child_inst_itgt << self
669
- mark = true
670
- break
671
710
  end
672
711
  end
673
712
 
@@ -700,18 +739,21 @@ class ItegrationVerb
700
739
  next if mark ## 找到了 就处理下一个Link
701
740
  ##
702
741
  ## 如果没有找到 再从 ItegrationVerb children里面找到比加入
703
- @@child.each do |c|
704
- explort_attrs = c.get_itgt_var('itegration_explort_collect')
705
- if (explort_attrs & container_attrs).sort == container_attrs.sort
706
- isp = @top_module.add_itegration(c.to_s,nickname:'implicit',implicit:true)
707
- @top_module.implicit_itgt_collect << isp
708
- ## 如果是隐性添加,先不要加入pin_map
742
+ ## 去除隐性引入
743
+ unless TopModule.itgt_implicit_reject
744
+ @@child.each do |c|
745
+ explort_attrs = c.get_itgt_var('itegration_explort_collect')
746
+ if (explort_attrs & container_attrs).sort == container_attrs.sort
747
+ isp = @top_module.add_itegration(c.to_s,nickname:'implicit',implicit:true)
748
+ @top_module.implicit_itgt_collect << isp
749
+ ## 如果是隐性添加,先不要加入pin_map
709
750
 
710
- define_singleton_method(e) do
711
- ItegrationVerbAgent.new(isp)
751
+ define_singleton_method(e) do
752
+ ItegrationVerbAgent.new(isp)
753
+ end
754
+ mark = true
755
+ break
712
756
  end
713
- mark = true
714
- break
715
757
  end
716
758
  end
717
759
 
@@ -734,65 +776,66 @@ class ItegrationVerb
734
776
  end
735
777
 
736
778
  ## 添加测试用例
737
-
779
+ @@_inst_test_unit_blocks_ = []
738
780
  def self.def_test_unit(name,path,&block)
739
- _inst_test_unit_blocks_ = instance_variable_get("@_inst_test_unit_blocks_")
740
- _inst_test_unit_blocks_ ||= []
741
- _inst_test_unit_blocks_ << [name.to_s, path, block]
742
- instance_variable_set("@_inst_test_unit_blocks_",_inst_test_unit_blocks_)
781
+ # @@_inst_test_unit_blocks_ = instance_variable_get("@_inst_test_unit_blocks_")
782
+ @@_inst_test_unit_blocks_ ||= []
783
+ @@_inst_test_unit_blocks_ << [name.to_s, path, block]
784
+ # instance_variable_set("@_inst_test_unit_blocks_",_inst_test_unit_blocks_)
785
+ @@_inst_test_unit_blocks_
743
786
  end
744
787
 
745
788
  ## 生成 itgt内的模块,
746
- def self.has_module(dir,*names)
747
- unless File.exist? dir
748
- Dir.mkdir dir
749
- end
750
- ## itgt 生成 sdl 模块
751
- names.each do |name|
752
- # unless container_hash[name.to_s]
753
- # container_hash[name.to_s] = []
754
- # end
755
- self.define_singleton_method("#{name}_sdl_eval") do |&block|
756
- _sdl_eval_blocks_hash_ = instance_variable_get("@_sdl_eval_blocks_hash_")
757
- _sdl_eval_dir_hash_ = instance_variable_get("@_sdl_eval_dir_hash_")
758
- _sdl_eval_blocks_hash_ ||= {}
759
- _sdl_eval_dir_hash_ ||= {}
760
-
761
- if _sdl_eval_blocks_hash_[name]
762
- _sdl_eval_blocks_hash_[name] << block
763
- # _sdl_eval_blocks_hash_[name] << $_implicit_curr_itgt_.wrap_nont_itgt(&block)
764
- # _sdl_eval_blocks_hash_[name] << lambda {|itgt| block.call }
765
- else
766
- _sdl_eval_blocks_hash_[name] = [block]
767
- # _sdl_eval_blocks_hash_[name] = [$_implicit_curr_itgt_.wrap_nont_itgt(&block)]
768
- # _sdl_eval_blocks_hash_[name] == [ lambda {|itgt| block.call }]
769
- end
770
-
771
- _sdl_eval_dir_hash_[name] = dir if dir
772
- instance_variable_set("@_sdl_eval_dir_hash_",_sdl_eval_dir_hash_)
773
- instance_variable_set("@_sdl_eval_blocks_hash_",_sdl_eval_blocks_hash_)
774
- end
775
- ## 在 top_module 后再执行
776
- self.define_singleton_method("#{name}_sdl_post_eval") do |&block|
777
- $_implicit_curr_itgt_.with_none_itgt do
778
- _blocks_hash_ = instance_variable_get("@_sdl_eval_blocks_post_hash_")
779
- _sdl_eval_dir_hash_ = instance_variable_get("@_sdl_eval_dir_hash_")
780
- _blocks_hash_ ||= {}
781
- _sdl_eval_dir_hash_ ||= {}
782
-
783
- if _blocks_hash_[name]
784
- _blocks_hash_[name] << block #$_implicit_curr_itgt_.wrap_nont_itgt(&block)
785
- else
786
- _blocks_hash_[name] = [block] #[$_implicit_curr_itgt_.wrap_nont_itgt(&block)]
787
- end
788
-
789
- _sdl_eval_dir_hash_[name] = dir if dir
790
- instance_variable_set("@_sdl_eval_dir_hash_",_sdl_eval_dir_hash_)
791
- instance_variable_set("@_sdl_eval_blocks_post_hash_",_blocks_hash_)
792
- end
793
- end
794
- end
795
- end
789
+ # def self.has_module(dir,*names)
790
+ # unless File.exist? dir
791
+ # Dir.mkdir dir
792
+ # end
793
+ # ## itgt 生成 sdl 模块
794
+ # names.each do |name|
795
+ # # unless container_hash[name.to_s]
796
+ # # container_hash[name.to_s] = []
797
+ # # end
798
+ # self.define_singleton_method("#{name}_sdl_eval") do |&block|
799
+ # _sdl_eval_blocks_hash_ = instance_variable_get("@_sdl_eval_blocks_hash_")
800
+ # _sdl_eval_dir_hash_ = instance_variable_get("@_sdl_eval_dir_hash_")
801
+ # _sdl_eval_blocks_hash_ ||= {}
802
+ # _sdl_eval_dir_hash_ ||= {}
803
+
804
+ # if _sdl_eval_blocks_hash_[name]
805
+ # _sdl_eval_blocks_hash_[name] << block
806
+ # # _sdl_eval_blocks_hash_[name] << $_implicit_curr_itgt_.wrap_nont_itgt(&block)
807
+ # # _sdl_eval_blocks_hash_[name] << lambda {|itgt| block.call }
808
+ # else
809
+ # _sdl_eval_blocks_hash_[name] = [block]
810
+ # # _sdl_eval_blocks_hash_[name] = [$_implicit_curr_itgt_.wrap_nont_itgt(&block)]
811
+ # # _sdl_eval_blocks_hash_[name] == [ lambda {|itgt| block.call }]
812
+ # end
813
+
814
+ # _sdl_eval_dir_hash_[name] = dir if dir
815
+ # instance_variable_set("@_sdl_eval_dir_hash_",_sdl_eval_dir_hash_)
816
+ # instance_variable_set("@_sdl_eval_blocks_hash_",_sdl_eval_blocks_hash_)
817
+ # end
818
+ # ## 在 top_module 后再执行
819
+ # self.define_singleton_method("#{name}_sdl_post_eval") do |&block|
820
+ # $_implicit_curr_itgt_.with_none_itgt do
821
+ # _blocks_hash_ = instance_variable_get("@_sdl_eval_blocks_post_hash_")
822
+ # _sdl_eval_dir_hash_ = instance_variable_get("@_sdl_eval_dir_hash_")
823
+ # _blocks_hash_ ||= {}
824
+ # _sdl_eval_dir_hash_ ||= {}
825
+
826
+ # if _blocks_hash_[name]
827
+ # _blocks_hash_[name] << block #$_implicit_curr_itgt_.wrap_nont_itgt(&block)
828
+ # else
829
+ # _blocks_hash_[name] = [block] #[$_implicit_curr_itgt_.wrap_nont_itgt(&block)]
830
+ # end
831
+
832
+ # _sdl_eval_dir_hash_[name] = dir if dir
833
+ # instance_variable_set("@_sdl_eval_dir_hash_",_sdl_eval_dir_hash_)
834
+ # instance_variable_set("@_sdl_eval_blocks_post_hash_",_blocks_hash_)
835
+ # end
836
+ # end
837
+ # end
838
+ # end
796
839
 
797
840
  def self.record_instance_var_block(name,default=[],&block)
798
841
  _inst_ccc_ = instance_variable_get("@_#{name}_")