axi_tdl 0.0.19 → 0.1.7
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- checksums.yaml +4 -4
- data/Rakefile +7 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
- data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
- data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +10 -10
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +2 -1
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +2 -1
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +9 -9
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +5 -5
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +9 -9
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +50 -0
- data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/common/test_write_mem.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +13 -13
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
- data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
- data/lib/axi/platform_ip/long_fifo_verb.sv +1 -1
- data/lib/axi/platform_ip/wide_fifo.sv +1 -1
- data/lib/axi/platform_ip/xilinx_fifo_verb.sv +1 -1
- data/lib/axi/platform_ip/xilinx_fifo_verc.sv +2 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +2 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
- data/lib/axi_tdl.rb +31 -1
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/public_atom_module/CheckPClock.sv +53 -0
- data/lib/public_atom_module/LICENSE.md +674 -0
- data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
- data/lib/public_atom_module/bits_decode.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
- data/lib/public_atom_module/broaden.v +43 -0
- data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
- data/lib/public_atom_module/ceiling.v +39 -0
- data/lib/public_atom_module/ceiling_A1.v +42 -0
- data/lib/public_atom_module/clock_rst.sv +64 -0
- data/lib/public_atom_module/cross_clk_sync.v +37 -0
- data/lib/public_atom_module/edge_generator.v +50 -0
- data/lib/public_atom_module/flooring.v +36 -0
- data/lib/public_atom_module/latch_data.v +30 -0
- data/lib/public_atom_module/latency.v +48 -0
- data/lib/public_atom_module/latency_dynamic.v +83 -0
- data/lib/public_atom_module/latency_long.v +84 -0
- data/lib/public_atom_module/latency_verb.v +52 -0
- data/lib/public_atom_module/once_event.sv +65 -0
- data/lib/public_atom_module/pipe_reg.v +93 -0
- data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
- data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
- data/lib/public_atom_module/sim/clock_rst_verc.sv +69 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
- data/lib/public_atom_module/sim_system_pkg.sv +4 -0
- data/lib/public_atom_module/synth_system_pkg.sv +4 -0
- data/lib/tdl/Logic/logic_edge.rb +1 -1
- data/lib/tdl/auto_script/import_hdl.rb +39 -4
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +47 -10
- data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
- data/lib/tdl/class_hdl/hdl_always_ff.rb +2 -2
- data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
- data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
- data/lib/tdl/class_hdl/hdl_function.rb +4 -4
- data/lib/tdl/class_hdl/hdl_generate.rb +4 -1
- data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
- data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
- data/lib/tdl/class_hdl/hdl_package.rb +45 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
- data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
- data/lib/tdl/elements/Reset.rb +5 -9
- data/lib/tdl/elements/clock.rb +5 -9
- data/lib/tdl/elements/data_inf.rb +0 -17
- data/lib/tdl/elements/logic.rb +9 -31
- data/lib/tdl/elements/mail_box.rb +6 -1
- data/lib/tdl/elements/originclass.rb +17 -47
- data/lib/tdl/elements/parameter.rb +5 -6
- data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +2 -2
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +9 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +2 -2
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +2 -2
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +41 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +2 -1
- data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +7 -7
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +2 -2
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +8 -8
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +9 -9
- data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
- data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
- data/lib/tdl/examples/8_top_module/dve.tcl +155 -2
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +29 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +7 -26
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +28 -0
- data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +13 -0
- data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +35 -0
- data/lib/tdl/examples/9_itegration/dve.tcl +155 -2
- data/lib/tdl/examples/9_itegration/tb_test_top.sv +2 -2
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -1
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +38 -0
- data/lib/tdl/examples/9_itegration/test_top.sv +4 -4
- data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +40 -0
- data/lib/tdl/examples/9_itegration/top.rb +1 -0
- data/lib/tdl/exlib/axis_verify.rb +4 -3
- data/lib/tdl/exlib/constraints_verb.rb +1 -0
- data/lib/tdl/exlib/itegration_verb.rb +212 -169
- data/lib/tdl/rebuild_ele/ele_base.rb +15 -10
- data/lib/tdl/sdlmodule/sdlmodule.rb +117 -51
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +3 -3
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
- data/lib/tdl/sdlmodule/test_unit_module.rb +12 -0
- data/lib/tdl/sdlmodule/top_module.rb +13 -10
- data/lib/tdl/tdl.rb +1 -11
- data/lib/tdl/tdlerror/tdlerror.rb +1 -1
- metadata +46 -5
- data/CODE_OF_CONDUCT.md +0 -74
- data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
@@ -5,7 +5,7 @@ _______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created:
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created: 2021-03-20 20:34:51 +0800
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***********************************************/
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`timescale 1ns/1ps
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//==========================================================================
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//-------- expression ------------------------------------------------------
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initial begin
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forever begin #(33ns);gl_clk = ~gl_clk;end;
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end
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endmodule
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/**********************************************
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_______________________________________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2021-04-03 14:05:10 +0800
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***********************************************/
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`timescale 1ns/1ps
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module tb_test_tttop_sim();
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//==========================================================================
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//-------- define ----------------------------------------------------------
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logic gl_clk;
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string test_unit_region;
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logic unit_pass_u;
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logic unit_pass_d;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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test_tttop_sim rtl_top(
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/* input clock */.global_sys_clk (gl_clk )
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);
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test_clock_bb test_unit_0(
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/* input */.from_up_pass (unit_pass_u ),
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/* output */.to_down_pass (unit_pass_d )
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);
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//==========================================================================
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//-------- expression ------------------------------------------------------
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initial begin
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forever begin #(33ns);gl_clk = ~gl_clk;end;
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end
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assign unit_pass_u = 1'b1;
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endmodule
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2021-03-20 20:34:51 +0800
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***********************************************/
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`timescale 1ns/1ps
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//==========================================================================
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//-------- expression ------------------------------------------------------
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assign
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assign
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assign
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assign x_origin_inf.axis_tvalid = 1'b0;
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assign x_origin_inf.axis_tdata = '0;
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assign x_origin_inf.axis_tlast = 1'b0;
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endmodule
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/**********************************************
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_______________________________________
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_______________________________________
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author : Cook.Darwin
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Version: VERA.0.0
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created: xxxx.xx.xx
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***********************************************/
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`timescale 1ns/1ps
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module test_tttop (
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input global_sys_clk
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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logic clock_100M;
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logic rstn_100M;
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axi_stream_inf #(.DSIZE(16),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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simple_clock simple_clock_inst(
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/* input clock */.sys_clk (global_sys_clk ),
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/* output clock */.clock (clock_100M ),
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/* output reset */.rst_n (rstn_100M )
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);
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a_test_md a_test_md_inst(
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/* input clock */.clock (clock_100M ),
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/* input reset */.rst (~rstn_100M ),
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/* axi_stream_inf.master */.origin_inf (x_origin_inf )
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);
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//==========================================================================
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//-------- expression ------------------------------------------------------
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assign x_origin_inf.axis_tvalid = 1'b0;
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assign x_origin_inf.axis_tdata = '0;
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assign x_origin_inf.axis_tlast = 1'b0;
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`timescale 1ns/1ps
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module test_tttop();
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initial begin
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#(1us);
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$warning("Check TopModule.sim,please!!!");
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$stop;
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end
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endmodule
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2021-05-04 20:03:49 +0800
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module test_tttop_sim (
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input global_sys_clk
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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logic clock_100M;
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logic rstn_100M;
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axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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simple_clock simple_clock_inst(
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/* input clock */.sys_clk (global_sys_clk ),
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/* output clock */.clock (clock_100M ),
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/* output reset */.rst_n (rstn_100M )
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);
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a_test_md a_test_md_inst(
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/* input clock */.clock (clock_100M ),
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/* input reset */.rst (~rstn_100M ),
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/* axi_stream_inf.master */.origin_inf (x_origin_inf )
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);
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//==========================================================================
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//-------- expression ------------------------------------------------------
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assign x_origin_inf.axis_tvalid = 1'b0;
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assign x_origin_inf.axis_tdata = '0;
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assign x_origin_inf.axis_tlast = 1'b0;
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endmodule
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class AxiStream
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def to_simple_sim_master_coe(length: [10,200], gap_len: [0,10], data: [ (0...100) ] , vld_perc: [50, 100], loop_coe: true)
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def to_simple_sim_master_coe(enable: 1.b1, length: [10,200], gap_len: [0,10], data: [ (0...100) ] , vld_perc: [50, 100], loop_coe: true)
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# raise TdlError.new "file cant be empty" unless file
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file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{globle_random_name_flag}.coe")
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file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","coe_#{self.name}_#{globle_random_name_flag}.coe")
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_sps = nil
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ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
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require_sdl 'axis_sim_master_model.rb'
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_sps
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end
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@belong_to_module.instance_exec(self,file,loop_coe) do |_self,file,loop_coe|
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@belong_to_module.instance_exec(self,file,loop_coe,enable) do |_self,file,loop_coe,_enable|
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Instance(:axis_sim_master_model,"sim_model_inst_#{_self.name}") do |h|
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h.param.LOOP (loop_coe ? "TRUE" : "FALSE")
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h.param.RAM_DEPTH File.open(File.expand_path(file)).readlines.size
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h.input.enable _enable
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h.input.load_trigger 1.b0
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h.input[32].total_length h.param.RAM_DEPTH
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h.input[512*8].mem_file File.expand_path(file) # {axis_tvalid, axis_tuser, axis_tkeep, axis_tlast, axis_tdata}
|
@@ -41,6 +41,7 @@ class ConstraintsVerb
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pulltype = ([pulltype] * pin_name.size ) unless pulltype.is_a? Array
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drive = ([drive] * pin_name.size ) unless drive.is_a? Array
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+
pin_name = ((pin_name.is_a?(Array) && pin_name) || [pin_name] )
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pin_name.each_index do |index|
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@package_pin_and_IOSTANDARD << [port_name[index],pin_name[index].to_s.upcase,iostandard[index].to_s.upcase,pulltype[index].to_s,drive[index].to_s]
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47
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@@ -354,25 +354,25 @@ class ItegrationVerb
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_names_pool_inst()
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# @itgt_links = ItgtLinks.new(self)
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## 为child module 生成方法
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-
init_children_modules()
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+
# init_children_modules()
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# init_children_modules_post()
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end
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def init_children_modules
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-
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# def init_children_modules
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# blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_hash_") || {}
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# blocks_hash_post = self.class.instance_variable_get("@_sdl_eval_blocks_post_hash_") || {}
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# dir_hash = self.class.instance_variable_get("@_sdl_eval_dir_hash_")
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-
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# blocks_hash = blocks_hash.merge blocks_hash_post
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-
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# blocks_hash.keys.each do |key|
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-
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-
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-
end
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+
# sdlm = SdlModule.new(name:self.class.to_s + "_#{@nickname}#{key}",out_sv_path:dir_hash[key])
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+
# define_singleton_method(key) do
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+
# sdlm
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# end
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+
# end
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+
# end
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# def init_children_modules_post
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378
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# blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_post_hash_")
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@@ -387,20 +387,20 @@ class ItegrationVerb
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387
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# end
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388
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# end
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389
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-
def gen_children_modules
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-
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-
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-
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-
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-
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-
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-
end
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390
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+
# def gen_children_modules
|
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|
+
# blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_hash_") || {}
|
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|
+
# blocks_hash_post = self.class.instance_variable_get("@_sdl_eval_blocks_post_hash_") || {}
|
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|
+
# blocks_hash = blocks_hash.merge blocks_hash_post
|
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+
# blocks_hash.keys.each do |key|
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+
# self.send(key).gen_sv_module()
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+
# end
|
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|
+
# end
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398
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399
|
# define_singleton_method(:inst) do
|
400
400
|
def inst
|
401
401
|
# 先生成子模块
|
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402
|
## 执行 生成 sdl module
|
403
|
-
inst_child_module()
|
403
|
+
# inst_child_module()
|
404
404
|
|
405
405
|
blocks = self.class.instance_variable_get("@_inst_blocks_")
|
406
406
|
ItegrationVerb.curr_itgt_push(self)
|
@@ -422,7 +422,7 @@ class ItegrationVerb
|
|
422
422
|
end
|
423
423
|
|
424
424
|
## 执行 生成 sdl module
|
425
|
-
inst_child_module_post()
|
425
|
+
# inst_child_module_post()
|
426
426
|
|
427
427
|
## 执行top module techbench eval
|
428
428
|
tb_inst()
|
@@ -431,7 +431,8 @@ class ItegrationVerb
|
|
431
431
|
## 执行 约束
|
432
432
|
inst_constraints()
|
433
433
|
## 执行单元测试
|
434
|
-
|
434
|
+
## 改到 运行 top_module _exec_add_test_unit 那边执行
|
435
|
+
# test_unit_inst()
|
435
436
|
end
|
436
437
|
|
437
438
|
def tb_inst
|
@@ -464,8 +465,11 @@ class ItegrationVerb
|
|
464
465
|
return if blocks.empty?
|
465
466
|
ItegrationVerb.curr_itgt_push self
|
466
467
|
|
467
|
-
|
468
|
-
|
468
|
+
unless TopModule.sim
|
469
|
+
ItegrationVerb.curr_itgt_pop
|
470
|
+
return
|
471
|
+
end
|
472
|
+
|
469
473
|
blocks.each do |b|
|
470
474
|
# @top_module.techbench.instance_exec(self,&b.clone)
|
471
475
|
sdlm = TestUnitModule.new(name: b[0],out_sv_path: b[1])
|
@@ -486,62 +490,94 @@ class ItegrationVerb
|
|
486
490
|
|
487
491
|
end
|
488
492
|
|
489
|
-
def
|
490
|
-
|
491
|
-
|
492
|
-
|
493
|
-
|
494
|
-
|
495
|
-
|
496
|
-
|
497
|
-
|
498
|
-
blocks = blocks_hash[key]
|
499
|
-
if blocks.length == 1
|
500
|
-
block = blocks[0]
|
501
|
-
sdlm.instance_exec(self,&block)
|
502
|
-
elsif blocks.length > 1
|
503
|
-
# block = Proc.new do
|
504
|
-
blocks.each do |b|
|
505
|
-
# b.call
|
506
|
-
sdlm.instance_exec(self,&b)
|
507
|
-
end
|
508
|
-
# end
|
509
|
-
else
|
510
|
-
;
|
511
|
-
end
|
512
|
-
end
|
513
|
-
end
|
514
|
-
ItegrationVerb.curr_itgt_pop
|
515
|
-
end
|
493
|
+
def self.test_unit_inst(&filter_block)
|
494
|
+
# blocks = self.instance_variable_get("@_inst_test_unit_blocks_")
|
495
|
+
# blocks = instance_variable_get("@_inst_test_unit_blocks_") || []
|
496
|
+
blocks = @@_inst_test_unit_blocks_ || []
|
497
|
+
return unless blocks
|
498
|
+
return if blocks.empty?
|
499
|
+
return unless TopModule.sim
|
516
500
|
|
517
|
-
|
518
|
-
blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_post_hash_")
|
519
|
-
return unless blocks_hash
|
520
|
-
ItegrationVerb.curr_itgt_push self
|
521
|
-
$_implicit_curr_itgt_.with_none_itgt do
|
522
|
-
blocks_hash.keys.each do |key|
|
523
|
-
sdlm = self.send(key)
|
524
|
-
# $_implicit_curr_itgt_ = self
|
501
|
+
ItegrationVerb.curr_itgt_push nil
|
525
502
|
|
526
|
-
|
527
|
-
|
528
|
-
|
529
|
-
|
530
|
-
|
531
|
-
|
532
|
-
|
533
|
-
|
534
|
-
|
535
|
-
|
536
|
-
|
537
|
-
|
538
|
-
|
503
|
+
blocks.each do |b|
|
504
|
+
# @top_module.techbench.instance_exec(self,&b.clone)
|
505
|
+
if !(block_given?) || filter_block.call(b[0])
|
506
|
+
sdlm = TestUnitModule.new(name: b[0],out_sv_path: b[1])
|
507
|
+
$_implicit_curr_itgt_.with_none_itgt do
|
508
|
+
sdlm.input - "from_up_pass"
|
509
|
+
sdlm.output.logic - "to_down_pass"
|
510
|
+
end
|
511
|
+
sdlm.instance_exec(nil,&b[2])
|
512
|
+
|
513
|
+
if b[1] && File.exist?(b[1])
|
514
|
+
sdlm.gen_sv_module
|
515
|
+
else
|
516
|
+
sdlm.origin_sv = true
|
539
517
|
end
|
540
518
|
end
|
541
519
|
end
|
520
|
+
|
542
521
|
ItegrationVerb.curr_itgt_pop
|
522
|
+
|
543
523
|
end
|
544
524
|
|
525
|
+
# def inst_child_module
|
526
|
+
# blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_hash_")
|
527
|
+
# return unless blocks_hash
|
528
|
+
# ItegrationVerb.curr_itgt_push self
|
529
|
+
# $_implicit_curr_itgt_.with_none_itgt do
|
530
|
+
# blocks_hash.keys.each do |key|
|
531
|
+
# sdlm = self.send(key)
|
532
|
+
|
533
|
+
|
534
|
+
# blocks = blocks_hash[key]
|
535
|
+
# if blocks.length == 1
|
536
|
+
# block = blocks[0]
|
537
|
+
# sdlm.instance_exec(self,&block)
|
538
|
+
# elsif blocks.length > 1
|
539
|
+
# # block = Proc.new do
|
540
|
+
# blocks.each do |b|
|
541
|
+
# # b.call
|
542
|
+
# sdlm.instance_exec(self,&b)
|
543
|
+
# end
|
544
|
+
# # end
|
545
|
+
# else
|
546
|
+
# ;
|
547
|
+
# end
|
548
|
+
# end
|
549
|
+
# end
|
550
|
+
# ItegrationVerb.curr_itgt_pop
|
551
|
+
# end
|
552
|
+
|
553
|
+
# def inst_child_module_post
|
554
|
+
# blocks_hash = self.class.instance_variable_get("@_sdl_eval_blocks_post_hash_")
|
555
|
+
# return unless blocks_hash
|
556
|
+
# ItegrationVerb.curr_itgt_push self
|
557
|
+
# $_implicit_curr_itgt_.with_none_itgt do
|
558
|
+
# blocks_hash.keys.each do |key|
|
559
|
+
# sdlm = self.send(key)
|
560
|
+
# # $_implicit_curr_itgt_ = self
|
561
|
+
|
562
|
+
# blocks = blocks_hash[key]
|
563
|
+
# if blocks.length == 1
|
564
|
+
# block = blocks[0]
|
565
|
+
# sdlm.instance_exec(self,&block)
|
566
|
+
# elsif blocks.length > 1
|
567
|
+
# # block = Proc.new do
|
568
|
+
# blocks.each do |b|
|
569
|
+
# # b.call
|
570
|
+
# sdlm.instance_exec(self,&b)
|
571
|
+
# end
|
572
|
+
# # end
|
573
|
+
# else
|
574
|
+
# next
|
575
|
+
# end
|
576
|
+
# end
|
577
|
+
# end
|
578
|
+
# ItegrationVerb.curr_itgt_pop
|
579
|
+
# end
|
580
|
+
|
545
581
|
def self.inherited(subclass)
|
546
582
|
unless @@child.include? subclass
|
547
583
|
@@child << subclass
|
@@ -589,7 +625,7 @@ class ItegrationVerb
|
|
589
625
|
public
|
590
626
|
def check_same_method(name)
|
591
627
|
if respond_to? name.to_s
|
592
|
-
raise TdlError.new("Itegration can't Redefine method #{name}")
|
628
|
+
raise TdlError.new("Itegration `#{to_s}` can't Redefine method #{name}")
|
593
629
|
end
|
594
630
|
end
|
595
631
|
|
@@ -635,39 +671,42 @@ class ItegrationVerb
|
|
635
671
|
end
|
636
672
|
end
|
637
673
|
## 先从 已经加入的隐性itgt搜索
|
638
|
-
|
639
|
-
|
640
|
-
|
641
|
-
|
642
|
-
|
643
|
-
|
644
|
-
|
645
|
-
|
646
|
-
|
674
|
+
## 去除隐性引入
|
675
|
+
unless TopModule.itgt_implicit_reject
|
676
|
+
@top_module.implicit_itgt_collect.each do |i|
|
677
|
+
explort_attrs = i.class.get_itgt_var('itegration_explort_collect')
|
678
|
+
if ((explort_attrs & container_attrs).sort == container_attrs.sort && i.flag_match(flag_attrs))
|
679
|
+
# puts "Itgt Good"
|
680
|
+
mark = true
|
681
|
+
unless self.respond_to? e
|
682
|
+
define_singleton_method(e) do
|
683
|
+
## 如果从其他模块调用则出发 dynac_active
|
684
|
+
ItegrationVerbAgent.new(i)
|
685
|
+
end
|
686
|
+
i.link_eval
|
687
|
+
i.child_inst_itgt << self
|
647
688
|
end
|
648
|
-
|
649
|
-
i.child_inst_itgt << self
|
689
|
+
break
|
650
690
|
end
|
651
|
-
break
|
652
691
|
end
|
653
|
-
|
654
|
-
|
655
|
-
|
656
|
-
|
657
|
-
|
658
|
-
|
659
|
-
|
660
|
-
|
661
|
-
|
662
|
-
|
663
|
-
|
664
|
-
|
665
|
-
|
692
|
+
next if mark ## 找到了 就处理下一个Link
|
693
|
+
## 如果没有找到 再从 ItegrationVerb children里面找到比加入
|
694
|
+
@@child.each do |c|
|
695
|
+
explort_attrs = c.get_itgt_var('itegration_explort_collect')
|
696
|
+
# puts explort_attrs
|
697
|
+
if ((explort_attrs & container_attrs).sort == container_attrs.sort && c.flag_match(flag_attrs))
|
698
|
+
# puts "Child Good"
|
699
|
+
isp = @top_module.add_itegration(c.to_s,nickname:'implicit',implicit:true)
|
700
|
+
@top_module.implicit_itgt_collect << isp
|
701
|
+
## 如果是隐性添加,先不要加入pin_map
|
702
|
+
define_singleton_method(e) do
|
703
|
+
ItegrationVerbAgent.new(isp)
|
704
|
+
end
|
705
|
+
isp.link_eval
|
706
|
+
isp.child_inst_itgt << self
|
707
|
+
mark = true
|
708
|
+
break
|
666
709
|
end
|
667
|
-
isp.link_eval
|
668
|
-
isp.child_inst_itgt << self
|
669
|
-
mark = true
|
670
|
-
break
|
671
710
|
end
|
672
711
|
end
|
673
712
|
|
@@ -700,18 +739,21 @@ class ItegrationVerb
|
|
700
739
|
next if mark ## 找到了 就处理下一个Link
|
701
740
|
##
|
702
741
|
## 如果没有找到 再从 ItegrationVerb children里面找到比加入
|
703
|
-
|
704
|
-
|
705
|
-
|
706
|
-
|
707
|
-
|
708
|
-
|
742
|
+
## 去除隐性引入
|
743
|
+
unless TopModule.itgt_implicit_reject
|
744
|
+
@@child.each do |c|
|
745
|
+
explort_attrs = c.get_itgt_var('itegration_explort_collect')
|
746
|
+
if (explort_attrs & container_attrs).sort == container_attrs.sort
|
747
|
+
isp = @top_module.add_itegration(c.to_s,nickname:'implicit',implicit:true)
|
748
|
+
@top_module.implicit_itgt_collect << isp
|
749
|
+
## 如果是隐性添加,先不要加入pin_map
|
709
750
|
|
710
|
-
|
711
|
-
|
751
|
+
define_singleton_method(e) do
|
752
|
+
ItegrationVerbAgent.new(isp)
|
753
|
+
end
|
754
|
+
mark = true
|
755
|
+
break
|
712
756
|
end
|
713
|
-
mark = true
|
714
|
-
break
|
715
757
|
end
|
716
758
|
end
|
717
759
|
|
@@ -734,65 +776,66 @@ class ItegrationVerb
|
|
734
776
|
end
|
735
777
|
|
736
778
|
## 添加测试用例
|
737
|
-
|
779
|
+
@@_inst_test_unit_blocks_ = []
|
738
780
|
def self.def_test_unit(name,path,&block)
|
739
|
-
_inst_test_unit_blocks_ = instance_variable_get("@_inst_test_unit_blocks_")
|
740
|
-
_inst_test_unit_blocks_ ||= []
|
741
|
-
_inst_test_unit_blocks_ << [name.to_s, path, block]
|
742
|
-
instance_variable_set("@_inst_test_unit_blocks_",_inst_test_unit_blocks_)
|
781
|
+
# @@_inst_test_unit_blocks_ = instance_variable_get("@_inst_test_unit_blocks_")
|
782
|
+
@@_inst_test_unit_blocks_ ||= []
|
783
|
+
@@_inst_test_unit_blocks_ << [name.to_s, path, block]
|
784
|
+
# instance_variable_set("@_inst_test_unit_blocks_",_inst_test_unit_blocks_)
|
785
|
+
@@_inst_test_unit_blocks_
|
743
786
|
end
|
744
787
|
|
745
788
|
## 生成 itgt内的模块,
|
746
|
-
def self.has_module(dir,*names)
|
747
|
-
|
748
|
-
|
749
|
-
|
750
|
-
|
751
|
-
|
752
|
-
|
753
|
-
|
754
|
-
|
755
|
-
|
756
|
-
|
757
|
-
|
758
|
-
|
759
|
-
|
760
|
-
|
761
|
-
|
762
|
-
|
763
|
-
|
764
|
-
|
765
|
-
|
766
|
-
|
767
|
-
|
768
|
-
|
769
|
-
|
770
|
-
|
771
|
-
|
772
|
-
|
773
|
-
|
774
|
-
|
775
|
-
|
776
|
-
|
777
|
-
|
778
|
-
|
779
|
-
|
780
|
-
|
781
|
-
|
782
|
-
|
783
|
-
|
784
|
-
|
785
|
-
|
786
|
-
|
787
|
-
|
788
|
-
|
789
|
-
|
790
|
-
|
791
|
-
|
792
|
-
|
793
|
-
|
794
|
-
|
795
|
-
end
|
789
|
+
# def self.has_module(dir,*names)
|
790
|
+
# unless File.exist? dir
|
791
|
+
# Dir.mkdir dir
|
792
|
+
# end
|
793
|
+
# ## itgt 生成 sdl 模块
|
794
|
+
# names.each do |name|
|
795
|
+
# # unless container_hash[name.to_s]
|
796
|
+
# # container_hash[name.to_s] = []
|
797
|
+
# # end
|
798
|
+
# self.define_singleton_method("#{name}_sdl_eval") do |&block|
|
799
|
+
# _sdl_eval_blocks_hash_ = instance_variable_get("@_sdl_eval_blocks_hash_")
|
800
|
+
# _sdl_eval_dir_hash_ = instance_variable_get("@_sdl_eval_dir_hash_")
|
801
|
+
# _sdl_eval_blocks_hash_ ||= {}
|
802
|
+
# _sdl_eval_dir_hash_ ||= {}
|
803
|
+
|
804
|
+
# if _sdl_eval_blocks_hash_[name]
|
805
|
+
# _sdl_eval_blocks_hash_[name] << block
|
806
|
+
# # _sdl_eval_blocks_hash_[name] << $_implicit_curr_itgt_.wrap_nont_itgt(&block)
|
807
|
+
# # _sdl_eval_blocks_hash_[name] << lambda {|itgt| block.call }
|
808
|
+
# else
|
809
|
+
# _sdl_eval_blocks_hash_[name] = [block]
|
810
|
+
# # _sdl_eval_blocks_hash_[name] = [$_implicit_curr_itgt_.wrap_nont_itgt(&block)]
|
811
|
+
# # _sdl_eval_blocks_hash_[name] == [ lambda {|itgt| block.call }]
|
812
|
+
# end
|
813
|
+
|
814
|
+
# _sdl_eval_dir_hash_[name] = dir if dir
|
815
|
+
# instance_variable_set("@_sdl_eval_dir_hash_",_sdl_eval_dir_hash_)
|
816
|
+
# instance_variable_set("@_sdl_eval_blocks_hash_",_sdl_eval_blocks_hash_)
|
817
|
+
# end
|
818
|
+
# ## 在 top_module 后再执行
|
819
|
+
# self.define_singleton_method("#{name}_sdl_post_eval") do |&block|
|
820
|
+
# $_implicit_curr_itgt_.with_none_itgt do
|
821
|
+
# _blocks_hash_ = instance_variable_get("@_sdl_eval_blocks_post_hash_")
|
822
|
+
# _sdl_eval_dir_hash_ = instance_variable_get("@_sdl_eval_dir_hash_")
|
823
|
+
# _blocks_hash_ ||= {}
|
824
|
+
# _sdl_eval_dir_hash_ ||= {}
|
825
|
+
|
826
|
+
# if _blocks_hash_[name]
|
827
|
+
# _blocks_hash_[name] << block #$_implicit_curr_itgt_.wrap_nont_itgt(&block)
|
828
|
+
# else
|
829
|
+
# _blocks_hash_[name] = [block] #[$_implicit_curr_itgt_.wrap_nont_itgt(&block)]
|
830
|
+
# end
|
831
|
+
|
832
|
+
# _sdl_eval_dir_hash_[name] = dir if dir
|
833
|
+
# instance_variable_set("@_sdl_eval_dir_hash_",_sdl_eval_dir_hash_)
|
834
|
+
# instance_variable_set("@_sdl_eval_blocks_post_hash_",_blocks_hash_)
|
835
|
+
# end
|
836
|
+
# end
|
837
|
+
# end
|
838
|
+
# end
|
796
839
|
|
797
840
|
def self.record_instance_var_block(name,default=[],&block)
|
798
841
|
_inst_ccc_ = instance_variable_get("@_#{name}_")
|