axi_tdl 0.0.19 → 0.1.7

data/lib/public_atom_module/altera_xilinx_always_block_sw.rb

@@ -0,0 +1,57 @@
+file_root_path = File.dirname(File.expand_path(__FILE__))
+# file_name = "/home/young/work/public_atom_modules/latency.v"
+$mode = "xilinx"
+def sw_always(to="xilinx",file_name)
+    all_str = File.open(file_name).read
+    altera_rep_0 = /always\s*@\s*\(\s*posedge\s+(?<clock_name>\w*(?i:clock|clk)\w*)\s*(?:,|or)\s*negedge\s+(?<rst_name>\w*(?:rst|reset)\w*)\s*\)/
+    xilinx_rep   = /always\s*@\s*\(posedge\s+(?<clock_name>\w*(?i:clock|clk)\w*)\s*\/\*.+\*\/\s*\)/
+    # altera_rep_0 = /always\s*@\s*\(\s*posedge\s+(?<clock_name>\s*(?i:clock|clk)\s*)\t*(?:,|or)\s*/
+    if(to.downcase=="xilinx")
+        all_str.gsub!(altera_rep_0) do |s|
+            "always@(posedge #{$~["clock_name"]}/*,negedge #{$~["rst_name"]}*/)"
+        end
+    elsif to.downcase=="altera"
+        all_str.gsub!(xilinx_rep) do |s|
+            s.sub('/*','').sub('*/','')
+        end
+    end
+
+    # if xilinx_rep.match("always@(posedge clk/*,negedge rst_n*/)")
+    #     puts "rep OK"
+    #     puts $~["clock_name"]
+    # else
+    #     puts "rep ERR"
+    # end
+    File.open(file_name,"w"){|f| f.print(all_str)}
+end
+
+def look_for_v(path)
+    paths = Dir::entries(path) - %w{. ..}
+
+    paths.each do |pf|
+        full_name = File.join(path,pf)
+        if(File.directory? full_name)
+            look_for_v(full_name)
+        elsif(File.file? full_name)
+            if(/\.v$/i =~ pf || /\.sv$/i =~ pf)
+                sw_always($mode,full_name)
+            end
+        end
+    end
+end
+
+if ARGV.empty?
+    puts "Pleace switch to xilinx or altera"
+elsif ARGV[0] == "xilinx"
+    $mode = "xilinx"
+    look_for_v(file_root_path)
+elsif ARGV[0] == "altera"
+    $mode = "altera"
+    look_for_v(file_root_path)
+else
+    puts "error ARVG"
+end
+
+
+# sw_always("xilinx",file_name)
+# sw_always("altera",file_name)

data/lib/public_atom_module/bits_decode.sv

@@ -0,0 +1,71 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version:
+creaded: xxxx.xx.xx
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module bits_decode_nc_verb #(
+    parameter NUM       = 16,
+    parameter NSIZE     = $clog2(NUM),
+    parameter MODE      = "H"       //Hight BIT first
+)(
+    input [NUM-1:0]             origin_bits,
+    output logic [NSIZE-1:0]    code
+);
+
+int KK;
+generate
+if(MODE!="H")begin
+    always_comb begin
+        code = NUM-1;
+        for(KK=NUM;KK>0;KK--)begin
+            if(origin_bits[KK-1])
+                    code    = KK-1;
+            else    code    = code;
+        end
+    end
+end else begin
+    always_comb begin
+        code = 0;
+        for(KK=0;KK<NUM;KK++)begin
+            if(origin_bits[KK])
+                    code    = KK;
+            else    code    = code;
+        end
+    end
+end
+endgenerate
+
+endmodule : bits_decode_nc_verb
+
+module bits_decode_verb #(
+    parameter NUM       = 16,
+    parameter NSIZE     = $clog2(NUM),
+    parameter MODE      = "H"       //Hight BIT first
+)(
+    input                       clock,
+    input                       rst_n,
+    input [NUM-1:0]             origin_bits,
+    output logic [NSIZE-1:0]    code
+);
+
+logic [NSIZE-1:0]   tmp;
+
+bits_decode_nc_verb #(
+    .NUM    (NUM    ),
+    .MODE   (MODE   )            //Hight BIT first
+)bits_decode_nc_inst(
+/*  input [NUM-1:0]          */   .origin_bits     (origin_bits   ),
+/*  output logic [NSIZE-1:0] */   .code     (tmp    )
+);
+
+always@(posedge clock,negedge rst_n)
+    if(~rst_n)  code    <= '0;
+    else        code    <= tmp;
+
+endmodule:bits_decode_verb

data/lib/public_atom_module/bits_decode_verb.sv

@@ -0,0 +1,71 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version:
+creaded: XXXX.XX.XX
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module bits_decode_nc #(
+    parameter NUM       = 16,
+    parameter NSIZE     = $clog2(NUM),
+    parameter MODE      = "H"       //Hight BIT first
+)(
+    input [NUM-1:0]             bits,
+    output logic [NSIZE-1:0]    code
+);
+
+int KK;
+generate
+if(MODE!="H")begin
+    always_comb begin
+        code = NUM-1;
+        for(KK=NUM;KK>0;KK--)begin
+            if(bits[KK-1])
+                    code    = KK-1;
+            else    code    = code;
+        end
+    end
+end else begin
+    always_comb begin
+        code = 0;
+        for(KK=0;KK<NUM;KK++)begin
+            if(bits[KK])
+                    code    = KK;
+            else    code    = code;
+        end
+    end
+end
+endgenerate
+
+endmodule : bits_decode_nc
+
+module bits_decode #(
+    parameter NUM       = 16,
+    parameter NSIZE     = $clog2(NUM),
+    parameter MODE      = "H"       //Hight BIT first
+)(
+    input                       clock,
+    input                       rst_n,
+    input [NUM-1:0]             bits,
+    output logic [NSIZE-1:0]    code
+);
+
+logic [NSIZE-1:0]   tmp;
+
+bits_decode_nc #(
+    .NUM    (NUM    ),
+    .MODE   (MODE   )            //Hight BIT first
+)bits_decode_nc_inst(
+/*  input [NUM-1:0]          */   .bits     (bits   ),
+/*  output logic [NSIZE-1:0] */   .code     (tmp    )
+);
+
+always@(posedge clock,negedge rst_n)
+    if(~rst_n)  code    <= '0;
+    else        code    <= tmp;
+
+endmodule:bits_decode

data/lib/public_atom_module/bits_decode_verb_sdl.rb

@@ -0,0 +1,24 @@
+
+sm = SdlModule.new(name:"bits_decode_nc_verb")
+sm.path = File.expand_path(__FILE__)
+sm.real_sv_path = File.join(File.expand_path(__dir__),"#{File.basename(__FILE__,'.rb').sub(/_sdl/,'')}.sv")
+sm.Parameter("NUM",16)
+sm.Parameter("NSIZE",NqString.new('$clog2(NUM)'))
+sm.Parameter("MODE","H")
+sm.Input("origin_bits",dsize:sm.NUM)
+sm.Output("code",dsize:sm.NSIZE)
+sm.origin_sv = true
+
+
+
+sm = SdlModule.new(name:"bits_decode_verb")
+sm.path = File.expand_path(__FILE__)
+sm.real_sv_path = File.join(File.expand_path(__dir__),"#{File.basename(__FILE__,'.rb').sub(/_sdl/,'')}.sv")
+sm.Parameter("NUM",16)
+sm.Parameter("NSIZE",NqString.new('$clog2(NUM)'))
+sm.Parameter("MODE","H")
+sm.Input 'clock'
+sm.Input 'rst_n'
+sm.Input("origin_bits",dsize:sm.NUM)
+sm.Output("code",dsize:sm.NSIZE)
+sm.origin_sv = true

data/lib/public_atom_module/broaden.v

@@ -0,0 +1,43 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version:
+creaded: 2015/5/14 14:37:22
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module broaden #(
+	parameter		PHASE	= "POSITIVE",  //POSITIVE NEGATIVE
+	parameter		LEN		= 4
+)(
+	input			clk,
+	input			rst_n,
+	input			d,
+	output			q
+);
+
+
+reg	[LEN-1:0]		dq;
+reg					q_reg;
+always@(posedge clk/*,negedge rst_n*/)
+	if(~rst_n)
+		if(PHASE == "POSITIVE")
+				dq	<= {LEN{1'b0}};
+		else	dq	<= {LEN{1'b1}};
+	else		dq	<= {dq[LEN-2:0],d};
+
+always@(posedge clk/*,negedge rst_n*/)
+	if(PHASE == "POSITIVE")
+		if(~rst_n)	q_reg	<= 1'b0;
+		else		q_reg	<= |dq;
+	else if(PHASE == "NEGATIVE")
+		if(~rst_n)	q_reg	<= 1'b1;
+		else		q_reg	<= &dq;
+
+
+assign	q	= q_reg;
+
+endmodule

data/lib/public_atom_module/broaden_and_cross_clk.v

@@ -0,0 +1,47 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version:
+creaded: 2015/5/14 14:52:00
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module broaden_and_cross_clk #(
+    parameter        PHASE    = "POSITIVE",  //POSITIVE NEGATIVE
+    parameter        LEN        = 4,
+    parameter        LAT        = 2
+)(
+    input            rclk,
+    input            rd_rst_n,
+    input            wclk,
+    input            wr_rst_n,
+    input            d,
+    output           q
+);
+
+wire        qq;
+
+broaden #(
+    .PHASE            (PHASE),
+    .LEN            (LEN)            //delay = LEN + 1
+)broaden_inst(
+    wclk,
+    wr_rst_n,
+    d,
+    qq
+);
+
+cross_clk_sync #(
+    .DSIZE        (1),
+    .LAT        (LAT)
+)cross_clk_sync_false_path(
+    rclk,
+    rd_rst_n,
+    qq,
+    q
+);
+
+endmodule

data/lib/public_atom_module/ceiling.v

@@ -0,0 +1,39 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.1 : 2015/10/30 10:57:22
+	xxxxx = xxxx_{|x12}
+creaded: 2015/7/23 13:56:28
+madified:2015/10/30 10:57:18
+***********************************************/
+`timescale 1ns/1ps
+module ceiling #(
+	parameter	DSIZE		= 16,
+	parameter	CSIZE		= 4,		//must smaller than DSIZE
+	parameter	OSIZE		= 8,        //must not bigger than DSIZE-CSIZE
+	parameter	SEQUENTIAL	= "TRUE"
+)(
+	input				clock	,
+	input [DSIZE-1:0]	indata  ,
+	output[OSIZE-1:0]	outdata
+);
+
+
+reg [OSIZE-1:0]		result = {OSIZE{1'b0}};
+wire[OSIZE-1:0]		cm_result;
+wire				carry_bit;
+// assign	carry_bit	= (DSIZE>(CSIZE+OSIZE))? indata[DSIZE-1-CSIZE-OSIZE] : 1'b0;
+assign	carry_bit	= 1'b0;
+
+assign	cm_result	= (indata[DSIZE-1-:CSIZE] == {CSIZE{1'b0}})? indata[DSIZE-1-CSIZE-:OSIZE]+carry_bit : {OSIZE{1'b1}};
+
+always@(posedge clock)
+	result	<= cm_result;
+
+
+assign	outdata	= (SEQUENTIAL == "TRUE")? result : (SEQUENTIAL == "FALSE")? cm_result : {OSIZE{1'b0}};
+
+endmodule

data/lib/public_atom_module/ceiling_A1.v

@@ -0,0 +1,42 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.1 : 2015/10/30 10:57:22
+	xxxxx = xxxx_{|x12}
+Version: VERA.1.0 : 2016/3/29 下午3:26:26
+    add reset signal
+creaded: 2015/7/23 13:56:28
+madified:2015/10/30 10:57:18
+***********************************************/
+`timescale 1ns/1ps
+module ceiling_A1 #(
+	parameter	DSIZE		= 16,
+	parameter	CSIZE		= 4,		//must smaller than DSIZE
+	parameter	OSIZE		= 8,        //must not bigger than DSIZE-CSIZE
+	parameter	SEQUENTIAL	= "TRUE"
+)(
+	input				clock	,
+    input               rst_n   ,
+	input [DSIZE-1:0]	indata  ,
+	output[OSIZE-1:0]	outdata
+);
+
+
+reg [OSIZE-1:0]		result;
+wire[OSIZE-1:0]		cm_result;
+wire				carry_bit;
+assign	carry_bit	= (DSIZE>(CSIZE+OSIZE))? indata[DSIZE-1-CSIZE-OSIZE] : 1'b0;
+
+assign	cm_result	= (indata[DSIZE-1-:CSIZE] == {CSIZE{1'b0}})? indata[DSIZE-1-CSIZE-:OSIZE]+carry_bit : {OSIZE{1'b1}};
+
+always@(posedge clock/*,negedge rst_n*/)
+    if(~rst_n)  result  <= {OSIZE{1'b0}};
+    else        result	<= cm_result;
+
+
+assign	outdata	= (SEQUENTIAL == "TRUE")? result : (SEQUENTIAL == "FALSE")? cm_result : {OSIZE{1'b0}};
+
+endmodule

data/lib/public_atom_module/clock_rst.sv

@@ -0,0 +1,64 @@
+/*******************************************************
+______________     ___  __   __       ______________
+______________\  /  |  |__} |  | |\ | ______________
+______________ \/   |  |  \ |__| | \| ______________
+
+--Module Name:clock_rst
+--Project Name:tmp_avalon
+--Chinese Description:
+	
+--English Description:
+
+--Version:
+--Data modified:
+--author:
+--E-mail: wumingyang@vtron.com
+--Data created:2013/12/18 15:12:37
+________________________________________________________
+********************************************************/
+`timescale 1ns/1ps
+module clock_rst(
+	output	bit clock,
+	output	bit rst
+);
+
+parameter bit	ACTIVE	= 1;
+
+int		clk_i	= 0;
+int		rst_i	= 0;
+longint		period_cnt	= 0;
+bit		clk_pause	= 1;
+int		rst_hold	= 10;
+real		clk_period	= 5;
+
+task run(
+input int		reset_hold	= 10,
+input real		period		= 5,
+input longint		period_count	= 0
+);
+begin
+	clk_pause	= 1;
+	clk_i		= 0;
+	rst_i		= 0;
+	rst		= ACTIVE;
+	rst_hold	= reset_hold;
+	clk_period	= period/2;
+	period_cnt	= period_count;
+//	$stop;
+	repeat(3)	#(period*3);
+	clk_pause	= 0;
+	repeat(rst_hold)	@(posedge clock);
+	rst		= !ACTIVE;
+end
+endtask
+
+always #clk_period begin
+	if(clk_pause == 0 && (period_cnt == 0 || clk_i<period_cnt))begin
+		clock	= ~clock;
+	end else begin
+		clock	=  clock;
+	end
+end
+
+
+endmodule