axi_tdl 0.0.19 → 0.1.7

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Files changed (146) hide show
  1. checksums.yaml +4 -4
  2. data/Rakefile +7 -0
  3. data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
  4. data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
  5. data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
  6. data/lib/axi/AXI4/axi4_dpram_cache.sv +10 -10
  7. data/lib/axi/AXI4/axi4_rd_burst_track.sv +2 -1
  8. data/lib/axi/AXI4/axi4_wr_burst_track.sv +2 -1
  9. data/lib/axi/AXI4/axis_to_axi4_wr.sv +9 -9
  10. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
  11. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +5 -5
  12. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
  13. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +9 -9
  14. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
  15. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
  16. data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
  17. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
  18. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  19. data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
  20. data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
  21. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  22. data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +50 -0
  23. data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
  24. data/lib/axi/common/common_ram_wrapper.sv +1 -1
  25. data/lib/axi/common/test_write_mem.sv +1 -1
  26. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +13 -13
  27. data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
  28. data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
  29. data/lib/axi/platform_ip/long_fifo_verb.sv +1 -1
  30. data/lib/axi/platform_ip/wide_fifo.sv +1 -1
  31. data/lib/axi/platform_ip/xilinx_fifo_verb.sv +1 -1
  32. data/lib/axi/platform_ip/xilinx_fifo_verc.sv +2 -1
  33. data/lib/axi/techbench/tb_axi_stream_split_channel.rb +2 -1
  34. data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
  35. data/lib/axi_tdl.rb +31 -1
  36. data/lib/axi_tdl/version.rb +1 -1
  37. data/lib/public_atom_module/CheckPClock.sv +53 -0
  38. data/lib/public_atom_module/LICENSE.md +674 -0
  39. data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
  40. data/lib/public_atom_module/bits_decode.sv +71 -0
  41. data/lib/public_atom_module/bits_decode_verb.sv +71 -0
  42. data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
  43. data/lib/public_atom_module/broaden.v +43 -0
  44. data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
  45. data/lib/public_atom_module/ceiling.v +39 -0
  46. data/lib/public_atom_module/ceiling_A1.v +42 -0
  47. data/lib/public_atom_module/clock_rst.sv +64 -0
  48. data/lib/public_atom_module/cross_clk_sync.v +37 -0
  49. data/lib/public_atom_module/edge_generator.v +50 -0
  50. data/lib/public_atom_module/flooring.v +36 -0
  51. data/lib/public_atom_module/latch_data.v +30 -0
  52. data/lib/public_atom_module/latency.v +48 -0
  53. data/lib/public_atom_module/latency_dynamic.v +83 -0
  54. data/lib/public_atom_module/latency_long.v +84 -0
  55. data/lib/public_atom_module/latency_verb.v +52 -0
  56. data/lib/public_atom_module/once_event.sv +65 -0
  57. data/lib/public_atom_module/pipe_reg.v +93 -0
  58. data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
  59. data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
  60. data/lib/public_atom_module/sim/clock_rst_verc.sv +69 -0
  61. data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
  62. data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
  63. data/lib/public_atom_module/sim_system_pkg.sv +4 -0
  64. data/lib/public_atom_module/synth_system_pkg.sv +4 -0
  65. data/lib/tdl/Logic/logic_edge.rb +1 -1
  66. data/lib/tdl/auto_script/import_hdl.rb +39 -4
  67. data/lib/tdl/axi4/axi4_interconnect_verb.rb +47 -10
  68. data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
  69. data/lib/tdl/class_hdl/hdl_always_ff.rb +2 -2
  70. data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
  71. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
  72. data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
  73. data/lib/tdl/class_hdl/hdl_function.rb +4 -4
  74. data/lib/tdl/class_hdl/hdl_generate.rb +4 -1
  75. data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
  76. data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
  77. data/lib/tdl/class_hdl/hdl_package.rb +45 -0
  78. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
  79. data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
  80. data/lib/tdl/elements/Reset.rb +5 -9
  81. data/lib/tdl/elements/clock.rb +5 -9
  82. data/lib/tdl/elements/data_inf.rb +0 -17
  83. data/lib/tdl/elements/logic.rb +9 -31
  84. data/lib/tdl/elements/mail_box.rb +6 -1
  85. data/lib/tdl/elements/originclass.rb +17 -47
  86. data/lib/tdl/elements/parameter.rb +5 -6
  87. data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
  88. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +2 -2
  89. data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +9 -0
  90. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +2 -2
  91. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +2 -2
  92. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
  93. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +41 -0
  94. data/lib/tdl/examples/11_test_unit/tu0.sv +2 -1
  95. data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
  96. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +3 -3
  97. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +3 -3
  98. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +3 -3
  99. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
  100. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +3 -3
  101. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +3 -3
  102. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
  103. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
  104. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +2 -2
  105. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +7 -7
  106. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
  107. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  108. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +2 -2
  109. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
  110. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +8 -8
  111. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +9 -9
  112. data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
  113. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
  114. data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
  115. data/lib/tdl/examples/8_top_module/dve.tcl +155 -2
  116. data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
  117. data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +29 -0
  118. data/lib/tdl/examples/8_top_module/test_top.sv +7 -26
  119. data/lib/tdl/examples/8_top_module/test_top_sim.sv +28 -0
  120. data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +13 -0
  121. data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +35 -0
  122. data/lib/tdl/examples/9_itegration/dve.tcl +155 -2
  123. data/lib/tdl/examples/9_itegration/tb_test_top.sv +2 -2
  124. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -1
  125. data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +38 -0
  126. data/lib/tdl/examples/9_itegration/test_top.sv +4 -4
  127. data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
  128. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +40 -0
  129. data/lib/tdl/examples/9_itegration/top.rb +1 -0
  130. data/lib/tdl/exlib/axis_verify.rb +4 -3
  131. data/lib/tdl/exlib/constraints_verb.rb +1 -0
  132. data/lib/tdl/exlib/itegration_verb.rb +212 -169
  133. data/lib/tdl/rebuild_ele/ele_base.rb +15 -10
  134. data/lib/tdl/sdlmodule/sdlmodule.rb +117 -51
  135. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
  136. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +3 -3
  137. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
  138. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
  139. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
  140. data/lib/tdl/sdlmodule/test_unit_module.rb +12 -0
  141. data/lib/tdl/sdlmodule/top_module.rb +13 -10
  142. data/lib/tdl/tdl.rb +1 -11
  143. data/lib/tdl/tdlerror/tdlerror.rb +1 -1
  144. metadata +46 -5
  145. data/CODE_OF_CONDUCT.md +0 -74
  146. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
data/lib/tdl/examples/11_test_unit/exp_test_unit.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: 2021-03-20 12:08:01 +0800
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+ created: 2021-05-04 20:03:48 +0800
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  madified:
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  ***********************************************/
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  `timescale 1ns/1ps
@@ -18,7 +18,7 @@ module exp_test_unit (
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  //==========================================================================
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  //-------- define ----------------------------------------------------------
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  logic enable;
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- axi_stream_inf #(.DSIZE(8),.USIZE(1)) axis_data_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
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+ axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) axis_data_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
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  //==========================================================================
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  //-------- instance --------------------------------------------------------
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  sub_md1 sub_md1_inst(
data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv ADDED
@@ -0,0 +1,9 @@
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+
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+ `timescale 1ns/1ps
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+ module exp_test_unit_sim();
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+ initial begin
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+ #(1us);
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+ $warning("Check TopModule.sim,please!!!");
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+ $stop;
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+ end
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+ endmodule
data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: 2021-03-20 12:08:00 +0800
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+ created: 2021-05-04 20:03:33 +0800
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  madified:
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  ***********************************************/
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  `timescale 1ns/1ps
@@ -20,7 +20,7 @@ module sub_md0 (
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  logic clock;
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  logic rst_n;
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  logic [10-1:0] cnt ;
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- data_inf_c #(.DSIZE(8)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
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+ data_inf_c #(.DSIZE(8),.FreqM(axis_in.FreqM)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
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  //==========================================================================
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  //-------- instance --------------------------------------------------------
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data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: 2021-03-20 12:08:00 +0800
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+ created: 2021-05-04 20:03:33 +0800
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  madified:
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  ***********************************************/
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  `timescale 1ns/1ps
@@ -20,7 +20,7 @@ module sub_md1 (
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  logic clock;
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  logic rst_n;
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  logic [10-1:0] cnt ;
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- data_inf_c #(.DSIZE(8)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
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+ data_inf_c #(.DSIZE(8),.FreqM(axis_out.FreqM)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
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  //==========================================================================
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  //-------- instance --------------------------------------------------------
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data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: 2021-03-20 12:08:01 +0800
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+ created: 2021-05-04 20:03:48 +0800
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  madified:
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  ***********************************************/
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  `timescale 1ns/1ps
data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv ADDED
@@ -0,0 +1,41 @@
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+ /**********************************************
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+ _______________________________________
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+ ___________ Cook Darwin __________
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+ _______________________________________
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+ descript:
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+ author : Cook.Darwin
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+ Version: VERA.0.0
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+ created: 2021-04-03 14:05:10 +0800
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+ madified:
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+ ***********************************************/
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+ `timescale 1ns/1ps
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+
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+ module tb_exp_test_unit_sim();
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+ //==========================================================================
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+ //-------- define ----------------------------------------------------------
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+ logic sys_clk;
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+ string test_unit_region;
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+ logic [2-1:0] unit_pass_u ;
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+ logic [2-1:0] unit_pass_d ;
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+
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+ //==========================================================================
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+ //-------- instance --------------------------------------------------------
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+ exp_test_unit_sim rtl_top(
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+ /* input clock */.clock (sys_clk ),
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+ /* input reset */.rst_n (1'b1 )
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+ );
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+ tu0 test_unit_0(
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+ /* input */.from_up_pass (unit_pass_u[0] ),
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+ /* output */.to_down_pass (unit_pass_d[0] )
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+ );
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+ tu1 test_unit_1(
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+ /* input */.from_up_pass (unit_pass_u[1] ),
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+ /* output */.to_down_pass (unit_pass_d[1] )
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+ );
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+ //==========================================================================
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+ //-------- expression ------------------------------------------------------
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+ assign unit_pass_u[0] = 1'b1;
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+
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+ assign unit_pass_u[1] = unit_pass_d[0];
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+
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+ endmodule
data/lib/tdl/examples/11_test_unit/tu0.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: 2021-03-20 12:08:00 +0800
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+ created: 2021-05-04 20:03:48 +0800
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  madified:
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  ***********************************************/
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  `timescale 1ns/1ps
@@ -28,6 +28,7 @@ initial begin
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  to_down_pass = 1'b0;
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  wait(from_up_pass);
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  $root.tb_exp_test_unit.test_unit_region = "tu0";
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+ $display("--------------- Current test_unit <%0s> --------------------", "tu0");
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  $root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b1;
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  #(1us);
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  $root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b0;
data/lib/tdl/examples/1_define_module/exmple_md.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: xxxx.xx.xx
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+ created: 2021-03-29 17:23:25 +0800
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  madified:
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  ***********************************************/
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  `timescale 1ns/1ps
data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: xxxx.xx.xx
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+ created: 2021-05-04 20:03:33 +0800
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  ***********************************************/
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  `timescale 1ns/1ps
@@ -15,8 +15,8 @@ module always_comb_test ();
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  //-------- define ----------------------------------------------------------
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  logic [1-1:0] tmp0[9-1:0][2-1:0] ;
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  logic tmp1;
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- data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
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- data_inf_c #(.DSIZE(18)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
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+ data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
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+ data_inf_c #(.DSIZE(18),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
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  //==========================================================================
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  //-------- instance --------------------------------------------------------
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data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: xxxx.xx.xx
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+ created: 2021-05-04 20:03:32 +0800
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  ***********************************************/
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  `timescale 1ns/1ps
@@ -21,8 +21,8 @@ module always_ff_test (
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  //-------- define ----------------------------------------------------------
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  logic [1-1:0] tmp0[9-1:0][2-1:0] ;
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  logic tmp1;
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- data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
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- data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
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+ data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
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+ data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
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  //==========================================================================
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  //-------- instance --------------------------------------------------------
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data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: xxxx.xx.xx
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+ created: 2021-05-04 20:03:33 +0800
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  ***********************************************/
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  `timescale 1ns/1ps
@@ -21,8 +21,8 @@ module case_test (
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  //-------- define ----------------------------------------------------------
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  logic [1-1:0] tmp0[9-1:0][2-1:0] ;
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  logic tmp1;
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- data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
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- data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
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+ data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
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+ data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
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  //==========================================================================
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  //-------- instance --------------------------------------------------------
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data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  author : Cook.Darwin
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7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-04-03 13:47:03 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-05-04 20:03:33 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -15,8 +15,8 @@ module simple_assign_test ();
15
15
  //-------- define ----------------------------------------------------------
16
16
  logic [1-1:0] tmp0[9-1:0][2-1:0] ;
17
17
  logic tmp1;
18
- data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
19
- data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
18
+ data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
19
+ data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
20
20
  //==========================================================================
21
21
  //-------- instance --------------------------------------------------------
22
22
 
data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-05-04 20:03:32 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -21,8 +21,8 @@ module state_case_test (
21
21
  //-------- define ----------------------------------------------------------
22
22
  logic [1-1:0] tmp0[9-1:0][2-1:0] ;
23
23
  logic tmp1;
24
- data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
25
- data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
24
+ data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
25
+ data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
26
26
  //==========================================================================
27
27
  //-------- instance --------------------------------------------------------
28
28
 
data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-04-03 13:47:04 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-05-04 20:03:33 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -21,9 +21,9 @@ module test_module (
21
21
  //==========================================================================
22
22
  //-------- define ----------------------------------------------------------
23
23
  logic [axi_wr_inf.ASIZE-1:0] addr ;
24
- logic [axi_wr_inf.IDSIZE-4-1:0] id ;
24
+ logic [(axi_wr_inf.IDSIZE - 4)-1:0] id ;
25
25
  logic [24-1:0] length ;
26
- axi_inf #(.DSIZE(axi_wr_inf.DSIZE),.IDSIZE(axi_wr_inf.IDSIZE-4),.ASIZE(axi_wr_inf.ASIZE),.LSIZE(24),.MODE("ONLY_WRITE"),.ADDR_STEP(8192)) pre_axi_wr_inf (.axi_aclk(axi_wr_inf.axi_aclk),.axi_aresetn(axi_wr_inf.axi_aresetn)) ;
26
+ axi_inf #(.DSIZE(axi_wr_inf.DSIZE),.IDSIZE((axi_wr_inf.IDSIZE - 4)),.ASIZE(axi_wr_inf.ASIZE),.LSIZE(24),.MODE("ONLY_WRITE"),.ADDR_STEP(8192),.FreqM(1.0)) pre_axi_wr_inf (.axi_aclk(axi_wr_inf.axi_aclk),.axi_aresetn(axi_wr_inf.axi_aresetn)) ;
27
27
  //==========================================================================
28
28
  //-------- instance --------------------------------------------------------
29
29
  axi_stream_cache_35bit cache_inst(
data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-05-04 20:03:33 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -21,7 +21,7 @@ module test_module_port (
21
21
  //==========================================================================
22
22
  //-------- define ----------------------------------------------------------
23
23
 
24
- data_inf_c #(.DSIZE(test_data_inf_c.DSIZE)) inherited_inf (.clock(test_data_inf_c.clock),.rst_n(test_data_inf_c.rst_n)) ;
24
+ data_inf_c #(.DSIZE(test_data_inf_c.DSIZE),.FreqM(test_data_inf_c.FreqM)) inherited_inf (.clock(test_data_inf_c.clock),.rst_n(test_data_inf_c.rst_n)) ;
25
25
  //==========================================================================
26
26
  //-------- instance --------------------------------------------------------
27
27
  test_module_port_sub test_module_port_sub_inst(
data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-03-20 13:20:54 +0800
8
+ created: 2021-05-04 20:03:48 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -19,13 +19,13 @@ module test_module_var #(
19
19
 
20
20
  //==========================================================================
21
21
  //-------- define ----------------------------------------------------------
22
- localparam ASIZE = 20 ;
23
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
24
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
25
- axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;
22
+ localparam ASIZE = 20;
23
+ axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
24
+ axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
25
+ axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295),.FreqM(100)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;
26
26
  data_inf #(.DSIZE(5)) tmp_data_inf();
27
- data_inf_c #(.DSIZE(3)) tmp_data_inf_c (.clock(clock),.rst_n(rst_n)) ;
28
- data_inf_c #(.DSIZE(3)) opopopopo (.clock(clock),.rst_n(rst_n)) ;
27
+ data_inf_c #(.DSIZE(3),.FreqM(100)) tmp_data_inf_c (.clock(clock),.rst_n(rst_n)) ;
28
+ data_inf_c #(.DSIZE(3),.FreqM(100)) opopopopo (.clock(clock),.rst_n(rst_n)) ;
29
29
  //==========================================================================
30
30
  //-------- instance --------------------------------------------------------
31
31
 
data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv CHANGED
@@ -5,12 +5,13 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-03-20 12:10:27 +0800
8
+ created: 2021-04-03 12:04:33 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
 
12
12
 
13
- module test_packageparameter NUM = 6;();
13
+ package test_package;
14
+ parameter NUM = 6;
14
15
  //==========================================================================
15
16
  //-------- define ----------------------------------------------------------
16
17
  typedef struct {
@@ -34,4 +35,4 @@ s_ing s_ing_v1;
34
35
  //-------- expression ------------------------------------------------------
35
36
  assign zing_v0.op[9] = 0;
36
37
 
37
- endmodule
38
+ endpackage:test_package
data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-03-20 13:24:07 +0800
8
+ created: 2021-05-04 20:03:48 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-05-04 20:03:33 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -19,7 +19,7 @@ module main_md (
19
19
  //==========================================================================
20
20
  //-------- define ----------------------------------------------------------
21
21
 
22
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
22
+ axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
23
23
  //==========================================================================
24
24
  //-------- instance --------------------------------------------------------
25
25
  sdl_md sdl_md_inst(
data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-04-03 13:14:02 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
data/lib/tdl/examples/6_module_with_interface/example_interface.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-05-04 20:03:32 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -24,13 +24,13 @@ module example_interface (
24
24
  //==========================================================================
25
25
  //-------- define ----------------------------------------------------------
26
26
 
27
- data_inf_c #(.DSIZE(8)) a_inf (.clock(dim.clock),.rst_n(dim.clock)) ;
28
- data_inf_c #(.DSIZE(8)) c_inf [7:0] (.clock(dim.clock),.rst_n(dim.clock)) ;
29
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) f_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
30
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) g_inf [1:0] (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
31
- axi_lite_inf #(.DSIZE(32),.ASIZE(32)) h_inf (.axi_aclk(alm.axi_aclk),.axi_aresetn(alm.axi_aresetn)) ;
32
- axi_inf #(.DSIZE(32),.IDSIZE(3),.ASIZE(32),.LSIZE(10),.MODE("BOTH"),.ADDR_STEP(4096)) i_inf (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
33
- axi_inf #(.DSIZE(31),.IDSIZE(3),.ASIZE(37),.LSIZE(12),.MODE("BOTH"),.ADDR_STEP(1024)) j_inf [8:0][4:0][2:0] (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
27
+ data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dim.clock),.rst_n(dim.clock)) ;
28
+ data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [7:0] (.clock(dim.clock),.rst_n(dim.clock)) ;
29
+ axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) f_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
30
+ axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) g_inf [1:0] (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
31
+ axi_lite_inf #(.DSIZE(32),.ASIZE(32),.FreqM(103)) h_inf (.axi_aclk(alm.axi_aclk),.axi_aresetn(alm.axi_aresetn)) ;
32
+ axi_inf #(.DSIZE(32),.IDSIZE(3),.ASIZE(32),.LSIZE(10),.MODE("BOTH"),.ADDR_STEP(4096),.FreqM(103)) i_inf (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
33
+ axi_inf #(.DSIZE(31),.IDSIZE(3),.ASIZE(37),.LSIZE(12),.MODE("BOTH"),.ADDR_STEP(1024),.FreqM(103)) j_inf [8:0][4:0][2:0] (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
34
34
  //==========================================================================
35
35
  //-------- instance --------------------------------------------------------
36
36
 
data/lib/tdl/examples/6_module_with_interface/inf_collect.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-05-04 20:03:32 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -24,14 +24,14 @@ module inf_collect (
24
24
  //==========================================================================
25
25
  //-------- define ----------------------------------------------------------
26
26
 
27
- data_inf_c #(.DSIZE(8)) a_inf (.clock(dim.clock),.rst_n(dim.clock)) ;
28
- data_inf_c #(.DSIZE(8)) c_inf [7:0] (.clock(dim.clock),.rst_n(dim.clock)) ;
29
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) f_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
30
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) p_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
31
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) g_inf [1:0] (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
32
- axi_lite_inf #(.DSIZE(32),.ASIZE(32)) h_inf (.axi_aclk(alm.axi_aclk),.axi_aresetn(alm.axi_aresetn)) ;
33
- axi_inf #(.DSIZE(32),.IDSIZE(3),.ASIZE(32),.LSIZE(10),.MODE("BOTH"),.ADDR_STEP(4096)) i_inf (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
34
- axi_inf #(.DSIZE(31),.IDSIZE(3),.ASIZE(37),.LSIZE(12),.MODE("BOTH"),.ADDR_STEP(1024)) j_inf [8:0][4:0][2:0] (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
27
+ data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dim.clock),.rst_n(dim.clock)) ;
28
+ data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [7:0] (.clock(dim.clock),.rst_n(dim.clock)) ;
29
+ axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) f_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
30
+ axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) p_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
31
+ axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) g_inf [1:0] (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
32
+ axi_lite_inf #(.DSIZE(32),.ASIZE(32),.FreqM(103)) h_inf (.axi_aclk(alm.axi_aclk),.axi_aresetn(alm.axi_aresetn)) ;
33
+ axi_inf #(.DSIZE(32),.IDSIZE(3),.ASIZE(32),.LSIZE(10),.MODE("BOTH"),.ADDR_STEP(4096),.FreqM(103)) i_inf (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
34
+ axi_inf #(.DSIZE(31),.IDSIZE(3),.ASIZE(37),.LSIZE(12),.MODE("BOTH"),.ADDR_STEP(1024),.FreqM(103)) j_inf [8:0][4:0][2:0] (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
35
35
  //==========================================================================
36
36
  //-------- instance --------------------------------------------------------
37
37