axi_tdl 0.0.19 → 0.1.7

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Files changed (146) hide show
  1. checksums.yaml +4 -4
  2. data/Rakefile +7 -0
  3. data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
  4. data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
  5. data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
  6. data/lib/axi/AXI4/axi4_dpram_cache.sv +10 -10
  7. data/lib/axi/AXI4/axi4_rd_burst_track.sv +2 -1
  8. data/lib/axi/AXI4/axi4_wr_burst_track.sv +2 -1
  9. data/lib/axi/AXI4/axis_to_axi4_wr.sv +9 -9
  10. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
  11. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +5 -5
  12. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
  13. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +9 -9
  14. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
  15. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
  16. data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
  17. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
  18. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  19. data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
  20. data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
  21. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  22. data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +50 -0
  23. data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
  24. data/lib/axi/common/common_ram_wrapper.sv +1 -1
  25. data/lib/axi/common/test_write_mem.sv +1 -1
  26. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +13 -13
  27. data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
  28. data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
  29. data/lib/axi/platform_ip/long_fifo_verb.sv +1 -1
  30. data/lib/axi/platform_ip/wide_fifo.sv +1 -1
  31. data/lib/axi/platform_ip/xilinx_fifo_verb.sv +1 -1
  32. data/lib/axi/platform_ip/xilinx_fifo_verc.sv +2 -1
  33. data/lib/axi/techbench/tb_axi_stream_split_channel.rb +2 -1
  34. data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
  35. data/lib/axi_tdl.rb +31 -1
  36. data/lib/axi_tdl/version.rb +1 -1
  37. data/lib/public_atom_module/CheckPClock.sv +53 -0
  38. data/lib/public_atom_module/LICENSE.md +674 -0
  39. data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
  40. data/lib/public_atom_module/bits_decode.sv +71 -0
  41. data/lib/public_atom_module/bits_decode_verb.sv +71 -0
  42. data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
  43. data/lib/public_atom_module/broaden.v +43 -0
  44. data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
  45. data/lib/public_atom_module/ceiling.v +39 -0
  46. data/lib/public_atom_module/ceiling_A1.v +42 -0
  47. data/lib/public_atom_module/clock_rst.sv +64 -0
  48. data/lib/public_atom_module/cross_clk_sync.v +37 -0
  49. data/lib/public_atom_module/edge_generator.v +50 -0
  50. data/lib/public_atom_module/flooring.v +36 -0
  51. data/lib/public_atom_module/latch_data.v +30 -0
  52. data/lib/public_atom_module/latency.v +48 -0
  53. data/lib/public_atom_module/latency_dynamic.v +83 -0
  54. data/lib/public_atom_module/latency_long.v +84 -0
  55. data/lib/public_atom_module/latency_verb.v +52 -0
  56. data/lib/public_atom_module/once_event.sv +65 -0
  57. data/lib/public_atom_module/pipe_reg.v +93 -0
  58. data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
  59. data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
  60. data/lib/public_atom_module/sim/clock_rst_verc.sv +69 -0
  61. data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
  62. data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
  63. data/lib/public_atom_module/sim_system_pkg.sv +4 -0
  64. data/lib/public_atom_module/synth_system_pkg.sv +4 -0
  65. data/lib/tdl/Logic/logic_edge.rb +1 -1
  66. data/lib/tdl/auto_script/import_hdl.rb +39 -4
  67. data/lib/tdl/axi4/axi4_interconnect_verb.rb +47 -10
  68. data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
  69. data/lib/tdl/class_hdl/hdl_always_ff.rb +2 -2
  70. data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
  71. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
  72. data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
  73. data/lib/tdl/class_hdl/hdl_function.rb +4 -4
  74. data/lib/tdl/class_hdl/hdl_generate.rb +4 -1
  75. data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
  76. data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
  77. data/lib/tdl/class_hdl/hdl_package.rb +45 -0
  78. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
  79. data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
  80. data/lib/tdl/elements/Reset.rb +5 -9
  81. data/lib/tdl/elements/clock.rb +5 -9
  82. data/lib/tdl/elements/data_inf.rb +0 -17
  83. data/lib/tdl/elements/logic.rb +9 -31
  84. data/lib/tdl/elements/mail_box.rb +6 -1
  85. data/lib/tdl/elements/originclass.rb +17 -47
  86. data/lib/tdl/elements/parameter.rb +5 -6
  87. data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
  88. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +2 -2
  89. data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +9 -0
  90. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +2 -2
  91. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +2 -2
  92. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
  93. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +41 -0
  94. data/lib/tdl/examples/11_test_unit/tu0.sv +2 -1
  95. data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
  96. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +3 -3
  97. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +3 -3
  98. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +3 -3
  99. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
  100. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +3 -3
  101. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +3 -3
  102. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
  103. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
  104. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +2 -2
  105. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +7 -7
  106. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
  107. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  108. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +2 -2
  109. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
  110. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +8 -8
  111. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +9 -9
  112. data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
  113. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
  114. data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
  115. data/lib/tdl/examples/8_top_module/dve.tcl +155 -2
  116. data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
  117. data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +29 -0
  118. data/lib/tdl/examples/8_top_module/test_top.sv +7 -26
  119. data/lib/tdl/examples/8_top_module/test_top_sim.sv +28 -0
  120. data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +13 -0
  121. data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +35 -0
  122. data/lib/tdl/examples/9_itegration/dve.tcl +155 -2
  123. data/lib/tdl/examples/9_itegration/tb_test_top.sv +2 -2
  124. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -1
  125. data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +38 -0
  126. data/lib/tdl/examples/9_itegration/test_top.sv +4 -4
  127. data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
  128. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +40 -0
  129. data/lib/tdl/examples/9_itegration/top.rb +1 -0
  130. data/lib/tdl/exlib/axis_verify.rb +4 -3
  131. data/lib/tdl/exlib/constraints_verb.rb +1 -0
  132. data/lib/tdl/exlib/itegration_verb.rb +212 -169
  133. data/lib/tdl/rebuild_ele/ele_base.rb +15 -10
  134. data/lib/tdl/sdlmodule/sdlmodule.rb +117 -51
  135. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
  136. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +3 -3
  137. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
  138. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
  139. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
  140. data/lib/tdl/sdlmodule/test_unit_module.rb +12 -0
  141. data/lib/tdl/sdlmodule/top_module.rb +13 -10
  142. data/lib/tdl/tdl.rb +1 -11
  143. data/lib/tdl/tdlerror/tdlerror.rb +1 -1
  144. metadata +46 -5
  145. data/CODE_OF_CONDUCT.md +0 -74
  146. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
@@ -66,7 +66,34 @@ class Axi4
66
66
  # next unless e.is_a? Axi4
67
67
  if e.is_a? Axi4
68
68
  e.band_params_from(self)
69
- @interconnect_up_streams << e
69
+
70
+ ## e is a Vector
71
+ if e.dimension[0].is_a?(Integer) && e.dimension[0] > 1
72
+ # require_hdl 'axi4_direct_B1.sv'
73
+ require_hdl 'axi4_direct_verc.sv'
74
+
75
+ e.dimension[0].times do |xi|
76
+ _ne = e.copy(name: "#{e.inst_name}_toM_#{xi}")
77
+ # _ne << e[xi]
78
+ # belong_to_module.Instance('axi4_direct_B1',"axi4_direc_#{e.inst_name}_toM_#{xi}") do |h|
79
+ # # h.param.MODE mode_str #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
80
+ # h.slaver_inf e[xi]
81
+ # h.master_inf _ne
82
+ # end
83
+
84
+ belong_to_module.Instance('axi4_direct_verc',"axi4_direc_#{e.inst_name}_toM_#{xi}") do |h|
85
+ h.param.MODE "#{_ne.mode}_to_#{_ne.mode}" # //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
86
+ h.param.SLAVER_MODE _ne.mode # //
87
+ h.param.MASTER_MODE _ne.mode # //
88
+ h.slaver_inf e[xi]
89
+ h.master_inf _ne
90
+ end
91
+
92
+ @interconnect_up_streams << _ne
93
+ end
94
+ else
95
+ @interconnect_up_streams << e
96
+ end
70
97
  else
71
98
  raise TdlError.new("When use `<<` for axi4's M2S ,argvs must be axi4 too.\nOtherwise use `naxi4_mix_interconnect_M2S` directly")
72
99
  end
@@ -218,11 +245,20 @@ class Axi4
218
245
  else
219
246
  mode_str = "ONLY_READ_to_BOTH"
220
247
  end
221
- require_hdl 'axi4_direct_B1.sv'
222
- # Axi4.axi4_direct_a1(mode:mode_str,slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
223
- belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
224
- # h.param.MODE mode_str #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
225
- h.slaver_inf lo
248
+ # require_hdl 'axi4_direct_B1.sv'
249
+ # # Axi4.axi4_direct_a1(mode:mode_str,slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
250
+ # belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
251
+ # # h.param.MODE mode_str #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
252
+ # h.slaver_inf lo
253
+ # h.master_inf "#{sub_name}[#{index}]".to_nq
254
+ # end
255
+
256
+ require_hdl 'axi4_direct_verc.sv'
257
+ belong_to_module.Instance('axi4_direct_verc',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
258
+ h.param.MODE mode_str # //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
259
+ h.param.SLAVER_MODE (wr_lg ? "ONLY_WRITE" : "ONLY_READ") # //
260
+ h.param.MASTER_MODE "BOTH" # //
261
+ h.slaver_inf (lo.respond_to?(:dimension) && lo.dimension[0]==1 && lo[0]) || lo
226
262
  h.master_inf "#{sub_name}[#{index}]".to_nq
227
263
  end
228
264
 
@@ -252,10 +288,11 @@ class Axi4
252
288
  @_long_slim_to_wide.each do |e|
253
289
  mode_str = e.mode + "_to_BOTH"
254
290
  # Axi4.axi4_direct_a1(mode:mode_str,slaver:e,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
291
+ require_hdl 'axi4_direct_B1.sv'
255
292
  belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_inst_long_to_wide_#{sub_name}") do |h|
256
293
  # h.param.MODE mode_str #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
257
- h.slaver e
258
- h.master "#{sub_name}[#{index}]".to_nq
294
+ h.slaver_inf e
295
+ h.master_inf "#{sub_name}[#{index}]".to_nq
259
296
  end
260
297
  index = index + 1
261
298
  end
@@ -311,8 +348,8 @@ class Axi4
311
348
  "\naxi4_direct_B1 /* #(
312
349
  .MODE (\"#{_str}\") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
313
350
  )*/ iterconnect_direct_A1_#{name}_instMM(
314
- /* axi_inf.slaver */ .slaver (sub_axi_#{name}_inf[0]),
315
- /* axi_inf.master */ .master (#{name})
351
+ /* axi_inf.slaver */ .slaver_inf (sub_axi_#{name}_inf[0]),
352
+ /* axi_inf.master */ .master_inf (#{name})
316
353
  );\n"
317
354
  end
318
355
 
@@ -7,6 +7,9 @@ module ClassHDL
7
7
  def initialize(belong_to_module)
8
8
  @opertor_chains = []
9
9
  @belong_to_module = belong_to_module
10
+ unless @belong_to_module
11
+ raise TdlError.new("HDLAlwaysCombBlock must have belong_to_module")
12
+ end
10
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  end
11
14
 
12
15
  def instance
@@ -17,7 +20,7 @@ module ClassHDL
17
20
  str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
18
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  else
19
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  unless op.slaver
20
- rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
23
+ rel_str = ClassHDL.compact_op_ch(op.instance(:assign, @belong_to_module))
21
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  str.push " #{rel_str};"
22
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  end
23
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  end
@@ -63,7 +63,7 @@ module ClassHDL
63
63
  str.push op.instance(:always_ff).gsub(/^./){ |m| " #{m}"}
64
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  else
65
65
  unless op.slaver
66
- rel_str = ClassHDL.compact_op_ch(op.instance(:always_ff))
66
+ rel_str = ClassHDL.compact_op_ch(op.instance(:always_ff, belong_to_module))
67
67
  str.push " #{rel_str};"
68
68
  end
69
69
  end
@@ -143,7 +143,7 @@ module ClassHDL
143
143
  str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
144
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  else
145
145
  unless op.slaver
146
- rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
146
+ rel_str = ClassHDL.compact_op_ch(op.instance(:assign, belong_to_module))
147
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  str.push " #{rel_str};"
148
148
  end
149
149
  end
@@ -8,14 +8,20 @@ module ClassHDL
8
8
  def initialize(belong_to_module)
9
9
  @opertor_chains = []
10
10
  @belong_to_module = belong_to_module
11
+ unless @belong_to_module
12
+ raise TdlError.new("HDLAssignBlock must have belong_to_module")
13
+ end
11
14
  end
12
15
 
13
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  def instance
17
+ unless @belong_to_module.is_a?(SdlModule)
18
+ raise TdlError.new("HDLAssignBlock must have belong_to_module")
19
+ end
14
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  str = []
15
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  opertor_chains.each do |op|
16
22
 
17
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  unless op.slaver
18
- sub_str = op.instance(:assign)
24
+ sub_str = op.instance(:assign,belong_to_module)
19
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  # if sub_str =~ /^(?<head>[\w\.\[\]\:]+\s*)(?<eq><?=\s*)\((?<body>.+)\)$/
20
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  # rel_str = $~[:head] + $~[:eq] + $~[:body]
21
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  # else
@@ -11,7 +11,7 @@ module ClassHDL
11
11
 
12
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  def instance(as_type= :cond)
13
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  if cond.is_a? ClassHDL::OpertorChain
14
- head_str = "if(#{cond.instance(:cond)})begin"
14
+ head_str = "if(#{cond.instance(:cond, belong_to_module)})begin"
15
15
  else
16
16
  head_str = "if(#{cond.to_s})begin"
17
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  end
@@ -20,7 +20,7 @@ module ClassHDL
20
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  opertor_chains.each do |oc|
21
21
  unless oc.is_a? BlockIF
22
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  unless oc.slaver
23
- rel_str = ClassHDL.compact_op_ch(oc.instance(as_type))
23
+ rel_str = ClassHDL.compact_op_ch(oc.instance(as_type, belong_to_module))
24
24
  sub_str.push " #{rel_str};"
25
25
  end
26
26
  else
@@ -36,7 +36,7 @@ module ClassHDL
36
36
  class BlockELSIF < BlockIF
37
37
  def instance(as_type= :cond)
38
38
  if cond.is_a? ClassHDL::OpertorChain
39
- head_str = "else if(#{cond.instance(:cond)})begin"
39
+ head_str = "else if(#{cond.instance(:cond, belong_to_module)})begin"
40
40
  else
41
41
  head_str = "else if(#{cond.to_s})begin"
42
42
  end
@@ -45,7 +45,7 @@ module ClassHDL
45
45
  opertor_chains.each do |oc|
46
46
  unless oc.is_a? BlockIF
47
47
  unless oc.slaver
48
- sub_str.push " #{oc.instance(as_type)};"
48
+ sub_str.push " #{oc.instance(as_type, belong_to_module)};"
49
49
  end
50
50
  else
51
51
  sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
@@ -66,7 +66,7 @@ module ClassHDL
66
66
  opertor_chains.each do |oc|
67
67
  unless oc.is_a? BlockIF
68
68
  unless oc.slaver
69
- sub_str.push " #{oc.instance(as_type)};"
69
+ sub_str.push " #{oc.instance(as_type, belong_to_module)};"
70
70
  end
71
71
  else
72
72
  sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
@@ -135,7 +135,7 @@ module ClassHDL
135
135
  opertor_chains.each do |oc|
136
136
  unless oc.is_a? BlockIF
137
137
  unless oc.slaver
138
- sub_str.push " #{oc.instance(as_type)};"
138
+ sub_str.push " #{oc.instance(as_type, belong_to_module)};"
139
139
  end
140
140
  else
141
141
  sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
@@ -168,7 +168,7 @@ module ClassHDL
168
168
  opertor_chains.each do |oc|
169
169
  unless oc.is_a? BlockIF
170
170
  unless oc.slaver
171
- sub_str.push " #{oc.instance(as_type)};"
171
+ sub_str.push " #{oc.instance(as_type, belong_to_module)};"
172
172
  end
173
173
  else
174
174
  sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
@@ -10,7 +10,7 @@ module ClassHDL
10
10
  opertor_chains.each do |oc|
11
11
  unless oc.is_a? BlockIF
12
12
  unless oc.slaver
13
- sub_str.push " #{oc.instance(as_type)};"
13
+ sub_str.push " #{oc.instance(as_type, belong_to_module)};"
14
14
  end
15
15
  else
16
16
  sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
@@ -36,7 +36,7 @@ module ClassHDL
36
36
  opertor_chains.each do |oc|
37
37
  unless oc.is_a? BlockIF
38
38
  unless oc.slaver
39
- sub_str.push " #{oc.instance(as_type)};"
39
+ sub_str.push " #{oc.instance(as_type,belong_to_module)};"
40
40
  end
41
41
  else
42
42
  sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
@@ -13,7 +13,7 @@ module ClassHDL
13
13
  if @func_inst.return_type.is_a? StructMeta
14
14
  @func_inst.return_type.struct_slots.each do |e|
15
15
  self.define_singleton_method(e.name) do
16
- TdlSpace::ArrayChain.new("#{@func_inst.name}.#{e.name}".to_nq)
16
+ TdlSpace::ArrayChain.create(obj: "#{@func_inst.name}.#{e.name}".to_nq, belong_to_module: @func_inst.belong_to_module )
17
17
  end
18
18
  end
19
19
  end
@@ -90,7 +90,7 @@ module ClassHDL
90
90
  str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
91
91
  else
92
92
  unless op.slaver
93
- rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
93
+ rel_str = ClassHDL.compact_op_ch(op.instance(:assign,belong_to_module))
94
94
  str.push " #{rel_str};"
95
95
  end
96
96
  end
@@ -193,7 +193,7 @@ module ClassHDL
193
193
  # pin,iostd = parse_pin_prop(pin_prop) if pin_prop
194
194
  # RedefOpertor.with_normal_operators do
195
195
  ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
196
- tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension)
196
+ tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension, belong_to_module: self)
197
197
  # add_to_new_module("@port_logics",tmp)
198
198
  # add_method_to_itgt(name,tmp)
199
199
  tmp
@@ -205,7 +205,7 @@ module ClassHDL
205
205
  # pin,iostd = parse_pin_prop(pin_prop) if pin_prop
206
206
  # RedefOpertor.with_normal_operators do
207
207
  ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
208
- tmp = Logic.new(name:name,dsize:dsize,port:"output logic",dimension:dimension)
208
+ tmp = Logic.new(name:name,dsize:dsize,port:"output logic",dimension:dimension, belong_to_module: self)
209
209
  # add_to_new_module("@port_logics",tmp)
210
210
 
211
211
  if block_given?
@@ -20,6 +20,9 @@ module ClassHDL
20
20
  def initialize(belong_to_module)
21
21
  @belong_to_module = belong_to_module
22
22
  super("genblk#{globle_random_name_flag()}")
23
+ unless @belong_to_module
24
+ raise TdlError.new("GenerateBlock must have belong_to_module")
25
+ end
23
26
  end
24
27
 
25
28
 
@@ -41,7 +44,7 @@ module ClassHDL
41
44
  def IF(cond,&block)
42
45
  if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? HDLAssignGenerateBlock
43
46
  if cond.respond_to?(:instance)
44
- head_str = "\nif(#{cond.instance(:cond)})begin\n"
47
+ head_str = "\nif(#{cond.instance(:cond, @belong_to_module)})begin\n"
45
48
  else
46
49
  head_str = "\nif(#{cond})begin\n"
47
50
  end
@@ -7,6 +7,9 @@ module ClassHDL
7
7
  def initialize(belong_to_module)
8
8
  @opertor_chains = []
9
9
  @belong_to_module = belong_to_module
10
+ unless @belong_to_module
11
+ raise TdlError.new("HDLInitialBlock must have belong_to_module")
12
+ end
10
13
  end
11
14
 
12
15
  def instance(block_name=nil)
@@ -17,7 +20,26 @@ module ClassHDL
17
20
  str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
18
21
  else
19
22
  unless op.slaver
20
- rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
23
+ rel_str = ClassHDL.compact_op_ch(op.instance(:assign, belong_to_module))
24
+ str.push " #{rel_str};"
25
+ end
26
+ end
27
+
28
+ end
29
+ str.push "end\n"
30
+ str.join("\n")
31
+ end
32
+
33
+ def instance_inspect()
34
+ str = []
35
+ block_name=nil
36
+ str.push "initial begin#{block_name ? ':'.concat(block_name.to_s) : ''}"
37
+ opertor_chains.each do |op|
38
+ unless op.is_a? OpertorChain
39
+ str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
40
+ else
41
+ unless op.slaver
42
+ rel_str = ClassHDL.compact_op_ch(op.instance(:assign,belong_to_module))
21
43
  str.push " #{rel_str};"
22
44
  end
23
45
  end
@@ -41,7 +63,7 @@ module ClassHDL
41
63
  class BlocAssertIF < BlockIF
42
64
  def instance(as_type= :cond)
43
65
  if cond.is_a? ClassHDL::OpertorChain
44
- head_str = "assert(#{cond.instance(:cond)})else begin"
66
+ head_str = "assert(#{cond.instance(:cond, belong_to_module)})else begin"
45
67
  else
46
68
  head_str = "assert(#{cond.to_s})else begin"
47
69
  end
@@ -50,7 +72,7 @@ module ClassHDL
50
72
  opertor_chains.each do |oc|
51
73
  unless oc.is_a? BlockIF
52
74
  unless oc.slaver
53
- sub_str.push " #{oc.instance(as_type)};"
75
+ sub_str.push " #{oc.instance(as_type,belong_to_module)};"
54
76
  end
55
77
  else
56
78
  sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
@@ -170,6 +170,9 @@ module ClassHDL
170
170
  def initialize(sdlm,args={})
171
171
  @chain = []
172
172
  @sdlm = sdlm
173
+ unless @sdlm
174
+ raise TdlError.new("ImplicitPortBase<#{args.to_s}> dont have belong_to_module")
175
+ end
173
176
  @up_args = args
174
177
  end
175
178
 
@@ -298,7 +301,7 @@ module ClassHDL
298
301
  if sub_type.is_a? StructMeta
299
302
  @sub_type.struct_slots.each do |e|
300
303
  obj.define_singleton_method(e.name) do
301
- TdlSpace::ArrayChain.new("#{obj.name}.#{e.name}".to_nq)
304
+ TdlSpace::ArrayChain.create(obj: "#{obj.name}.#{e.name}".to_nq, belong_to_module: obj.belong_to_module)
302
305
  end
303
306
  end
304
307
  end
@@ -380,27 +383,27 @@ class SdlModule
380
383
 
381
384
  def >>(*args)
382
385
  str = "{>>{#{args.map{|e| e.to_s }.join(',')}}}"
383
- TdlSpace::ArrayChain.new(str)
386
+ TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
384
387
  end
385
388
 
386
389
  def <<(*args)
387
390
  str = "{<<{#{args.map{|e| e.to_s }.join(',')}}}"
388
- TdlSpace::ArrayChain.new(str)
391
+ TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
389
392
  end
390
393
 
391
394
  def logic_bind_(*args)
392
395
  str = "{#{args.map{|e| e.to_s }.join(',')}}"
393
- TdlSpace::ArrayChain.new(str)
396
+ TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
394
397
  end
395
398
 
396
399
  def clog2(arg)
397
400
  str = "$clog2(#{arg.to_s})"
398
- TdlSpace::ArrayChain.new(str)
401
+ TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
399
402
  end
400
403
 
401
404
  def bits(arg)
402
405
  str = "$bits(#{arg.to_s})"
403
- TdlSpace::ArrayChain.new(str)
406
+ TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
404
407
  end
405
408
 
406
409
  end
@@ -90,6 +90,51 @@ module ClassHDL
90
90
  return str
91
91
  end
92
92
 
93
+ def build_module_verb(ex_param: "",ex_port: "",ex_up_code: "",ex_down_code: "")
94
+ # Tdl.Puts pagination(module_name)
95
+ Tdl.Build_SdlModule_Puts(module_name)
96
+
97
+ ex_param = ex_param.to_s unless ex_param
98
+ ex_port = ex_port.to_s unless ex_port
99
+ ex_up_code = ex_up_code.to_s unless ex_up_code
100
+ ex_down_code = ex_down_code.to_s unless ex_down_code
101
+
102
+ # gen_auto_method # auto generate class method for interface
103
+ # draw = Tdl.inst + Tdl.draw
104
+
105
+ instance_draw_str = instance_draw # It must run before vars_define_inst,because some signals define when inst
106
+ vars_exec_inst_str = vars_exec_inst # It must run before vars_define_inst,because some signals define when vars exec
107
+
108
+ post_str = post_inst_stack_call()
109
+
110
+ unless post_str.strip.empty?
111
+ post_str = pagination("ROOT REF") + post_str
112
+ end
113
+
114
+ draw = pagination("define") + vars_define_inst + pagination("instance") + instance_draw_str + pagination("expression") + vars_exec_inst_str + post_str
115
+
116
+ unless ex_up_code.empty?
117
+ ex_up_code = "\n//------>> EX CODE <<-------------------\n" + ex_up_code + "//------<< EX CODE >>-------------------\n"
118
+ end
119
+
120
+ unless ex_down_code.empty?
121
+ ex_down_code = "//------>> EX CODE <<-------------------\n" + ex_down_code + "//------<< EX CODE >>-------------------\n"
122
+ end
123
+
124
+
125
+ module_name_str = @module_name
126
+
127
+
128
+ # str = module_head+"package #{module_name_str};\n" + build_params(ex_param) + ex_up_code + draw + ex_down_code + "\nendpackage:#{module_name_str}\n" + add_sub_module_file_paths
129
+ str = "package #{module_name_str};\n" + build_params(ex_param) + ex_up_code + draw + ex_down_code + "\nendpackage:#{module_name_str}\n" + add_sub_module_file_paths
130
+
131
+ create_vivado_tcl if @create_tcl
132
+ create_constraints_file if @create_sdc
133
+
134
+ return [module_head_verb,str]
135
+ end
136
+
137
+
93
138
  end
94
139
 
95
140
  # class ReqPakcgeLine
@@ -47,6 +47,20 @@ module ClassHDL
47
47
  @tree << arg
48
48
  end
49
49
  @belong_to_module = belong_to_module
50
+ unless @belong_to_module
51
+ raise TdlError.new("OpertorChain must have belong_to_module")
52
+ end
53
+ end
54
+
55
+ def instance_inspect
56
+ str = ["self belong_to_module:#{belong_to_module.module_name}"]
57
+ index = 0
58
+ @tree.each do |node|
59
+ bl = "#{node[0].respond_to?(:belong_to_module) ? "belong_to_module:#{node[0].belong_to_module.module_name }" : '' }"
60
+ str << "{{ tree[#{index}][1]node[1]SYMB{#{node[1].to_s}} tree[#{index}][0]node[0]#{node[0].to_s} #{node[0].class} #{bl}}}"
61
+ index += 1
62
+ end
63
+ str.join(" ")
50
64
  end
51
65
 
52
66
  ClassHDL::OP_SYMBOLS.each do |os|
@@ -103,17 +117,20 @@ module ClassHDL
103
117
  # self.nege = true
104
118
  # return self
105
119
  self.slaver = true
106
- new_op = OpertorChain.new(["~(#{self.instance})".to_nq])
120
+ bel = belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
121
+ new_op = OpertorChain.new(["~(#{self.instance(:assign, bel)})".to_nq])
107
122
  end
108
123
 
109
124
  def brackets
110
125
  self.slaver = true
111
- new_op = OpertorChain.new(["(#{self.instance})".to_nq], belong_to_module)
126
+ bel = ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
127
+ new_op = OpertorChain.new(["(#{self.instance(:assign, belong_to_module || bel)})".to_nq], belong_to_module)
112
128
  end
113
129
 
114
130
  def clog2
115
131
  self.slaver = true
116
- new_op = OpertorChain.new(["$clog2(#{self.instance})".to_nq],belong_to_module)
132
+ bel = belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
133
+ new_op = OpertorChain.new(["$clog2(#{self.instance(:aasign, bel)})".to_nq],belong_to_module)
117
134
  end
118
135
 
119
136
  def self.define_op_flag(ruby_op,hdl_op)
@@ -143,10 +160,13 @@ module ClassHDL
143
160
 
144
161
 
145
162
  def to_s
146
- instance(type=:cond)
163
+ instance(type=:cond,belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module ) )
147
164
  end
148
165
 
149
- def instance(type=:assign)
166
+ def instance(type=:assign,block_belong_to_module=nil,show=nil)
167
+ unless block_belong_to_module
168
+ raise TdlError.new("OpertorChain must has block_belong_to_module")
169
+ end
150
170
  AssignDefOpertor.with_rollback_opertors(:old) do
151
171
  str = ''
152
172
  # both_symb_used = false
@@ -160,39 +180,75 @@ module ClassHDL
160
180
  sb = " = "
161
181
  end
162
182
  else
163
- # if(node[1].respond_to?(:belong_to_module) && node[1].belong_to_module && node[1].belong_to_module != belong_to_module)
164
- # sb = "#{node[1].root_ref.to_s}"
165
- # else
166
- sb = "#{node[1].to_s}"
167
- # end
183
+
184
+ sb = "#{node[1].to_s}"
168
185
  end
169
186
  else
170
- # if(node[1].respond_to?(:belong_to_module) && node[1].belong_to_module && node[1].belong_to_module != belong_to_module)
171
- # sb = "#{node[1].root_ref.to_s}"
172
- # else
173
- sb = "#{node[1].to_s}"
174
- # end
187
+ sb = "#{node[1].to_s}"
188
+ end
189
+
190
+ if cnt==1 && show
191
+ puts "tree[1][1]<#{node[1]}> 使用 #{sb}"
175
192
  end
176
193
 
177
194
  unless node[0].is_a? OpertorChain
178
195
  ## 判断是不是属于 Var <= "String" 形式
179
196
  if (@tree.length == 2) && node[0].instance_of?(String) && !@slaver
180
197
  str += (sb + '"' + node[0].to_s + '"')
198
+ if show
199
+ puts "tree 长度等于2; tree[#{cnt}][0] is string; op is not slaver"
200
+ end
181
201
  elsif node[0].instance_of?(String)
182
202
  # "如果是字符串 则原始输出"
183
203
  str += (sb + '"' + node[0].to_s + '"')
204
+ if show
205
+ puts "tree[#{cnt}][0] is string"
206
+ end
184
207
  else
185
208
  # str += (sb + node[0].to_s)
186
- if(node[0].respond_to?(:root_ref) && node[0].respond_to?(:belong_to_module) && node[0].belong_to_module && (node[0].belong_to_module != belong_to_module) && node[0].belong_to_module.top_tb_ref? )
209
+ if block_belong_to_module
210
+ if (node[0].respond_to?(:root_ref) && node[0].respond_to?(:belong_to_module) && node[0].belong_to_module && (node[0].belong_to_module != block_belong_to_module) && node[0].belong_to_module.top_tb_ref? )
211
+
212
+ str += (sb + node[0].root_ref)
213
+
214
+ if show
215
+ puts "tree[#{cnt}][0].belong_to_module<#{node[0].belong_to_module.module_name}> != block_belong_to_module<#{block_belong_to_module.module_name}>"
216
+ end
217
+ ## 反向添加到 TestUnitModule
218
+ if block_belong_to_module.is_a?(TestUnitModule)
219
+ block_belong_to_module.add_root_ref_ele(node[0])
220
+ if show
221
+ puts "block_belong_to_module<#{block_belong_to_module.module_name}> is TestUnitModule"
222
+ end
223
+ end
224
+ else
225
+ str += (sb + node[0].to_s)
226
+ if show
227
+ mmm = node[0].respond_to?(:belong_to_module) && node[0].belong_to_module.module_name
228
+ puts "tree[#{cnt}][0]<#{node[0].class}>: ref_root<#{node[0].respond_to?(:root_ref).to_s}> belong_to_module<#{mmm}> block_belong_to_module<#{block_belong_to_module.module_name}> ...."
229
+ end
230
+ end
231
+ elsif(node[0].respond_to?(:root_ref) && node[0].respond_to?(:belong_to_module) && node[0].belong_to_module && (node[0].belong_to_module != belong_to_module) && node[0].belong_to_module.top_tb_ref? )
187
232
  # sb = "#{node[1].root_ref.to_s}"
188
233
  str += (sb + node[0].root_ref)
234
+
235
+ if show
236
+ puts "tree[#{cnt}][0].belong_to_module<#{node[0].belong_to_module.module_name}> != op.belong_to_module<#{belong_to_module.module_name}>"
237
+ end
238
+
189
239
  ## 反向添加到 TestUnitModule
190
240
  if belong_to_module.is_a?(TestUnitModule)
191
241
  belong_to_module.add_root_ref_ele(node[0])
242
+ if show
243
+ puts "tree[#{cnt}][0]: op.belong_to_module<#{belong_to_module.module_name}> is TestUnitModule"
244
+ end
192
245
  end
193
246
  else
194
247
  # sb = "#{node[1].to_s}"
195
248
  str += (sb + node[0].to_s)
249
+ if show
250
+ puts "tree[#{cnt}][0]: op.belong_to_module<#{belong_to_module.module_name}> ..."
251
+ end
196
252
  end
197
253
  end
198
254
  else
@@ -203,13 +259,17 @@ module ClassHDL
203
259
  # if node[0].tree.length>2 && ["&","|","<",">"].include?(node[0].tree[1][1])
204
260
 
205
261
  # else
262
+
206
263
  if sb =~/(\||&){2,2}/
207
- str += " #{sb}#{node[0].instance(:slaver).to_s}"
264
+ str += " #{sb}#{node[0].instance(:slaver,block_belong_to_module || belong_to_module).to_s}"
208
265
  else
209
- str += "#{sb}(#{node[0].instance(:slaver).to_s})"
266
+ str += "#{sb}(#{node[0].instance(:slaver,block_belong_to_module || belong_to_module).to_s})"
210
267
  end
211
- # end
212
- # str += "#{sb}(#{"Node"})"
268
+
269
+ if show
270
+ puts "tree[#{cnt}][0] is op, block_belong_to_module<#{block_belong_to_module.to_s}> op.belong_to_module<#{belong_to_module.to_s}>"
271
+ end
272
+
213
273
  end
214
274
  cnt += 1
215
275
  end
@@ -235,8 +295,10 @@ module ClassHDL
235
295
 
236
296
  module AssignDefOpertor
237
297
  @@included_class = []
238
- @@curr_assign_block = HDLAssignBlock.new(nil) ##HDLAssignBlock ##HDLAlwaysCombBlock
239
- @@curr_assign_block_stack = [HDLAssignBlock.new(nil) ]
298
+ @@curr_assign_block = HDLAssignBlock.new(true) ##HDLAssignBlock ##HDLAlwaysCombBlock
299
+ # @@curr_assign_block = nil
300
+ @@curr_assign_block_stack = [HDLAssignBlock.new(true) ]
301
+ # @@curr_assign_block_stack = []
240
302
  @@curr_opertor_stack = [:old]
241
303
 
242
304
  def self.curr_opertor_stack
@@ -296,7 +358,18 @@ module ClassHDL
296
358
  b.slaver = true
297
359
  end
298
360
  ## 当 进行 X < Y 等运算时OpertorChain 需要获取 assign block的 belong_to_module
299
- new_op = OpertorChain.new(nil,@@curr_assign_block && @@curr_assign_block.belong_to_module)
361
+ if @@curr_assign_block
362
+ bblm = @@curr_assign_block.belong_to_module
363
+ elsif self.respond_to?(:belong_to_module)
364
+ bblm = self.belong_to_module
365
+ elsif b.respond_to?(:belong_to_module)
366
+ bblm = b.belong_to_module
367
+
368
+ else
369
+ bblm = nil
370
+ end
371
+
372
+ new_op = OpertorChain.new(nil, bblm)
300
373
  new_op.tree.push([self])
301
374
  new_op.tree.push([b,symb])
302
375
  if @@curr_assign_block
@@ -511,7 +584,7 @@ class BaseElm
511
584
 
512
585
  @_array_chain_hash_[name.to_s] = rel
513
586
  end
514
- TdlSpace::ArrayChain.new(@_array_chain_hash_[name.to_s],[])
587
+ TdlSpace::ArrayChain.create(obj: @_array_chain_hash_[name.to_s], lchain:[], belong_to_module: self.belong_to_module)
515
588
  end
516
589
  end
517
590
  end
@@ -576,9 +649,8 @@ module TdlSpace
576
649
  end
577
650
  ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
578
651
  unless b
579
- ArrayChain.new(obj,chain+[a])
652
+ ArrayChain.create(obj: obj,lchain: chain+[a],belong_to_module: belong_to_module)
580
653
  else
581
- # ArrayChain.new(&obj,chain,[a,b])
582
654
  @end_slice = [a,b]
583
655
  self
584
656
  end
@@ -610,7 +682,7 @@ module TdlSpace
610
682
  end
611
683
 
612
684
  def ~
613
- ArrayChain.new("~#{self.to_s}")
685
+ ArrayChain.create(obj: "~#{self.to_s}", belong_to_module: belong_to_module)
614
686
  end
615
687
  end
616
688
  end