qiskit 2.1.0rc1__cp39-abi3-manylinux2014_aarch64.manylinux_2_17_aarch64.whl

qiskit/transpiler/passes/optimization/collect_multiqubit_blocks.py

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+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2017, 2021.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""Collect sequences of uninterrupted gates acting on a number of qubits."""
+
+from qiskit.transpiler.basepasses import AnalysisPass
+from qiskit.circuit import Gate
+from qiskit.dagcircuit import DAGOpNode, DAGInNode
+
+
+class CollectMultiQBlocks(AnalysisPass):
+    """Collect sequences of uninterrupted gates acting on groups of qubits.
+    ``max_block_size`` specifies the maximum number of qubits that can be acted upon
+    by any single group of gates
+
+    Traverse the DAG and find blocks of gates that act consecutively on
+    groups of qubits. Write the blocks to ``property_set`` as a list of blocks
+    of the form::
+
+        [[g0, g1, g2], [g4, g5]]
+
+    Blocks are reported in a valid topological order. Further, the gates
+    within each block are also reported in topological order
+    Some gates may not be present in any block (e.g. if the number
+    of operands is greater than ``max_block_size``)
+
+    By default, blocks are collected in the direction from the inputs towards the
+    outputs of the DAG. The option ``collect_from_back`` allows to change this
+    direction, that is to collect blocks from the outputs towards the inputs.
+    Note that the blocks are still reported in a valid topological order.
+
+    A Disjoint Set Union data structure (DSU) is used to maintain blocks as
+    gates are processed. This data structure points each qubit to a set at all
+    times and the sets correspond to current blocks. These change over time
+    and the data structure allows these changes to be done quickly.
+    """
+
+    def __init__(self, max_block_size=2, collect_from_back=False):
+        super().__init__()
+        self.parent = {}  # parent array for the union
+
+        # the dicts belowed are keyed by a qubit signifying the root of a
+        #    set in the DSU data structure
+        self.bit_groups = {}  # current groups of bits stored at top of trees
+        self.gate_groups = {}  # current gate lists for the groups
+
+        self.max_block_size = max_block_size  # maximum block size
+        self.collect_from_back = collect_from_back  # backward collection
+
+    def find_set(self, index):
+        """DSU function for finding root of set of items
+        If my parent is myself, I am the root. Otherwise we recursively
+        find the root for my parent. After that, we assign my parent to be
+        my root, saving recursion in the future.
+        """
+
+        if index not in self.parent:
+            self.parent[index] = index
+            self.bit_groups[index] = [index]
+            self.gate_groups[index] = []
+        if self.parent[index] == index:
+            return index
+        self.parent[index] = self.find_set(self.parent[index])
+        return self.parent[index]
+
+    def union_set(self, set1, set2):
+        """DSU function for unioning two sets together
+        Find the roots of each set. Then assign one to have the other
+        as its parent, thus liking the sets.
+        Merges smaller set into larger set in order to have better runtime
+        """
+
+        set1 = self.find_set(set1)
+        set2 = self.find_set(set2)
+        if set1 == set2:
+            return
+        if len(self.gate_groups[set1]) < len(self.gate_groups[set2]):
+            set1, set2 = set2, set1
+        self.parent[set2] = set1
+        self.gate_groups[set1].extend(self.gate_groups[set2])
+        self.bit_groups[set1].extend(self.bit_groups[set2])
+        self.gate_groups[set2].clear()
+        self.bit_groups[set2].clear()
+
+    def run(self, dag):
+        """Run the CollectMultiQBlocks pass on `dag`.
+
+        The blocks contain "op" nodes in topological sort order
+        such that all gates in a block act on the same set of
+        qubits and are adjacent in the circuit.
+
+        The blocks are built by examining predecessors and successors of
+        "cx" gates in the circuit. u1, u2, u3, cx, id gates will be included.
+
+        After the execution, ``property_set['block_list']`` is set to
+        a list of tuples of ``DAGNode`` objects
+        """
+
+        self.parent = {}  # reset all variables on run
+        self.bit_groups = {}
+        self.gate_groups = {}
+
+        block_list = []
+
+        def collect_key(x):
+            """special key function for topological ordering.
+            Heuristic for this is to push all gates involving measurement
+            or barriers, etc. as far back as possible (because they force
+            blocks to end). After that, we process gates in order of lowest
+            number of qubits acted on to largest number of qubits acted on
+            because these have less chance of increasing the size of blocks
+            The key also processes all the non operation notes first so that
+            input nodes do not mess with the top sort of op nodes
+            """
+            if isinstance(x, DAGInNode):
+                return "a"
+            if not isinstance(x, DAGOpNode):
+                return "d"
+            if isinstance(x.op, Gate):
+                if x.op.is_parameterized() or getattr(x.op, "_condition", None) is not None:
+                    return "c"
+                return "b" + chr(ord("a") + len(x.qargs))
+            return "d"
+
+        op_nodes = dag.topological_op_nodes(key=collect_key)
+
+        # When collecting from the back, the order of nodes is reversed
+        if self.collect_from_back:
+            op_nodes = reversed(list(op_nodes))
+
+        for nd in op_nodes:
+            can_process = True
+            makes_too_big = False
+
+            # check if the node is a gate and if it is parameterized
+            if (
+                getattr(nd.op, "_condition", None) is not None
+                or nd.op.is_parameterized()
+                or not isinstance(nd.op, Gate)
+            ):
+                can_process = False
+
+            cur_qubits = {dag.find_bit(bit).index for bit in nd.qargs}
+
+            if can_process:
+                # if the gate is valid, check if grouping up the bits
+                # in the gate would fit within our desired max size
+                c_tops = set()
+                for bit in cur_qubits:
+                    c_tops.add(self.find_set(bit))
+                tot_size = 0
+                for group in c_tops:
+                    tot_size += len(self.bit_groups[group])
+                if tot_size > self.max_block_size:
+                    makes_too_big = True
+
+            if not can_process:
+                # resolve the case where we cannot process this node
+                for bit in cur_qubits:
+                    # create a gate out of me
+                    bit = self.find_set(bit)
+                    if len(self.gate_groups[bit]) == 0:
+                        continue
+                    block_list.append(self.gate_groups[bit][:])
+                    cur_set = set(self.bit_groups[bit])
+                    for v in cur_set:
+                        # reset this bit
+                        self.parent[v] = v
+                        self.bit_groups[v] = [v]
+                        self.gate_groups[v] = []
+
+            if makes_too_big:
+                # adding in all of the new qubits would make the group too big
+                # we must block off sub portions of the groups until the new
+                # group would no longer be too big
+                savings = {}
+                tot_size = 0
+                for bit in cur_qubits:
+                    top = self.find_set(bit)
+                    if top in savings:
+                        savings[top] = savings[top] - 1
+                    else:
+                        savings[top] = len(self.bit_groups[top]) - 1
+                        tot_size += len(self.bit_groups[top])
+                slist = []
+                for item, value in savings.items():
+                    slist.append((value, item))
+                slist.sort(reverse=True)
+                savings_need = tot_size - self.max_block_size
+                for item in slist:
+                    # remove groups until the size created would be acceptable
+                    # start with blocking out the group that would decrease
+                    # the new size the most. This heuristic for which blocks we
+                    # create does not necessarily give the optimal blocking. Other
+                    # heuristics may be worth considering
+                    if savings_need > 0:
+                        savings_need = savings_need - item[0]
+                        if len(self.gate_groups[item[1]]) >= 1:
+                            block_list.append(self.gate_groups[item[1]][:])
+                        cur_set = set(self.bit_groups[item[1]])
+                        for v in cur_set:
+                            self.parent[v] = v
+                            self.bit_groups[v] = [v]
+                            self.gate_groups[v] = []
+
+            if can_process:
+                # if the operation is a gate, either skip it if it is too large
+                # or group up all of the qubits involved in the gate
+                if len(cur_qubits) > self.max_block_size:
+                    # gates acting on more qubits than max_block_size cannot
+                    #   be a part of any block and thus we skip them here.
+                    # we have already finalized the blocks involving the gate's
+                    #   qubits in the above makes_too_big block
+                    continue  # unable to be part of a group
+                prev = -1
+                for bit in cur_qubits:
+                    if prev != -1:
+                        self.union_set(prev, bit)
+                    prev = bit
+                self.gate_groups[self.find_set(prev)].append(nd)
+        # need to turn all groups that still exist into their own blocks
+        for index, item in self.parent.items():
+            if item == index and len(self.gate_groups[index]) != 0:
+                block_list.append(self.gate_groups[index][:])
+
+        # When collecting from the back, both the order of the blocks
+        # and the order of nodes in each block should be reversed.
+        if self.collect_from_back:
+            block_list = [block[::-1] for block in block_list[::-1]]
+
+        self.property_set["block_list"] = block_list
+
+        return dag

qiskit/transpiler/passes/optimization/commutation_analysis.py

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+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2017, 2023.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""Analysis pass to find commutation relations between DAG nodes."""
+
+from qiskit.circuit.commutation_library import SessionCommutationChecker as scc
+from qiskit.transpiler.basepasses import AnalysisPass
+from qiskit._accelerate.commutation_analysis import analyze_commutations
+
+
+class CommutationAnalysis(AnalysisPass):
+    r"""Analysis pass to find commutation relations between DAG nodes.
+
+    This sets ``property_set['commutation_set']`` to a dictionary that describes
+    the commutation relations on a given wire: all the gates on a wire
+    are grouped into a set of gates that commute.
+    """
+
+    def __init__(self, *, _commutation_checker=None):
+        super().__init__()
+        # allow setting a private commutation checker, this allows better performance if we
+        # do not care about commutations of all gates, but just a subset
+        if _commutation_checker is None:
+            _commutation_checker = scc
+
+        self.comm_checker = _commutation_checker
+
+    def run(self, dag):
+        """Run the CommutationAnalysis pass on `dag`.
+
+        Run the pass on the DAG, and write the discovered commutation relations
+        into the ``property_set``.
+        """
+        # Initiate the commutation set
+        self.property_set["commutation_set"] = analyze_commutations(dag, self.comm_checker.cc)

qiskit/transpiler/passes/optimization/commutative_cancellation.py

@@ -0,0 +1,82 @@
+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2017, 2019.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""Cancel the redundant (self-adjoint) gates through commutation relations."""
+from qiskit.transpiler.basepasses import TransformationPass
+from qiskit.circuit.commutation_library import StandardGateCommutations
+
+from qiskit.circuit.library.standard_gates.u1 import U1Gate
+from qiskit.circuit.library.standard_gates.p import PhaseGate
+from qiskit.circuit.library.standard_gates.rz import RZGate
+from qiskit._accelerate import commutation_cancellation
+from qiskit._accelerate.commutation_checker import CommutationChecker
+
+from qiskit.transpiler.passes.utils.control_flow import trivial_recurse
+
+_CUTOFF_PRECISION = 1e-5
+
+
+class CommutativeCancellation(TransformationPass):
+    """Cancel the redundant (self-adjoint) gates through commutation relations.
+
+    Pass for cancelling self-inverse gates/rotations. The cancellation utilizes
+    the commutation relations in the circuit. Gates considered include::
+
+        H, X, Y, Z, CX, CY, CZ
+    """
+
+    def __init__(self, basis_gates=None, target=None):
+        """
+        CommutativeCancellation initializer.
+
+        Args:
+            basis_gates (list[str]): Basis gates to consider, e.g.
+                ``['u3', 'cx']``. For the effects of this pass, the basis is
+                the set intersection between the ``basis_gates`` parameter
+                and the gates in the dag.
+            target (Target): The :class:`~.Target` representing the target backend, if both
+                ``basis_gates`` and ``target`` are specified then this argument will take
+                precedence and ``basis_gates`` will be ignored.
+        """
+        super().__init__()
+        if basis_gates:
+            self.basis = set(basis_gates)
+        else:
+            self.basis = set()
+        self.target = target
+        if target is not None:
+            self.basis = set(target.operation_names)
+
+        self._var_z_map = {"rz": RZGate, "p": PhaseGate, "u1": U1Gate}
+
+        self._z_rotations = {"p", "z", "u1", "rz", "t", "s"}
+        self._x_rotations = {"x", "rx"}
+        self._gates = {"cx", "cy", "cz", "h", "y"}  # Now the gates supported are hard-coded
+
+        # build a commutation checker restricted to the gates we cancel -- the others we
+        # do not have to investigate, which allows to save time
+        self._commutation_checker = CommutationChecker(
+            StandardGateCommutations, gates=self._gates | self._z_rotations | self._x_rotations
+        )
+
+    @trivial_recurse
+    def run(self, dag):
+        """Run the CommutativeCancellation pass on `dag`.
+
+        Args:
+            dag (DAGCircuit): the DAG to be optimized.
+
+        Returns:
+            DAGCircuit: the optimized DAG.
+        """
+        commutation_cancellation.cancel_commutations(dag, self._commutation_checker, self.basis)
+        return dag

qiskit/transpiler/passes/optimization/commutative_inverse_cancellation.py

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+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2017, 2024.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""Cancel pairs of inverse gates exploiting commutation relations."""
+from qiskit.circuit.commutation_library import SessionCommutationChecker as scc
+
+from qiskit.dagcircuit import DAGCircuit, DAGOpNode
+from qiskit.quantum_info import Operator
+from qiskit.quantum_info.operators.predicates import matrix_equal
+from qiskit.transpiler.basepasses import TransformationPass
+
+
+class CommutativeInverseCancellation(TransformationPass):
+    """Cancel pairs of inverse gates exploiting commutation relations."""
+
+    def __init__(self, matrix_based: bool = False, max_qubits: int = 4):
+        """
+        Args:
+            matrix_based: If ``True``, uses matrix representations to check whether two
+                operations are inverse of each other. This makes the checks more powerful,
+                and, in addition, allows canceling pairs of operations that are inverse up to a
+                phase, while updating the global phase of the circuit accordingly.
+                Generally this leads to more reductions at the expense of increased runtime.
+            max_qubits: Limits the number of qubits in matrix-based commutativity and
+                inverse checks.
+        """
+        self._matrix_based = matrix_based
+        self._max_qubits = max_qubits
+        self.comm_checker = scc
+        super().__init__()
+
+    def _skip_node(self, node):
+        """Returns True if we should skip this node for the analysis."""
+        if not isinstance(node, DAGOpNode):
+            return True
+
+        # We are currently taking an over-conservative approach with respect to which nodes
+        # can be inverses of which other nodes, and do not allow reductions for barriers, measures,
+        # conditional gates or parameterized gates. Possibly both this and commutativity
+        # checking can be extended to cover additional cases.
+        if getattr(node.op, "_directive", False) or node.name in {"measure", "reset", "delay"}:
+            return True
+        if getattr(node, "condition", None):
+            return True
+        if node.op.is_parameterized():
+            return True
+        return False
+
+    def _check_inverse(self, node1, node2):
+        """Checks whether op1 and op2 are inverse up to a phase, that is whether
+        ``op2 = e^{i * d} op1^{-1})`` for some phase difference ``d``.
+        If this is the case, we can replace ``op2 * op1`` by `e^{i * d} I``.
+        The input to this function is a pair of DAG nodes.
+        The output is a tuple representing whether the two nodes
+        are inverse up to a phase and that phase difference.
+        """
+        phase_difference = 0
+        if not self._matrix_based:
+            is_inverse = node1.op.inverse() == node2.op
+        elif len(node2.qargs) > self._max_qubits:
+            is_inverse = False
+        else:
+            mat1 = Operator(node1.op.inverse()).data
+            mat2 = Operator(node2.op).data
+            props = {}
+            is_inverse = matrix_equal(mat1, mat2, ignore_phase=True, props=props)
+            if is_inverse:
+                # mat2 = e^{i * phase_difference} mat1
+                phase_difference = props["phase_difference"]
+        return is_inverse, phase_difference
+
+    def run(self, dag: DAGCircuit):
+        """
+        Run the CommutativeInverseCancellation pass on `dag`.
+
+        Args:
+            dag: the directed acyclic graph to run on.
+
+        Returns:
+            DAGCircuit: Transformed DAG.
+        """
+        topo_sorted_nodes = list(dag.topological_op_nodes())
+
+        circ_size = len(topo_sorted_nodes)
+
+        removed = [False for _ in range(circ_size)]
+
+        phase_update = 0
+
+        for idx1 in range(0, circ_size):
+            if self._skip_node(topo_sorted_nodes[idx1]):
+                continue
+
+            matched_idx2 = -1
+
+            for idx2 in range(idx1 - 1, -1, -1):
+                if removed[idx2]:
+                    continue
+
+                if (
+                    not self._skip_node(topo_sorted_nodes[idx2])
+                    and topo_sorted_nodes[idx2].qargs == topo_sorted_nodes[idx1].qargs
+                    and topo_sorted_nodes[idx2].cargs == topo_sorted_nodes[idx1].cargs
+                ):
+                    is_inverse, phase = self._check_inverse(
+                        topo_sorted_nodes[idx1], topo_sorted_nodes[idx2]
+                    )
+                    if is_inverse:
+                        phase_update += phase
+                        matched_idx2 = idx2
+                        break
+
+                if not self.comm_checker.commute_nodes(
+                    topo_sorted_nodes[idx1],
+                    topo_sorted_nodes[idx2],
+                    max_num_qubits=self._max_qubits,
+                ):
+                    break
+
+            if matched_idx2 != -1:
+                removed[idx1] = True
+                removed[matched_idx2] = True
+
+        for idx in range(circ_size):
+            if removed[idx]:
+                dag.remove_op_node(topo_sorted_nodes[idx])
+
+        if phase_update != 0:
+            dag.global_phase += phase_update
+
+        return dag

qiskit/transpiler/passes/optimization/consolidate_blocks.py

@@ -0,0 +1,176 @@
+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2017, 2019.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""Replace each block of consecutive gates by a single Unitary node."""
+from __future__ import annotations
+
+from qiskit.synthesis.two_qubit import TwoQubitBasisDecomposer, TwoQubitControlledUDecomposer
+from qiskit.circuit.library.standard_gates import (
+    CXGate,
+    CZGate,
+    iSwapGate,
+    ECRGate,
+    RXXGate,
+    RYYGate,
+    RZZGate,
+    RZXGate,
+    CRXGate,
+    CRYGate,
+    CRZGate,
+    CPhaseGate,
+)
+
+from qiskit.transpiler.basepasses import TransformationPass
+from qiskit.transpiler.passmanager import PassManager
+from qiskit._accelerate.consolidate_blocks import consolidate_blocks
+
+from .collect_1q_runs import Collect1qRuns
+from .collect_2q_blocks import Collect2qBlocks
+
+KAK_GATE_NAMES = {
+    "cx": CXGate(),
+    "cz": CZGate(),
+    "iswap": iSwapGate(),
+    "ecr": ECRGate(),
+}
+
+KAK_GATE_PARAM_NAMES = {
+    "rxx": RXXGate,
+    "rzz": RZZGate,
+    "ryy": RYYGate,
+    "rzx": RZXGate,
+    "cphase": CPhaseGate,
+    "crx": CRXGate,
+    "cry": CRYGate,
+    "crz": CRZGate,
+}
+
+
+class ConsolidateBlocks(TransformationPass):
+    """Replace each block of consecutive gates by a single Unitary node.
+
+    Pass to consolidate sequences of uninterrupted gates acting on
+    the same qubits into a Unitary node, to be resynthesized later,
+    to a potentially more optimal subcircuit.
+
+    Notes:
+        This pass assumes that the 'blocks_list' property that it reads is
+        given such that blocks are in topological order. The blocks are
+        collected by a previous pass, such as `Collect2qBlocks`.
+    """
+
+    def __init__(
+        self,
+        kak_basis_gate=None,
+        force_consolidate=False,
+        basis_gates=None,
+        approximation_degree=1.0,
+        target=None,
+    ):
+        """ConsolidateBlocks initializer.
+
+        If ``kak_basis_gate`` is not ``None`` it will be used as the basis gate for KAK decomposition.
+        Otherwise, if ``basis_gates`` is not ``None`` a basis gate will be chosen from this list.
+        Otherwise, the basis gate will be :class:`.CXGate`.
+
+        Args:
+            kak_basis_gate (Gate): Basis gate for KAK decomposition.
+            force_consolidate (bool): Force block consolidation.
+            basis_gates (List(str)): Basis gates from which to choose a KAK gate.
+            approximation_degree (float): a float between :math:`[0.0, 1.0]`. Lower approximates more.
+            target (Target): The target object for the compilation target backend.
+        """
+        super().__init__()
+        self.basis_gates = None
+        self.basis_gate_name = None
+        # Bypass target if it doesn't contain any basis gates (i.e. it's a _FakeTarget), as this
+        # not part of the official target model.
+        self.target = target if target is not None and len(target.operation_names) > 0 else None
+        if basis_gates is not None:
+            self.basis_gates = set(basis_gates)
+        self.force_consolidate = force_consolidate
+        if kak_basis_gate is not None:
+            self.decomposer = TwoQubitBasisDecomposer(kak_basis_gate)
+            self.basis_gate_name = kak_basis_gate.name
+        elif basis_gates is not None:
+            kak_gates = KAK_GATE_NAMES.keys() & (basis_gates or [])
+            kak_param_gates = KAK_GATE_PARAM_NAMES.keys() & (basis_gates or [])
+            if kak_param_gates:
+                self.decomposer = TwoQubitControlledUDecomposer(
+                    KAK_GATE_PARAM_NAMES[list(kak_param_gates)[0]]
+                )
+                self.basis_gate_name = list(kak_param_gates)[0]
+            elif kak_gates:
+                self.decomposer = TwoQubitBasisDecomposer(
+                    KAK_GATE_NAMES[list(kak_gates)[0]], basis_fidelity=approximation_degree or 1.0
+                )
+                self.basis_gate_name = list(kak_gates)[0]
+            else:
+                self.decomposer = None
+        else:
+            self.decomposer = TwoQubitBasisDecomposer(CXGate())
+            self.basis_gate_name = "cx"
+
+    def run(self, dag):
+        """Run the ConsolidateBlocks pass on `dag`.
+
+        Iterate over each block and replace it with an equivalent Unitary
+        on the same wires.
+        """
+        if self.decomposer is None:
+            return dag
+
+        blocks = self.property_set["block_list"]
+        if blocks is not None:
+            blocks = [[node._node_id for node in block] for block in blocks]
+        runs = self.property_set["run_list"]
+        if runs is not None:
+            runs = [[node._node_id for node in run] for run in runs]
+
+        consolidate_blocks(
+            dag,
+            self.decomposer._inner_decomposer,
+            self.basis_gate_name,
+            self.force_consolidate,
+            target=self.target,
+            basis_gates=self.basis_gates,
+            blocks=blocks,
+            runs=runs,
+        )
+        dag = self._handle_control_flow_ops(dag)
+
+        # Clear collected blocks and runs as they are no longer valid after consolidation
+        if "run_list" in self.property_set:
+            del self.property_set["run_list"]
+        if "block_list" in self.property_set:
+            del self.property_set["block_list"]
+
+        return dag
+
+    def _handle_control_flow_ops(self, dag):
+        """
+        This is similar to transpiler/passes/utils/control_flow.py except that the
+        collect blocks is redone for the control flow blocks.
+        """
+
+        pass_manager = PassManager()
+        if "run_list" in self.property_set:
+            pass_manager.append(Collect1qRuns())
+            pass_manager.append(Collect2qBlocks())
+
+        pass_manager.append(self)
+        for node in dag.control_flow_op_nodes():
+            dag.substitute_node(
+                node,
+                node.op.replace_blocks(pass_manager.run(block) for block in node.op.blocks),
+            )
+        return dag