wasmtime 12.0.1 → 13.0.0
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- checksums.yaml +4 -4
- data/Cargo.lock +176 -221
- data/ext/Cargo.toml +6 -6
- data/ext/cargo-vendor/cap-net-ext-2.0.0/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.100.0/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/trapcode.rs +144 -0
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- data/ext/cargo-vendor/cranelift-codegen-meta-0.100.0/src/constant_hash.rs +63 -0
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- data/ext/cargo-vendor/cranelift-codegen-shared-0.100.0/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/cranelift-entity-0.100.0/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/cranelift-wasm-0.100.0/.cargo-checksum.json +1 -0
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- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-and-include-world/root.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-and-include-world.wit.result +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict.wit.result +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict2.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict2.wit.result +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict3.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict3.wit.result +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-cycle1.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-cycle1.wit.result +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-cycle4.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-cycle4.wit.result +0 -0
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- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-shadow1.wit.result +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-world/deps/bar/baz.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-world/root.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-world.wit.result +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-interface-clash.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-interface-clash.wit.result +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-same-fields2.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-same-fields2.wit.result +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-same-fields3.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-same-fields3.wit.result +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-top-level-func.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-top-level-func.wit.result +0 -0
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- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-empty.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-multiple-returns-borrow.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-multiple-returns-own.wit +0 -0
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- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-return-borrow.wit +0 -0
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- /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/stress-export-elaborate.wit +0 -0
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;; riscv64 instruction selection and CLIF-to-MachInst lowering.
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;; The main lowering constructor term: takes a clif `Inst` and returns the
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;; register(s) within which the lowered instruction's result values live.
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(decl partial lower (Inst) InstOutput)
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;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty (iconst (u64_from_imm64 n))))
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(imm ty n))
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;; ;;;; Rules for `vconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (ty_vec_fits_in_register ty) (vconst n)))
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(gen_constant ty (const_to_vconst n)))
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;;;; Rules for `f32const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (f32const (u32_from_ieee32 n)))
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;;;; Rules for `f64const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (f64const (u64_from_ieee64 n)))
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;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty (null)))
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;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Base case, simply adding things in registers.
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(rule 0 (lower (has_type (ty_int_ref_scalar_64 ty) (iadd x y)))
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(rv_add x y))
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;; Special cases for when one operand is an immediate that fits in 12 bits.
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(alu_rr_imm12 (select_addi ty) x y))
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(rule 2 (lower (has_type (ty_int_ref_scalar_64 ty) (iadd (imm12_from_value x) y)))
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(alu_rr_imm12 (select_addi ty) y x))
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;; Special case when one of the operands is uextended
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(rule 3 (lower (has_type $I64 (iadd x (uextend y @ (value_type $I32)))))
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(if-let $true (has_zba))
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(rv_adduw y x))
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(rule 4 (lower (has_type $I64 (iadd (uextend x @ (value_type $I32)) y)))
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;; Add with const shift. We have a few of these instructions with `Zba`.
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(decl pure partial match_shnadd (Imm64) AluOPRRR)
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(rule (match_shnadd (u64_from_imm64 1)) (AluOPRRR.Sh1add))
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(rule (match_shnadd (u64_from_imm64 2)) (AluOPRRR.Sh2add))
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(rule (match_shnadd (u64_from_imm64 3)) (AluOPRRR.Sh3add))
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(rule 3 (lower (has_type $I64 (iadd x (ishl y (maybe_uextend (iconst n))))))
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(if-let $true (has_zba))
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(if-let shnadd (match_shnadd n))
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(alu_rrr shnadd y x))
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(rule 4 (lower (has_type $I64 (iadd (ishl x (maybe_uextend (iconst n))) y)))
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(if-let $true (has_zba))
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(if-let shnadd (match_shnadd n))
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;; Add with uextended const shift. We have a few of these instructions with `Zba`.
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;;
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;; !!! Important !!!
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;; These rules only work for (ishl (uextend _) _) and not for (uextend (ishl _ _))!
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;; Getting this wrong means a potential misscalculation of the shift amount.
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;; Additionaly we can only ensure that this is correct if the uextend is 32 to 64 bits.
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(decl pure partial match_shnadd_uw (Imm64) AluOPRRR)
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(rule (match_shnadd_uw (u64_from_imm64 1)) (AluOPRRR.Sh1adduw))
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(rule (match_shnadd_uw (u64_from_imm64 2)) (AluOPRRR.Sh2adduw))
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(rule (match_shnadd_uw (u64_from_imm64 3)) (AluOPRRR.Sh3adduw))
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(rule 5 (lower (has_type $I64 (iadd x (ishl (uextend y @ (value_type $I32)) (maybe_uextend (iconst n))))))
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(if-let $true (has_zba))
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(if-let shnadd_uw (match_shnadd_uw n))
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(alu_rrr shnadd_uw y x))
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(rule 6 (lower (has_type $I64 (iadd (ishl (uextend x @ (value_type $I32)) (maybe_uextend (iconst n))) y)))
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(if-let $true (has_zba))
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(if-let shnadd_uw (match_shnadd_uw n))
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(alu_rrr shnadd_uw x y))
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;; I128 cases
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(rule 7 (lower (has_type $I128 (iadd x y)))
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(let ((low XReg (rv_add (value_regs_get x 0) (value_regs_get y 0)))
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;; compute carry.
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(carry XReg (rv_sltu low (value_regs_get y 0)))
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;;
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(high_tmp XReg (rv_add (value_regs_get x 1) (value_regs_get y 1)))
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;; add carry.
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(high XReg (rv_add high_tmp carry)))
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(value_regs low high)))
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;; SIMD Vectors
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(rule 8 (lower (has_type (ty_vec_fits_in_register ty) (iadd x y)))
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(if-let half_ty (ty_half_width ty))
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(if-let $true (ty_equal (lane_type half_ty) sext_ty))
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(rv_vwadd_wx x y (unmasked) (vstate_mf2 half_ty)))
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(rule 10 (lower (has_type (ty_vec_fits_in_register ty) (iadd x (splat (uextend y @ (value_type uext_ty))))))
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(if-let half_ty (ty_half_width ty))
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(if-let $true (ty_equal (lane_type half_ty) uext_ty))
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(rv_vwaddu_wx x y (unmasked) (vstate_mf2 half_ty)))
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(rule 11 (lower (has_type (ty_vec_fits_in_register ty) (iadd x (replicated_imm5 y))))
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(rv_vadd_vi x y (unmasked) ty))
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(rule 12 (lower (has_type (ty_vec_fits_in_register ty) (iadd (splat x) y)))
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(rv_vadd_vx y x (unmasked) ty))
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(rule 13 (lower (has_type (ty_vec_fits_in_register ty) (iadd (splat (sextend x @ (value_type sext_ty))) y)))
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(if-let half_ty (ty_half_width ty))
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(if-let $true (ty_equal (lane_type half_ty) sext_ty))
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(rv_vwadd_wx y x (unmasked) (vstate_mf2 half_ty)))
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(rule 13 (lower (has_type (ty_vec_fits_in_register ty) (iadd (splat (uextend x @ (value_type uext_ty))) y)))
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(if-let half_ty (ty_half_width ty))
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(if-let $true (ty_equal (lane_type half_ty) uext_ty))
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(rv_vwaddu_wx y x (unmasked) (vstate_mf2 half_ty)))
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(rule 14 (lower (has_type (ty_vec_fits_in_register ty) (iadd (replicated_imm5 x) y)))
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(rv_vadd_vi y x (unmasked) ty))
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;; Signed Widening Low Additions
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(rule 9 (lower (has_type (ty_vec_fits_in_register _) (iadd x (swiden_low y @ (value_type in_ty)))))
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(rv_vwadd_wv x y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
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(rule 12 (lower (has_type (ty_vec_fits_in_register _) (iadd (swiden_low x @ (value_type in_ty)) y)))
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(rv_vwadd_wv y x (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
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(rule 13 (lower (has_type (ty_vec_fits_in_register _) (iadd (swiden_low x @ (value_type in_ty))
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(swiden_low y))))
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(rv_vwadd_vv x y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
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(rule 13 (lower (has_type (ty_vec_fits_in_register _) (iadd (swiden_low x @ (value_type in_ty))
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(splat (sextend y @ (value_type sext_ty))))))
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(if-let $true (ty_equal (lane_type in_ty) sext_ty))
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(rv_vwadd_vx x y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
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(rule 14 (lower (has_type (ty_vec_fits_in_register _) (iadd (splat (sextend x @ (value_type sext_ty)))
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(swiden_low y @ (value_type in_ty)))))
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(if-let $true (ty_equal (lane_type in_ty) sext_ty))
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(rv_vwadd_vx y x (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
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;; Signed Widening High Additions
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;; These are the same as the low additions, but we first slide down the inputs.
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(rule 9 (lower (has_type (ty_vec_fits_in_register _) (iadd x (swiden_high y @ (value_type in_ty)))))
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(rv_vwadd_wv x (gen_slidedown_half in_ty y) (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
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(rule 12 (lower (has_type (ty_vec_fits_in_register _) (iadd (swiden_high x @ (value_type in_ty)) y)))
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(rv_vwadd_wv y (gen_slidedown_half in_ty x) (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
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(rule 13 (lower (has_type (ty_vec_fits_in_register _) (iadd (swiden_high x @ (value_type in_ty))
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(swiden_high y))))
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|
-
(rv_vwadd_vv (gen_slidedown_half in_ty x) (gen_slidedown_half in_ty y) (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
176
|
-
|
177
|
-
(rule 13 (lower (has_type (ty_vec_fits_in_register _) (iadd (swiden_high x @ (value_type in_ty))
|
178
|
-
(splat (sextend y @ (value_type sext_ty))))))
|
179
|
-
(if-let $true (ty_equal (lane_type in_ty) sext_ty))
|
180
|
-
(rv_vwadd_vx (gen_slidedown_half in_ty x) y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
181
|
-
|
182
|
-
(rule 14 (lower (has_type (ty_vec_fits_in_register _) (iadd (splat (sextend x @ (value_type sext_ty)))
|
183
|
-
(swiden_high y @ (value_type in_ty)))))
|
184
|
-
(if-let $true (ty_equal (lane_type in_ty) sext_ty))
|
185
|
-
(rv_vwadd_vx (gen_slidedown_half in_ty y) x (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
186
|
-
|
187
|
-
;; Unsigned Widening Low Additions
|
188
|
-
|
189
|
-
(rule 9 (lower (has_type (ty_vec_fits_in_register _) (iadd x (uwiden_low y @ (value_type in_ty)))))
|
190
|
-
(rv_vwaddu_wv x y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
191
|
-
|
192
|
-
(rule 12 (lower (has_type (ty_vec_fits_in_register _) (iadd (uwiden_low x @ (value_type in_ty)) y)))
|
193
|
-
(rv_vwaddu_wv y x (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
194
|
-
|
195
|
-
(rule 13 (lower (has_type (ty_vec_fits_in_register _) (iadd (uwiden_low x @ (value_type in_ty))
|
196
|
-
(uwiden_low y))))
|
197
|
-
(rv_vwaddu_vv x y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
198
|
-
|
199
|
-
(rule 13 (lower (has_type (ty_vec_fits_in_register _) (iadd (uwiden_low x @ (value_type in_ty))
|
200
|
-
(splat (uextend y @ (value_type uext_ty))))))
|
201
|
-
(if-let $true (ty_equal (lane_type in_ty) uext_ty))
|
202
|
-
(rv_vwaddu_vx x y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
203
|
-
|
204
|
-
(rule 14 (lower (has_type (ty_vec_fits_in_register _) (iadd (splat (uextend x @ (value_type uext_ty)))
|
205
|
-
(uwiden_low y @ (value_type in_ty)))))
|
206
|
-
(if-let $true (ty_equal (lane_type in_ty) uext_ty))
|
207
|
-
(rv_vwaddu_vx y x (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
208
|
-
|
209
|
-
;; Unsigned Widening High Additions
|
210
|
-
;; These are the same as the low additions, but we first slide down the inputs.
|
211
|
-
|
212
|
-
(rule 9 (lower (has_type (ty_vec_fits_in_register _) (iadd x (uwiden_high y @ (value_type in_ty)))))
|
213
|
-
(rv_vwaddu_wv x (gen_slidedown_half in_ty y) (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
214
|
-
|
215
|
-
(rule 12 (lower (has_type (ty_vec_fits_in_register _) (iadd (uwiden_high x @ (value_type in_ty)) y)))
|
216
|
-
(rv_vwaddu_wv y (gen_slidedown_half in_ty x) (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
217
|
-
|
218
|
-
(rule 13 (lower (has_type (ty_vec_fits_in_register _) (iadd (uwiden_high x @ (value_type in_ty))
|
219
|
-
(uwiden_high y))))
|
220
|
-
(rv_vwaddu_vv (gen_slidedown_half in_ty x) (gen_slidedown_half in_ty y) (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
221
|
-
|
222
|
-
(rule 13 (lower (has_type (ty_vec_fits_in_register _) (iadd (uwiden_high x @ (value_type in_ty))
|
223
|
-
(splat (uextend y @ (value_type uext_ty))))))
|
224
|
-
(if-let $true (ty_equal (lane_type in_ty) uext_ty))
|
225
|
-
(rv_vwaddu_vx (gen_slidedown_half in_ty x) y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
226
|
-
|
227
|
-
(rule 14 (lower (has_type (ty_vec_fits_in_register _) (iadd (splat (uextend y @ (value_type uext_ty)))
|
228
|
-
(uwiden_high x @ (value_type in_ty)))))
|
229
|
-
(if-let $true (ty_equal (lane_type in_ty) uext_ty))
|
230
|
-
(rv_vwaddu_vx (gen_slidedown_half in_ty x) y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
231
|
-
|
232
|
-
;; Signed Widening Mixed High/Low Additions
|
233
|
-
|
234
|
-
(rule 13 (lower (has_type (ty_vec_fits_in_register _) (iadd (swiden_low x @ (value_type in_ty))
|
235
|
-
(swiden_high y))))
|
236
|
-
(rv_vwadd_vv x (gen_slidedown_half in_ty y) (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
237
|
-
|
238
|
-
(rule 13 (lower (has_type (ty_vec_fits_in_register _) (iadd (swiden_high x @ (value_type in_ty))
|
239
|
-
(swiden_low y))))
|
240
|
-
(rv_vwadd_vv (gen_slidedown_half in_ty x) y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
241
|
-
|
242
|
-
;; Unsigned Widening Mixed High/Low Additions
|
243
|
-
|
244
|
-
(rule 13 (lower (has_type (ty_vec_fits_in_register _) (iadd (uwiden_low x @ (value_type in_ty))
|
245
|
-
(uwiden_high y))))
|
246
|
-
(rv_vwaddu_vv x (gen_slidedown_half in_ty y) (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
247
|
-
|
248
|
-
(rule 13 (lower (has_type (ty_vec_fits_in_register _) (iadd (uwiden_high x @ (value_type in_ty))
|
249
|
-
(uwiden_low y))))
|
250
|
-
(rv_vwaddu_vv (gen_slidedown_half in_ty x) y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
251
|
-
|
252
|
-
|
253
|
-
;;; Rules for `uadd_overflow_trap` ;;;;;;;;;;;;;
|
254
|
-
(rule
|
255
|
-
(lower (has_type (fits_in_64 ty) (uadd_overflow_trap x y tc)))
|
256
|
-
(let ((res ValueRegs (lower_uadd_overflow x y ty))
|
257
|
-
(_ InstOutput (gen_trapif (value_regs_get res 1) tc)))
|
258
|
-
(value_regs_get res 0)))
|
259
|
-
|
260
|
-
|
261
|
-
;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
262
|
-
;; Base case, simply subtracting things in registers.
|
263
|
-
|
264
|
-
(rule (lower (has_type (ty_int_ref_scalar_64 ty) (isub x y)))
|
265
|
-
(rv_sub x y))
|
266
|
-
|
267
|
-
(rule 1 (lower (has_type (fits_in_32 (ty_int ty)) (isub x y)))
|
268
|
-
(rv_subw x y))
|
269
|
-
|
270
|
-
(rule 2 (lower (has_type $I128 (isub x y)))
|
271
|
-
(i128_sub x y))
|
272
|
-
|
273
|
-
;; SIMD Vectors
|
274
|
-
(rule 3 (lower (has_type (ty_vec_fits_in_register ty) (isub x y)))
|
275
|
-
(rv_vsub_vv x y (unmasked) ty))
|
276
|
-
|
277
|
-
(rule 4 (lower (has_type (ty_vec_fits_in_register ty) (isub x (splat y))))
|
278
|
-
(rv_vsub_vx x y (unmasked) ty))
|
279
|
-
|
280
|
-
(rule 5 (lower (has_type (ty_vec_fits_in_register ty) (isub x (splat (sextend y @ (value_type sext_ty))))))
|
281
|
-
(if-let half_ty (ty_half_width ty))
|
282
|
-
(if-let $true (ty_equal (lane_type half_ty) sext_ty))
|
283
|
-
(rv_vwsub_wx x y (unmasked) (vstate_mf2 half_ty)))
|
284
|
-
|
285
|
-
(rule 5 (lower (has_type (ty_vec_fits_in_register ty) (isub x (splat (uextend y @ (value_type uext_ty))))))
|
286
|
-
(if-let half_ty (ty_half_width ty))
|
287
|
-
(if-let $true (ty_equal (lane_type half_ty) uext_ty))
|
288
|
-
(rv_vwsubu_wx x y (unmasked) (vstate_mf2 half_ty)))
|
289
|
-
|
290
|
-
(rule 6 (lower (has_type (ty_vec_fits_in_register ty) (isub (splat x) y)))
|
291
|
-
(rv_vrsub_vx y x (unmasked) ty))
|
292
|
-
|
293
|
-
(rule 7 (lower (has_type (ty_vec_fits_in_register ty) (isub (replicated_imm5 x) y)))
|
294
|
-
(rv_vrsub_vi y x (unmasked) ty))
|
295
|
-
|
296
|
-
|
297
|
-
;; Signed Widening Low Subtractions
|
298
|
-
|
299
|
-
(rule 5 (lower (has_type (ty_vec_fits_in_register _) (isub x (swiden_low y @ (value_type in_ty)))))
|
300
|
-
(rv_vwsub_wv x y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
301
|
-
|
302
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register _) (isub (swiden_low x @ (value_type in_ty))
|
303
|
-
(swiden_low y))))
|
304
|
-
(rv_vwsub_vv x y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
305
|
-
|
306
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register _) (isub (swiden_low x @ (value_type in_ty))
|
307
|
-
(splat (sextend y @ (value_type sext_ty))))))
|
308
|
-
(if-let $true (ty_equal (lane_type in_ty) sext_ty))
|
309
|
-
(rv_vwsub_vx x y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
310
|
-
|
311
|
-
;; Signed Widening High Subtractions
|
312
|
-
;; These are the same as the low widenings, but we first slide down the inputs.
|
313
|
-
|
314
|
-
(rule 5 (lower (has_type (ty_vec_fits_in_register _) (isub x (swiden_high y @ (value_type in_ty)))))
|
315
|
-
(rv_vwsub_wv x (gen_slidedown_half in_ty y) (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
316
|
-
|
317
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register _) (isub (swiden_high x @ (value_type in_ty))
|
318
|
-
(swiden_high y))))
|
319
|
-
(rv_vwsub_vv (gen_slidedown_half in_ty x) (gen_slidedown_half in_ty y) (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
320
|
-
|
321
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register _) (isub (swiden_high x @ (value_type in_ty))
|
322
|
-
(splat (sextend y @ (value_type sext_ty))))))
|
323
|
-
(if-let $true (ty_equal (lane_type in_ty) sext_ty))
|
324
|
-
(rv_vwsub_vx (gen_slidedown_half in_ty x) y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
325
|
-
|
326
|
-
;; Unsigned Widening Low Subtractions
|
327
|
-
|
328
|
-
(rule 5 (lower (has_type (ty_vec_fits_in_register _) (isub x (uwiden_low y @ (value_type in_ty)))))
|
329
|
-
(rv_vwsubu_wv x y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
330
|
-
|
331
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register _) (isub (uwiden_low x @ (value_type in_ty))
|
332
|
-
(uwiden_low y))))
|
333
|
-
(rv_vwsubu_vv x y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
334
|
-
|
335
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register _) (isub (uwiden_low x @ (value_type in_ty))
|
336
|
-
(splat (uextend y @ (value_type uext_ty))))))
|
337
|
-
(if-let $true (ty_equal (lane_type in_ty) uext_ty))
|
338
|
-
(rv_vwsubu_vx x y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
339
|
-
|
340
|
-
;; Unsigned Widening High Subtractions
|
341
|
-
;; These are the same as the low widenings, but we first slide down the inputs.
|
342
|
-
|
343
|
-
(rule 5 (lower (has_type (ty_vec_fits_in_register _) (isub x (uwiden_high y @ (value_type in_ty)))))
|
344
|
-
(rv_vwsubu_wv x (gen_slidedown_half in_ty y) (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
345
|
-
|
346
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register _) (isub (uwiden_high x @ (value_type in_ty))
|
347
|
-
(uwiden_high y))))
|
348
|
-
(rv_vwsubu_vv (gen_slidedown_half in_ty x) (gen_slidedown_half in_ty y) (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
349
|
-
|
350
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register _) (isub (uwiden_high x @ (value_type in_ty))
|
351
|
-
(splat (uextend y @ (value_type uext_ty))))))
|
352
|
-
(if-let $true (ty_equal (lane_type in_ty) uext_ty))
|
353
|
-
(rv_vwsubu_vx (gen_slidedown_half in_ty x) y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
354
|
-
|
355
|
-
;; Signed Widening Mixed High/Low Subtractions
|
356
|
-
|
357
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register _) (isub (swiden_low x @ (value_type in_ty))
|
358
|
-
(swiden_high y))))
|
359
|
-
(rv_vwsub_vv x (gen_slidedown_half in_ty y) (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
360
|
-
|
361
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register _) (isub (swiden_high x @ (value_type in_ty))
|
362
|
-
(swiden_low y))))
|
363
|
-
(rv_vwsub_vv (gen_slidedown_half in_ty x) y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
364
|
-
|
365
|
-
;; Unsigned Widening Mixed High/Low Subtractions
|
366
|
-
|
367
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register _) (isub (uwiden_low x @ (value_type in_ty))
|
368
|
-
(uwiden_high y))))
|
369
|
-
(rv_vwsubu_vv x (gen_slidedown_half in_ty y) (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
370
|
-
|
371
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register _) (isub (uwiden_high x @ (value_type in_ty))
|
372
|
-
(uwiden_low y))))
|
373
|
-
(rv_vwsubu_vv (gen_slidedown_half in_ty x) y (unmasked) (vstate_mf2 (ty_half_lanes in_ty))))
|
374
|
-
|
375
|
-
|
376
|
-
;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
377
|
-
|
378
|
-
(rule (lower (has_type (ty_int ty) (ineg val)))
|
379
|
-
(neg ty val))
|
380
|
-
|
381
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (ineg x)))
|
382
|
-
(rv_vneg_v x (unmasked) ty))
|
383
|
-
|
384
|
-
|
385
|
-
;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
386
|
-
|
387
|
-
(rule 0 (lower (has_type (ty_int_ref_scalar_64 ty) (imul x y)))
|
388
|
-
(rv_mul x y))
|
389
|
-
|
390
|
-
(rule 1 (lower (has_type (fits_in_32 (ty_int ty)) (imul x y)))
|
391
|
-
(rv_mulw x y))
|
392
|
-
|
393
|
-
;; for I128
|
394
|
-
(rule 2 (lower (has_type $I128 (imul x y)))
|
395
|
-
(let
|
396
|
-
((x_regs ValueRegs x)
|
397
|
-
(x_lo XReg (value_regs_get x_regs 0))
|
398
|
-
(x_hi XReg (value_regs_get x_regs 1))
|
399
|
-
|
400
|
-
;; Get the high/low registers for `y`.
|
401
|
-
(y_regs ValueRegs y)
|
402
|
-
(y_lo XReg (value_regs_get y_regs 0))
|
403
|
-
(y_hi XReg (value_regs_get y_regs 1))
|
404
|
-
|
405
|
-
;; 128bit mul formula:
|
406
|
-
;; dst_lo = x_lo * y_lo
|
407
|
-
;; dst_hi = mulhu(x_lo, y_lo) + (x_lo * y_hi) + (x_hi * y_lo)
|
408
|
-
;;
|
409
|
-
;; We can convert the above formula into the following
|
410
|
-
;; mulhu dst_hi, x_lo, y_lo
|
411
|
-
;; madd dst_hi, x_lo, y_hi, dst_hi
|
412
|
-
;; madd dst_hi, x_hi, y_lo, dst_hi
|
413
|
-
;; madd dst_lo, x_lo, y_lo, zero
|
414
|
-
(dst_hi1 XReg (rv_mulhu x_lo y_lo))
|
415
|
-
(dst_hi2 XReg (madd x_lo y_hi dst_hi1))
|
416
|
-
(dst_hi XReg (madd x_hi y_lo dst_hi2))
|
417
|
-
(dst_lo XReg (madd x_lo y_lo (zero_reg))))
|
418
|
-
(value_regs dst_lo dst_hi)))
|
419
|
-
|
420
|
-
(rule 3 (lower (has_type (ty_vec_fits_in_register ty) (imul x y)))
|
421
|
-
(rv_vmul_vv x y (unmasked) ty))
|
422
|
-
|
423
|
-
(rule 4 (lower (has_type (ty_vec_fits_in_register ty) (imul (splat x) y)))
|
424
|
-
(rv_vmul_vx y x (unmasked) ty))
|
425
|
-
|
426
|
-
(rule 5 (lower (has_type (ty_vec_fits_in_register ty) (imul x (splat y))))
|
427
|
-
(rv_vmul_vx x y (unmasked) ty))
|
428
|
-
|
429
|
-
;;;; Rules for `smulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
430
|
-
(rule 0 (lower (has_type (ty_int_ref_scalar_64 ty) (smulhi x y)))
|
431
|
-
(lower_smlhi ty (sext x ty $I64) (sext y ty $I64)))
|
432
|
-
|
433
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (smulhi x y)))
|
434
|
-
(rv_vmulh_vv x y (unmasked) ty))
|
435
|
-
|
436
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (smulhi (splat x) y)))
|
437
|
-
(rv_vmulh_vx y x (unmasked) ty))
|
438
|
-
|
439
|
-
(rule 3 (lower (has_type (ty_vec_fits_in_register ty) (smulhi x (splat y))))
|
440
|
-
(rv_vmulh_vx x y (unmasked) ty))
|
441
|
-
|
442
|
-
;;;; Rules for `umulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
443
|
-
(rule 0 (lower (has_type (ty_int_ref_scalar_64 ty) (umulhi x y)))
|
444
|
-
(lower_umlhi ty (zext x ty $I64) (zext y ty $I64)))
|
445
|
-
|
446
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (umulhi x y)))
|
447
|
-
(rv_vmulhu_vv x y (unmasked) ty))
|
448
|
-
|
449
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (umulhi (splat x) y)))
|
450
|
-
(rv_vmulhu_vx y x (unmasked) ty))
|
451
|
-
|
452
|
-
(rule 3 (lower (has_type (ty_vec_fits_in_register ty) (umulhi x (splat y))))
|
453
|
-
(rv_vmulhu_vx x y (unmasked) ty))
|
454
|
-
|
455
|
-
;;;; Rules for `div` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
456
|
-
|
457
|
-
(rule -1 (lower (has_type (fits_in_32 ty) (udiv x y)))
|
458
|
-
(let
|
459
|
-
((y2 XReg (zext y ty $I64))
|
460
|
-
(_ InstOutput (gen_div_by_zero y2)))
|
461
|
-
(rv_divuw (zext x ty $I64) y2)))
|
462
|
-
|
463
|
-
(rule -1 (lower (has_type (fits_in_32 ty) (sdiv x y)))
|
464
|
-
(let
|
465
|
-
((a XReg (sext x ty $I64))
|
466
|
-
(b XReg (sext y ty $I64))
|
467
|
-
(_ InstOutput (gen_div_overflow a b ty))
|
468
|
-
(_ InstOutput (gen_div_by_zero b)))
|
469
|
-
(rv_divw a b)))
|
470
|
-
|
471
|
-
(rule (lower (has_type $I64 (sdiv x y)))
|
472
|
-
(let
|
473
|
-
((_ InstOutput (gen_div_overflow x y $I64))
|
474
|
-
(_ InstOutput (gen_div_by_zero y)) )
|
475
|
-
(rv_div x y)))
|
476
|
-
|
477
|
-
(rule (lower (has_type $I64 (udiv x y)))
|
478
|
-
(let
|
479
|
-
((_ InstOutput (gen_div_by_zero y)))
|
480
|
-
(rv_divu x y)))
|
481
|
-
|
482
|
-
;;;; Rules for `rem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
483
|
-
|
484
|
-
(rule -1 (lower (has_type (fits_in_16 ty) (urem x y)))
|
485
|
-
(let
|
486
|
-
((y2 XReg (zext y ty $I64))
|
487
|
-
(_ InstOutput (gen_div_by_zero y2)))
|
488
|
-
(rv_remuw (zext x ty $I64) y2)))
|
489
|
-
|
490
|
-
(rule -1 (lower (has_type (fits_in_16 ty) (srem x y)))
|
491
|
-
(let
|
492
|
-
((y2 XReg (sext y ty $I64))
|
493
|
-
(_ InstOutput (gen_div_by_zero y2)))
|
494
|
-
(rv_remw (sext x ty $I64) y2)))
|
495
|
-
|
496
|
-
(rule (lower (has_type $I32 (srem x y)))
|
497
|
-
(let
|
498
|
-
((y2 XReg (sext y $I32 $I64))
|
499
|
-
(_ InstOutput (gen_div_by_zero y2)))
|
500
|
-
(rv_remw x y2)))
|
501
|
-
|
502
|
-
(rule (lower (has_type $I32 (urem x y)))
|
503
|
-
(let
|
504
|
-
((y2 XReg (zext y $I32 $I64))
|
505
|
-
(_ InstOutput (gen_div_by_zero y2)))
|
506
|
-
(rv_remuw x y2)))
|
507
|
-
|
508
|
-
(rule (lower (has_type $I64 (srem x y)))
|
509
|
-
(let
|
510
|
-
((_ InstOutput (gen_div_by_zero y)))
|
511
|
-
(rv_rem x y)))
|
512
|
-
|
513
|
-
(rule (lower (has_type $I64 (urem x y)))
|
514
|
-
(let
|
515
|
-
((_ InstOutput (gen_div_by_zero y)))
|
516
|
-
(rv_remu x y)))
|
517
|
-
|
518
|
-
;;;; Rules for `and` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
519
|
-
(rule 0 (lower (has_type (ty_int ty) (band x y)))
|
520
|
-
(gen_and ty x y))
|
521
|
-
|
522
|
-
;; Special cases for when one operand is an immediate that fits in 12 bits.
|
523
|
-
(rule 1 (lower (has_type (fits_in_64 (ty_int ty)) (band x (imm12_from_value y))))
|
524
|
-
(rv_andi x y))
|
525
|
-
|
526
|
-
(rule 2 (lower (has_type (fits_in_64 (ty_int ty)) (band (imm12_from_value x) y)))
|
527
|
-
(rv_andi y x))
|
528
|
-
|
529
|
-
(rule 3 (lower (has_type (ty_scalar_float ty) (band x y)))
|
530
|
-
(lower_float_binary (AluOPRRR.And) x y ty))
|
531
|
-
|
532
|
-
;; Specialized lowerings for `(band x (bnot y))` which is additionally produced
|
533
|
-
;; by Cranelift's `band_not` instruction that is legalized into the simpler
|
534
|
-
;; forms early on.
|
535
|
-
|
536
|
-
(rule 4 (lower (has_type (fits_in_64 (ty_int ty)) (band x (bnot y))))
|
537
|
-
(if-let $true (has_zbb))
|
538
|
-
(rv_andn x y))
|
539
|
-
|
540
|
-
(rule 5 (lower (has_type (fits_in_64 (ty_int ty)) (band (bnot y) x)))
|
541
|
-
(if-let $true (has_zbb))
|
542
|
-
(rv_andn x y))
|
543
|
-
|
544
|
-
(rule 6 (lower (has_type $I128 (band x (bnot y))))
|
545
|
-
(if-let $true (has_zbb))
|
546
|
-
(let ((low XReg (rv_andn (value_regs_get x 0) (value_regs_get y 0)))
|
547
|
-
(high XReg (rv_andn (value_regs_get x 1) (value_regs_get y 1))))
|
548
|
-
(value_regs low high)))
|
549
|
-
|
550
|
-
(rule 7 (lower (has_type $I128 (band (bnot y) x)))
|
551
|
-
(if-let $true (has_zbb))
|
552
|
-
(let ((low XReg (rv_andn (value_regs_get x 0) (value_regs_get y 0)))
|
553
|
-
(high XReg (rv_andn (value_regs_get x 1) (value_regs_get y 1))))
|
554
|
-
(value_regs low high)))
|
555
|
-
|
556
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register ty) (band x y)))
|
557
|
-
(rv_vand_vv x y (unmasked) ty))
|
558
|
-
|
559
|
-
(rule 9 (lower (has_type (ty_vec_fits_in_register ty) (band x (splat y))))
|
560
|
-
(if (ty_vector_not_float ty))
|
561
|
-
(rv_vand_vx x y (unmasked) ty))
|
562
|
-
|
563
|
-
(rule 10 (lower (has_type (ty_vec_fits_in_register ty) (band (splat x) y)))
|
564
|
-
(if (ty_vector_not_float ty))
|
565
|
-
(rv_vand_vx y x (unmasked) ty))
|
566
|
-
|
567
|
-
(rule 11 (lower (has_type (ty_vec_fits_in_register ty) (band x (replicated_imm5 y))))
|
568
|
-
(rv_vand_vi x y (unmasked) ty))
|
569
|
-
|
570
|
-
(rule 12 (lower (has_type (ty_vec_fits_in_register ty) (band (replicated_imm5 x) y)))
|
571
|
-
(rv_vand_vi y x (unmasked) ty))
|
572
|
-
|
573
|
-
|
574
|
-
;;;; Rules for `or` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
575
|
-
(rule 0 (lower (has_type (ty_int ty) (bor x y)))
|
576
|
-
(gen_or ty x y))
|
577
|
-
|
578
|
-
;; Special cases for when one operand is an immediate that fits in 12 bits.
|
579
|
-
(rule 1 (lower (has_type (fits_in_64 (ty_int ty)) (bor x (imm12_from_value y))))
|
580
|
-
(rv_ori x y))
|
581
|
-
|
582
|
-
(rule 2 (lower (has_type (fits_in_64 (ty_int ty)) (bor (imm12_from_value x) y)))
|
583
|
-
(rv_ori y x))
|
584
|
-
|
585
|
-
(rule 3 (lower (has_type (ty_scalar_float ty) (bor x y)))
|
586
|
-
(lower_float_binary (AluOPRRR.Or) x y ty))
|
587
|
-
|
588
|
-
;; Specialized lowerings for `(bor x (bnot y))` which is additionally produced
|
589
|
-
;; by Cranelift's `bor_not` instruction that is legalized into the simpler
|
590
|
-
;; forms early on.
|
591
|
-
|
592
|
-
(rule 4 (lower (has_type (fits_in_64 (ty_int ty)) (bor x (bnot y))))
|
593
|
-
(if-let $true (has_zbb))
|
594
|
-
(rv_orn x y))
|
595
|
-
|
596
|
-
(rule 5 (lower (has_type (fits_in_64 (ty_int ty)) (bor (bnot y) x)))
|
597
|
-
(if-let $true (has_zbb))
|
598
|
-
(rv_orn x y))
|
599
|
-
|
600
|
-
(rule 6 (lower (has_type $I128 (bor x (bnot y))))
|
601
|
-
(if-let $true (has_zbb))
|
602
|
-
(let ((low XReg (rv_orn (value_regs_get x 0) (value_regs_get y 0)))
|
603
|
-
(high XReg (rv_orn (value_regs_get x 1) (value_regs_get y 1))))
|
604
|
-
(value_regs low high)))
|
605
|
-
|
606
|
-
(rule 7 (lower (has_type $I128 (bor (bnot y) x)))
|
607
|
-
(if-let $true (has_zbb))
|
608
|
-
(let ((low XReg (rv_orn (value_regs_get x 0) (value_regs_get y 0)))
|
609
|
-
(high XReg (rv_orn (value_regs_get x 1) (value_regs_get y 1))))
|
610
|
-
(value_regs low high)))
|
611
|
-
|
612
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register ty) (bor x y)))
|
613
|
-
(rv_vor_vv x y (unmasked) ty))
|
614
|
-
|
615
|
-
(rule 9 (lower (has_type (ty_vec_fits_in_register ty) (bor x (splat y))))
|
616
|
-
(if (ty_vector_not_float ty))
|
617
|
-
(rv_vor_vx x y (unmasked) ty))
|
618
|
-
|
619
|
-
(rule 10 (lower (has_type (ty_vec_fits_in_register ty) (bor (splat x) y)))
|
620
|
-
(if (ty_vector_not_float ty))
|
621
|
-
(rv_vor_vx y x (unmasked) ty))
|
622
|
-
|
623
|
-
(rule 11 (lower (has_type (ty_vec_fits_in_register ty) (bor x (replicated_imm5 y))))
|
624
|
-
(rv_vor_vi x y (unmasked) ty))
|
625
|
-
|
626
|
-
(rule 12 (lower (has_type (ty_vec_fits_in_register ty) (bor (replicated_imm5 x) y)))
|
627
|
-
(rv_vor_vi y x (unmasked) ty))
|
628
|
-
|
629
|
-
|
630
|
-
;;;; Rules for `xor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
631
|
-
(rule 0 (lower (has_type (fits_in_64 (ty_int ty)) (bxor x y)))
|
632
|
-
(rv_xor x y))
|
633
|
-
|
634
|
-
;; Special cases for when one operand is an immediate that fits in 12 bits.
|
635
|
-
(rule 1 (lower (has_type (fits_in_64 (ty_int ty)) (bxor x (imm12_from_value y))))
|
636
|
-
(rv_xori x y))
|
637
|
-
|
638
|
-
(rule 2 (lower (has_type (fits_in_64 (ty_int ty)) (bxor (imm12_from_value x) y)))
|
639
|
-
(rv_xori y x))
|
640
|
-
|
641
|
-
(rule 3 (lower (has_type $I128 (bxor x y)))
|
642
|
-
(lower_b128_binary (AluOPRRR.Xor) x y))
|
643
|
-
|
644
|
-
(rule 4 (lower (has_type (ty_scalar_float ty) (bxor x y)))
|
645
|
-
(lower_float_binary (AluOPRRR.Xor) x y ty))
|
646
|
-
|
647
|
-
(rule 5 (lower (has_type (ty_vec_fits_in_register ty) (bxor x y)))
|
648
|
-
(rv_vxor_vv x y (unmasked) ty))
|
649
|
-
|
650
|
-
(rule 6 (lower (has_type (ty_vec_fits_in_register ty) (bxor x (splat y))))
|
651
|
-
(if (ty_vector_not_float ty))
|
652
|
-
(rv_vxor_vx x y (unmasked) ty))
|
653
|
-
|
654
|
-
(rule 7 (lower (has_type (ty_vec_fits_in_register ty) (bxor (splat x) y)))
|
655
|
-
(if (ty_vector_not_float ty))
|
656
|
-
(rv_vxor_vx y x (unmasked) ty))
|
657
|
-
|
658
|
-
(rule 8 (lower (has_type (ty_vec_fits_in_register ty) (bxor x (replicated_imm5 y))))
|
659
|
-
(rv_vxor_vi x y (unmasked) ty))
|
660
|
-
|
661
|
-
(rule 9 (lower (has_type (ty_vec_fits_in_register ty) (bxor (replicated_imm5 x) y)))
|
662
|
-
(rv_vxor_vi y x (unmasked) ty))
|
663
|
-
|
664
|
-
|
665
|
-
;;;; Rules for `bnot` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
666
|
-
(rule 0 (lower (has_type (ty_scalar ty) (bnot x)))
|
667
|
-
(gen_bnot ty x))
|
668
|
-
|
669
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (bnot x)))
|
670
|
-
(rv_vnot_v x (unmasked) ty))
|
671
|
-
|
672
|
-
;;;; Rules for `bit_reverse` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
673
|
-
(rule (lower (has_type (fits_in_64 (ty_int ty)) (bitrev x)))
|
674
|
-
(lower_bit_reverse x ty))
|
675
|
-
|
676
|
-
(rule 1 (lower (has_type $I128 (bitrev x)))
|
677
|
-
(let ((val ValueRegs x)
|
678
|
-
(lo_rev XReg (lower_bit_reverse (value_regs_get val 0) $I64))
|
679
|
-
(hi_rev XReg (lower_bit_reverse (value_regs_get val 1) $I64)))
|
680
|
-
(value_regs hi_rev lo_rev)))
|
681
|
-
|
682
|
-
;;;; Rules for `bswap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
683
|
-
(rule 1 (lower (has_type (fits_in_64 (ty_int ty)) (bswap x)))
|
684
|
-
(gen_bswap ty x))
|
685
|
-
|
686
|
-
(rule 2 (lower (has_type $I128 (bswap x)))
|
687
|
-
(value_regs
|
688
|
-
(gen_bswap $I64 (value_regs_get x 1))
|
689
|
-
(gen_bswap $I64 (value_regs_get x 0))))
|
690
|
-
|
691
|
-
|
692
|
-
;;;; Rules for `ctz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
693
|
-
(rule (lower (has_type (fits_in_64 ty) (ctz x)))
|
694
|
-
(lower_ctz ty x))
|
695
|
-
|
696
|
-
(rule 1 (lower (has_type $I128 (ctz x)))
|
697
|
-
(lower_ctz_128 x))
|
698
|
-
|
699
|
-
;;;; Rules for `clz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
700
|
-
(rule (lower (has_type (fits_in_64 ty) (clz x)))
|
701
|
-
(lower_clz ty x))
|
702
|
-
|
703
|
-
(rule 1 (lower (has_type $I128 (clz x)))
|
704
|
-
(lower_clz_i128 x))
|
705
|
-
|
706
|
-
;;;; Rules for `cls` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
707
|
-
(rule (lower (has_type (fits_in_64 ty) (cls x)))
|
708
|
-
(lower_cls ty x))
|
709
|
-
|
710
|
-
(rule 1 (lower (has_type $I128 (cls x)))
|
711
|
-
(lower_cls_i128 x))
|
712
|
-
|
713
|
-
;;;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
714
|
-
(rule (lower (has_type out_ty (uextend val @ (value_type in_ty))))
|
715
|
-
(extend val (ExtendOp.Zero) in_ty out_ty))
|
716
|
-
|
717
|
-
;;;; Rules for `sextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
718
|
-
(rule (lower (has_type out_ty (sextend val @ (value_type in_ty))))
|
719
|
-
(extend val (ExtendOp.Signed) in_ty out_ty))
|
720
|
-
|
721
|
-
;; The instructions below are present in RV64I and sign-extend the result to 64 bits.
|
722
|
-
|
723
|
-
(rule 1 (lower (has_type $I64 (sextend (has_type $I32 (iadd x y)))))
|
724
|
-
(rv_addw x y))
|
725
|
-
|
726
|
-
(rule 1 (lower (has_type $I64 (sextend (has_type $I32 (isub x y)))))
|
727
|
-
(rv_subw x y))
|
728
|
-
|
729
|
-
(rule 1 (lower (has_type $I64 (sextend (has_type $I32 (ishl x y)))))
|
730
|
-
(rv_sllw x (value_regs_get y 0)))
|
731
|
-
|
732
|
-
(rule 1 (lower (has_type $I64 (sextend (has_type $I32 (ushr x y)))))
|
733
|
-
(rv_srlw x (value_regs_get y 0)))
|
734
|
-
|
735
|
-
(rule 1 (lower (has_type $I64 (sextend (has_type $I32 (sshr x y)))))
|
736
|
-
(rv_sraw x (value_regs_get y 0)))
|
737
|
-
|
738
|
-
|
739
|
-
(rule 2 (lower (has_type $I64 (sextend (has_type $I32 (iadd x (imm12_from_value y))))))
|
740
|
-
(rv_addiw x y))
|
741
|
-
|
742
|
-
(rule 3 (lower (has_type $I64 (sextend (has_type $I32 (iadd (imm12_from_value x) y)))))
|
743
|
-
(rv_addiw y x))
|
744
|
-
|
745
|
-
(rule 2 (lower (has_type $I64 (sextend (has_type $I32 (ishl x (imm12_from_value y))))))
|
746
|
-
(rv_slliw x y))
|
747
|
-
|
748
|
-
(rule 2 (lower (has_type $I64 (sextend (has_type $I32 (ushr x (imm12_from_value y))))))
|
749
|
-
(rv_srliw x y))
|
750
|
-
|
751
|
-
(rule 2 (lower (has_type $I64 (sextend (has_type $I32 (sshr x (imm12_from_value y))))))
|
752
|
-
(rv_sraiw x y))
|
753
|
-
|
754
|
-
;;;; Rules for `popcnt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
755
|
-
|
756
|
-
(rule 0 (lower (has_type (ty_int_ref_scalar_64 ty) (popcnt x)))
|
757
|
-
(lower_popcnt x ty))
|
758
|
-
|
759
|
-
(rule 1 (lower (has_type $I128 (popcnt x)))
|
760
|
-
(lower_popcnt_i128 x))
|
761
|
-
|
762
|
-
;; Popcount using multiply.
|
763
|
-
;; This is popcount64c() from
|
764
|
-
;; http://en.wikipedia.org/wiki/Hamming_weight
|
765
|
-
;;
|
766
|
-
;; Here's the C version for 32 bits:
|
767
|
-
;; x = x - ((x>> 1) & 0x55555555);
|
768
|
-
;; x = (x & 0x33333333) + ((x >> 2) & 0x33333333);
|
769
|
-
;; x = ((x + (x >> 4)) & 0x0F0F0F0F);
|
770
|
-
;; return (x * 0x01010101) >> 24; // Here 24 is the type width - 8.
|
771
|
-
;;
|
772
|
-
;; TODO: LLVM generates a much better implementation for I8X16. See: https://godbolt.org/z/qr6vf9Gr3
|
773
|
-
;; For the other types it seems to be largely the same.
|
774
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (popcnt x)))
|
775
|
-
(if-let one (u64_to_uimm5 1))
|
776
|
-
(if-let two (u64_to_uimm5 2))
|
777
|
-
(if-let four (u64_to_uimm5 4))
|
778
|
-
|
779
|
-
(let (;; x = x - ((x >> 1) & 0x55555555);
|
780
|
-
(mask_55 XReg (imm (lane_type ty) (u64_and 0x5555555555555555 (ty_mask (lane_type ty)))))
|
781
|
-
(count2_shr VReg (rv_vsrl_vi x one (unmasked) ty))
|
782
|
-
(count2_and VReg (rv_vand_vx count2_shr mask_55 (unmasked) ty))
|
783
|
-
(count2 VReg (rv_vsub_vv x count2_and (unmasked) ty))
|
784
|
-
|
785
|
-
;; x = (x & 0x33333333) + ((x >> 2) & 0x33333333);
|
786
|
-
(mask_33 XReg (imm (lane_type ty) (u64_and 0x3333333333333333 (ty_mask (lane_type ty)))))
|
787
|
-
(count4_shr VReg (rv_vsrl_vi count2 two (unmasked) ty))
|
788
|
-
(count4_and VReg (rv_vand_vx count4_shr mask_33 (unmasked) ty))
|
789
|
-
(count4_lhs VReg (rv_vand_vx count2 mask_33 (unmasked) ty))
|
790
|
-
(count4 VReg (rv_vadd_vv count4_lhs count4_and (unmasked) ty))
|
791
|
-
|
792
|
-
;; x = (x + (x >> 4)) & 0x0F0F0F0F;
|
793
|
-
(mask_0f XReg (imm (lane_type ty) (u64_and 0x0f0f0f0f0f0f0f0f (ty_mask (lane_type ty)))))
|
794
|
-
(count8_shr VReg (rv_vsrl_vi count4 four (unmasked) ty))
|
795
|
-
(count8_add VReg (rv_vadd_vv count4 count8_shr (unmasked) ty))
|
796
|
-
(count8 VReg (rv_vand_vx count8_add mask_0f (unmasked) ty))
|
797
|
-
|
798
|
-
;; (x * 0x01010101) >> (<ty_width> - 8)
|
799
|
-
(mask_01 XReg (imm (lane_type ty) (u64_and 0x0101010101010101 (ty_mask (lane_type ty)))))
|
800
|
-
(mul VReg (rv_vmul_vx count8 mask_01 (unmasked) ty))
|
801
|
-
(shift XReg (imm $I64 (u64_sub (ty_bits (lane_type ty)) 8)))
|
802
|
-
(res VReg (rv_vsrl_vx mul shift (unmasked) ty)))
|
803
|
-
res))
|
804
|
-
|
805
|
-
;;;; Rules for `ishl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
806
|
-
|
807
|
-
;; 8/16 bit types need a mask on the shift amount
|
808
|
-
(rule 0 (lower (has_type (ty_int (ty_8_or_16 ty)) (ishl x y)))
|
809
|
-
(if-let mask (u64_to_imm12 (shift_mask ty)))
|
810
|
-
(rv_sllw x (rv_andi (value_regs_get y 0) mask)))
|
811
|
-
|
812
|
-
;; Using the 32bit version of `sll` automatically masks the shift amount.
|
813
|
-
(rule 1 (lower (has_type $I32 (ishl x y)))
|
814
|
-
(rv_sllw x (value_regs_get y 0)))
|
815
|
-
|
816
|
-
;; Similarly, the 64bit version does the right thing.
|
817
|
-
(rule 1 (lower (has_type $I64 (ishl x y)))
|
818
|
-
(rv_sll x (value_regs_get y 0)))
|
819
|
-
|
820
|
-
;; If the shift amount is known. We can mask it and encode it in the instruction.
|
821
|
-
(rule 2 (lower (has_type (int_fits_in_32 ty) (ishl x (maybe_uextend (imm12_from_value y)))))
|
822
|
-
(rv_slliw x (imm12_and y (shift_mask ty))))
|
823
|
-
|
824
|
-
;; We technically don't need to mask the shift amount here. The instruction
|
825
|
-
;; does the right thing. But it's neater when pretty printing it.
|
826
|
-
(rule 3 (lower (has_type ty @ $I64 (ishl x (maybe_uextend (imm12_from_value y)))))
|
827
|
-
(rv_slli x (imm12_and y (shift_mask ty))))
|
828
|
-
|
829
|
-
;; With `Zba` we have a shift that zero extends the LHS argument.
|
830
|
-
(rule 4 (lower (has_type $I64 (ishl (uextend x @ (value_type $I32)) (maybe_uextend (imm12_from_value y)))))
|
831
|
-
(if-let $true (has_zba))
|
832
|
-
(rv_slliuw x y))
|
833
|
-
|
834
|
-
;; I128 cases
|
835
|
-
(rule 4 (lower (has_type $I128 (ishl x y)))
|
836
|
-
(let ((tmp ValueRegs (gen_shamt $I128 (value_regs_get y 0)))
|
837
|
-
(shamt XReg (value_regs_get tmp 0))
|
838
|
-
(len_sub_shamt XReg (value_regs_get tmp 1))
|
839
|
-
;;
|
840
|
-
(low XReg (rv_sll (value_regs_get x 0) shamt))
|
841
|
-
;; high part.
|
842
|
-
(high_part1 XReg (rv_srl (value_regs_get x 0) len_sub_shamt))
|
843
|
-
(high_part2 XReg (gen_select_reg (IntCC.Equal) shamt (zero_reg) (zero_reg) high_part1))
|
844
|
-
;;
|
845
|
-
(high_part3 XReg (rv_sll (value_regs_get x 1) shamt))
|
846
|
-
(high XReg (rv_or high_part2 high_part3))
|
847
|
-
;;
|
848
|
-
(const64 XReg (load_u64_constant 64))
|
849
|
-
(shamt_128 XReg (rv_andi (value_regs_get y 0) (imm12_const 127))))
|
850
|
-
(value_regs
|
851
|
-
(gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 (zero_reg) low)
|
852
|
-
(gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 low high))))
|
853
|
-
|
854
|
-
;; SIMD Cases
|
855
|
-
;; We don't need to mask anything since it is done by the instruction according to SEW.
|
856
|
-
|
857
|
-
(rule 5 (lower (has_type (ty_vec_fits_in_register ty) (ishl x y)))
|
858
|
-
(rv_vsll_vx x (value_regs_get y 0) (unmasked) ty))
|
859
|
-
|
860
|
-
(rule 6 (lower (has_type (ty_vec_fits_in_register ty) (ishl x (maybe_uextend (uimm5_from_value y)))))
|
861
|
-
(rv_vsll_vi x y (unmasked) ty))
|
862
|
-
|
863
|
-
;;;; Rules for `ushr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
864
|
-
|
865
|
-
;; 8/16 bit types need a mask on the shift amount, and the LHS needs to be
|
866
|
-
;; zero extended.
|
867
|
-
(rule 0 (lower (has_type (ty_int (fits_in_16 ty)) (ushr x y)))
|
868
|
-
(if-let mask (u64_to_imm12 (shift_mask ty)))
|
869
|
-
(rv_srlw (zext x ty $I64) (rv_andi (value_regs_get y 0) mask)))
|
870
|
-
|
871
|
-
;; Using the 32bit version of `srl` automatically masks the shift amount.
|
872
|
-
(rule 1 (lower (has_type $I32 (ushr x y)))
|
873
|
-
(rv_srlw x (value_regs_get y 0)))
|
874
|
-
|
875
|
-
;; Similarly, the 64bit version does the right thing.
|
876
|
-
(rule 1 (lower (has_type $I64 (ushr x y)))
|
877
|
-
(rv_srl x (value_regs_get y 0)))
|
878
|
-
|
879
|
-
;; When the RHS is known we can just encode it in the instruction.
|
880
|
-
(rule 2 (lower (has_type (ty_int (fits_in_16 ty)) (ushr x (maybe_uextend (imm12_from_value y)))))
|
881
|
-
(rv_srliw (zext x ty $I64) (imm12_and y (shift_mask ty))))
|
882
|
-
|
883
|
-
(rule 3 (lower (has_type $I32 (ushr x (maybe_uextend (imm12_from_value y)))))
|
884
|
-
(rv_srliw x y))
|
885
|
-
|
886
|
-
(rule 3 (lower (has_type $I64 (ushr x (maybe_uextend (imm12_from_value y)))))
|
887
|
-
(rv_srli x y))
|
888
|
-
|
889
|
-
(rule 3 (lower (has_type $I128 (ushr x y)))
|
890
|
-
(let ((tmp ValueRegs (gen_shamt $I128 (value_regs_get y 0)))
|
891
|
-
(shamt XReg (value_regs_get tmp 0))
|
892
|
-
(len_sub_shamt XReg (value_regs_get tmp 1))
|
893
|
-
;; low part.
|
894
|
-
(low_part1 XReg (rv_sll (value_regs_get x 1) len_sub_shamt))
|
895
|
-
(low_part2 XReg (gen_select_reg (IntCC.Equal) shamt (zero_reg) (zero_reg) low_part1))
|
896
|
-
;;
|
897
|
-
(low_part3 XReg (rv_srl (value_regs_get x 0) shamt))
|
898
|
-
(low XReg (rv_or low_part2 low_part3))
|
899
|
-
;;
|
900
|
-
(const64 XReg (load_u64_constant 64))
|
901
|
-
;;
|
902
|
-
(high XReg (rv_srl (value_regs_get x 1) shamt))
|
903
|
-
(shamt_128 XReg (rv_andi (value_regs_get y 0) (imm12_const 127))))
|
904
|
-
(value_regs
|
905
|
-
(gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 high low)
|
906
|
-
(gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 (zero_reg) high))))
|
907
|
-
|
908
|
-
;; SIMD Cases
|
909
|
-
;; We don't need to mask or extend anything since it is done by the instruction according to SEW.
|
910
|
-
|
911
|
-
(rule 4 (lower (has_type (ty_vec_fits_in_register ty) (ushr x y)))
|
912
|
-
(rv_vsrl_vx x (value_regs_get y 0) (unmasked) ty))
|
913
|
-
|
914
|
-
(rule 5 (lower (has_type (ty_vec_fits_in_register ty) (ushr x (maybe_uextend (uimm5_from_value y)))))
|
915
|
-
(rv_vsrl_vi x y (unmasked) ty))
|
916
|
-
|
917
|
-
;;;; Rules for `sshr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
918
|
-
|
919
|
-
;; 8/16 bit types need a mask on the shift amount, and the LHS needs to be
|
920
|
-
;; zero extended.
|
921
|
-
(rule 0 (lower (has_type (ty_int (fits_in_16 ty)) (sshr x y)))
|
922
|
-
(if-let mask (u64_to_imm12 (shift_mask ty)))
|
923
|
-
(rv_sraw (sext x ty $I64) (rv_andi (value_regs_get y 0) mask)))
|
924
|
-
|
925
|
-
;; Using the 32bit version of `sra` automatically masks the shift amount.
|
926
|
-
(rule 1 (lower (has_type $I32 (sshr x y)))
|
927
|
-
(rv_sraw x (value_regs_get y 0)))
|
928
|
-
|
929
|
-
;; Similarly, the 64bit version does the right thing.
|
930
|
-
(rule 1 (lower (has_type $I64 (sshr x y)))
|
931
|
-
(rv_sra x (value_regs_get y 0)))
|
932
|
-
|
933
|
-
;; When the RHS is known we can just encode it in the instruction.
|
934
|
-
(rule 2 (lower (has_type (ty_int (fits_in_16 ty)) (sshr x (maybe_uextend (imm12_from_value y)))))
|
935
|
-
(rv_sraiw (sext x ty $I64) (imm12_and y (shift_mask ty))))
|
936
|
-
|
937
|
-
(rule 3 (lower (has_type $I32 (sshr x (maybe_uextend (imm12_from_value y)))))
|
938
|
-
(rv_sraiw x y))
|
939
|
-
|
940
|
-
(rule 3 (lower (has_type $I64 (sshr x (maybe_uextend (imm12_from_value y)))))
|
941
|
-
(rv_srai x y))
|
942
|
-
|
943
|
-
(rule 3 (lower (has_type $I128 (sshr x y)))
|
944
|
-
(let ((tmp ValueRegs (gen_shamt $I128 (value_regs_get y 0)))
|
945
|
-
(shamt XReg (value_regs_get tmp 0))
|
946
|
-
(len_sub_shamt XReg (value_regs_get tmp 1))
|
947
|
-
;; low part.
|
948
|
-
(low_part1 XReg (rv_sll (value_regs_get x 1) len_sub_shamt))
|
949
|
-
(low_part2 XReg (gen_select_reg (IntCC.Equal) shamt (zero_reg) (zero_reg) low_part1))
|
950
|
-
;;
|
951
|
-
(low_part3 XReg (rv_srl (value_regs_get x 0) shamt))
|
952
|
-
(low XReg (rv_or low_part2 low_part3))
|
953
|
-
;;
|
954
|
-
(const64 XReg (load_u64_constant 64))
|
955
|
-
;;
|
956
|
-
(high XReg (rv_sra (value_regs_get x 1) shamt))
|
957
|
-
;;
|
958
|
-
(const_neg_1 XReg (load_imm12 -1))
|
959
|
-
;;
|
960
|
-
(high_replacement XReg (gen_select_reg (IntCC.SignedLessThan) (value_regs_get x 1) (zero_reg) const_neg_1 (zero_reg)))
|
961
|
-
(const64 XReg (load_u64_constant 64))
|
962
|
-
(shamt_128 XReg (rv_andi (value_regs_get y 0) (imm12_const 127))))
|
963
|
-
(value_regs
|
964
|
-
(gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 high low)
|
965
|
-
(gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 high_replacement high))))
|
966
|
-
|
967
|
-
;; SIMD Cases
|
968
|
-
;; We don't need to mask or extend anything since it is done by the instruction according to SEW.
|
969
|
-
|
970
|
-
(rule 4 (lower (has_type (ty_vec_fits_in_register ty) (sshr x y)))
|
971
|
-
(rv_vsra_vx x (value_regs_get y 0) (unmasked) ty))
|
972
|
-
|
973
|
-
(rule 5 (lower (has_type (ty_vec_fits_in_register ty) (sshr x (maybe_uextend (uimm5_from_value y)))))
|
974
|
-
(rv_vsra_vi x y (unmasked) ty))
|
975
|
-
|
976
|
-
|
977
|
-
;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
978
|
-
(rule (lower (has_type (fits_in_64 ty) (rotl x y)))
|
979
|
-
(lower_rotl ty (zext x ty $I64) (value_regs_get y 0)))
|
980
|
-
|
981
|
-
(rule 1 (lower (has_type $I128 (rotl x y)))
|
982
|
-
(lower_i128_rotl x y))
|
983
|
-
|
984
|
-
;;;; Rules for `rotr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
985
|
-
(rule (lower (has_type (fits_in_64 ty) (rotr x y)))
|
986
|
-
(lower_rotr ty (zext x ty $I64) (value_regs_get y 0)))
|
987
|
-
|
988
|
-
(rule 1 (lower (has_type $I128 (rotr x y)))
|
989
|
-
(lower_i128_rotr x y))
|
990
|
-
|
991
|
-
|
992
|
-
;;;; Rules for `fabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
993
|
-
(rule 0 (lower (has_type (ty_scalar_float ty) (fabs x)))
|
994
|
-
(rv_fabs ty x))
|
995
|
-
|
996
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fabs x)))
|
997
|
-
(rv_vfabs_v x (unmasked) ty))
|
998
|
-
|
999
|
-
;;;; Rules for `fneg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1000
|
-
(rule 0 (lower (has_type (ty_scalar_float ty) (fneg x)))
|
1001
|
-
(rv_fneg ty x))
|
1002
|
-
|
1003
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fneg x)))
|
1004
|
-
(rv_vfneg_v x (unmasked) ty))
|
1005
|
-
|
1006
|
-
;;;; Rules for `fcopysign` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1007
|
-
(rule 0 (lower (has_type (ty_scalar_float ty) (fcopysign x y)))
|
1008
|
-
(rv_fsgnj ty x y))
|
1009
|
-
|
1010
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fcopysign x y)))
|
1011
|
-
(rv_vfsgnj_vv x y (unmasked) ty))
|
1012
|
-
|
1013
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (fcopysign x (splat y))))
|
1014
|
-
(rv_vfsgnj_vf x y (unmasked) ty))
|
1015
|
-
|
1016
|
-
;;;; Rules for `fma` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1017
|
-
(rule (lower (has_type ty (fma x y z)))
|
1018
|
-
(rv_fmadd ty x y z))
|
1019
|
-
|
1020
|
-
|
1021
|
-
;;;; Rules for `sqrt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1022
|
-
(rule 0 (lower (has_type (ty_scalar_float ty) (sqrt x)))
|
1023
|
-
(rv_fsqrt ty x))
|
1024
|
-
|
1025
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (sqrt x)))
|
1026
|
-
(rv_vfsqrt_v x (unmasked) ty))
|
1027
|
-
|
1028
|
-
;;;; Rules for `AtomicRMW` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1029
|
-
(rule -1
|
1030
|
-
;;
|
1031
|
-
(lower
|
1032
|
-
(has_type (valid_atomic_transaction ty) (atomic_rmw flags op addr x)))
|
1033
|
-
(gen_atomic (get_atomic_rmw_op ty op) addr x (atomic_amo)))
|
1034
|
-
|
1035
|
-
;;; for I8 and I16
|
1036
|
-
(rule 1
|
1037
|
-
(lower
|
1038
|
-
(has_type (valid_atomic_transaction (fits_in_16 ty)) (atomic_rmw flags op addr x)))
|
1039
|
-
(gen_atomic_rmw_loop op ty addr x))
|
1040
|
-
|
1041
|
-
;;;special for I8 and I16 max min etc.
|
1042
|
-
;;;because I need uextend or sextend the value.
|
1043
|
-
(rule 2
|
1044
|
-
(lower
|
1045
|
-
(has_type (valid_atomic_transaction (fits_in_16 ty)) (atomic_rmw flags (is_atomic_rmw_max_etc op $true) addr x)))
|
1046
|
-
(gen_atomic_rmw_loop op ty addr (sext x ty $I64)))
|
1047
|
-
|
1048
|
-
|
1049
|
-
(rule 2
|
1050
|
-
;;
|
1051
|
-
(lower
|
1052
|
-
(has_type (valid_atomic_transaction (fits_in_16 ty)) (atomic_rmw flags (is_atomic_rmw_max_etc op $false) addr x)))
|
1053
|
-
;;
|
1054
|
-
(gen_atomic_rmw_loop op ty addr (zext x ty $I64)))
|
1055
|
-
|
1056
|
-
;;;;; Rules for `AtomicRmwOp.Sub`
|
1057
|
-
(rule
|
1058
|
-
(lower
|
1059
|
-
(has_type (valid_atomic_transaction ty) (atomic_rmw flags (AtomicRmwOp.Sub) addr x)))
|
1060
|
-
(let
|
1061
|
-
((tmp WritableReg (temp_writable_reg ty))
|
1062
|
-
(x2 Reg (rv_neg x)))
|
1063
|
-
(gen_atomic (get_atomic_rmw_op ty (AtomicRmwOp.Add)) addr x2 (atomic_amo))))
|
1064
|
-
|
1065
|
-
(decl gen_atomic_rmw_loop (AtomicRmwOp Type XReg XReg) XReg)
|
1066
|
-
(rule
|
1067
|
-
(gen_atomic_rmw_loop op ty addr x)
|
1068
|
-
(let
|
1069
|
-
((dst WritableXReg (temp_writable_xreg))
|
1070
|
-
(t0 WritableXReg (temp_writable_xreg))
|
1071
|
-
(_ Unit (emit (MInst.AtomicRmwLoop (gen_atomic_offset addr ty) op dst ty (gen_atomic_p addr ty) x t0))))
|
1072
|
-
(writable_reg_to_reg dst)))
|
1073
|
-
|
1074
|
-
;;;;; Rules for `AtomicRmwOp.Nand`
|
1075
|
-
(rule
|
1076
|
-
(lower
|
1077
|
-
(has_type (valid_atomic_transaction ty) (atomic_rmw flags (AtomicRmwOp.Nand) addr x)))
|
1078
|
-
(gen_atomic_rmw_loop (AtomicRmwOp.Nand) ty addr x))
|
1079
|
-
|
1080
|
-
(decl is_atomic_rmw_max_etc (AtomicRmwOp bool) AtomicRmwOp)
|
1081
|
-
(extern extractor is_atomic_rmw_max_etc is_atomic_rmw_max_etc)
|
1082
|
-
|
1083
|
-
;;;;; Rules for `atomic load`;;;;;;;;;;;;;;;;;
|
1084
|
-
(rule
|
1085
|
-
(lower (has_type (valid_atomic_transaction ty) (atomic_load flags p)))
|
1086
|
-
(gen_atomic_load p ty))
|
1087
|
-
|
1088
|
-
|
1089
|
-
;;;;; Rules for `atomic store`;;;;;;;;;;;;;;;;;
|
1090
|
-
(rule
|
1091
|
-
(lower (atomic_store flags src @ (value_type (valid_atomic_transaction ty)) p))
|
1092
|
-
(gen_atomic_store p ty src))
|
1093
|
-
|
1094
|
-
(decl gen_atomic_offset (XReg Type) XReg)
|
1095
|
-
(rule 1 (gen_atomic_offset p (fits_in_16 ty))
|
1096
|
-
(rv_slli (rv_andi p (imm12_const 3)) (imm12_const 3)))
|
1097
|
-
|
1098
|
-
(rule (gen_atomic_offset p _)
|
1099
|
-
(zero_reg))
|
1100
|
-
|
1101
|
-
(decl gen_atomic_p (XReg Type) XReg)
|
1102
|
-
(rule 1 (gen_atomic_p p (fits_in_16 ty))
|
1103
|
-
(rv_andi p (imm12_const -4)))
|
1104
|
-
|
1105
|
-
(rule (gen_atomic_p p _)
|
1106
|
-
p)
|
1107
|
-
|
1108
|
-
|
1109
|
-
;;;;; Rules for `atomic cas`;;;;;;;;;;;;;;;;;
|
1110
|
-
(rule
|
1111
|
-
(lower (has_type (valid_atomic_transaction ty) (atomic_cas flags p e x)))
|
1112
|
-
(let
|
1113
|
-
((t0 WritableReg (temp_writable_reg ty))
|
1114
|
-
(dst WritableReg (temp_writable_reg ty))
|
1115
|
-
(_ Unit (emit (MInst.AtomicCas (gen_atomic_offset p ty) t0 dst (zext e ty $I64) (gen_atomic_p p ty) x ty))))
|
1116
|
-
(writable_reg_to_reg dst)))
|
1117
|
-
|
1118
|
-
;;;;; Rules for `ireduce`;;;;;;;;;;;;;;;;;
|
1119
|
-
(rule
|
1120
|
-
(lower (has_type ty (ireduce x)))
|
1121
|
-
(value_regs_get x 0))
|
1122
|
-
|
1123
|
-
;;;;; Rules for `fpromote`;;;;;;;;;;;;;;;;;
|
1124
|
-
(rule (lower (fpromote x))
|
1125
|
-
(rv_fcvtds x))
|
1126
|
-
|
1127
|
-
;;;;; Rules for `fdemote`;;;;;;;;;;;;;;;;;;
|
1128
|
-
(rule (lower (fdemote x))
|
1129
|
-
(rv_fcvtsd x))
|
1130
|
-
|
1131
|
-
|
1132
|
-
;;;;; Rules for for float arithmetic
|
1133
|
-
|
1134
|
-
|
1135
|
-
;;;; Rules for `fadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1136
|
-
|
1137
|
-
(rule 0 (lower (has_type (ty_scalar_float ty) (fadd x y)))
|
1138
|
-
(rv_fadd ty x y))
|
1139
|
-
|
1140
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fadd x y)))
|
1141
|
-
(rv_vfadd_vv x y (unmasked) ty))
|
1142
|
-
|
1143
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (fadd x (splat y))))
|
1144
|
-
(rv_vfadd_vf x y (unmasked) ty))
|
1145
|
-
|
1146
|
-
(rule 3 (lower (has_type (ty_vec_fits_in_register ty) (fadd (splat x) y)))
|
1147
|
-
(rv_vfadd_vf y x (unmasked) ty))
|
1148
|
-
|
1149
|
-
|
1150
|
-
;;;; Rules for `fsub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1151
|
-
(rule 0 (lower (has_type (ty_scalar_float ty) (fsub x y)))
|
1152
|
-
(rv_fsub ty x y))
|
1153
|
-
|
1154
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fsub x y)))
|
1155
|
-
(rv_vfsub_vv x y (unmasked) ty))
|
1156
|
-
|
1157
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (fsub x (splat y))))
|
1158
|
-
(rv_vfsub_vf x y (unmasked) ty))
|
1159
|
-
|
1160
|
-
(rule 3 (lower (has_type (ty_vec_fits_in_register ty) (fsub (splat x) y)))
|
1161
|
-
(rv_vfrsub_vf y x (unmasked) ty))
|
1162
|
-
|
1163
|
-
;;;; Rules for `fmul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1164
|
-
(rule 0 (lower (has_type (ty_scalar_float ty) (fmul x y)))
|
1165
|
-
(rv_fmul ty x y))
|
1166
|
-
|
1167
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fmul x y)))
|
1168
|
-
(rv_vfmul_vv x y (unmasked) ty))
|
1169
|
-
|
1170
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (fmul x (splat y))))
|
1171
|
-
(rv_vfmul_vf x y (unmasked) ty))
|
1172
|
-
|
1173
|
-
(rule 3 (lower (has_type (ty_vec_fits_in_register ty) (fmul (splat x) y)))
|
1174
|
-
(rv_vfmul_vf y x (unmasked) ty))
|
1175
|
-
|
1176
|
-
|
1177
|
-
;;;; Rules for `fdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1178
|
-
(rule 0 (lower (has_type (ty_scalar_float ty) (fdiv x y)))
|
1179
|
-
(rv_fdiv ty x y))
|
1180
|
-
|
1181
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fdiv x y)))
|
1182
|
-
(rv_vfdiv_vv x y (unmasked) ty))
|
1183
|
-
|
1184
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (fdiv x (splat y))))
|
1185
|
-
(rv_vfdiv_vf x y (unmasked) ty))
|
1186
|
-
|
1187
|
-
(rule 3 (lower (has_type (ty_vec_fits_in_register ty) (fdiv (splat x) y)))
|
1188
|
-
(rv_vfrdiv_vf y x (unmasked) ty))
|
1189
|
-
|
1190
|
-
;;;; Rules for `fmin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1191
|
-
|
1192
|
-
(rule 0 (lower (has_type (ty_scalar_float ty) (fmin x y)))
|
1193
|
-
(gen_float_select (FloatSelectOP.Min) x y ty))
|
1194
|
-
|
1195
|
-
;; vfmin does almost the right thing, but it does not handle NaN's correctly.
|
1196
|
-
;; We should return a NaN if any of the inputs is a NaN, but vfmin returns the
|
1197
|
-
;; number input instead.
|
1198
|
-
;;
|
1199
|
-
;; TODO: We can improve this by using a masked `fmin` instruction that modifies
|
1200
|
-
;; the canonical nan register. That way we could avoid the `vmerge.vv` instruction.
|
1201
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fmin x y)))
|
1202
|
-
(let ((is_not_nan VReg (gen_fcmp_mask ty (FloatCC.Ordered) x y))
|
1203
|
-
(nan XReg (imm $I64 (canonical_nan_u64 (lane_type ty))))
|
1204
|
-
(vec_nan VReg (rv_vmv_vx nan ty))
|
1205
|
-
(min VReg (rv_vfmin_vv x y (unmasked) ty)))
|
1206
|
-
(rv_vmerge_vvm vec_nan min is_not_nan ty)))
|
1207
|
-
|
1208
|
-
;;;; Rules for `fmax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1209
|
-
|
1210
|
-
(rule 0 (lower (has_type (ty_scalar_float ty) (fmax x y)))
|
1211
|
-
(gen_float_select (FloatSelectOP.Max) x y ty))
|
1212
|
-
|
1213
|
-
;; vfmax does almost the right thing, but it does not handle NaN's correctly.
|
1214
|
-
;; We should return a NaN if any of the inputs is a NaN, but vfmax returns the
|
1215
|
-
;; number input instead.
|
1216
|
-
;;
|
1217
|
-
;; TODO: We can improve this by using a masked `fmax` instruction that modifies
|
1218
|
-
;; the canonical nan register. That way we could avoid the `vmerge.vv` instruction.
|
1219
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fmax x y)))
|
1220
|
-
(let ((is_not_nan VReg (gen_fcmp_mask ty (FloatCC.Ordered) x y))
|
1221
|
-
(nan XReg (imm $I64 (canonical_nan_u64 (lane_type ty))))
|
1222
|
-
(vec_nan VReg (rv_vmv_vx nan ty))
|
1223
|
-
(max VReg (rv_vfmax_vv x y (unmasked) ty)))
|
1224
|
-
(rv_vmerge_vvm vec_nan max is_not_nan ty)))
|
1225
|
-
|
1226
|
-
;;;; Rules for `fmin_pseudo` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1227
|
-
|
1228
|
-
(rule 0 (lower (has_type (ty_scalar_float ty) (fmin_pseudo x y)))
|
1229
|
-
(gen_float_select_pseudo (FloatSelectOP.Min) x y ty))
|
1230
|
-
|
1231
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fmin_pseudo x y)))
|
1232
|
-
(let ((mask VReg (gen_fcmp_mask ty (FloatCC.LessThan) y x)))
|
1233
|
-
(rv_vmerge_vvm x y mask ty)))
|
1234
|
-
|
1235
|
-
;;;; Rules for `fmax_pseudo` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1236
|
-
|
1237
|
-
(rule 0 (lower (has_type (ty_scalar_float ty) (fmax_pseudo x y)))
|
1238
|
-
(gen_float_select_pseudo (FloatSelectOP.Max) x y ty))
|
1239
|
-
|
1240
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fmax_pseudo x y)))
|
1241
|
-
(let ((mask VReg (gen_fcmp_mask ty (FloatCC.LessThan) x y)))
|
1242
|
-
(rv_vmerge_vvm x y mask ty)))
|
1243
|
-
|
1244
|
-
;;;;; Rules for `stack_addr`;;;;;;;;;
|
1245
|
-
(rule
|
1246
|
-
(lower (stack_addr ss offset))
|
1247
|
-
(gen_stack_addr ss offset))
|
1248
|
-
|
1249
|
-
;;;;; Rules for `is_null`;;;;;;;;;
|
1250
|
-
|
1251
|
-
;; Null references are represented by the constant value `0`.
|
1252
|
-
(rule (lower (is_null v))
|
1253
|
-
(rv_seqz v))
|
1254
|
-
|
1255
|
-
;;;;; Rules for `is_invalid`;;;;;;;;;
|
1256
|
-
|
1257
|
-
;; Invalid references are represented by the constant value `-1`.
|
1258
|
-
(rule (lower (is_invalid v))
|
1259
|
-
(rv_seqz (rv_addi v (imm12_const 1))))
|
1260
|
-
|
1261
|
-
;;;;; Rules for `select`;;;;;;;;;
|
1262
|
-
(rule
|
1263
|
-
(lower (has_type ty (select c @ (value_type cty) x y)))
|
1264
|
-
(gen_select ty (truthy_to_reg cty (normalize_cmp_value cty c (ExtendOp.Zero))) x y))
|
1265
|
-
|
1266
|
-
(rule 1
|
1267
|
-
(lower (has_type (fits_in_64 ty) (select (icmp cc a b @ (value_type (fits_in_64 in_ty))) x y)))
|
1268
|
-
(let ((a XReg (truthy_to_reg in_ty (normalize_cmp_value in_ty a (intcc_to_extend_op cc))))
|
1269
|
-
(b XReg (truthy_to_reg in_ty (normalize_cmp_value in_ty b (intcc_to_extend_op cc)))))
|
1270
|
-
(gen_select_reg cc a b x y)))
|
1271
|
-
|
1272
|
-
;;;;; Rules for `bitselect`;;;;;;;;;
|
1273
|
-
|
1274
|
-
;; Do a (c & x) | (~c & y) operation.
|
1275
|
-
(rule 0 (lower (has_type (ty_int_ref_scalar_64 ty) (bitselect c x y)))
|
1276
|
-
(let ((tmp_x XReg (rv_and c x))
|
1277
|
-
(c_inverse XReg (rv_not c))
|
1278
|
-
(tmp_y XReg (rv_and c_inverse y)))
|
1279
|
-
(rv_or tmp_x tmp_y)))
|
1280
|
-
|
1281
|
-
;; For vectors, we also do the same operation.
|
1282
|
-
;; We can technically use any type in the bitwise operations, but prefer
|
1283
|
-
;; using the type of the inputs so that we avoid emitting unnecessary
|
1284
|
-
;; `vsetvl` instructions. It's likeley that the vector unit is already
|
1285
|
-
;; configured for that type.
|
1286
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (bitselect c x y)))
|
1287
|
-
(let ((tmp_x VReg (rv_vand_vv c x (unmasked) ty))
|
1288
|
-
(c_inverse VReg (rv_vnot_v c (unmasked) ty))
|
1289
|
-
(tmp_y VReg (rv_vand_vv c_inverse y (unmasked) ty)))
|
1290
|
-
(rv_vor_vv tmp_x tmp_y (unmasked) ty)))
|
1291
|
-
|
1292
|
-
;;;;; Rules for `isplit`;;;;;;;;;
|
1293
|
-
(rule
|
1294
|
-
(lower (isplit x))
|
1295
|
-
(let
|
1296
|
-
((t1 XReg (value_regs_get x 0))
|
1297
|
-
(t2 XReg (value_regs_get x 1)))
|
1298
|
-
(output_pair t1 t2)))
|
1299
|
-
|
1300
|
-
;;;;; Rules for `iconcat`;;;;;;;;;
|
1301
|
-
(rule
|
1302
|
-
(lower (has_type $I128 (iconcat x y)))
|
1303
|
-
(let
|
1304
|
-
((t1 XReg x)
|
1305
|
-
(t2 XReg y))
|
1306
|
-
(value_regs t1 t2)))
|
1307
|
-
|
1308
|
-
|
1309
|
-
;;;;; Rules for `smax`;;;;;;;;;
|
1310
|
-
|
1311
|
-
(rule 0 (lower (has_type (ty_int ty) (smax x y)))
|
1312
|
-
(gen_int_select ty (IntSelectOP.Smax) (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
|
1313
|
-
|
1314
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (smax x y)))
|
1315
|
-
(rv_vmax_vv x y (unmasked) ty))
|
1316
|
-
|
1317
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (smax x (splat y))))
|
1318
|
-
(rv_vmax_vx x y (unmasked) ty))
|
1319
|
-
|
1320
|
-
(rule 3 (lower (has_type (ty_vec_fits_in_register ty) (smax (splat x) y)))
|
1321
|
-
(rv_vmax_vx y x (unmasked) ty))
|
1322
|
-
|
1323
|
-
;;;;; Rules for `smin`;;;;;;;;;
|
1324
|
-
|
1325
|
-
(rule 0 (lower (has_type (ty_int ty) (smin x y)))
|
1326
|
-
(gen_int_select ty (IntSelectOP.Smin) (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
|
1327
|
-
|
1328
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (smin x y)))
|
1329
|
-
(rv_vmin_vv x y (unmasked) ty))
|
1330
|
-
|
1331
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (smin x (splat y))))
|
1332
|
-
(rv_vmin_vx x y (unmasked) ty))
|
1333
|
-
|
1334
|
-
(rule 3 (lower (has_type (ty_vec_fits_in_register ty) (smin (splat x) y)))
|
1335
|
-
(rv_vmin_vx y x (unmasked) ty))
|
1336
|
-
|
1337
|
-
;;;;; Rules for `umax`;;;;;;;;;
|
1338
|
-
|
1339
|
-
(rule 0 (lower (has_type (ty_int ty) (umax x y)))
|
1340
|
-
(gen_int_select ty (IntSelectOP.Umax) (ext_int_if_need $false x ty) (ext_int_if_need $false y ty)))
|
1341
|
-
|
1342
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (umax x y)))
|
1343
|
-
(rv_vmaxu_vv x y (unmasked) ty))
|
1344
|
-
|
1345
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (umax x (splat y))))
|
1346
|
-
(rv_vmaxu_vx x y (unmasked) ty))
|
1347
|
-
|
1348
|
-
(rule 3 (lower (has_type (ty_vec_fits_in_register ty) (umax (splat x) y)))
|
1349
|
-
(rv_vmaxu_vx y x (unmasked) ty))
|
1350
|
-
|
1351
|
-
;;;;; Rules for `umin`;;;;;;;;;
|
1352
|
-
|
1353
|
-
(rule 0 (lower (has_type (ty_int ty) (umin x y)))
|
1354
|
-
(gen_int_select ty (IntSelectOP.Umin) (ext_int_if_need $false x ty) (ext_int_if_need $false y ty)))
|
1355
|
-
|
1356
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (umin x y)))
|
1357
|
-
(rv_vminu_vv x y (unmasked) ty))
|
1358
|
-
|
1359
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (umin x (splat y))))
|
1360
|
-
(rv_vminu_vx x y (unmasked) ty))
|
1361
|
-
|
1362
|
-
(rule 3 (lower (has_type (ty_vec_fits_in_register ty) (umin (splat x) y)))
|
1363
|
-
(rv_vminu_vx y x (unmasked) ty))
|
1364
|
-
|
1365
|
-
|
1366
|
-
;;;;; Rules for `debugtrap`;;;;;;;;;
|
1367
|
-
(rule
|
1368
|
-
(lower (debugtrap))
|
1369
|
-
(side_effect (SideEffectNoResult.Inst (MInst.EBreak))))
|
1370
|
-
|
1371
|
-
;;;;; Rules for `fence`;;;;;;;;;
|
1372
|
-
(rule
|
1373
|
-
(lower (fence))
|
1374
|
-
(side_effect (SideEffectNoResult.Inst (MInst.Fence 15 15))))
|
1375
|
-
|
1376
|
-
;;;;; Rules for `trap`;;;;;;;;;
|
1377
|
-
(rule
|
1378
|
-
(lower (trap code))
|
1379
|
-
(udf code))
|
1380
|
-
|
1381
|
-
;;;;; Rules for `resumable_trap`;;;;;;;;;
|
1382
|
-
(rule
|
1383
|
-
(lower (resumable_trap code))
|
1384
|
-
(udf code))
|
1385
|
-
|
1386
|
-
;;;;; Rules for `uload8`;;;;;;;;;
|
1387
|
-
(rule
|
1388
|
-
(lower (uload8 flags p @ (value_type (ty_addr64 _)) offset))
|
1389
|
-
(gen_load p offset (int_load_op $false 8) flags $I64))
|
1390
|
-
;;;;; Rules for `sload8`;;;;;;;;;
|
1391
|
-
(rule
|
1392
|
-
(lower (sload8 flags p @ (value_type (ty_addr64 _)) offset))
|
1393
|
-
(gen_load p offset (int_load_op $true 8) flags $I64))
|
1394
|
-
;;;;; Rules for `uload16`;;;;;;;;;
|
1395
|
-
(rule
|
1396
|
-
(lower (uload16 flags p @ (value_type (ty_addr64 _)) offset))
|
1397
|
-
(gen_load p offset (int_load_op $false 16) flags $I64))
|
1398
|
-
|
1399
|
-
;;;;; Rules for `iload16`;;;;;;;;;
|
1400
|
-
(rule
|
1401
|
-
(lower (sload16 flags p @ (value_type (ty_addr64 _)) offset))
|
1402
|
-
(gen_load p offset (int_load_op $true 16) flags $I64))
|
1403
|
-
|
1404
|
-
;;;;; Rules for `uload32`;;;;;;;;;
|
1405
|
-
(rule
|
1406
|
-
(lower (uload32 flags p @ (value_type (ty_addr64 _)) offset))
|
1407
|
-
(gen_load p offset (int_load_op $false 32) flags $I64))
|
1408
|
-
|
1409
|
-
;;;;; Rules for `iload16`;;;;;;;;;
|
1410
|
-
(rule
|
1411
|
-
(lower (sload32 flags p @ (value_type (ty_addr64 _)) offset))
|
1412
|
-
(gen_load p offset (int_load_op $true 32) flags $I64))
|
1413
|
-
|
1414
|
-
(rule
|
1415
|
-
(lower (has_type ty (load flags p @ (value_type (ty_addr64 _)) offset)))
|
1416
|
-
(gen_load p offset (load_op ty) flags ty)
|
1417
|
-
)
|
1418
|
-
;;;; for I128
|
1419
|
-
(rule 1
|
1420
|
-
(lower (has_type $I128 (load flags p @ (value_type (ty_addr64 _)) offset)))
|
1421
|
-
(gen_load_128 p offset flags))
|
1422
|
-
|
1423
|
-
(rule 2
|
1424
|
-
(lower (has_type (ty_vec_fits_in_register ty) (load flags p @ (value_type (ty_addr64 _)) offset)))
|
1425
|
-
(let ((eew VecElementWidth (element_width_from_type ty)))
|
1426
|
-
(vec_load eew (VecAMode.UnitStride (gen_amode p offset $I64)) flags (unmasked) ty)))
|
1427
|
-
|
1428
|
-
;;;;; Rules for Load + Extend Combos ;;;;;;;;;
|
1429
|
-
|
1430
|
-
;; These rules cover the special loads that load a 64bit value and do some sort of extension.
|
1431
|
-
;; We don't have any special instructions to do this, so just load the 64 bits as a vector, and
|
1432
|
-
;; do a SEW/2 extension. This only reads half width elements from the source vector register
|
1433
|
-
;; extends it, and writes the back the full register.
|
1434
|
-
|
1435
|
-
(decl gen_load64_extend (Type ExtendOp MemFlags XReg Offset32) VReg)
|
1436
|
-
|
1437
|
-
(rule (gen_load64_extend ty (ExtendOp.Signed) flags addr offset)
|
1438
|
-
(let ((eew VecElementWidth (element_width_from_type $I64))
|
1439
|
-
(load_state VState (vstate_from_type $I64))
|
1440
|
-
(loaded VReg (vec_load eew (VecAMode.UnitStride (gen_amode addr offset $I64)) flags (unmasked) load_state)))
|
1441
|
-
(rv_vsext_vf2 loaded (unmasked) ty)))
|
1442
|
-
|
1443
|
-
(rule (gen_load64_extend ty (ExtendOp.Zero) flags addr offset)
|
1444
|
-
(let ((eew VecElementWidth (element_width_from_type $I64))
|
1445
|
-
(load_state VState (vstate_from_type $I64))
|
1446
|
-
(loaded VReg (vec_load eew (VecAMode.UnitStride (gen_amode addr offset $I64)) flags (unmasked) load_state)))
|
1447
|
-
(rv_vzext_vf2 loaded (unmasked) ty)))
|
1448
|
-
|
1449
|
-
;;;;; Rules for `uload8x8`;;;;;;;;;;
|
1450
|
-
(rule (lower (has_type (ty_vec_fits_in_register ty @ $I16X8) (uload8x8 flags addr @ (value_type (ty_addr64 _)) offset)))
|
1451
|
-
(gen_load64_extend ty (ExtendOp.Zero) flags addr offset))
|
1452
|
-
|
1453
|
-
;;;;; Rules for `uload16x4`;;;;;;;;;
|
1454
|
-
(rule (lower (has_type (ty_vec_fits_in_register ty @ $I32X4) (uload16x4 flags addr @ (value_type (ty_addr64 _)) offset)))
|
1455
|
-
(gen_load64_extend ty (ExtendOp.Zero) flags addr offset))
|
1456
|
-
|
1457
|
-
;;;;; Rules for `uload32x2`;;;;;;;;;
|
1458
|
-
(rule (lower (has_type (ty_vec_fits_in_register ty @ $I64X2) (uload32x2 flags addr @ (value_type (ty_addr64 _)) offset)))
|
1459
|
-
(gen_load64_extend ty (ExtendOp.Zero) flags addr offset))
|
1460
|
-
|
1461
|
-
;;;;; Rules for `sload8x8`;;;;;;;;;;
|
1462
|
-
(rule (lower (has_type (ty_vec_fits_in_register ty @ $I16X8) (sload8x8 flags addr @ (value_type (ty_addr64 _)) offset)))
|
1463
|
-
(gen_load64_extend ty (ExtendOp.Signed) flags addr offset))
|
1464
|
-
|
1465
|
-
;;;;; Rules for `sload16x4`;;;;;;;;;
|
1466
|
-
(rule (lower (has_type (ty_vec_fits_in_register ty @ $I32X4) (sload16x4 flags addr @ (value_type (ty_addr64 _)) offset)))
|
1467
|
-
(gen_load64_extend ty (ExtendOp.Signed) flags addr offset))
|
1468
|
-
|
1469
|
-
;;;;; Rules for `sload32x2`;;;;;;;;;
|
1470
|
-
(rule (lower (has_type (ty_vec_fits_in_register ty @ $I64X2) (sload32x2 flags addr @ (value_type (ty_addr64 _)) offset)))
|
1471
|
-
(gen_load64_extend ty (ExtendOp.Signed) flags addr offset))
|
1472
|
-
|
1473
|
-
;;;;; Rules for `istore8`;;;;;;;;;
|
1474
|
-
(rule
|
1475
|
-
(lower (istore8 flags x p @ (value_type (ty_addr64 _)) offset))
|
1476
|
-
(gen_store p offset (StoreOP.Sb) flags x))
|
1477
|
-
;;;;; Rules for `istore16`;;;;;;;;;
|
1478
|
-
(rule
|
1479
|
-
(lower (istore16 flags x p @ (value_type (ty_addr64 _)) offset))
|
1480
|
-
(gen_store p offset (StoreOP.Sh) flags x))
|
1481
|
-
|
1482
|
-
;;;;; Rules for `istore32`;;;;;;;;;
|
1483
|
-
(rule
|
1484
|
-
(lower (istore32 flags x p @ (value_type (ty_addr64 _)) offset))
|
1485
|
-
(gen_store p offset (StoreOP.Sw) flags x))
|
1486
|
-
|
1487
|
-
;;;;; Rules for `store`;;;;;;;;;
|
1488
|
-
(rule
|
1489
|
-
(lower (store flags x @ (value_type ty) p @ (value_type (ty_addr64 _)) offset))
|
1490
|
-
(gen_store p offset (store_op ty) flags x))
|
1491
|
-
|
1492
|
-
;;; special for I128
|
1493
|
-
(rule 1
|
1494
|
-
(lower (store flags x @ (value_type $I128 ) p @ (value_type (ty_addr64 _)) offset))
|
1495
|
-
(gen_store_128 p offset flags x))
|
1496
|
-
|
1497
|
-
(rule 2
|
1498
|
-
(lower (store flags x @ (value_type (ty_vec_fits_in_register ty)) p @ (value_type (ty_addr64 _)) offset))
|
1499
|
-
(let ((eew VecElementWidth (element_width_from_type ty)))
|
1500
|
-
(vec_store eew (VecAMode.UnitStride (gen_amode p offset $I64)) x flags (unmasked) ty)))
|
1501
|
-
|
1502
|
-
(decl gen_icmp (IntCC ValueRegs ValueRegs Type) XReg)
|
1503
|
-
(rule
|
1504
|
-
(gen_icmp cc x y ty)
|
1505
|
-
(let
|
1506
|
-
((result WritableXReg (temp_writable_xreg))
|
1507
|
-
(_ Unit (emit (MInst.Icmp cc result x y ty))))
|
1508
|
-
result))
|
1509
|
-
|
1510
|
-
;;;;; Rules for `icmp`;;;;;;;;;
|
1511
|
-
(rule 0 (lower (icmp cc x @ (value_type (ty_int ty)) y))
|
1512
|
-
(lower_icmp cc x y ty))
|
1513
|
-
|
1514
|
-
(rule 1 (lower (icmp cc x @ (value_type (ty_vec_fits_in_register ty)) y))
|
1515
|
-
(gen_expand_mask ty (gen_icmp_mask ty cc x y)))
|
1516
|
-
|
1517
|
-
|
1518
|
-
;;;;; Rules for `fcmp`;;;;;;;;;
|
1519
|
-
(rule 0 (lower (fcmp cc x @ (value_type (ty_scalar_float ty)) y))
|
1520
|
-
(cmp_value (emit_fcmp cc ty x y)))
|
1521
|
-
|
1522
|
-
(rule 1 (lower (fcmp cc x @ (value_type (ty_vec_fits_in_register ty)) y))
|
1523
|
-
(gen_expand_mask ty (gen_fcmp_mask ty cc x y)))
|
1524
|
-
|
1525
|
-
;;;;; Rules for `func_addr`;;;;;;;;;
|
1526
|
-
(rule
|
1527
|
-
(lower (func_addr (func_ref_data _ name _)))
|
1528
|
-
(load_ext_name name 0))
|
1529
|
-
|
1530
|
-
;;;;; Rules for `fcvt_to_uint`;;;;;;;;;
|
1531
|
-
(rule
|
1532
|
-
(lower (has_type to (fcvt_to_uint v @ (value_type from))))
|
1533
|
-
(gen_fcvt_int $false v $false from to))
|
1534
|
-
|
1535
|
-
;;;;; Rules for `fcvt_to_sint`;;;;;;;;;
|
1536
|
-
(rule
|
1537
|
-
(lower (has_type to (fcvt_to_sint v @ (value_type from))))
|
1538
|
-
(gen_fcvt_int $false v $true from to))
|
1539
|
-
|
1540
|
-
;;;;; Rules for `fcvt_to_sint_sat`;;;;;;;;;
|
1541
|
-
(rule
|
1542
|
-
(lower (has_type to (fcvt_to_sint_sat v @ (value_type from))))
|
1543
|
-
(gen_fcvt_int $true v $true from to))
|
1544
|
-
|
1545
|
-
;;;;; Rules for `fcvt_to_uint_sat`;;;;;;;;;
|
1546
|
-
(rule
|
1547
|
-
(lower (has_type to (fcvt_to_uint_sat v @ (value_type from))))
|
1548
|
-
(gen_fcvt_int $true v $false from to))
|
1549
|
-
|
1550
|
-
;;;;; Rules for `fcvt_from_sint`;;;;;;;;;
|
1551
|
-
(rule
|
1552
|
-
(lower (has_type to (fcvt_from_sint v @ (value_type from_ty))))
|
1553
|
-
(let ((float_op FpuOPRR (int_convert_2_float_op from_ty $true to))
|
1554
|
-
(value XReg (normalize_fcvt_from_int v from_ty (ExtendOp.Signed))))
|
1555
|
-
(fpu_rr float_op to value)))
|
1556
|
-
|
1557
|
-
;;;;; Rules for `fcvt_from_uint`;;;;;;;;;
|
1558
|
-
(rule
|
1559
|
-
(lower (has_type to (fcvt_from_uint v @ (value_type from_ty))))
|
1560
|
-
(let ((float_op FpuOPRR (int_convert_2_float_op from_ty $false to))
|
1561
|
-
(value XReg (normalize_fcvt_from_int v from_ty (ExtendOp.Zero))))
|
1562
|
-
(fpu_rr float_op to value)))
|
1563
|
-
|
1564
|
-
;;;;; Rules for `symbol_value`;;;;;;;;;
|
1565
|
-
(rule
|
1566
|
-
(lower (symbol_value (symbol_value_data name _ offset)))
|
1567
|
-
(load_ext_name name offset)
|
1568
|
-
)
|
1569
|
-
;;;;; Rules for `bitcast`;;;;;;;;;
|
1570
|
-
(rule
|
1571
|
-
(lower (has_type out_ty (bitcast _ v @ (value_type in_ty))))
|
1572
|
-
(gen_bitcast v in_ty out_ty))
|
1573
|
-
|
1574
|
-
;;;;; Rules for `ceil`;;;;;;;;;
|
1575
|
-
(rule
|
1576
|
-
(lower (has_type ty (ceil x)))
|
1577
|
-
(gen_float_round (FloatRoundOP.Ceil) x ty)
|
1578
|
-
)
|
1579
|
-
|
1580
|
-
;;;;; Rules for `floor`;;;;;;;;;
|
1581
|
-
(rule
|
1582
|
-
(lower (has_type ty (floor x)))
|
1583
|
-
(gen_float_round (FloatRoundOP.Floor) x ty))
|
1584
|
-
;;;;; Rules for `trunc`;;;;;;;;;
|
1585
|
-
(rule
|
1586
|
-
(lower (has_type ty (trunc x)))
|
1587
|
-
(gen_float_round (FloatRoundOP.Trunc) x ty))
|
1588
|
-
|
1589
|
-
;;;;; Rules for `nearest`;;;;;;;;;
|
1590
|
-
(rule
|
1591
|
-
(lower (has_type ty (nearest x)))
|
1592
|
-
(gen_float_round (FloatRoundOP.Nearest) x ty))
|
1593
|
-
|
1594
|
-
|
1595
|
-
;;;;; Rules for `select_spectre_guard`;;;;;;;;;
|
1596
|
-
|
1597
|
-
;; SelectSpectreGuard is equivalent to Select, but we should not use a branch based
|
1598
|
-
;; lowering for it. Instead we use a conditional move based lowering.
|
1599
|
-
;;
|
1600
|
-
;; We don't have cmov's in RISC-V either, but we can emulate those using bitwise
|
1601
|
-
;; operations, which is what we do below.
|
1602
|
-
(rule (lower (has_type ty (select_spectre_guard cmp @ (value_type cmp_ty) x @ (value_type arg_ty) y)))
|
1603
|
-
(let (;; Build a mask that is 0 or -1 depending on the input comparision value.
|
1604
|
-
;; `lower_bmask` handles normalizing the input.
|
1605
|
-
(mask ValueRegs (lower_bmask arg_ty cmp_ty cmp))
|
1606
|
-
;; Using the mask above we can select either `x` or `y` by
|
1607
|
-
;; performing a bitwise `and` on both sides and then merging them
|
1608
|
-
;; together. We know that only the bits of one of the sides will be selected.
|
1609
|
-
;; TODO: We can use `andn` here if we have `Zbb`
|
1610
|
-
(lhs ValueRegs (gen_and arg_ty x mask))
|
1611
|
-
(rhs ValueRegs (gen_and arg_ty y (gen_bnot arg_ty mask))))
|
1612
|
-
(gen_or arg_ty lhs rhs)))
|
1613
|
-
|
1614
|
-
;;;;; Rules for `bmask`;;;;;;;;;
|
1615
|
-
(rule
|
1616
|
-
(lower (has_type oty (bmask x @ (value_type ity))))
|
1617
|
-
(lower_bmask oty ity x))
|
1618
|
-
|
1619
|
-
;; N.B.: the Ret itself is generated by the ABI.
|
1620
|
-
(rule (lower (return args))
|
1621
|
-
(lower_return args))
|
1622
|
-
|
1623
|
-
;;; Rules for `get_{frame,stack}_pointer` and `get_return_address` ;;;;;;;;;;;;;
|
1624
|
-
|
1625
|
-
(rule (lower (get_frame_pointer))
|
1626
|
-
(gen_mov_from_preg (fp_reg)))
|
1627
|
-
|
1628
|
-
(rule (lower (get_stack_pointer))
|
1629
|
-
(gen_mov_from_preg (sp_reg)))
|
1630
|
-
|
1631
|
-
(rule (lower (get_return_address))
|
1632
|
-
(load_ra))
|
1633
|
-
|
1634
|
-
;;; Rules for `iabs` ;;;;;;;;;;;;;
|
1635
|
-
|
1636
|
-
;; I64 and lower
|
1637
|
-
;; Generate the following code:
|
1638
|
-
;; sext.{b,h,w} a0, a0
|
1639
|
-
;; neg a1, a0
|
1640
|
-
;; max a0, a0, a1
|
1641
|
-
(rule 0 (lower (has_type (ty_int_ref_scalar_64 ty) (iabs x)))
|
1642
|
-
(let ((extended XReg (sext x ty $I64))
|
1643
|
-
(negated XReg (rv_neg extended)))
|
1644
|
-
(max $I64 extended negated)))
|
1645
|
-
|
1646
|
-
;; For vectors we generate the same code, but with vector instructions
|
1647
|
-
;; we can skip the sign extension, since the vector unit will only process
|
1648
|
-
;; Element Sized chunks.
|
1649
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (iabs x)))
|
1650
|
-
(let ((negated VReg (rv_vneg_v x (unmasked) ty)))
|
1651
|
-
(rv_vmax_vv x negated (unmasked) ty)))
|
1652
|
-
|
1653
|
-
;;;; Rules for calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1654
|
-
|
1655
|
-
(rule (lower (call (func_ref_data sig_ref extname dist) inputs))
|
1656
|
-
(gen_call sig_ref extname dist inputs))
|
1657
|
-
|
1658
|
-
(rule (lower (call_indirect sig_ref val inputs))
|
1659
|
-
(gen_call_indirect sig_ref val inputs))
|
1660
|
-
|
1661
|
-
;;;; Rules for `return_call` and `return_call_indirect` ;;;;;;;;;;;;;;;;;;;;;;;;
|
1662
|
-
|
1663
|
-
(rule (lower (return_call (func_ref_data sig_ref extname dist) args))
|
1664
|
-
(gen_return_call sig_ref extname dist args))
|
1665
|
-
|
1666
|
-
(rule (lower (return_call_indirect sig_ref callee args))
|
1667
|
-
(gen_return_call_indirect sig_ref callee args))
|
1668
|
-
|
1669
|
-
|
1670
|
-
;;;; Rules for `extractlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1671
|
-
|
1672
|
-
(rule (lower (extractlane x @ (value_type ty) (u8_from_uimm8 idx)))
|
1673
|
-
(gen_extractlane ty x idx))
|
1674
|
-
|
1675
|
-
;;;; Rules for `insertlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1676
|
-
|
1677
|
-
;; We can insert a lane by using a masked splat from an X register.
|
1678
|
-
;; Build a mask that is only enabled in the lane we want to insert.
|
1679
|
-
;; Then use a masked splat (vmerge) to insert the value.
|
1680
|
-
(rule 0 (lower (insertlane vec @ (value_type (ty_vec_fits_in_register ty))
|
1681
|
-
val @ (value_type (ty_int _))
|
1682
|
-
(u8_from_uimm8 lane)))
|
1683
|
-
(let ((mask VReg (gen_vec_mask (u64_shl 1 lane))))
|
1684
|
-
(rv_vmerge_vxm vec val mask ty)))
|
1685
|
-
|
1686
|
-
;; Similar to above, but using the float variants of the instructions.
|
1687
|
-
(rule 1 (lower (insertlane vec @ (value_type (ty_vec_fits_in_register ty))
|
1688
|
-
val @ (value_type (ty_scalar_float _))
|
1689
|
-
(u8_from_uimm8 lane)))
|
1690
|
-
(let ((mask VReg (gen_vec_mask (u64_shl 1 lane))))
|
1691
|
-
(rv_vfmerge_vfm vec val mask ty)))
|
1692
|
-
|
1693
|
-
;; If we are inserting from an Imm5 const we can use the immediate
|
1694
|
-
;; variant of vmerge.
|
1695
|
-
(rule 2 (lower (insertlane vec @ (value_type (ty_vec_fits_in_register ty))
|
1696
|
-
(iconst (u64_from_imm64 (imm5_from_u64 imm)))
|
1697
|
-
(u8_from_uimm8 lane)))
|
1698
|
-
(let ((mask VReg (gen_vec_mask (u64_shl 1 lane))))
|
1699
|
-
(rv_vmerge_vim vec imm mask ty)))
|
1700
|
-
|
1701
|
-
;;;; Rules for `splat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1702
|
-
|
1703
|
-
(rule 0 (lower (has_type ty (splat n @ (value_type (ty_scalar_float _)))))
|
1704
|
-
(rv_vfmv_vf n ty))
|
1705
|
-
|
1706
|
-
(rule 1 (lower (has_type ty (splat n @ (value_type (ty_int_ref_scalar_64 _)))))
|
1707
|
-
(rv_vmv_vx n ty))
|
1708
|
-
|
1709
|
-
(rule 2 (lower (has_type ty (splat (iconst (u64_from_imm64 (imm5_from_u64 imm))))))
|
1710
|
-
(rv_vmv_vi imm ty))
|
1711
|
-
|
1712
|
-
;; TODO: We can splat out more patterns by using for example a vmv.v.i i8x16 for
|
1713
|
-
;; a i64x2 const with a compatible bit pattern. The AArch64 Backend does something
|
1714
|
-
;; similar in its splat rules.
|
1715
|
-
;; TODO: Look through bitcasts when splatting out registers. We can use
|
1716
|
-
;; `vmv.v.x` in a `(splat.f32x4 (bitcast.f32 val))`. And vice versa for integers.
|
1717
|
-
|
1718
|
-
;;;; Rules for `uadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1719
|
-
|
1720
|
-
(rule 0 (lower (has_type (ty_vec_fits_in_register ty) (uadd_sat x y)))
|
1721
|
-
(rv_vsaddu_vv x y (unmasked) ty))
|
1722
|
-
|
1723
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (uadd_sat x (splat y))))
|
1724
|
-
(rv_vsaddu_vx x y (unmasked) ty))
|
1725
|
-
|
1726
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (uadd_sat (splat x) y)))
|
1727
|
-
(rv_vsaddu_vx y x (unmasked) ty))
|
1728
|
-
|
1729
|
-
(rule 3 (lower (has_type (ty_vec_fits_in_register ty) (uadd_sat x (replicated_imm5 y))))
|
1730
|
-
(rv_vsaddu_vi x y (unmasked) ty))
|
1731
|
-
|
1732
|
-
(rule 4 (lower (has_type (ty_vec_fits_in_register ty) (uadd_sat (replicated_imm5 x) y)))
|
1733
|
-
(rv_vsaddu_vi y x (unmasked) ty))
|
1734
|
-
|
1735
|
-
;;;; Rules for `sadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1736
|
-
|
1737
|
-
(rule 0 (lower (has_type (ty_vec_fits_in_register ty) (sadd_sat x y)))
|
1738
|
-
(rv_vsadd_vv x y (unmasked) ty))
|
1739
|
-
|
1740
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (sadd_sat x (splat y))))
|
1741
|
-
(rv_vsadd_vx x y (unmasked) ty))
|
1742
|
-
|
1743
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (sadd_sat (splat x) y)))
|
1744
|
-
(rv_vsadd_vx y x (unmasked) ty))
|
1745
|
-
|
1746
|
-
(rule 3 (lower (has_type (ty_vec_fits_in_register ty) (sadd_sat x (replicated_imm5 y))))
|
1747
|
-
(rv_vsadd_vi x y (unmasked) ty))
|
1748
|
-
|
1749
|
-
(rule 4 (lower (has_type (ty_vec_fits_in_register ty) (sadd_sat (replicated_imm5 x) y)))
|
1750
|
-
(rv_vsadd_vi y x (unmasked) ty))
|
1751
|
-
|
1752
|
-
;;;; Rules for `usub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1753
|
-
|
1754
|
-
(rule 0 (lower (has_type (ty_vec_fits_in_register ty) (usub_sat x y)))
|
1755
|
-
(rv_vssubu_vv x y (unmasked) ty))
|
1756
|
-
|
1757
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (usub_sat x (splat y))))
|
1758
|
-
(rv_vssubu_vx x y (unmasked) ty))
|
1759
|
-
|
1760
|
-
;;;; Rules for `ssub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1761
|
-
|
1762
|
-
(rule 0 (lower (has_type (ty_vec_fits_in_register ty) (ssub_sat x y)))
|
1763
|
-
(rv_vssub_vv x y (unmasked) ty))
|
1764
|
-
|
1765
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (ssub_sat x (splat y))))
|
1766
|
-
(rv_vssub_vx x y (unmasked) ty))
|
1767
|
-
|
1768
|
-
;;;; Rules for `vall_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1769
|
-
|
1770
|
-
;; Here we do a Vector Reduce operation. Get the unsigned minimum value of any
|
1771
|
-
;; lane in the vector. The fixed input to the reduce operation is a 1.
|
1772
|
-
;; This way, if any lane is 0, the result will be 0. Otherwise, the result will
|
1773
|
-
;; be a 1.
|
1774
|
-
;; The reduce operation leaves the result in the lowest lane, we then move it
|
1775
|
-
;; into the destination X register.
|
1776
|
-
(rule (lower (vall_true x @ (value_type (ty_vec_fits_in_register ty))))
|
1777
|
-
(if-let one (imm5_from_i8 1))
|
1778
|
-
;; We don't need to broadcast the immediate into all lanes, only into lane 0.
|
1779
|
-
;; I did it this way since it uses one less instruction than with a vmv.s.x.
|
1780
|
-
(let ((fixed VReg (rv_vmv_vi one ty))
|
1781
|
-
(min VReg (rv_vredminu_vs x fixed (unmasked) ty)))
|
1782
|
-
(rv_vmv_xs min ty)))
|
1783
|
-
|
1784
|
-
|
1785
|
-
;;;; Rules for `vany_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1786
|
-
|
1787
|
-
;; Here we do a Vector Reduce operation. Get the unsigned maximum value of the
|
1788
|
-
;; input vector register. Move the max to an X register, and do a `snez` on it
|
1789
|
-
;; to ensure its either 1 or 0.
|
1790
|
-
(rule (lower (vany_true x @ (value_type (ty_vec_fits_in_register ty))))
|
1791
|
-
(let ((max VReg (rv_vredmaxu_vs x x (unmasked) ty))
|
1792
|
-
(x_max XReg (rv_vmv_xs max ty)))
|
1793
|
-
(rv_snez x_max)))
|
1794
|
-
|
1795
|
-
|
1796
|
-
;;;; Rules for `vhigh_bits` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1797
|
-
|
1798
|
-
;; To check if the MSB of a lane is set, we do a `vmslt` with zero, this sets
|
1799
|
-
;; the mask bit to 1 if the value is negative (MSB 1) and 0 if not. We can then
|
1800
|
-
;; just move that mask to an X Register.
|
1801
|
-
;;
|
1802
|
-
;; We must ensure that the move to the X register has a SEW with enough bits
|
1803
|
-
;; to hold the full mask. Additionally, in some cases (e.g. i64x2) we are going
|
1804
|
-
;; to read some tail bits. These are undefined, so we need to further mask them
|
1805
|
-
;; off.
|
1806
|
-
(rule (lower (vhigh_bits x @ (value_type (ty_vec_fits_in_register ty))))
|
1807
|
-
(let ((mask VReg (rv_vmslt_vx x (zero_reg) (unmasked) ty))
|
1808
|
-
;; Here we only need I64X1, but emit an AVL of 2 since it
|
1809
|
-
;; saves one vector state change in the case of I64X2.
|
1810
|
-
;;
|
1811
|
-
;; TODO: For types that have more lanes than element bits, we can
|
1812
|
-
;; use the original type as a VState and avoid a state change.
|
1813
|
-
(x_mask XReg (rv_vmv_xs mask (vstate_from_type $I64X2))))
|
1814
|
-
(gen_andi x_mask (ty_lane_mask ty))))
|
1815
|
-
|
1816
|
-
;;;; Rules for `swizzle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1817
|
-
|
1818
|
-
(rule 0 (lower (has_type (ty_vec_fits_in_register ty) (swizzle x y)))
|
1819
|
-
(rv_vrgather_vv x y (unmasked) ty))
|
1820
|
-
|
1821
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (swizzle x (splat y))))
|
1822
|
-
(rv_vrgather_vx x y (unmasked) ty))
|
1823
|
-
|
1824
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (swizzle x (replicated_uimm5 y))))
|
1825
|
-
(rv_vrgather_vi x y (unmasked) ty))
|
1826
|
-
|
1827
|
-
;;;; Rules for `shuffle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1828
|
-
|
1829
|
-
;; Use a vrgather to load all 0-15 lanes from x. And then modify the mask to load all
|
1830
|
-
;; 16-31 lanes from y. Finally, use a vor to combine the two vectors.
|
1831
|
-
;;
|
1832
|
-
;; vrgather will insert a 0 for lanes that are out of bounds, so we can let it load
|
1833
|
-
;; negative and out of bounds indexes.
|
1834
|
-
(rule (lower (has_type (ty_vec_fits_in_register ty @ $I8X16) (shuffle x y (vconst_from_immediate mask))))
|
1835
|
-
(if-let neg16 (imm5_from_i8 -16))
|
1836
|
-
(let ((x_mask VReg (gen_constant ty mask))
|
1837
|
-
(x_lanes VReg (rv_vrgather_vv x x_mask (unmasked) ty))
|
1838
|
-
(y_mask VReg (rv_vadd_vi x_mask neg16 (unmasked) ty))
|
1839
|
-
(y_lanes VReg (rv_vrgather_vv y y_mask (unmasked) ty)))
|
1840
|
-
(rv_vor_vv x_lanes y_lanes (unmasked) ty)))
|
1841
|
-
|
1842
|
-
;;;; Rules for `swiden_high` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1843
|
-
|
1844
|
-
;; Slide down half the vector, and do a signed extension.
|
1845
|
-
(rule 0 (lower (has_type (ty_vec_fits_in_register out_ty) (swiden_high x @ (value_type in_ty))))
|
1846
|
-
(rv_vsext_vf2 (gen_slidedown_half in_ty x) (unmasked) out_ty))
|
1847
|
-
|
1848
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register out_ty) (swiden_high (swiden_high x @ (value_type in_ty)))))
|
1849
|
-
(if-let (uimm5_from_u64 amt) (u64_sub (ty_lane_count in_ty) (ty_lane_count out_ty)))
|
1850
|
-
(rv_vsext_vf4 (rv_vslidedown_vi x amt (unmasked) in_ty) (unmasked) out_ty))
|
1851
|
-
|
1852
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register out_ty) (swiden_high (swiden_high (swiden_high x @ (value_type in_ty))))))
|
1853
|
-
(if-let (uimm5_from_u64 amt) (u64_sub (ty_lane_count in_ty) (ty_lane_count out_ty)))
|
1854
|
-
(rv_vsext_vf8 (rv_vslidedown_vi x amt (unmasked) in_ty) (unmasked) out_ty))
|
1855
|
-
|
1856
|
-
;;;; Rules for `uwiden_high` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1857
|
-
|
1858
|
-
;; Slide down half the vector, and do a zero extension.
|
1859
|
-
(rule 0 (lower (has_type (ty_vec_fits_in_register out_ty) (uwiden_high x @ (value_type in_ty))))
|
1860
|
-
(rv_vzext_vf2 (gen_slidedown_half in_ty x) (unmasked) out_ty))
|
1861
|
-
|
1862
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register out_ty) (uwiden_high (uwiden_high x @ (value_type in_ty)))))
|
1863
|
-
(if-let (uimm5_from_u64 amt) (u64_sub (ty_lane_count in_ty) (ty_lane_count out_ty)))
|
1864
|
-
(rv_vzext_vf4 (rv_vslidedown_vi x amt (unmasked) in_ty) (unmasked) out_ty))
|
1865
|
-
|
1866
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register out_ty) (uwiden_high (uwiden_high (uwiden_high x @ (value_type in_ty))))))
|
1867
|
-
(if-let (uimm5_from_u64 amt) (u64_sub (ty_lane_count in_ty) (ty_lane_count out_ty)))
|
1868
|
-
(rv_vzext_vf8 (rv_vslidedown_vi x amt (unmasked) in_ty) (unmasked) out_ty))
|
1869
|
-
|
1870
|
-
;;;; Rules for `swiden_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1871
|
-
|
1872
|
-
(rule 0 (lower (has_type (ty_vec_fits_in_register out_ty) (swiden_low x)))
|
1873
|
-
(rv_vsext_vf2 x (unmasked) out_ty))
|
1874
|
-
|
1875
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register out_ty) (swiden_low (swiden_low x))))
|
1876
|
-
(rv_vsext_vf4 x (unmasked) out_ty))
|
1877
|
-
|
1878
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register out_ty) (swiden_low (swiden_low (swiden_low x)))))
|
1879
|
-
(rv_vsext_vf8 x (unmasked) out_ty))
|
1880
|
-
|
1881
|
-
;;;; Rules for `uwiden_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1882
|
-
|
1883
|
-
(rule 0 (lower (has_type (ty_vec_fits_in_register out_ty) (uwiden_low x)))
|
1884
|
-
(rv_vzext_vf2 x (unmasked) out_ty))
|
1885
|
-
|
1886
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register out_ty) (uwiden_low (uwiden_low x))))
|
1887
|
-
(rv_vzext_vf4 x (unmasked) out_ty))
|
1888
|
-
|
1889
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register out_ty) (uwiden_low (uwiden_low (uwiden_low x)))))
|
1890
|
-
(rv_vzext_vf8 x (unmasked) out_ty))
|
1891
|
-
|
1892
|
-
;;;; Rules for `iadd_pairwise` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1893
|
-
|
1894
|
-
;; We don't have a dedicated instruction for this, rearrange the register elements
|
1895
|
-
;; and use a vadd.
|
1896
|
-
;;
|
1897
|
-
;; We do this by building two masks, one for the even elements and one for the odd
|
1898
|
-
;; elements. Using vcompress we can extract the elements and group them together.
|
1899
|
-
;;
|
1900
|
-
;; This is likely not the optimal way of doing this. LLVM does this using a bunch
|
1901
|
-
;; of vrgathers (See: https://godbolt.org/z/jq8Wj8WG4), that doesen't seem to be
|
1902
|
-
;; too much better than this.
|
1903
|
-
;;
|
1904
|
-
;; However V8 does something better. They use 2 vcompresses using LMUL2, that means
|
1905
|
-
;; that they can do the whole thing in 3 instructions (2 vcompress + vadd). We don't
|
1906
|
-
;; support LMUL > 1, so we can't do that.
|
1907
|
-
(rule (lower (has_type (ty_vec_fits_in_register ty) (iadd_pairwise x y)))
|
1908
|
-
(if-let half_size (u64_to_uimm5 (u64_udiv (ty_lane_count ty) 2)))
|
1909
|
-
(let ((odd_mask VReg (gen_vec_mask 0x5555555555555555))
|
1910
|
-
(lhs_lo VReg (rv_vcompress_vm x odd_mask ty))
|
1911
|
-
(lhs_hi VReg (rv_vcompress_vm y odd_mask ty))
|
1912
|
-
(lhs VReg (rv_vslideup_vvi lhs_lo lhs_hi half_size (unmasked) ty))
|
1913
|
-
|
1914
|
-
(even_mask VReg (gen_vec_mask 0xAAAAAAAAAAAAAAAA))
|
1915
|
-
(rhs_lo VReg (rv_vcompress_vm x even_mask ty))
|
1916
|
-
(rhs_hi VReg (rv_vcompress_vm y even_mask ty))
|
1917
|
-
(rhs VReg (rv_vslideup_vvi rhs_lo rhs_hi half_size (unmasked) ty)))
|
1918
|
-
(rv_vadd_vv lhs rhs (unmasked) ty)))
|
1919
|
-
|
1920
|
-
;;;; Rules for `avg_round` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1921
|
-
|
1922
|
-
;; `avg_round` computes the unsigned average with rounding: a := (x + y + 1) // 2
|
1923
|
-
;;
|
1924
|
-
;; See Section "2–5 Average of Two Integers" of the Hacker's Delight book
|
1925
|
-
;;
|
1926
|
-
;; The floor average of two integers without overflow can be computed as:
|
1927
|
-
;; t = (x & y) + ((x ^ y) >> 1)
|
1928
|
-
;;
|
1929
|
-
;; The right shift should be a logical shift if the integers are unsigned.
|
1930
|
-
;;
|
1931
|
-
;; We are however interested in the ceiling average (x + y + 1). For that
|
1932
|
-
;; we use a special rounding mode in the right shift instruction.
|
1933
|
-
;;
|
1934
|
-
;; For the right shift instruction we use `vssrl` which is a Scaling Shift
|
1935
|
-
;; Right Logical instruction using the `vxrm` fixed-point rouding mode. The
|
1936
|
-
;; default rounding mode is `rnu` (round-to-nearest-up (add +0.5 LSB)).
|
1937
|
-
;; Which is coincidentally the rounding mode we want for `avg_round`.
|
1938
|
-
(rule (lower (has_type (ty_vec_fits_in_register ty) (avg_round x y)))
|
1939
|
-
(if-let one (u64_to_uimm5 1))
|
1940
|
-
(let ((lhs VReg (rv_vand_vv x y (unmasked) ty))
|
1941
|
-
(xor VReg (rv_vxor_vv x y (unmasked) ty))
|
1942
|
-
(rhs VReg (rv_vssrl_vi xor one (unmasked) ty)))
|
1943
|
-
(rv_vadd_vv lhs rhs (unmasked) ty)))
|
1944
|
-
|
1945
|
-
;;;; Rules for `scalar_to_vector` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1946
|
-
|
1947
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (scalar_to_vector x)))
|
1948
|
-
(if (ty_vector_not_float ty))
|
1949
|
-
(let ((zero VReg (rv_vmv_vx (zero_reg) ty))
|
1950
|
-
(mask VReg (gen_vec_mask 1)))
|
1951
|
-
(rv_vmerge_vxm zero x mask ty)))
|
1952
|
-
|
1953
|
-
(rule 0 (lower (has_type (ty_vec_fits_in_register ty) (scalar_to_vector x)))
|
1954
|
-
(if (ty_vector_float ty))
|
1955
|
-
(let ((zero VReg (rv_vmv_vx (zero_reg) ty))
|
1956
|
-
(elem VReg (rv_vfmv_sf x ty))
|
1957
|
-
(mask VReg (gen_vec_mask 1)))
|
1958
|
-
(rv_vmerge_vvm zero elem mask ty)))
|
1959
|
-
|
1960
|
-
;;;; Rules for `sqmul_round_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1961
|
-
|
1962
|
-
(rule 0 (lower (has_type (ty_vec_fits_in_register ty) (sqmul_round_sat x y)))
|
1963
|
-
(rv_vsmul_vv x y (unmasked) ty))
|
1964
|
-
|
1965
|
-
(rule 1 (lower (has_type (ty_vec_fits_in_register ty) (sqmul_round_sat x (splat y))))
|
1966
|
-
(rv_vsmul_vx x y (unmasked) ty))
|
1967
|
-
|
1968
|
-
(rule 2 (lower (has_type (ty_vec_fits_in_register ty) (sqmul_round_sat (splat x) y)))
|
1969
|
-
(rv_vsmul_vx y x (unmasked) ty))
|
1970
|
-
|
1971
|
-
;;;; Rules for `snarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1972
|
-
|
1973
|
-
(rule (lower (has_type (ty_vec_fits_in_register out_ty) (snarrow x @ (value_type in_ty) y)))
|
1974
|
-
(if-let lane_diff (u64_to_uimm5 (u64_udiv (ty_lane_count out_ty) 2)))
|
1975
|
-
(if-let zero (u64_to_uimm5 0))
|
1976
|
-
(let ((x_clip VReg (rv_vnclip_wi x zero (unmasked) (vstate_mf2 (ty_half_lanes out_ty))))
|
1977
|
-
(y_clip VReg (rv_vnclip_wi y zero (unmasked) (vstate_mf2 (ty_half_lanes out_ty)))))
|
1978
|
-
(rv_vslideup_vvi x_clip y_clip lane_diff (unmasked) out_ty)))
|
1979
|
-
|
1980
|
-
;;;; Rules for `uunarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1981
|
-
|
1982
|
-
(rule (lower (has_type (ty_vec_fits_in_register out_ty) (uunarrow x @ (value_type in_ty) y)))
|
1983
|
-
(if-let lane_diff (u64_to_uimm5 (u64_udiv (ty_lane_count out_ty) 2)))
|
1984
|
-
(if-let zero (u64_to_uimm5 0))
|
1985
|
-
(let ((x_clip VReg (rv_vnclipu_wi x zero (unmasked) (vstate_mf2 (ty_half_lanes out_ty))))
|
1986
|
-
(y_clip VReg (rv_vnclipu_wi y zero (unmasked) (vstate_mf2 (ty_half_lanes out_ty)))))
|
1987
|
-
(rv_vslideup_vvi x_clip y_clip lane_diff (unmasked) out_ty)))
|
1988
|
-
|
1989
|
-
;;;; Rules for `unarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
1990
|
-
|
1991
|
-
;; We don't have a instruction that saturates a signed source into an unsigned destination.
|
1992
|
-
;; To correct for this we just remove negative values using `vmax` and then use the normal
|
1993
|
-
;; unsigned to unsigned narrowing instruction.
|
1994
|
-
|
1995
|
-
(rule (lower (has_type (ty_vec_fits_in_register out_ty) (unarrow x @ (value_type in_ty) y)))
|
1996
|
-
(if-let lane_diff (u64_to_uimm5 (u64_udiv (ty_lane_count out_ty) 2)))
|
1997
|
-
(if-let zero (u64_to_uimm5 0))
|
1998
|
-
(let ((x_pos VReg (rv_vmax_vx x (zero_reg) (unmasked) in_ty))
|
1999
|
-
(y_pos VReg (rv_vmax_vx y (zero_reg) (unmasked) in_ty))
|
2000
|
-
(x_clip VReg (rv_vnclipu_wi x_pos zero (unmasked) (vstate_mf2 (ty_half_lanes out_ty))))
|
2001
|
-
(y_clip VReg (rv_vnclipu_wi y_pos zero (unmasked) (vstate_mf2 (ty_half_lanes out_ty)))))
|
2002
|
-
(rv_vslideup_vvi x_clip y_clip lane_diff (unmasked) out_ty)))
|