wasmtime 12.0.1 → 13.0.0

data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/isa/riscv64/inst/encode.rs

@@ -1,281 +0,0 @@
-//! Contains the RISC-V instruction encoding logic.
-//!
-//! These formats are specified in the RISC-V specification in section 2.2.
-//! See: https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
-//!
-//! Some instructions especially in extensions have slight variations from
-//! the base RISC-V specification.
-
-use super::{Imm12, Imm5, UImm5, VType};
-use crate::isa::riscv64::inst::reg_to_gpr_num;
-use crate::isa::riscv64::lower::isle::generated_code::{
-    VecAluOpRImm5, VecAluOpRR, VecAluOpRRImm5, VecAluOpRRR, VecAluOpRRRImm5, VecElementWidth,
-    VecOpCategory, VecOpMasking,
-};
-use crate::machinst::isle::WritableReg;
-use crate::Reg;
-
-fn unsigned_field_width(value: u32, width: u8) -> u32 {
-    debug_assert_eq!(value & (!0 << width), 0);
-    value
-}
-
-/// Layout:
-/// 0-------6-7-------11-12------14-15------19-20------24-25-------31
-/// | Opcode |   rd     |  funct3  |   rs1    |   rs2    |   funct7  |
-fn encode_r_type_bits(opcode: u32, rd: u32, funct3: u32, rs1: u32, rs2: u32, funct7: u32) -> u32 {
-    let mut bits = 0;
-    bits |= unsigned_field_width(opcode, 7);
-    bits |= unsigned_field_width(rd, 5) << 7;
-    bits |= unsigned_field_width(funct3, 3) << 12;
-    bits |= unsigned_field_width(rs1, 5) << 15;
-    bits |= unsigned_field_width(rs2, 5) << 20;
-    bits |= unsigned_field_width(funct7, 7) << 25;
-    bits
-}
-
-/// Encode an R-type instruction.
-pub fn encode_r_type(
-    opcode: u32,
-    rd: WritableReg,
-    funct3: u32,
-    rs1: Reg,
-    rs2: Reg,
-    funct7: u32,
-) -> u32 {
-    encode_r_type_bits(
-        opcode,
-        reg_to_gpr_num(rd.to_reg()),
-        funct3,
-        reg_to_gpr_num(rs1),
-        reg_to_gpr_num(rs2),
-        funct7,
-    )
-}
-
-/// Encode an I-type instruction.
-///
-/// Layout:
-/// 0-------6-7-------11-12------14-15------19-20------------------31
-/// | Opcode |   rd     |  width   |   rs1    |     Offset[11:0]    |
-pub fn encode_i_type(opcode: u32, rd: WritableReg, width: u32, rs1: Reg, offset: Imm12) -> u32 {
-    let mut bits = 0;
-    bits |= unsigned_field_width(opcode, 7);
-    bits |= reg_to_gpr_num(rd.to_reg()) << 7;
-    bits |= unsigned_field_width(width, 3) << 12;
-    bits |= reg_to_gpr_num(rs1) << 15;
-    bits |= unsigned_field_width(offset.as_u32(), 12) << 20;
-    bits
-}
-
-/// Encode an S-type instruction.
-///
-/// Layout:
-/// 0-------6-7-------11-12------14-15------19-20---24-25-------------31
-/// | Opcode | imm[4:0] |  width   |   base   |  src  |    imm[11:5]   |
-pub fn encode_s_type(opcode: u32, width: u32, base: Reg, src: Reg, offset: Imm12) -> u32 {
-    let mut bits = 0;
-    bits |= unsigned_field_width(opcode, 7);
-    bits |= (offset.as_u32() & 0b11111) << 7;
-    bits |= unsigned_field_width(width, 3) << 12;
-    bits |= reg_to_gpr_num(base) << 15;
-    bits |= reg_to_gpr_num(src) << 20;
-    bits |= unsigned_field_width(offset.as_u32() >> 5, 7) << 25;
-    bits
-}
-
-/// Encodes a Vector ALU instruction.
-///
-/// Fields:
-/// - opcode (7 bits)
-/// - vd     (5 bits)
-/// - funct3 (3 bits)
-/// - vs1    (5 bits)
-/// - vs2    (5 bits)
-/// - vm     (1 bit)
-/// - funct6 (6 bits)
-///
-/// See: https://github.com/riscv/riscv-v-spec/blob/master/valu-format.adoc
-pub fn encode_valu(
-    op: VecAluOpRRR,
-    vd: WritableReg,
-    vs1: Reg,
-    vs2: Reg,
-    masking: VecOpMasking,
-) -> u32 {
-    let funct7 = (op.funct6() << 1) | masking.encode();
-    encode_r_type_bits(
-        op.opcode(),
-        reg_to_gpr_num(vd.to_reg()),
-        op.funct3(),
-        reg_to_gpr_num(vs1),
-        reg_to_gpr_num(vs2),
-        funct7,
-    )
-}
-
-/// Encodes a Vector ALU+Imm instruction.
-/// This is just a Vector ALU instruction with an immediate in the VS1 field.
-///
-/// Fields:
-/// - opcode (7 bits)
-/// - vd     (5 bits)
-/// - funct3 (3 bits)
-/// - imm    (5 bits)
-/// - vs2    (5 bits)
-/// - vm     (1 bit)
-/// - funct6 (6 bits)
-///
-/// See: https://github.com/riscv/riscv-v-spec/blob/master/valu-format.adoc
-pub fn encode_valu_rr_imm(
-    op: VecAluOpRRImm5,
-    vd: WritableReg,
-    imm: Imm5,
-    vs2: Reg,
-    masking: VecOpMasking,
-) -> u32 {
-    let funct7 = (op.funct6() << 1) | masking.encode();
-    let imm = imm.bits() as u32;
-    encode_r_type_bits(
-        op.opcode(),
-        reg_to_gpr_num(vd.to_reg()),
-        op.funct3(),
-        imm,
-        reg_to_gpr_num(vs2),
-        funct7,
-    )
-}
-
-pub fn encode_valu_rrr_imm(
-    op: VecAluOpRRRImm5,
-    vd: WritableReg,
-    imm: Imm5,
-    vs2: Reg,
-    masking: VecOpMasking,
-) -> u32 {
-    let funct7 = (op.funct6() << 1) | masking.encode();
-    let imm = imm.bits() as u32;
-    encode_r_type_bits(
-        op.opcode(),
-        reg_to_gpr_num(vd.to_reg()),
-        op.funct3(),
-        imm,
-        reg_to_gpr_num(vs2),
-        funct7,
-    )
-}
-
-pub fn encode_valu_rr(op: VecAluOpRR, vd: WritableReg, vs: Reg, masking: VecOpMasking) -> u32 {
-    let funct7 = (op.funct6() << 1) | masking.encode();
-
-    let (vs1, vs2) = if op.vs_is_vs2_encoded() {
-        (op.aux_encoding(), reg_to_gpr_num(vs))
-    } else {
-        (reg_to_gpr_num(vs), op.aux_encoding())
-    };
-
-    encode_r_type_bits(
-        op.opcode(),
-        reg_to_gpr_num(vd.to_reg()),
-        op.funct3(),
-        vs1,
-        vs2,
-        funct7,
-    )
-}
-
-pub fn encode_valu_r_imm(
-    op: VecAluOpRImm5,
-    vd: WritableReg,
-    imm: Imm5,
-    masking: VecOpMasking,
-) -> u32 {
-    let funct7 = (op.funct6() << 1) | masking.encode();
-
-    // This is true for this opcode, not sure if there are any other ones.
-    debug_assert_eq!(op, VecAluOpRImm5::VmvVI);
-    let vs1 = imm.bits() as u32;
-    let vs2 = op.aux_encoding();
-
-    encode_r_type_bits(
-        op.opcode(),
-        reg_to_gpr_num(vd.to_reg()),
-        op.funct3(),
-        vs1,
-        vs2,
-        funct7,
-    )
-}
-
-/// Encodes a Vector CFG Imm instruction.
-///
-/// See: https://github.com/riscv/riscv-v-spec/blob/master/vcfg-format.adoc
-// TODO: Check if this is any of the known instruction types in the spec.
-pub fn encode_vcfg_imm(opcode: u32, rd: Reg, imm: UImm5, vtype: &VType) -> u32 {
-    let mut bits = 0;
-    bits |= unsigned_field_width(opcode, 7);
-    bits |= reg_to_gpr_num(rd) << 7;
-    bits |= VecOpCategory::OPCFG.encode() << 12;
-    bits |= unsigned_field_width(imm.bits(), 5) << 15;
-    bits |= unsigned_field_width(vtype.encode(), 10) << 20;
-    bits |= 0b11 << 30;
-    bits
-}
-
-/// Encodes a Vector Mem Unit Stride Load instruction.
-///
-/// See: https://github.com/riscv/riscv-v-spec/blob/master/vmem-format.adoc
-/// TODO: These instructions share opcode space with LOAD-FP and STORE-FP
-pub fn encode_vmem_load(
-    opcode: u32,
-    vd: Reg,
-    width: VecElementWidth,
-    rs1: Reg,
-    lumop: u32,
-    masking: VecOpMasking,
-    mop: u32,
-    nf: u32,
-) -> u32 {
-    // Width is encoded differently to avoid a clash with the FP load/store sizes.
-    let width = match width {
-        VecElementWidth::E8 => 0b000,
-        VecElementWidth::E16 => 0b101,
-        VecElementWidth::E32 => 0b110,
-        VecElementWidth::E64 => 0b111,
-    };
-
-    let mut bits = 0;
-    bits |= unsigned_field_width(opcode, 7);
-    bits |= reg_to_gpr_num(vd) << 7;
-    bits |= width << 12;
-    bits |= reg_to_gpr_num(rs1) << 15;
-    bits |= unsigned_field_width(lumop, 5) << 20;
-    bits |= masking.encode() << 25;
-    bits |= unsigned_field_width(mop, 2) << 26;
-
-    // The mew bit (inst[28]) when set is expected to be used to encode expanded
-    // memory sizes of 128 bits and above, but these encodings are currently reserved.
-    bits |= 0b0 << 28;
-
-    bits |= unsigned_field_width(nf, 3) << 29;
-    bits
-}
-
-/// Encodes a Vector Mem Unit Stride Load instruction.
-///
-/// See: https://github.com/riscv/riscv-v-spec/blob/master/vmem-format.adoc
-/// TODO: These instructions share opcode space with LOAD-FP and STORE-FP
-pub fn encode_vmem_store(
-    opcode: u32,
-    vs3: Reg,
-    width: VecElementWidth,
-    rs1: Reg,
-    sumop: u32,
-    masking: VecOpMasking,
-    mop: u32,
-    nf: u32,
-) -> u32 {
-    // This is pretty much the same as the load instruction, just
-    // with different names on the fields.
-    encode_vmem_load(opcode, vs3, width, rs1, sumop, masking, mop, nf)
-}

data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/isa/riscv64/inst/imms.rs

@@ -1,250 +0,0 @@
-//! Riscv64 ISA definitions: immediate constants.
-
-// Some variants are never constructed, but we still want them as options in the future.
-use super::Inst;
-#[allow(dead_code)]
-use std::fmt::{Debug, Display, Formatter, Result};
-
-#[derive(Copy, Clone, Debug, Default)]
-pub struct Imm12 {
-    pub bits: i16,
-}
-
-impl Imm12 {
-    pub(crate) const FALSE: Self = Self { bits: 0 };
-    pub(crate) const TRUE: Self = Self { bits: 1 };
-    pub fn maybe_from_u64(val: u64) -> Option<Imm12> {
-        let sign_bit = 1 << 11;
-        if val == 0 {
-            Some(Imm12 { bits: 0 })
-        } else if (val & sign_bit) != 0 && (val >> 12) == 0xffff_ffff_ffff_f {
-            Some(Imm12 {
-                bits: (val & 0xffff) as i16,
-            })
-        } else if (val & sign_bit) == 0 && (val >> 12) == 0 {
-            Some(Imm12 {
-                bits: (val & 0xffff) as i16,
-            })
-        } else {
-            None
-        }
-    }
-    #[inline]
-    pub fn from_bits(bits: i16) -> Self {
-        Self { bits: bits & 0xfff }
-    }
-    /// Create a zero immediate of this format.
-    #[inline]
-    pub fn zero() -> Self {
-        Imm12 { bits: 0 }
-    }
-    #[inline]
-    pub fn as_i16(self) -> i16 {
-        self.bits
-    }
-    #[inline]
-    pub fn as_u32(&self) -> u32 {
-        (self.bits as u32) & 0xfff
-    }
-}
-
-impl Into<i64> for Imm12 {
-    fn into(self) -> i64 {
-        self.bits as i64
-    }
-}
-
-impl Display for Imm12 {
-    fn fmt(&self, f: &mut Formatter<'_>) -> Result {
-        write!(f, "{:+}", self.bits)
-    }
-}
-
-impl std::ops::Neg for Imm12 {
-    type Output = Self;
-    fn neg(self) -> Self::Output {
-        Self { bits: -self.bits }
-    }
-}
-
-// singed
-#[derive(Clone, Copy, Default)]
-pub struct Imm20 {
-    /// The immediate bits.
-    pub bits: i32,
-}
-
-impl Imm20 {
-    #[inline]
-    pub fn from_bits(bits: i32) -> Self {
-        Self {
-            bits: bits & 0xf_ffff,
-        }
-    }
-    #[inline]
-    pub fn as_u32(&self) -> u32 {
-        (self.bits as u32) & 0xf_ffff
-    }
-}
-
-impl Debug for Imm20 {
-    fn fmt(&self, f: &mut Formatter<'_>) -> Result {
-        write!(f, "{}", self.bits)
-    }
-}
-
-impl Display for Imm20 {
-    fn fmt(&self, f: &mut Formatter<'_>) -> Result {
-        write!(f, "{}", self.bits)
-    }
-}
-
-/// An unsigned 5-bit immediate.
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub struct UImm5 {
-    value: u8,
-}
-
-impl UImm5 {
-    /// Create an unsigned 5-bit immediate from u8.
-    pub fn maybe_from_u8(value: u8) -> Option<UImm5> {
-        if value < 32 {
-            Some(UImm5 { value })
-        } else {
-            None
-        }
-    }
-
-    /// Bits for encoding.
-    pub fn bits(&self) -> u32 {
-        u32::from(self.value)
-    }
-}
-
-impl Display for UImm5 {
-    fn fmt(&self, f: &mut Formatter<'_>) -> Result {
-        write!(f, "{}", self.value)
-    }
-}
-
-/// A Signed 5-bit immediate.
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub struct Imm5 {
-    value: i8,
-}
-
-impl Imm5 {
-    /// Create an signed 5-bit immediate from an i8.
-    pub fn maybe_from_i8(value: i8) -> Option<Imm5> {
-        if value >= -16 && value <= 15 {
-            Some(Imm5 { value })
-        } else {
-            None
-        }
-    }
-
-    pub fn from_bits(value: u8) -> Imm5 {
-        assert_eq!(value & 0x1f, value);
-        let signed = ((value << 3) as i8) >> 3;
-        Imm5 { value: signed }
-    }
-
-    /// Bits for encoding.
-    pub fn bits(&self) -> u8 {
-        self.value as u8 & 0x1f
-    }
-}
-
-impl Display for Imm5 {
-    fn fmt(&self, f: &mut Formatter<'_>) -> Result {
-        write!(f, "{}", self.value)
-    }
-}
-
-impl Inst {
-    pub(crate) fn imm_min() -> i64 {
-        let imm20_max: i64 = (1 << 19) << 12;
-        let imm12_max = 1 << 11;
-        -imm20_max - imm12_max
-    }
-    pub(crate) fn imm_max() -> i64 {
-        let imm20_max: i64 = ((1 << 19) - 1) << 12;
-        let imm12_max = (1 << 11) - 1;
-        imm20_max + imm12_max
-    }
-
-    /// An imm20 immediate and an Imm12 immediate can generate a 32-bit immediate.
-    /// This helper produces an imm12, imm20, or both to generate the value.
-    ///
-    /// `value` must be between `imm_min()` and `imm_max()`, or else
-    /// this helper returns `None`.
-    pub(crate) fn generate_imm<R>(
-        value: u64,
-        mut handle_imm: impl FnMut(Option<Imm20>, Option<Imm12>) -> R,
-    ) -> Option<R> {
-        if let Some(imm12) = Imm12::maybe_from_u64(value) {
-            // can be load using single imm12.
-            let r = handle_imm(None, Some(imm12));
-            return Some(r);
-        }
-        let value = value as i64;
-        if !(value >= Self::imm_min() && value <= Self::imm_max()) {
-            // not in range, return None.
-            return None;
-        }
-        const MOD_NUM: i64 = 4096;
-        let (imm20, imm12) = if value > 0 {
-            let mut imm20 = value / MOD_NUM;
-            let mut imm12 = value % MOD_NUM;
-            if imm12 >= 2048 {
-                imm12 -= MOD_NUM;
-                imm20 += 1;
-            }
-            assert!(imm12 >= -2048 && imm12 <= 2047);
-            (imm20, imm12)
-        } else {
-            // this is the abs value.
-            let value_abs = value.abs();
-            let imm20 = value_abs / MOD_NUM;
-            let imm12 = value_abs % MOD_NUM;
-            let mut imm20 = -imm20;
-            let mut imm12 = -imm12;
-            if imm12 < -2048 {
-                imm12 += MOD_NUM;
-                imm20 -= 1;
-            }
-            (imm20, imm12)
-        };
-        assert!(imm20 >= -(0x7_ffff + 1) && imm20 <= 0x7_ffff);
-        assert!(imm20 != 0 || imm12 != 0);
-        Some(handle_imm(
-            if imm20 != 0 {
-                Some(Imm20::from_bits(imm20 as i32))
-            } else {
-                None
-            },
-            if imm12 != 0 {
-                Some(Imm12::from_bits(imm12 as i16))
-            } else {
-                None
-            },
-        ))
-    }
-}
-
-#[cfg(test)]
-mod test {
-    use super::*;
-    #[test]
-    fn test_imm12() {
-        let x = Imm12::zero();
-        assert_eq!(0, x.as_u32());
-        Imm12::maybe_from_u64(0xffff_ffff_ffff_ffff).unwrap();
-    }
-
-    #[test]
-    fn imm20_and_imm12() {
-        assert!(Inst::imm_max() == (i32::MAX - 2048) as i64);
-        assert!(Inst::imm_min() == i32::MIN as i64 - 2048);
-    }
-}