wasmtime 12.0.1 → 13.0.0

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Files changed (2318) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +176 -221
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/cargo-vendor/cap-net-ext-2.0.0/.cargo-checksum.json +1 -0
  5. data/ext/cargo-vendor/cap-net-ext-2.0.0/COPYRIGHT +29 -0
  6. data/ext/cargo-vendor/cap-net-ext-2.0.0/Cargo.toml +38 -0
  7. data/ext/cargo-vendor/cap-net-ext-2.0.0/README.md +24 -0
  8. data/ext/cargo-vendor/cap-net-ext-2.0.0/src/lib.rs +771 -0
  9. data/ext/cargo-vendor/cranelift-bforest-0.100.0/.cargo-checksum.json +1 -0
  10. data/ext/cargo-vendor/cranelift-bforest-0.100.0/Cargo.toml +31 -0
  11. data/ext/cargo-vendor/cranelift-bforest-0.100.0/src/lib.rs +184 -0
  12. data/ext/cargo-vendor/cranelift-bforest-0.100.0/src/map.rs +922 -0
  13. data/ext/cargo-vendor/cranelift-bforest-0.100.0/src/pool.rs +219 -0
  14. data/ext/cargo-vendor/cranelift-bforest-0.100.0/src/set.rs +597 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.100.0/.cargo-checksum.json +1 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.100.0/Cargo.toml +164 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/binemit/mod.rs +141 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/binemit/stack_map.rs +155 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/bitset.rs +166 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/context.rs +372 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/incremental_cache.rs +256 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/atomic_rmw_op.rs +104 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/condcodes.rs +404 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/constant.rs +463 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/dfg.rs +1686 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/dynamic_type.rs +55 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/entities.rs +567 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/extfunc.rs +411 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/extname.rs +333 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/function.rs +475 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/globalvalue.rs +155 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/immediates.rs +1615 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/instructions.rs +1000 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/jumptable.rs +168 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/known_symbol.rs +47 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/libcall.rs +232 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/memflags.rs +279 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/mod.rs +106 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/sourceloc.rs +117 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/stackslot.rs +216 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/table.rs +40 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/trapcode.rs +144 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/types.rs +630 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/abi.rs +1573 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/inst/args.rs +747 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/inst/emit.rs +3911 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/inst/emit_tests.rs +7951 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/inst/mod.rs +3049 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/inst.isle +4173 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/lower/isle.rs +871 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/lower.isle +2889 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/lower.rs +132 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/lower_dynamic_neon.isle +98 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/call_conv.rs +119 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/abi.rs +981 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst/args.rs +1900 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst/emit.rs +3203 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst/encode.rs +326 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst/imms.rs +236 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst/mod.rs +2162 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst/vector.rs +1059 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst.isle +3092 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst_vector.isle +1887 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/lower/isle.rs +620 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/lower.isle +2119 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/s390x/abi.rs +949 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/s390x/inst/mod.rs +3430 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/s390x/inst.isle +5043 -0
  69. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/s390x/lower.isle +3982 -0
  70. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/unwind/systemv.rs +272 -0
  71. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/unwind/winx64.rs +334 -0
  72. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/unwind.rs +182 -0
  73. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/abi.rs +1200 -0
  74. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/encoding/evex.rs +749 -0
  75. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/encoding/rex.rs +589 -0
  76. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/inst/args.rs +2188 -0
  77. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/inst/emit.rs +4300 -0
  78. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/inst/emit_tests.rs +5474 -0
  79. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/inst/mod.rs +2763 -0
  80. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/inst.isle +5110 -0
  81. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/lower/isle.rs +1096 -0
  82. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/lower.isle +4675 -0
  83. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/lower.rs +340 -0
  84. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isle_prelude.rs +899 -0
  85. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/legalizer/mod.rs +356 -0
  86. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/lib.rs +107 -0
  87. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/machinst/abi.rs +2644 -0
  88. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/machinst/buffer.rs +2362 -0
  89. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/machinst/isle.rs +846 -0
  90. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/machinst/mod.rs +553 -0
  91. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/machinst/reg.rs +556 -0
  92. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/machinst/vcode.rs +1646 -0
  93. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/opts/bitops.isle +147 -0
  94. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/opts/cprop.isle +200 -0
  95. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/opts/extends.isle +34 -0
  96. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/opts/icmp.isle +177 -0
  97. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/opts/selects.isle +59 -0
  98. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/opts/vector.isle +88 -0
  99. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/prelude.isle +603 -0
  100. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/prelude_lower.isle +1029 -0
  101. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/value_label.rs +32 -0
  102. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/verifier/mod.rs +1986 -0
  103. data/ext/cargo-vendor/cranelift-codegen-meta-0.100.0/.cargo-checksum.json +1 -0
  104. data/ext/cargo-vendor/cranelift-codegen-meta-0.100.0/Cargo.toml +26 -0
  105. data/ext/cargo-vendor/cranelift-codegen-meta-0.100.0/src/constant_hash.rs +63 -0
  106. data/ext/cargo-vendor/cranelift-codegen-meta-0.100.0/src/gen_inst.rs +1784 -0
  107. data/ext/cargo-vendor/cranelift-codegen-meta-0.100.0/src/shared/instructions.rs +3810 -0
  108. data/ext/cargo-vendor/cranelift-codegen-shared-0.100.0/.cargo-checksum.json +1 -0
  109. data/ext/cargo-vendor/cranelift-codegen-shared-0.100.0/Cargo.toml +22 -0
  110. data/ext/cargo-vendor/cranelift-codegen-shared-0.100.0/src/lib.rs +12 -0
  111. data/ext/cargo-vendor/cranelift-control-0.100.0/.cargo-checksum.json +1 -0
  112. data/ext/cargo-vendor/cranelift-control-0.100.0/Cargo.toml +30 -0
  113. data/ext/cargo-vendor/cranelift-entity-0.100.0/.cargo-checksum.json +1 -0
  114. data/ext/cargo-vendor/cranelift-entity-0.100.0/Cargo.toml +41 -0
  115. data/ext/cargo-vendor/cranelift-entity-0.100.0/src/lib.rs +316 -0
  116. data/ext/cargo-vendor/cranelift-entity-0.100.0/src/list.rs +955 -0
  117. data/ext/cargo-vendor/cranelift-entity-0.100.0/src/packed_option.rs +171 -0
  118. data/ext/cargo-vendor/cranelift-entity-0.100.0/src/primary.rs +456 -0
  119. data/ext/cargo-vendor/cranelift-entity-0.100.0/src/sparse.rs +368 -0
  120. data/ext/cargo-vendor/cranelift-frontend-0.100.0/.cargo-checksum.json +1 -0
  121. data/ext/cargo-vendor/cranelift-frontend-0.100.0/Cargo.toml +54 -0
  122. data/ext/cargo-vendor/cranelift-frontend-0.100.0/src/lib.rs +191 -0
  123. data/ext/cargo-vendor/cranelift-isle-0.100.0/.cargo-checksum.json +1 -0
  124. data/ext/cargo-vendor/cranelift-isle-0.100.0/Cargo.toml +37 -0
  125. data/ext/cargo-vendor/cranelift-native-0.100.0/.cargo-checksum.json +1 -0
  126. data/ext/cargo-vendor/cranelift-native-0.100.0/Cargo.toml +38 -0
  127. data/ext/cargo-vendor/cranelift-native-0.100.0/src/lib.rs +190 -0
  128. data/ext/cargo-vendor/cranelift-wasm-0.100.0/.cargo-checksum.json +1 -0
  129. data/ext/cargo-vendor/cranelift-wasm-0.100.0/Cargo.toml +92 -0
  130. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/code_translator.rs +3641 -0
  131. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/environ/dummy.rs +942 -0
  132. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/environ/spec.rs +949 -0
  133. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/func_translator.rs +432 -0
  134. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/heap.rs +108 -0
  135. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/lib.rs +64 -0
  136. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/sections_translator.rs +408 -0
  137. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/translation_utils.rs +97 -0
  138. data/ext/cargo-vendor/fallible-iterator-0.3.0/.cargo-checksum.json +1 -0
  139. data/ext/cargo-vendor/fallible-iterator-0.3.0/CHANGELOG.md +39 -0
  140. data/ext/cargo-vendor/fallible-iterator-0.3.0/Cargo.toml +29 -0
  141. data/ext/cargo-vendor/fallible-iterator-0.3.0/README.md +16 -0
  142. data/ext/cargo-vendor/fallible-iterator-0.3.0/src/lib.rs +2808 -0
  143. data/ext/cargo-vendor/fallible-iterator-0.3.0/src/test.rs +477 -0
  144. data/ext/cargo-vendor/serde-1.0.188/.cargo-checksum.json +1 -0
  145. data/ext/cargo-vendor/serde-1.0.188/Cargo.toml +69 -0
  146. data/ext/cargo-vendor/serde-1.0.188/build.rs +90 -0
  147. data/ext/cargo-vendor/serde-1.0.188/src/de/ignored_any.rs +238 -0
  148. data/ext/cargo-vendor/serde-1.0.188/src/de/impls.rs +2966 -0
  149. data/ext/cargo-vendor/serde-1.0.188/src/de/mod.rs +2290 -0
  150. data/ext/cargo-vendor/serde-1.0.188/src/de/value.rs +1708 -0
  151. data/ext/cargo-vendor/serde-1.0.188/src/integer128.rs +9 -0
  152. data/ext/cargo-vendor/serde-1.0.188/src/lib.rs +327 -0
  153. data/ext/cargo-vendor/serde-1.0.188/src/macros.rs +231 -0
  154. data/ext/cargo-vendor/serde-1.0.188/src/ser/fmt.rs +170 -0
  155. data/ext/cargo-vendor/serde-1.0.188/src/ser/impls.rs +998 -0
  156. data/ext/cargo-vendor/serde-1.0.188/src/ser/mod.rs +1952 -0
  157. data/ext/cargo-vendor/serde_derive-1.0.188/.cargo-checksum.json +1 -0
  158. data/ext/cargo-vendor/serde_derive-1.0.188/Cargo.toml +59 -0
  159. data/ext/cargo-vendor/serde_derive-1.0.188/src/lib.rs +102 -0
  160. data/ext/cargo-vendor/serde_derive-1.0.188/src/ser.rs +1359 -0
  161. data/ext/cargo-vendor/wasi-cap-std-sync-13.0.0/.cargo-checksum.json +1 -0
  162. data/ext/cargo-vendor/wasi-cap-std-sync-13.0.0/Cargo.toml +96 -0
  163. data/ext/cargo-vendor/wasi-cap-std-sync-13.0.0/src/lib.rs +161 -0
  164. data/ext/cargo-vendor/wasi-common-13.0.0/.cargo-checksum.json +1 -0
  165. data/ext/cargo-vendor/wasi-common-13.0.0/Cargo.toml +87 -0
  166. data/ext/cargo-vendor/wasm-encoder-0.32.0/.cargo-checksum.json +1 -0
  167. data/ext/cargo-vendor/wasm-encoder-0.32.0/Cargo.toml +33 -0
  168. data/ext/cargo-vendor/wasm-encoder-0.32.0/src/component/types.rs +769 -0
  169. data/ext/cargo-vendor/wasm-encoder-0.33.1/.cargo-checksum.json +1 -0
  170. data/ext/cargo-vendor/wasm-encoder-0.33.1/Cargo.toml +33 -0
  171. data/ext/cargo-vendor/wasm-encoder-0.33.1/README.md +80 -0
  172. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/aliases.rs +160 -0
  173. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/builder.rs +449 -0
  174. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/canonicals.rs +159 -0
  175. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/components.rs +29 -0
  176. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/exports.rs +127 -0
  177. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/imports.rs +200 -0
  178. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/instances.rs +200 -0
  179. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/modules.rs +29 -0
  180. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/names.rs +149 -0
  181. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/start.rs +52 -0
  182. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/types.rs +769 -0
  183. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component.rs +168 -0
  184. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/code.rs +2913 -0
  185. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/custom.rs +73 -0
  186. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/data.rs +185 -0
  187. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/dump.rs +627 -0
  188. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/elements.rs +220 -0
  189. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/exports.rs +85 -0
  190. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/functions.rs +63 -0
  191. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/globals.rs +90 -0
  192. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/imports.rs +142 -0
  193. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/linking.rs +263 -0
  194. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/memories.rs +99 -0
  195. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/names.rs +265 -0
  196. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/producers.rs +180 -0
  197. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/start.rs +39 -0
  198. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/tables.rs +104 -0
  199. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/tags.rs +85 -0
  200. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/types.rs +372 -0
  201. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core.rs +168 -0
  202. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/lib.rs +215 -0
  203. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/raw.rs +30 -0
  204. data/ext/cargo-vendor/wasmparser-0.112.0/.cargo-checksum.json +1 -0
  205. data/ext/cargo-vendor/wasmparser-0.112.0/Cargo.lock +644 -0
  206. data/ext/cargo-vendor/wasmparser-0.112.0/Cargo.toml +54 -0
  207. data/ext/cargo-vendor/wasmparser-0.112.0/src/limits.rs +58 -0
  208. data/ext/cargo-vendor/wasmparser-0.112.0/src/readers/component/types.rs +542 -0
  209. data/ext/cargo-vendor/wasmparser-0.112.0/src/readers/core/types.rs +1303 -0
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  1253. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/s390x/settings.rs +0 -0
  1254. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/encoding/mod.rs +0 -0
  1255. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/encoding/vex.rs +0 -0
  1256. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/inst/emit_state.rs +0 -0
  1257. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/inst/regs.rs +0 -0
  1258. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1259. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1260. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/inst/unwind.rs +0 -0
  1261. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1262. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/mod.rs +0 -0
  1263. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/settings.rs +0 -0
  1264. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/iterators.rs +0 -0
  1265. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/legalizer/globalvalue.rs +0 -0
  1266. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/legalizer/table.rs +0 -0
  1267. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/loop_analysis.rs +0 -0
  1268. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/machinst/blockorder.rs +0 -0
  1269. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/machinst/compile.rs +0 -0
  1270. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/machinst/helpers.rs +0 -0
  1271. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/machinst/inst_common.rs +0 -0
  1272. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/machinst/lower.rs +0 -0
  1273. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/machinst/valueregs.rs +0 -0
  1274. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/nan_canonicalization.rs +0 -0
  1275. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/opts/README.md +0 -0
  1276. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/opts/arithmetic.isle +0 -0
  1277. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/opts/generated_code.rs +0 -0
  1278. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/opts/remat.isle +0 -0
  1279. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/opts/shifts.isle +0 -0
  1280. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/opts.rs +0 -0
  1281. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/prelude_opt.isle +0 -0
  1282. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/print_errors.rs +0 -0
  1283. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/remove_constant_phis.rs +0 -0
  1284. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/result.rs +0 -0
  1285. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/scoped_hash_map.rs +0 -0
  1286. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/settings.rs +0 -0
  1287. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/souper_harvest.rs +0 -0
  1288. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/timing.rs +0 -0
  1289. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/unionfind.rs +0 -0
  1290. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/unreachable_code.rs +0 -0
  1291. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/write.rs +0 -0
  1292. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.99.1 → cranelift-codegen-meta-0.100.0}/LICENSE +0 -0
  1293. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/README.md +0 -0
  1294. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/formats.rs +0 -0
  1295. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/instructions.rs +0 -0
  1296. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/isa.rs +0 -0
  1297. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/mod.rs +0 -0
  1298. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/operands.rs +0 -0
  1299. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/settings.rs +0 -0
  1300. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/types.rs +0 -0
  1301. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/typevar.rs +0 -0
  1302. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/error.rs +0 -0
  1303. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/gen_settings.rs +0 -0
  1304. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/gen_types.rs +0 -0
  1305. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/isa/arm64.rs +0 -0
  1306. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/isa/mod.rs +0 -0
  1307. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/isa/riscv64.rs +0 -0
  1308. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/isa/s390x.rs +0 -0
  1309. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/isa/x86.rs +0 -0
  1310. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/lib.rs +0 -0
  1311. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/shared/entities.rs +0 -0
  1312. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/shared/formats.rs +0 -0
  1313. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/shared/immediates.rs +0 -0
  1314. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/shared/mod.rs +0 -0
  1315. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/shared/settings.rs +0 -0
  1316. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/shared/types.rs +0 -0
  1317. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/srcgen.rs +0 -0
  1318. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/unique_table.rs +0 -0
  1319. /data/ext/cargo-vendor/{cranelift-control-0.99.1 → cranelift-codegen-shared-0.100.0}/LICENSE +0 -0
  1320. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.99.1 → cranelift-codegen-shared-0.100.0}/README.md +0 -0
  1321. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.99.1 → cranelift-codegen-shared-0.100.0}/src/constant_hash.rs +0 -0
  1322. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.99.1 → cranelift-codegen-shared-0.100.0}/src/constants.rs +0 -0
  1323. /data/ext/cargo-vendor/{cranelift-entity-0.99.1 → cranelift-control-0.100.0}/LICENSE +0 -0
  1324. /data/ext/cargo-vendor/{cranelift-control-0.99.1 → cranelift-control-0.100.0}/README.md +0 -0
  1325. /data/ext/cargo-vendor/{cranelift-control-0.99.1 → cranelift-control-0.100.0}/src/chaos.rs +0 -0
  1326. /data/ext/cargo-vendor/{cranelift-control-0.99.1 → cranelift-control-0.100.0}/src/lib.rs +0 -0
  1327. /data/ext/cargo-vendor/{cranelift-control-0.99.1 → cranelift-control-0.100.0}/src/zero_sized.rs +0 -0
  1328. /data/ext/cargo-vendor/{cranelift-frontend-0.99.1 → cranelift-entity-0.100.0}/LICENSE +0 -0
  1329. /data/ext/cargo-vendor/{cranelift-entity-0.99.1 → cranelift-entity-0.100.0}/README.md +0 -0
  1330. /data/ext/cargo-vendor/{cranelift-entity-0.99.1 → cranelift-entity-0.100.0}/src/boxed_slice.rs +0 -0
  1331. /data/ext/cargo-vendor/{cranelift-entity-0.99.1 → cranelift-entity-0.100.0}/src/iter.rs +0 -0
  1332. /data/ext/cargo-vendor/{cranelift-entity-0.99.1 → cranelift-entity-0.100.0}/src/keys.rs +0 -0
  1333. /data/ext/cargo-vendor/{cranelift-entity-0.99.1 → cranelift-entity-0.100.0}/src/map.rs +0 -0
  1334. /data/ext/cargo-vendor/{cranelift-entity-0.99.1 → cranelift-entity-0.100.0}/src/set.rs +0 -0
  1335. /data/ext/cargo-vendor/{cranelift-native-0.99.1 → cranelift-frontend-0.100.0}/LICENSE +0 -0
  1336. /data/ext/cargo-vendor/{cranelift-frontend-0.99.1 → cranelift-frontend-0.100.0}/README.md +0 -0
  1337. /data/ext/cargo-vendor/{cranelift-frontend-0.99.1 → cranelift-frontend-0.100.0}/src/frontend.rs +0 -0
  1338. /data/ext/cargo-vendor/{cranelift-frontend-0.99.1 → cranelift-frontend-0.100.0}/src/ssa.rs +0 -0
  1339. /data/ext/cargo-vendor/{cranelift-frontend-0.99.1 → cranelift-frontend-0.100.0}/src/switch.rs +0 -0
  1340. /data/ext/cargo-vendor/{cranelift-frontend-0.99.1 → cranelift-frontend-0.100.0}/src/variable.rs +0 -0
  1341. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/README.md +0 -0
  1342. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/build.rs +0 -0
  1343. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/bad_converters.isle +0 -0
  1344. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1345. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1346. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/error1.isle +0 -0
  1347. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/extra_parens.isle +0 -0
  1348. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/impure_expression.isle +0 -0
  1349. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/impure_rhs.isle +0 -0
  1350. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1351. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/multi_prio.isle +0 -0
  1352. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/borrows.isle +0 -0
  1353. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/borrows_main.rs +0 -0
  1354. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/iflets.isle +0 -0
  1355. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/iflets_main.rs +0 -0
  1356. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/multi_constructor.isle +0 -0
  1357. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/multi_constructor_main.rs +0 -0
  1358. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/multi_extractor.isle +0 -0
  1359. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/multi_extractor_main.rs +0 -0
  1360. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/test.isle +0 -0
  1361. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/test_main.rs +0 -0
  1362. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/bound_var.isle +0 -0
  1363. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/construct_and_extract.isle +0 -0
  1364. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/conversions.isle +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/conversions_extern.isle +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/let.isle +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/nodebug.isle +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/prio_trie_bug.isle +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/test2.isle +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/test3.isle +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/test4.isle +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/tutorial.isle +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/run/iconst.isle +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/run/iconst_main.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/run/let_shadowing.isle +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/run/let_shadowing_main.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/ast.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/codegen.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/compile.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/error.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/lexer.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/lib.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/log.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/overlap.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/parser.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/sema.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/serialize.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/trie_again.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/tests/run_tests.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-wasm-0.99.1 → cranelift-native-0.100.0}/LICENSE +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-native-0.99.1 → cranelift-native-0.100.0}/README.md +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-native-0.99.1 → cranelift-native-0.100.0}/src/riscv.rs +0 -0
  1393. /data/ext/cargo-vendor/{wasi-cap-std-sync-12.0.1 → cranelift-wasm-0.100.0}/LICENSE +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-wasm-0.99.1 → cranelift-wasm-0.100.0}/README.md +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-wasm-0.99.1 → cranelift-wasm-0.100.0}/src/code_translator/bounds_checks.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-wasm-0.99.1 → cranelift-wasm-0.100.0}/src/environ/mod.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-wasm-0.99.1 → cranelift-wasm-0.100.0}/src/module_translator.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-wasm-0.99.1 → cranelift-wasm-0.100.0}/src/state.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-wasm-0.99.1 → cranelift-wasm-0.100.0}/tests/wasm_testsuite.rs +0 -0
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  1492. /data/ext/cargo-vendor/{wasi-cap-std-sync-12.0.1 → wasi-cap-std-sync-13.0.0}/src/net.rs +0 -0
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  1496. /data/ext/cargo-vendor/{wasi-cap-std-sync-12.0.1 → wasi-cap-std-sync-13.0.0}/src/stdio.rs +0 -0
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  1551. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/component/modules.rs +0 -0
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  1557. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/data.rs +0 -0
  1558. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/dump.rs +0 -0
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  1564. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/linking.rs +0 -0
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  1567. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/producers.rs +0 -0
  1568. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/start.rs +0 -0
  1569. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/tables.rs +0 -0
  1570. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/tags.rs +0 -0
  1571. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/types.rs +0 -0
  1572. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core.rs +0 -0
  1573. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/lib.rs +0 -0
  1574. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/raw.rs +0 -0
  1575. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasm-encoder-0.33.1}/LICENSE +0 -0
  1576. /data/ext/cargo-vendor/{wasmprinter-0.2.63 → wasmparser-0.112.0}/LICENSE +0 -0
  1577. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/README.md +0 -0
  1578. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/benches/benchmark.rs +0 -0
  1579. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/examples/simple.rs +0 -0
  1580. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/binary_reader.rs +0 -0
  1581. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/lib.rs +0 -0
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  1584. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/component/canonicals.rs +0 -0
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  1590. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/component.rs +0 -0
  1591. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/code.rs +0 -0
  1592. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/coredumps.rs +0 -0
  1593. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/custom.rs +0 -0
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  1595. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.112.0}/src/readers/core/dylink0.rs +0 -0
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  1598. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/functions.rs +0 -0
  1599. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/globals.rs +0 -0
  1600. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/imports.rs +0 -0
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  1604. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/operators.rs +0 -0
  1605. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/producers.rs +0 -0
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  1613. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/validator/operators.rs +0 -0
  1614. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/tests/big-module.rs +0 -0
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  1617. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/benches/benchmark.rs +0 -0
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  1623. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/component/imports.rs +0 -0
  1624. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/component/instances.rs +0 -0
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  1629. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/coredumps.rs +0 -0
  1630. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/custom.rs +0 -0
  1631. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/data.rs +0 -0
  1632. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/elements.rs +0 -0
  1633. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/exports.rs +0 -0
  1634. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/functions.rs +0 -0
  1635. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/globals.rs +0 -0
  1636. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/imports.rs +0 -0
  1637. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/init.rs +0 -0
  1638. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/memories.rs +0 -0
  1639. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/names.rs +0 -0
  1640. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/operators.rs +0 -0
  1641. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/producers.rs +0 -0
  1642. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/tables.rs +0 -0
  1643. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/tags.rs +0 -0
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  1647. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/validator/names.rs +0 -0
  1648. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/tests/big-module.rs +0 -0
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  1651. /data/ext/cargo-vendor/{wasmprinter-0.2.63 → wasmprinter-0.2.66}/tests/all.rs +0 -0
  1652. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-13.0.0}/LICENSE +0 -0
  1653. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/README.md +0 -0
  1654. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/code.rs +0 -0
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  1657. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/component/func/options.rs +0 -0
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  1661. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/component/storage.rs +0 -0
  1662. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/component/store.rs +0 -0
  1663. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/coredump.rs +0 -0
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  1665. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/func/typed.rs +0 -0
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  1668. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/linker.rs +0 -0
  1669. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/memory.rs +0 -0
  1670. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/module/registry.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/profiling.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/ref.rs +0 -0
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  1675. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/store/context.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/store/data.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/store/func_refs.rs +0 -0
  1678. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/trampoline/func.rs +0 -0
  1679. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/trampoline/global.rs +0 -0
  1680. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/trampoline/table.rs +0 -0
  1681. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/trap.rs +0 -0
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  1684. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/unix.rs +0 -0
  1685. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/values.rs +0 -0
  1686. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/windows.rs +0 -0
  1687. /data/ext/cargo-vendor/{wasmtime-asm-macros-12.0.1 → wasmtime-asm-macros-13.0.0}/src/lib.rs +0 -0
  1688. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-cache-13.0.0}/LICENSE +0 -0
  1689. /data/ext/cargo-vendor/{wasmtime-cache-12.0.1 → wasmtime-cache-13.0.0}/build.rs +0 -0
  1690. /data/ext/cargo-vendor/{wasmtime-cache-12.0.1 → wasmtime-cache-13.0.0}/src/config/tests.rs +0 -0
  1691. /data/ext/cargo-vendor/{wasmtime-cache-12.0.1 → wasmtime-cache-13.0.0}/src/lib.rs +0 -0
  1692. /data/ext/cargo-vendor/{wasmtime-cache-12.0.1 → wasmtime-cache-13.0.0}/src/tests.rs +0 -0
  1693. /data/ext/cargo-vendor/{wasmtime-cache-12.0.1 → wasmtime-cache-13.0.0}/src/worker/tests/system_time_stub.rs +0 -0
  1694. /data/ext/cargo-vendor/{wasmtime-cache-12.0.1 → wasmtime-cache-13.0.0}/tests/cache_write_default_config.rs +0 -0
  1695. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/src/lib.rs +0 -0
  1696. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/char.wit +0 -0
  1697. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/conventions.wit +0 -0
  1698. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/direct-import.wit +0 -0
  1699. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/empty.wit +0 -0
  1700. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/flags.wit +0 -0
  1701. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/floats.wit +0 -0
  1702. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/function-new.wit +0 -0
  1703. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/integers.wit +0 -0
  1704. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/lists.wit +0 -0
  1705. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/many-arguments.wit +0 -0
  1706. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/multi-return.wit +0 -0
  1707. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/records.wit +0 -0
  1708. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/rename.wit +0 -0
  1709. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/share-types.wit +0 -0
  1710. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/simple-functions.wit +0 -0
  1711. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/simple-lists.wit +0 -0
  1712. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/simple-wasi.wit +0 -0
  1713. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/small-anonymous.wit +0 -0
  1714. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/smoke-default.wit +0 -0
  1715. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/smoke-export.wit +0 -0
  1716. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/smoke.wit +0 -0
  1717. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/strings.wit +0 -0
  1718. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/use-paths.wit +0 -0
  1719. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/worlds-with-types.wit +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen.rs +0 -0
  1721. /data/ext/cargo-vendor/{wasmtime-component-util-12.0.1 → wasmtime-component-util-13.0.0}/src/lib.rs +0 -0
  1722. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-cranelift-13.0.0}/LICENSE +0 -0
  1723. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/SECURITY.md +0 -0
  1724. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/compiler/component.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/gc.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/address_transform.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/expression.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/line_program.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/mod.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/range_info_builder.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/refs.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/simulate.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/unit.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/utils.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/write_debuginfo.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/lib.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-12.0.1 → wasmtime-cranelift-shared-13.0.0}/src/compiled_function.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-12.0.1 → wasmtime-cranelift-shared-13.0.0}/src/isa_builder.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-12.0.1 → wasmtime-cranelift-shared-13.0.0}/src/lib.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-12.0.1 → wasmtime-cranelift-shared-13.0.0}/src/obj.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-environ-13.0.0}/LICENSE +0 -0
  1742. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/examples/factc.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/component/dfg.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/component/translate/adapt.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/component/translate/inline.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/component/translate.rs +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/component/types/resources.rs +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/component/vmcomponent_offsets.rs +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/component.rs +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/fact/core_types.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/fact/signature.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/fact/traps.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/fact.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/obj.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/ref_bits.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/scopevec.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/trap_encoding.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-fiber-13.0.0}/LICENSE +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/build.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/lib.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/unix/aarch64.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/unix/arm.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/unix/riscv64.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/unix/s390x.S +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/unix/x86.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/unix/x86_64.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/unix.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/windows.c +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/windows.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-types-12.0.1 → wasmtime-jit-13.0.0}/LICENSE +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/code_memory.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/debug.rs +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/demangling.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/profiling/jitdump.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/profiling/perfmap.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/profiling/vtune.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/profiling.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/unwind.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-jit-debug-12.0.1 → wasmtime-jit-debug-13.0.0}/README.md +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-jit-debug-12.0.1 → wasmtime-jit-debug-13.0.0}/src/gdb_jit_int.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-jit-debug-12.0.1 → wasmtime-jit-debug-13.0.0}/src/lib.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-jit-debug-12.0.1 → wasmtime-jit-debug-13.0.0}/src/perf_jitdump.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-12.0.1 → wasmtime-jit-icache-coherence-13.0.0}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-12.0.1 → wasmtime-jit-icache-coherence-13.0.0}/src/libc.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-12.0.1 → wasmtime-jit-icache-coherence-13.0.0}/src/miri.rs +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-12.0.1 → wasmtime-jit-icache-coherence-13.0.0}/src/win.rs +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-runtime-13.0.0}/LICENSE +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/build.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/component/libcalls.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/component/resources.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/component.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/cow.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/debug_builtins.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/export.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/externref.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/helpers.c +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/imports.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/instance/allocator/pooling/unix.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/instance/allocator/pooling/windows.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/mmap/miri.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/mmap/unix.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/mmap/windows.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/mmap.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/mmap_vec.rs +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/module_id.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/send_sync_ptr.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/store_box.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/trampolines/aarch64.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/trampolines/riscv64.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/trampolines/s390x.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/trampolines/x86_64.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/trampolines.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/backtrace/s390x.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/backtrace.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/coredump.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/unix.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/windows.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/vmcontext/vm_host_func_context.rs +0 -0
  1822. /data/ext/cargo-vendor/{wast-63.0.0 → wasmtime-types-13.0.0}/LICENSE +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-types-12.0.1 → wasmtime-types-13.0.0}/src/error.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-versioned-export-macros-12.0.1 → wasmtime-versioned-export-macros-13.0.0}/src/lib.rs +0 -0
  1825. /data/ext/cargo-vendor/{wat-1.0.70 → wasmtime-wasi-13.0.0}/LICENSE +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/README.md +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/build.rs +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/src/preview2/clocks/host.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/src/preview2/clocks.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/src/preview2/error.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1/src/preview2/preview2 → wasmtime-wasi-13.0.0/src/preview2/host}/random.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/src/preview2/poll.rs +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/src/preview2/random.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1/wit/deps/wasi-cli-base → wasmtime-wasi-13.0.0/wit/deps/cli}/stdio.wit +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/clocks/monotonic-clock.wit +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/clocks/timezone.wit +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/clocks/wall-clock.wit +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/http/incoming-handler.wit +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/http/outgoing-handler.wit +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/poll/poll.wit +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/random/insecure-seed.wit +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/random/insecure.wit +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/random/random.wit +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/sockets/instance-network.wit +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/witx/typenames.witx +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/witx/wasi_snapshot_preview1.witx +0 -0
  1847. /data/ext/cargo-vendor/{file-per-thread-logger-0.2.0 → wasmtime-winch-13.0.0}/LICENSE +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-winch-12.0.1 → wasmtime-winch-13.0.0}/src/builder.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-winch-12.0.1 → wasmtime-winch-13.0.0}/src/compiler.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-winch-12.0.1 → wasmtime-winch-13.0.0}/src/lib.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-12.0.1 → wasmtime-wit-bindgen-13.0.0}/src/source.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-12.0.1 → wast-65.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/README.md +0 -0
  1854. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/alias.rs +0 -0
  1855. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/component.rs +0 -0
  1856. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/custom.rs +0 -0
  1857. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/export.rs +0 -0
  1858. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/func.rs +0 -0
  1859. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/import.rs +0 -0
  1860. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/instance.rs +0 -0
  1861. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/item_ref.rs +0 -0
  1862. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/module.rs +0 -0
  1863. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component.rs +0 -0
  1864. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/custom.rs +0 -0
  1865. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/export.rs +0 -0
  1866. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/func.rs +0 -0
  1867. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/global.rs +0 -0
  1868. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/import.rs +0 -0
  1869. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/memory.rs +0 -0
  1870. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/module.rs +0 -0
  1871. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/resolve/deinline_import_export.rs +0 -0
  1872. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/resolve/mod.rs +0 -0
  1873. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/resolve/names.rs +0 -0
  1874. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/resolve/types.rs +0 -0
  1875. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/tag.rs +0 -0
  1876. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core.rs +0 -0
  1877. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/encode.rs +0 -0
  1878. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/error.rs +0 -0
  1879. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/gensym.rs +0 -0
  1880. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/lexer.rs +0 -0
  1881. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/names.rs +0 -0
  1882. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/parser.rs +0 -0
  1883. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/token.rs +0 -0
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  2009. /data/ext/cargo-vendor/{wiggle-12.0.1 → wiggle-13.0.0}/src/wasmtime.rs +0 -0
  2010. /data/ext/cargo-vendor/{wiggle-generate-12.0.1 → wiggle-generate-13.0.0}/README.md +0 -0
  2011. /data/ext/cargo-vendor/{wiggle-generate-12.0.1 → wiggle-generate-13.0.0}/src/codegen_settings.rs +0 -0
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  2017. /data/ext/cargo-vendor/{wiggle-generate-12.0.1 → wiggle-generate-13.0.0}/src/types/error.rs +0 -0
  2018. /data/ext/cargo-vendor/{wiggle-generate-12.0.1 → wiggle-generate-13.0.0}/src/types/flags.rs +0 -0
  2019. /data/ext/cargo-vendor/{wiggle-generate-12.0.1 → wiggle-generate-13.0.0}/src/types/handle.rs +0 -0
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  2022. /data/ext/cargo-vendor/{wiggle-macro-12.0.1 → wiggle-macro-13.0.0}/src/lib.rs +0 -0
  2023. /data/ext/cargo-vendor/{wasmtime-winch-12.0.1 → winch-codegen-0.11.0}/LICENSE +0 -0
  2024. /data/ext/cargo-vendor/{winch-codegen-0.10.1 → winch-codegen-0.11.0}/build.rs +0 -0
  2025. /data/ext/cargo-vendor/{winch-codegen-0.10.1 → winch-codegen-0.11.0}/src/abi/local.rs +0 -0
  2026. /data/ext/cargo-vendor/{winch-codegen-0.10.1 → winch-codegen-0.11.0}/src/codegen/env.rs +0 -0
  2027. /data/ext/cargo-vendor/{winch-codegen-0.10.1 → winch-codegen-0.11.0}/src/frame/mod.rs +0 -0
  2028. /data/ext/cargo-vendor/{winch-codegen-0.10.1 → winch-codegen-0.11.0}/src/isa/aarch64/mod.rs +0 -0
  2029. /data/ext/cargo-vendor/{winch-codegen-0.10.1 → winch-codegen-0.11.0}/src/isa/mod.rs +0 -0
  2030. /data/ext/cargo-vendor/{winch-codegen-0.10.1 → winch-codegen-0.11.0}/src/lib.rs +0 -0
  2031. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/README.md +0 -0
  2032. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/src/ast/toposort.rs +0 -0
  2033. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/comments.wit +0 -0
  2034. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/complex-include/deps/bar/root.wit +0 -0
  2035. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/complex-include/deps/baz/root.wit +0 -0
  2036. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/complex-include/root.wit +0 -0
  2037. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/cross-package-resource/deps/foo/foo.wit +0 -0
  2038. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/cross-package-resource/foo.wit +0 -0
  2039. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/diamond1/deps/dep1/types.wit +0 -0
  2040. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/diamond1/deps/dep2/types.wit +0 -0
  2041. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/diamond1/join.wit +0 -0
  2042. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/disambiguate-diamond/shared1.wit +0 -0
  2043. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/disambiguate-diamond/shared2.wit +0 -0
  2044. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/disambiguate-diamond/world.wit +0 -0
  2045. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/embedded.wit.md +0 -0
  2046. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/empty.wit +0 -0
  2047. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/deps/another-pkg/other-doc.wit +0 -0
  2048. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/deps/corp/saas.wit +0 -0
  2049. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/deps/different-pkg/the-doc.wit +0 -0
  2050. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/deps/foreign-pkg/the-doc.wit +0 -0
  2051. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/deps/some-pkg/some-doc.wit +0 -0
  2052. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/deps/wasi/clocks.wit +0 -0
  2053. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/deps/wasi/filesystem.wit +0 -0
  2054. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/root.wit +0 -0
  2055. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/another-pkg/other-doc.wit +0 -0
  2056. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/corp/saas.wit +0 -0
  2057. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/different-pkg/the-doc.wit +0 -0
  2058. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/foreign-pkg/the-doc.wit +0 -0
  2059. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/some-pkg/some-doc.wit +0 -0
  2060. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/wasi/clocks.wit +0 -0
  2061. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/wasi/filesystem.wit +0 -0
  2062. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/wasi/wasi.wit +0 -0
  2063. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/root.wit +0 -0
  2064. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/functions.wit +0 -0
  2065. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/ignore-files-deps/deps/bar/types.wit +0 -0
  2066. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/ignore-files-deps/deps/ignore-me.txt +0 -0
  2067. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/ignore-files-deps/world.wit +0 -0
  2068. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/include-reps.wit +0 -0
  2069. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/kebab-name-include-with.wit +0 -0
  2070. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/many-names/a.wit +0 -0
  2071. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/many-names/b.wit +0 -0
  2072. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/multi-file/bar.wit +0 -0
  2073. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/multi-file/cycle-a.wit +0 -0
  2074. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/multi-file/cycle-b.wit +0 -0
  2075. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/multi-file/foo.wit +0 -0
  2076. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/name-both-resource-and-type/deps/dep/foo.wit +0 -0
  2077. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/name-both-resource-and-type/foo.wit +0 -0
  2078. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/package-syntax1.wit +0 -0
  2079. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/package-syntax3.wit +0 -0
  2080. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/package-syntax4.wit +0 -0
  2081. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  2082. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/alias-no-type.wit.result +0 -0
  2083. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/async.wit.result +0 -0
  2084. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/async1.wit.result +0 -0
  2085. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-function.wit +0 -0
  2086. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-function.wit.result +0 -0
  2087. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-function2.wit +0 -0
  2088. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-function2.wit.result +0 -0
  2089. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-include1.wit +0 -0
  2090. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-include1.wit.result +0 -0
  2091. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-include2.wit +0 -0
  2092. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-include2.wit.result +0 -0
  2093. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-include3.wit +0 -0
  2094. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-include3.wit.result +0 -0
  2095. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-list.wit +0 -0
  2096. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  2097. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg1/root.wit +0 -0
  2098. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg1.wit.result +0 -0
  2099. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg2/deps/bar/empty.wit +0 -0
  2100. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg2/root.wit +0 -0
  2101. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg2.wit.result +0 -0
  2102. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg3/deps/bar/baz.wit +0 -0
  2103. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg3/root.wit +0 -0
  2104. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg3.wit.result +0 -0
  2105. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg4/deps/bar/baz.wit +0 -0
  2106. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg4/root.wit +0 -0
  2107. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg4.wit.result +0 -0
  2108. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg5/deps/bar/baz.wit +0 -0
  2109. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg5/root.wit +0 -0
  2110. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg5.wit.result +0 -0
  2111. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg6/deps/bar/baz.wit +0 -0
  2112. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg6/root.wit +0 -0
  2113. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg6.wit.result +0 -0
  2114. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource1.wit +0 -0
  2115. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource1.wit.result +0 -0
  2116. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource10.wit +0 -0
  2117. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource10.wit.result +0 -0
  2118. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource11.wit +0 -0
  2119. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource11.wit.result +0 -0
  2120. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource12.wit +0 -0
  2121. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource12.wit.result +0 -0
  2122. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource13.wit +0 -0
  2123. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource13.wit.result +0 -0
  2124. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource14.wit +0 -0
  2125. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource14.wit.result +0 -0
  2126. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource15/deps/foo/foo.wit +0 -0
  2127. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource15/foo.wit +0 -0
  2128. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource15.wit.result +0 -0
  2129. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource2.wit +0 -0
  2130. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource2.wit.result +0 -0
  2131. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource3.wit +0 -0
  2132. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource3.wit.result +0 -0
  2133. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource4.wit +0 -0
  2134. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource4.wit.result +0 -0
  2135. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource5.wit +0 -0
  2136. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource5.wit.result +0 -0
  2137. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource6.wit +0 -0
  2138. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource6.wit.result +0 -0
  2139. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource7.wit +0 -0
  2140. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource7.wit.result +0 -0
  2141. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource8.wit +0 -0
  2142. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource8.wit.result +0 -0
  2143. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource9.wit +0 -0
  2144. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource9.wit.result +0 -0
  2145. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-world-type1.wit +0 -0
  2146. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-world-type1.wit.result +0 -0
  2147. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/conflicting-package/a.wit +0 -0
  2148. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/conflicting-package/b.wit +0 -0
  2149. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/conflicting-package.wit.result +0 -0
  2150. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle.wit +0 -0
  2151. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle.wit.result +0 -0
  2152. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle2.wit +0 -0
  2153. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle2.wit.result +0 -0
  2154. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle3.wit +0 -0
  2155. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle3.wit.result +0 -0
  2156. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle4.wit +0 -0
  2157. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle4.wit.result +0 -0
  2158. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle5.wit +0 -0
  2159. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle5.wit.result +0 -0
  2160. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/dangling-type.wit +0 -0
  2161. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  2162. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-functions.wit +0 -0
  2163. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-functions.wit.result +0 -0
  2164. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-interface.wit +0 -0
  2165. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-interface.wit.result +0 -0
  2166. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-interface2/foo.wit +0 -0
  2167. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-interface2/foo2.wit +0 -0
  2168. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-interface2.wit.result +0 -0
  2169. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-type.wit +0 -0
  2170. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-type.wit.result +0 -0
  2171. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/empty-enum.wit +0 -0
  2172. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/empty-enum.wit.result +0 -0
  2173. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/empty-variant1.wit +0 -0
  2174. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/empty-variant1.wit.result +0 -0
  2175. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/export-twice.wit +0 -0
  2176. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/export-twice.wit.result +0 -0
  2177. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export1.wit +0 -0
  2178. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export1.wit.result +0 -0
  2179. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export2.wit +0 -0
  2180. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export2.wit.result +0 -0
  2181. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export3.wit +0 -0
  2182. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export3.wit.result +0 -0
  2183. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export4.wit +0 -0
  2184. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export4.wit.result +0 -0
  2185. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export5.wit +0 -0
  2186. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export5.wit.result +0 -0
  2187. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-export-overlap1.wit +0 -0
  2188. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-export-overlap1.wit.result +0 -0
  2189. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-export-overlap2.wit +0 -0
  2190. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-export-overlap2.wit.result +0 -0
  2191. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-twice.wit +0 -0
  2192. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-twice.wit.result +0 -0
  2193. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-cycle.wit +0 -0
  2194. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-cycle.wit.result +0 -0
  2195. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-foreign/deps/bar/empty.wit +0 -0
  2196. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-foreign/root.wit +0 -0
  2197. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-foreign.wit.result +0 -0
  2198. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-with-id.wit +0 -0
  2199. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-with-id.wit.result +0 -0
  2200. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-with-on-id.wit +0 -0
  2201. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-with-on-id.wit.result +0 -0
  2202. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-md.md +0 -0
  2203. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-md.wit.result +0 -0
  2204. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  2205. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  2206. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-type-reference.wit +0 -0
  2207. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-type-reference.wit.result +0 -0
  2208. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-type-reference2.wit +0 -0
  2209. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-type-reference2.wit.result +0 -0
  2210. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/kebab-name-include-not-found.wit +0 -0
  2211. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/kebab-name-include-not-found.wit.result +0 -0
  2212. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/kebab-name-include.wit +0 -0
  2213. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/kebab-name-include.wit.result +0 -0
  2214. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/keyword.wit +0 -0
  2215. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/keyword.wit.result +0 -0
  2216. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/missing-package.wit +0 -0
  2217. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/missing-package.wit.result +0 -0
  2218. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/no-access-to-sibling-use/bar.wit +0 -0
  2219. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/no-access-to-sibling-use/foo.wit +0 -0
  2220. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/no-access-to-sibling-use.wit.result +0 -0
  2221. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/non-existance-world-include/deps/bar/baz.wit +0 -0
  2222. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/non-existance-world-include/root.wit +0 -0
  2223. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/non-existance-world-include.wit.result +0 -0
  2224. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/pkg-cycle/deps/a1/root.wit +0 -0
  2225. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/pkg-cycle/root.wit +0 -0
  2226. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/pkg-cycle.wit.result +0 -0
  2227. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/pkg-cycle2/deps/a1/root.wit +0 -0
  2228. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/pkg-cycle2/deps/a2/root.wit +0 -0
  2229. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/pkg-cycle2/root.wit +0 -0
  2230. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/pkg-cycle2.wit.result +0 -0
  2231. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/type-and-resource-same-name/deps/dep/foo.wit +0 -0
  2232. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/type-and-resource-same-name/foo.wit +0 -0
  2233. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/type-and-resource-same-name.wit.result +0 -0
  2234. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/undefined-typed.wit +0 -0
  2235. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/undefined-typed.wit.result +0 -0
  2236. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/union-fuzz-2.wit +0 -0
  2237. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/union-fuzz-2.wit.result +0 -0
  2238. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unknown-interface.wit +0 -0
  2239. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unknown-interface.wit.result +0 -0
  2240. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface1.wit +0 -0
  2241. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface1.wit.result +0 -0
  2242. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface2.wit +0 -0
  2243. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface2.wit.result +0 -0
  2244. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface3.wit +0 -0
  2245. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface3.wit.result +0 -0
  2246. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface4.wit +0 -0
  2247. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface4.wit.result +0 -0
  2248. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use1.wit +0 -0
  2249. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use1.wit.result +0 -0
  2250. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use10/bar.wit +0 -0
  2251. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  2252. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use10.wit.result +0 -0
  2253. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use2.wit +0 -0
  2254. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use2.wit.result +0 -0
  2255. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use3.wit +0 -0
  2256. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use3.wit.result +0 -0
  2257. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use7.wit +0 -0
  2258. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use7.wit.result +0 -0
  2259. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use8.wit +0 -0
  2260. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use8.wit.result +0 -0
  2261. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use9.wit +0 -0
  2262. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use9.wit.result +0 -0
  2263. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
  2264. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-and-include-world/deps/bar/baz.wit +0 -0
  2265. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-and-include-world/root.wit +0 -0
  2266. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-and-include-world.wit.result +0 -0
  2267. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict.wit +0 -0
  2268. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict.wit.result +0 -0
  2269. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict2.wit +0 -0
  2270. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict2.wit.result +0 -0
  2271. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict3.wit +0 -0
  2272. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict3.wit.result +0 -0
  2273. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-cycle1.wit +0 -0
  2274. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-cycle1.wit.result +0 -0
  2275. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-cycle4.wit +0 -0
  2276. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-cycle4.wit.result +0 -0
  2277. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-shadow1.wit +0 -0
  2278. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-shadow1.wit.result +0 -0
  2279. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-world/deps/bar/baz.wit +0 -0
  2280. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-world/root.wit +0 -0
  2281. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-world.wit.result +0 -0
  2282. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-interface-clash.wit +0 -0
  2283. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-interface-clash.wit.result +0 -0
  2284. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-same-fields2.wit +0 -0
  2285. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-same-fields2.wit.result +0 -0
  2286. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-same-fields3.wit +0 -0
  2287. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-same-fields3.wit.result +0 -0
  2288. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-top-level-func.wit +0 -0
  2289. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-top-level-func.wit.result +0 -0
  2290. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-top-level-func2.wit +0 -0
  2291. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-top-level-func2.wit.result +0 -0
  2292. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-empty.wit +0 -0
  2293. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-multiple-returns-borrow.wit +0 -0
  2294. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-multiple-returns-own.wit +0 -0
  2295. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-multiple.wit +0 -0
  2296. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-return-borrow.wit +0 -0
  2297. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-return-own.wit +0 -0
  2298. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources.wit +0 -0
  2299. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources1.wit +0 -0
  2300. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/shared-types.wit +0 -0
  2301. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/stress-export-elaborate.wit +0 -0
  2302. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/type-then-eof.wit +0 -0
  2303. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/union-fuzz-1.wit +0 -0
  2304. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/use-chain.wit +0 -0
  2305. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/use.wit +0 -0
  2306. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/versions/deps/a1/foo.wit +0 -0
  2307. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/versions/deps/a2/foo.wit +0 -0
  2308. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/versions/foo.wit +0 -0
  2309. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/wasi.wit +0 -0
  2310. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/world-iface-no-collide.wit +0 -0
  2311. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/world-implicit-import1.wit +0 -0
  2312. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/world-implicit-import2.wit +0 -0
  2313. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/world-implicit-import3.wit +0 -0
  2314. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/world-same-fields4.wit +0 -0
  2315. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/world-top-level-funcs.wit +0 -0
  2316. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/world-top-level-resources.wit +0 -0
  2317. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/worlds-union-dedup.wit +0 -0
  2318. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/worlds-with-types.wit +0 -0
@@ -1,1650 +0,0 @@
1
- ;; Represents the possible widths of an element when used in an operation.
2
- (type VecElementWidth (enum
3
- (E8)
4
- (E16)
5
- (E32)
6
- (E64)
7
- ))
8
-
9
- ;; Vector Register Group Multiplier (LMUL)
10
- ;;
11
- ;; The LMUL setting specifies how we should group registers together. LMUL can
12
- ;; also be a fractional value, reducing the number of bits used in a single
13
- ;; vector register. Fractional LMUL is used to increase the number of effective
14
- ;; usable vector register groups when operating on mixed-width values.
15
- (type VecLmul (enum
16
- (LmulF8)
17
- (LmulF4)
18
- (LmulF2)
19
- (Lmul1)
20
- (Lmul2)
21
- (Lmul4)
22
- (Lmul8)
23
- ))
24
-
25
- ;; Tail Mode
26
- ;;
27
- ;; The tail mode specifies how the tail elements of a vector register are handled.
28
- (type VecTailMode (enum
29
- ;; Tail Agnostic means that the tail elements are left in an undefined state.
30
- (Agnostic)
31
- ;; Tail Undisturbed means that the tail elements are left in their original values.
32
- (Undisturbed)
33
- ))
34
-
35
- ;; Mask Mode
36
- ;;
37
- ;; The mask mode specifies how the masked elements of a vector register are handled.
38
- (type VecMaskMode (enum
39
- ;; Mask Agnostic means that the masked out elements are left in an undefined state.
40
- (Agnostic)
41
- ;; Mask Undisturbed means that the masked out elements are left in their original values.
42
- (Undisturbed)
43
- ))
44
-
45
- ;; Application Vector Length (AVL)
46
- ;;
47
- ;; This setting specifies the number of elements that are going to be processed
48
- ;; in a single instruction. Note: We may end up processing fewer elements than
49
- ;; the AVL setting, if they don't fit in a single register.
50
- (type VecAvl (enum
51
- ;; Static AVL emits a `vsetivli` that uses a constant value
52
- (Static (size UImm5))
53
- ;; TODO: Add a dynamic, register based AVL mode when we are able to properly test it
54
- ))
55
-
56
- (type VType (primitive VType))
57
- (type VState (primitive VState))
58
-
59
-
60
- ;; Vector Opcode Category
61
- ;;
62
- ;; These categories are used to determine the type of operands that are allowed in the
63
- ;; instruction.
64
- (type VecOpCategory (enum
65
- (OPIVV)
66
- (OPFVV)
67
- (OPMVV)
68
- (OPIVI)
69
- (OPIVX)
70
- (OPFVF)
71
- (OPMVX)
72
- (OPCFG)
73
- ))
74
-
75
- ;; Vector Opcode Masking
76
- ;;
77
- ;; When masked, the instruction will only operate on the elements that are dictated by
78
- ;; the mask register. Currently this is always fixed to v0.
79
- (type VecOpMasking (enum
80
- (Enabled (reg Reg))
81
- (Disabled)
82
- ))
83
-
84
- (decl pure masked (VReg) VecOpMasking)
85
- (rule (masked reg) (VecOpMasking.Enabled reg))
86
-
87
- (decl pure unmasked () VecOpMasking)
88
- (rule (unmasked) (VecOpMasking.Disabled))
89
-
90
- ;; Register to Register ALU Ops
91
- (type VecAluOpRRR (enum
92
- ;; Vector-Vector Opcodes
93
- (VaddVV)
94
- (VsaddVV)
95
- (VsadduVV)
96
- (VwaddVV)
97
- (VwaddWV)
98
- (VwadduVV)
99
- (VwadduWV)
100
- (VsubVV)
101
- (VwsubVV)
102
- (VwsubWV)
103
- (VwsubuVV)
104
- (VwsubuWV)
105
- (VssubVV)
106
- (VssubuVV)
107
- (VmulVV)
108
- (VmulhVV)
109
- (VmulhuVV)
110
- (VsmulVV)
111
- (VsllVV)
112
- (VsrlVV)
113
- (VsraVV)
114
- (VandVV)
115
- (VorVV)
116
- (VxorVV)
117
- (VmaxVV)
118
- (VmaxuVV)
119
- (VminVV)
120
- (VminuVV)
121
- (VfaddVV)
122
- (VfsubVV)
123
- (VfmulVV)
124
- (VfdivVV)
125
- (VfminVV)
126
- (VfmaxVV)
127
- (VfsgnjVV)
128
- (VfsgnjnVV)
129
- (VfsgnjxVV)
130
- (VmergeVVM)
131
- (VredmaxuVS)
132
- (VredminuVS)
133
- (VrgatherVV)
134
- (VcompressVM)
135
- (VmseqVV)
136
- (VmsneVV)
137
- (VmsltuVV)
138
- (VmsltVV)
139
- (VmsleuVV)
140
- (VmsleVV)
141
- (VmfeqVV)
142
- (VmfneVV)
143
- (VmfltVV)
144
- (VmfleVV)
145
- (VmandMM)
146
- (VmorMM)
147
- (VmnandMM)
148
- (VmnorMM)
149
-
150
-
151
- ;; Vector-Scalar Opcodes
152
- (VaddVX)
153
- (VsaddVX)
154
- (VsadduVX)
155
- (VwaddVX)
156
- (VwaddWX)
157
- (VwadduVX)
158
- (VwadduWX)
159
- (VsubVX)
160
- (VrsubVX)
161
- (VwsubVX)
162
- (VwsubWX)
163
- (VwsubuVX)
164
- (VwsubuWX)
165
- (VssubVX)
166
- (VssubuVX)
167
- (VmulVX)
168
- (VmulhVX)
169
- (VmulhuVX)
170
- (VsmulVX)
171
- (VsllVX)
172
- (VsrlVX)
173
- (VsraVX)
174
- (VandVX)
175
- (VorVX)
176
- (VxorVX)
177
- (VmaxVX)
178
- (VmaxuVX)
179
- (VminVX)
180
- (VminuVX)
181
- (VslidedownVX)
182
- (VfaddVF)
183
- (VfsubVF)
184
- (VfrsubVF)
185
- (VfmulVF)
186
- (VfdivVF)
187
- (VfsgnjVF)
188
- (VfrdivVF)
189
- (VmergeVXM)
190
- (VfmergeVFM)
191
- (VrgatherVX)
192
- (VmseqVX)
193
- (VmsneVX)
194
- (VmsltuVX)
195
- (VmsltVX)
196
- (VmsleuVX)
197
- (VmsleVX)
198
- (VmsgtuVX)
199
- (VmsgtVX)
200
- (VmfeqVF)
201
- (VmfneVF)
202
- (VmfltVF)
203
- (VmfleVF)
204
- (VmfgtVF)
205
- (VmfgeVF)
206
- ))
207
-
208
-
209
-
210
- ;; Register-Imm ALU Ops that modify the destination register
211
- (type VecAluOpRRRImm5 (enum
212
- (VslideupVI)
213
- ))
214
-
215
- ;; Register-Imm ALU Ops
216
- (type VecAluOpRRImm5 (enum
217
- ;; Regular VI Opcodes
218
- (VaddVI)
219
- (VsaddVI)
220
- (VsadduVI)
221
- (VrsubVI)
222
- (VsllVI)
223
- (VsrlVI)
224
- (VsraVI)
225
- (VandVI)
226
- (VorVI)
227
- (VxorVI)
228
- (VssrlVI)
229
- (VslidedownVI)
230
- (VmergeVIM)
231
- (VrgatherVI)
232
- ;; This opcode represents multiple instructions `vmv1r`/`vmv2r`/`vmv4r`/etc...
233
- ;; The immediate field specifies how many registers should be copied.
234
- (VmvrV)
235
- (VnclipWI)
236
- (VnclipuWI)
237
- (VmseqVI)
238
- (VmsneVI)
239
- (VmsleuVI)
240
- (VmsleVI)
241
- (VmsgtuVI)
242
- (VmsgtVI)
243
- ))
244
-
245
- ;; Imm only ALU Ops
246
- (type VecAluOpRImm5 (enum
247
- (VmvVI)
248
- ))
249
-
250
- ;; These are all of the special cases that have weird encodings. They are all
251
- ;; single source, single destination instructions, and usually use one of
252
- ;; the two source registers as auxiliary encoding space.
253
- (type VecAluOpRR (enum
254
- (VmvSX)
255
- (VmvXS)
256
- (VfmvSF)
257
- (VfmvFS)
258
- ;; vmv.v* is special in that vs2 must be v0 (and is ignored) otherwise the instruction is illegal.
259
- (VmvVV)
260
- (VmvVX)
261
- (VfmvVF)
262
- (VfsqrtV)
263
- (VsextVF2)
264
- (VsextVF4)
265
- (VsextVF8)
266
- (VzextVF2)
267
- (VzextVF4)
268
- (VzextVF8)
269
- ))
270
-
271
- ;; Returns the canonical destination type for a VecAluOpRRImm5.
272
- (decl pure vec_alu_rr_dst_type (VecAluOpRR) Type)
273
- (extern constructor vec_alu_rr_dst_type vec_alu_rr_dst_type)
274
-
275
-
276
- ;; Vector Addressing Mode
277
- (type VecAMode (enum
278
- ;; Vector unit-stride operations access elements stored contiguously in memory
279
- ;; starting from the base effective address.
280
- (UnitStride
281
- (base AMode))
282
- ;; TODO: Constant Stride
283
- ;; TODO: Indexed Operations
284
- ))
285
-
286
-
287
- ;; Builds a static VState matching a SIMD type.
288
- ;; The VState is guaranteed to be static with AVL set to the number of lanes.
289
- ;; Element size is set to the size of the type.
290
- ;; LMUL is set to 1.
291
- ;; Tail mode is set to agnostic.
292
- ;; Mask mode is set to agnostic.
293
- (decl pure vstate_from_type (Type) VState)
294
- (extern constructor vstate_from_type vstate_from_type)
295
- (convert Type VState vstate_from_type)
296
-
297
- ;; Alters the LMUL of a VState to mf2
298
- (decl pure vstate_mf2 (VState) VState)
299
- (extern constructor vstate_mf2 vstate_mf2)
300
-
301
- ;; Extracts an element width from a SIMD type.
302
- (decl pure element_width_from_type (Type) VecElementWidth)
303
- (rule (element_width_from_type ty)
304
- (if-let $I8 (lane_type ty))
305
- (VecElementWidth.E8))
306
- (rule (element_width_from_type ty)
307
- (if-let $I16 (lane_type ty))
308
- (VecElementWidth.E16))
309
- (rule (element_width_from_type ty)
310
- (if-let $I32 (lane_type ty))
311
- (VecElementWidth.E32))
312
- (rule (element_width_from_type ty)
313
- (if-let $F32 (lane_type ty))
314
- (VecElementWidth.E32))
315
- (rule (element_width_from_type ty)
316
- (if-let $I64 (lane_type ty))
317
- (VecElementWidth.E64))
318
- (rule (element_width_from_type ty)
319
- (if-let $F64 (lane_type ty))
320
- (VecElementWidth.E64))
321
-
322
- (decl pure min_vec_reg_size () u64)
323
- (extern constructor min_vec_reg_size min_vec_reg_size)
324
-
325
- ;; An extractor that matches any type that is known to fit in a single vector
326
- ;; register.
327
- (decl ty_vec_fits_in_register (Type) Type)
328
- (extern extractor ty_vec_fits_in_register ty_vec_fits_in_register)
329
-
330
- ;;;; Instruction Helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
331
-
332
- ;; As noted in the RISC-V Vector Extension Specification, rs2 is the first
333
- ;; source register and rs1 is the second source register. This is the opposite
334
- ;; of the usual RISC-V register order.
335
- ;; See Section 10.1 of the RISC-V Vector Extension Specification.
336
-
337
-
338
- ;; Helper for emitting `MInst.VecAluRRRImm5` instructions.
339
- ;; These instructions modify the destination register.
340
- (decl vec_alu_rrr_imm5 (VecAluOpRRRImm5 VReg VReg Imm5 VecOpMasking VState) VReg)
341
- (rule (vec_alu_rrr_imm5 op vd_src vs2 imm mask vstate)
342
- (let ((vd WritableVReg (temp_writable_vreg))
343
- (_ Unit (emit (MInst.VecAluRRRImm5 op vd vd_src vs2 imm mask vstate))))
344
- vd))
345
-
346
- ;; Helper for emitting `MInst.VecAluRRRImm5` instructions where the immediate
347
- ;; is zero extended instead of sign extended.
348
- (decl vec_alu_rrr_uimm5 (VecAluOpRRRImm5 VReg VReg UImm5 VecOpMasking VState) VReg)
349
- (rule (vec_alu_rrr_uimm5 op vd_src vs2 imm mask vstate)
350
- (vec_alu_rrr_imm5 op vd_src vs2 (uimm5_bitcast_to_imm5 imm) mask vstate))
351
-
352
- ;; Helper for emitting `MInst.VecAluRRR` instructions.
353
- (decl vec_alu_rrr (VecAluOpRRR Reg Reg VecOpMasking VState) Reg)
354
- (rule (vec_alu_rrr op vs2 vs1 mask vstate)
355
- (let ((vd WritableVReg (temp_writable_vreg))
356
- (_ Unit (emit (MInst.VecAluRRR op vd vs2 vs1 mask vstate))))
357
- vd))
358
-
359
- ;; Helper for emitting `MInst.VecAluRRImm5` instructions.
360
- (decl vec_alu_rr_imm5 (VecAluOpRRImm5 Reg Imm5 VecOpMasking VState) Reg)
361
- (rule (vec_alu_rr_imm5 op vs2 imm mask vstate)
362
- (let ((vd WritableVReg (temp_writable_vreg))
363
- (_ Unit (emit (MInst.VecAluRRImm5 op vd vs2 imm mask vstate))))
364
- vd))
365
-
366
- ;; Helper for emitting `MInst.VecAluRRImm5` instructions where the immediate
367
- ;; is zero extended instead of sign extended.
368
- (decl vec_alu_rr_uimm5 (VecAluOpRRImm5 Reg UImm5 VecOpMasking VState) Reg)
369
- (rule (vec_alu_rr_uimm5 op vs2 imm mask vstate)
370
- (vec_alu_rr_imm5 op vs2 (uimm5_bitcast_to_imm5 imm) mask vstate))
371
-
372
- ;; Helper for emitting `MInst.VecAluRRImm5` instructions that use the Imm5 as
373
- ;; auxiliary encoding space.
374
- (decl vec_alu_rr (VecAluOpRR Reg VecOpMasking VState) Reg)
375
- (rule (vec_alu_rr op vs mask vstate)
376
- (let ((vd WritableReg (temp_writable_reg (vec_alu_rr_dst_type op)))
377
- (_ Unit (emit (MInst.VecAluRR op vd vs mask vstate))))
378
- vd))
379
-
380
- ;; Helper for emitting `MInst.VecAluRImm5` instructions.
381
- (decl vec_alu_r_imm5 (VecAluOpRImm5 Imm5 VecOpMasking VState) Reg)
382
- (rule (vec_alu_r_imm5 op imm mask vstate)
383
- (let ((vd WritableVReg (temp_writable_vreg))
384
- (_ Unit (emit (MInst.VecAluRImm5 op vd imm mask vstate))))
385
- vd))
386
-
387
- ;; Helper for emitting `MInst.VecLoad` instructions.
388
- (decl vec_load (VecElementWidth VecAMode MemFlags VecOpMasking VState) Reg)
389
- (rule (vec_load eew from flags mask vstate)
390
- (let ((vd WritableVReg (temp_writable_vreg))
391
- (_ Unit (emit (MInst.VecLoad eew vd from flags mask vstate))))
392
- vd))
393
-
394
- ;; Helper for emitting `MInst.VecStore` instructions.
395
- (decl vec_store (VecElementWidth VecAMode VReg MemFlags VecOpMasking VState) InstOutput)
396
- (rule (vec_store eew to from flags mask vstate)
397
- (side_effect
398
- (SideEffectNoResult.Inst (MInst.VecStore eew to from flags mask vstate))))
399
-
400
- ;; Helper for emitting the `vadd.vv` instruction.
401
- (decl rv_vadd_vv (VReg VReg VecOpMasking VState) VReg)
402
- (rule (rv_vadd_vv vs2 vs1 mask vstate)
403
- (vec_alu_rrr (VecAluOpRRR.VaddVV) vs2 vs1 mask vstate))
404
-
405
- ;; Helper for emitting the `vadd.vx` instruction.
406
- (decl rv_vadd_vx (VReg XReg VecOpMasking VState) VReg)
407
- (rule (rv_vadd_vx vs2 vs1 mask vstate)
408
- (vec_alu_rrr (VecAluOpRRR.VaddVX) vs2 vs1 mask vstate))
409
-
410
- ;; Helper for emitting the `vadd.vi` instruction.
411
- (decl rv_vadd_vi (VReg Imm5 VecOpMasking VState) VReg)
412
- (rule (rv_vadd_vi vs2 imm mask vstate)
413
- (vec_alu_rr_imm5 (VecAluOpRRImm5.VaddVI) vs2 imm mask vstate))
414
-
415
- ;; Helper for emitting the `vsadd.vv` instruction.
416
- (decl rv_vsadd_vv (VReg VReg VecOpMasking VState) VReg)
417
- (rule (rv_vsadd_vv vs2 vs1 mask vstate)
418
- (vec_alu_rrr (VecAluOpRRR.VsaddVV) vs2 vs1 mask vstate))
419
-
420
- ;; Helper for emitting the `vsadd.vx` instruction.
421
- (decl rv_vsadd_vx (VReg XReg VecOpMasking VState) VReg)
422
- (rule (rv_vsadd_vx vs2 vs1 mask vstate)
423
- (vec_alu_rrr (VecAluOpRRR.VsaddVX) vs2 vs1 mask vstate))
424
-
425
- ;; Helper for emitting the `vsadd.vi` instruction.
426
- (decl rv_vsadd_vi (VReg Imm5 VecOpMasking VState) VReg)
427
- (rule (rv_vsadd_vi vs2 imm mask vstate)
428
- (vec_alu_rr_imm5 (VecAluOpRRImm5.VsaddVI) vs2 imm mask vstate))
429
-
430
- ;; Helper for emitting the `vsaddu.vv` instruction.
431
- (decl rv_vsaddu_vv (VReg VReg VecOpMasking VState) VReg)
432
- (rule (rv_vsaddu_vv vs2 vs1 mask vstate)
433
- (vec_alu_rrr (VecAluOpRRR.VsadduVV) vs2 vs1 mask vstate))
434
-
435
- ;; Helper for emitting the `vsaddu.vx` instruction.
436
- (decl rv_vsaddu_vx (VReg XReg VecOpMasking VState) VReg)
437
- (rule (rv_vsaddu_vx vs2 vs1 mask vstate)
438
- (vec_alu_rrr (VecAluOpRRR.VsadduVX) vs2 vs1 mask vstate))
439
-
440
- ;; Helper for emitting the `vsaddu.vi` instruction.
441
- (decl rv_vsaddu_vi (VReg Imm5 VecOpMasking VState) VReg)
442
- (rule (rv_vsaddu_vi vs2 imm mask vstate)
443
- (vec_alu_rr_imm5 (VecAluOpRRImm5.VsadduVI) vs2 imm mask vstate))
444
-
445
- ;; Helper for emitting the `vwadd.vv` instruction.
446
- ;;
447
- ;; Widening integer add, 2*SEW = SEW + SEW
448
- (decl rv_vwadd_vv (VReg VReg VecOpMasking VState) VReg)
449
- (rule (rv_vwadd_vv vs2 vs1 mask vstate)
450
- (vec_alu_rrr (VecAluOpRRR.VwaddVV) vs2 vs1 mask vstate))
451
-
452
- ;; Helper for emitting the `vwadd.vx` instruction.
453
- ;;
454
- ;; Widening integer add, 2*SEW = SEW + SEW
455
- (decl rv_vwadd_vx (VReg XReg VecOpMasking VState) VReg)
456
- (rule (rv_vwadd_vx vs2 vs1 mask vstate)
457
- (vec_alu_rrr (VecAluOpRRR.VwaddVX) vs2 vs1 mask vstate))
458
-
459
- ;; Helper for emitting the `vwadd.wv` instruction.
460
- ;;
461
- ;; Widening integer add, 2*SEW = 2*SEW + SEW
462
- (decl rv_vwadd_wv (VReg VReg VecOpMasking VState) VReg)
463
- (rule (rv_vwadd_wv vs2 vs1 mask vstate)
464
- (vec_alu_rrr (VecAluOpRRR.VwaddWV) vs2 vs1 mask vstate))
465
-
466
- ;; Helper for emitting the `vwadd.wx` instruction.
467
- ;;
468
- ;; Widening integer add, 2*SEW = 2*SEW + SEW
469
- (decl rv_vwadd_wx (VReg XReg VecOpMasking VState) VReg)
470
- (rule (rv_vwadd_wx vs2 vs1 mask vstate)
471
- (vec_alu_rrr (VecAluOpRRR.VwaddWX) vs2 vs1 mask vstate))
472
-
473
- ;; Helper for emitting the `vwaddu.vv` instruction.
474
- ;;
475
- ;; Widening unsigned integer add, 2*SEW = SEW + SEW
476
- (decl rv_vwaddu_vv (VReg VReg VecOpMasking VState) VReg)
477
- (rule (rv_vwaddu_vv vs2 vs1 mask vstate)
478
- (vec_alu_rrr (VecAluOpRRR.VwadduVV) vs2 vs1 mask vstate))
479
-
480
- ;; Helper for emitting the `vwaddu.vv` instruction.
481
- ;;
482
- ;; Widening unsigned integer add, 2*SEW = SEW + SEW
483
- (decl rv_vwaddu_vx (VReg XReg VecOpMasking VState) VReg)
484
- (rule (rv_vwaddu_vx vs2 vs1 mask vstate)
485
- (vec_alu_rrr (VecAluOpRRR.VwadduVX) vs2 vs1 mask vstate))
486
-
487
- ;; Helper for emitting the `vwaddu.wv` instruction.
488
- ;;
489
- ;; Widening integer add, 2*SEW = 2*SEW + SEW
490
- (decl rv_vwaddu_wv (VReg VReg VecOpMasking VState) VReg)
491
- (rule (rv_vwaddu_wv vs2 vs1 mask vstate)
492
- (vec_alu_rrr (VecAluOpRRR.VwadduWV) vs2 vs1 mask vstate))
493
-
494
- ;; Helper for emitting the `vwaddu.wx` instruction.
495
- ;;
496
- ;; Widening integer add, 2*SEW = 2*SEW + SEW
497
- (decl rv_vwaddu_wx (VReg XReg VecOpMasking VState) VReg)
498
- (rule (rv_vwaddu_wx vs2 vs1 mask vstate)
499
- (vec_alu_rrr (VecAluOpRRR.VwadduWX) vs2 vs1 mask vstate))
500
-
501
- ;; Helper for emitting the `vsub.vv` instruction.
502
- (decl rv_vsub_vv (VReg VReg VecOpMasking VState) VReg)
503
- (rule (rv_vsub_vv vs2 vs1 mask vstate)
504
- (vec_alu_rrr (VecAluOpRRR.VsubVV) vs2 vs1 mask vstate))
505
-
506
- ;; Helper for emitting the `vsub.vx` instruction.
507
- (decl rv_vsub_vx (VReg XReg VecOpMasking VState) VReg)
508
- (rule (rv_vsub_vx vs2 vs1 mask vstate)
509
- (vec_alu_rrr (VecAluOpRRR.VsubVX) vs2 vs1 mask vstate))
510
-
511
- ;; Helper for emitting the `vrsub.vx` instruction.
512
- (decl rv_vrsub_vx (VReg XReg VecOpMasking VState) VReg)
513
- (rule (rv_vrsub_vx vs2 vs1 mask vstate)
514
- (vec_alu_rrr (VecAluOpRRR.VrsubVX) vs2 vs1 mask vstate))
515
-
516
- ;; Helper for emitting the `vwsub.vv` instruction.
517
- ;;
518
- ;; Widening integer sub, 2*SEW = SEW + SEW
519
- (decl rv_vwsub_vv (VReg VReg VecOpMasking VState) VReg)
520
- (rule (rv_vwsub_vv vs2 vs1 mask vstate)
521
- (vec_alu_rrr (VecAluOpRRR.VwsubVV) vs2 vs1 mask vstate))
522
-
523
- ;; Helper for emitting the `vwsub.vx` instruction.
524
- ;;
525
- ;; Widening integer sub, 2*SEW = SEW + SEW
526
- (decl rv_vwsub_vx (VReg XReg VecOpMasking VState) VReg)
527
- (rule (rv_vwsub_vx vs2 vs1 mask vstate)
528
- (vec_alu_rrr (VecAluOpRRR.VwsubVX) vs2 vs1 mask vstate))
529
-
530
- ;; Helper for emitting the `vwsub.wv` instruction.
531
- ;;
532
- ;; Widening integer sub, 2*SEW = 2*SEW + SEW
533
- (decl rv_vwsub_wv (VReg VReg VecOpMasking VState) VReg)
534
- (rule (rv_vwsub_wv vs2 vs1 mask vstate)
535
- (vec_alu_rrr (VecAluOpRRR.VwsubWV) vs2 vs1 mask vstate))
536
-
537
- ;; Helper for emitting the `vwsub.wx` instruction.
538
- ;;
539
- ;; Widening integer sub, 2*SEW = 2*SEW + SEW
540
- (decl rv_vwsub_wx (VReg XReg VecOpMasking VState) VReg)
541
- (rule (rv_vwsub_wx vs2 vs1 mask vstate)
542
- (vec_alu_rrr (VecAluOpRRR.VwsubWX) vs2 vs1 mask vstate))
543
-
544
- ;; Helper for emitting the `vwsubu.vv` instruction.
545
- ;;
546
- ;; Widening unsigned integer sub, 2*SEW = SEW + SEW
547
- (decl rv_vwsubu_vv (VReg VReg VecOpMasking VState) VReg)
548
- (rule (rv_vwsubu_vv vs2 vs1 mask vstate)
549
- (vec_alu_rrr (VecAluOpRRR.VwsubuVV) vs2 vs1 mask vstate))
550
-
551
- ;; Helper for emitting the `vwsubu.vv` instruction.
552
- ;;
553
- ;; Widening unsigned integer sub, 2*SEW = SEW + SEW
554
- (decl rv_vwsubu_vx (VReg XReg VecOpMasking VState) VReg)
555
- (rule (rv_vwsubu_vx vs2 vs1 mask vstate)
556
- (vec_alu_rrr (VecAluOpRRR.VwsubuVX) vs2 vs1 mask vstate))
557
-
558
- ;; Helper for emitting the `vwsubu.wv` instruction.
559
- ;;
560
- ;; Widening integer sub, 2*SEW = 2*SEW + SEW
561
- (decl rv_vwsubu_wv (VReg VReg VecOpMasking VState) VReg)
562
- (rule (rv_vwsubu_wv vs2 vs1 mask vstate)
563
- (vec_alu_rrr (VecAluOpRRR.VwsubuWV) vs2 vs1 mask vstate))
564
-
565
- ;; Helper for emitting the `vwsubu.wx` instruction.
566
- ;;
567
- ;; Widening integer sub, 2*SEW = 2*SEW + SEW
568
- (decl rv_vwsubu_wx (VReg XReg VecOpMasking VState) VReg)
569
- (rule (rv_vwsubu_wx vs2 vs1 mask vstate)
570
- (vec_alu_rrr (VecAluOpRRR.VwsubuWX) vs2 vs1 mask vstate))
571
-
572
- ;; Helper for emitting the `vssub.vv` instruction.
573
- (decl rv_vssub_vv (VReg VReg VecOpMasking VState) VReg)
574
- (rule (rv_vssub_vv vs2 vs1 mask vstate)
575
- (vec_alu_rrr (VecAluOpRRR.VssubVV) vs2 vs1 mask vstate))
576
-
577
- ;; Helper for emitting the `vssub.vx` instruction.
578
- (decl rv_vssub_vx (VReg XReg VecOpMasking VState) VReg)
579
- (rule (rv_vssub_vx vs2 vs1 mask vstate)
580
- (vec_alu_rrr (VecAluOpRRR.VssubVX) vs2 vs1 mask vstate))
581
-
582
- ;; Helper for emitting the `vssubu.vv` instruction.
583
- (decl rv_vssubu_vv (VReg VReg VecOpMasking VState) VReg)
584
- (rule (rv_vssubu_vv vs2 vs1 mask vstate)
585
- (vec_alu_rrr (VecAluOpRRR.VssubuVV) vs2 vs1 mask vstate))
586
-
587
- ;; Helper for emitting the `vssubu.vx` instruction.
588
- (decl rv_vssubu_vx (VReg XReg VecOpMasking VState) VReg)
589
- (rule (rv_vssubu_vx vs2 vs1 mask vstate)
590
- (vec_alu_rrr (VecAluOpRRR.VssubuVX) vs2 vs1 mask vstate))
591
-
592
- ;; Helper for emitting the `vneg.v` pseudo-instruction.
593
- (decl rv_vneg_v (VReg VecOpMasking VState) VReg)
594
- (rule (rv_vneg_v vs2 mask vstate)
595
- (vec_alu_rrr (VecAluOpRRR.VrsubVX) vs2 (zero_reg) mask vstate))
596
-
597
- ;; Helper for emitting the `vrsub.vi` instruction.
598
- (decl rv_vrsub_vi (VReg Imm5 VecOpMasking VState) VReg)
599
- (rule (rv_vrsub_vi vs2 imm mask vstate)
600
- (vec_alu_rr_imm5 (VecAluOpRRImm5.VrsubVI) vs2 imm mask vstate))
601
-
602
- ;; Helper for emitting the `vmul.vv` instruction.
603
- (decl rv_vmul_vv (VReg VReg VecOpMasking VState) VReg)
604
- (rule (rv_vmul_vv vs2 vs1 mask vstate)
605
- (vec_alu_rrr (VecAluOpRRR.VmulVV) vs2 vs1 mask vstate))
606
-
607
- ;; Helper for emitting the `vmul.vx` instruction.
608
- (decl rv_vmul_vx (VReg XReg VecOpMasking VState) VReg)
609
- (rule (rv_vmul_vx vs2 vs1 mask vstate)
610
- (vec_alu_rrr (VecAluOpRRR.VmulVX) vs2 vs1 mask vstate))
611
-
612
- ;; Helper for emitting the `vmulh.vv` instruction.
613
- (decl rv_vmulh_vv (VReg VReg VecOpMasking VState) VReg)
614
- (rule (rv_vmulh_vv vs2 vs1 mask vstate)
615
- (vec_alu_rrr (VecAluOpRRR.VmulhVV) vs2 vs1 mask vstate))
616
-
617
- ;; Helper for emitting the `vmulh.vx` instruction.
618
- (decl rv_vmulh_vx (VReg XReg VecOpMasking VState) VReg)
619
- (rule (rv_vmulh_vx vs2 vs1 mask vstate)
620
- (vec_alu_rrr (VecAluOpRRR.VmulhVX) vs2 vs1 mask vstate))
621
-
622
- ;; Helper for emitting the `vmulhu.vv` instruction.
623
- (decl rv_vmulhu_vv (VReg VReg VecOpMasking VState) VReg)
624
- (rule (rv_vmulhu_vv vs2 vs1 mask vstate)
625
- (vec_alu_rrr (VecAluOpRRR.VmulhuVV) vs2 vs1 mask vstate))
626
-
627
- ;; Helper for emitting the `vmulhu.vx` instruction.
628
- (decl rv_vmulhu_vx (VReg XReg VecOpMasking VState) VReg)
629
- (rule (rv_vmulhu_vx vs2 vs1 mask vstate)
630
- (vec_alu_rrr (VecAluOpRRR.VmulhuVX) vs2 vs1 mask vstate))
631
-
632
- ;; Helper for emitting the `vsmul.vv` instruction.
633
- ;;
634
- ;; Signed saturating and rounding fractional multiply
635
- ;; # vd[i] = clip(roundoff_signed(vs2[i]*vs1[i], SEW-1))
636
- (decl rv_vsmul_vv (VReg VReg VecOpMasking VState) VReg)
637
- (rule (rv_vsmul_vv vs2 vs1 mask vstate)
638
- (vec_alu_rrr (VecAluOpRRR.VsmulVV) vs2 vs1 mask vstate))
639
-
640
- ;; Helper for emitting the `vsmul.vx` instruction.
641
- ;;
642
- ;; Signed saturating and rounding fractional multiply
643
- ;; # vd[i] = clip(roundoff_signed(vs2[i]*x[rs1], SEW-1))
644
- (decl rv_vsmul_vx (VReg XReg VecOpMasking VState) VReg)
645
- (rule (rv_vsmul_vx vs2 vs1 mask vstate)
646
- (vec_alu_rrr (VecAluOpRRR.VsmulVX) vs2 vs1 mask vstate))
647
-
648
- ;; Helper for emitting the `sll.vv` instruction.
649
- (decl rv_vsll_vv (VReg VReg VecOpMasking VState) VReg)
650
- (rule (rv_vsll_vv vs2 vs1 mask vstate)
651
- (vec_alu_rrr (VecAluOpRRR.VsllVV) vs2 vs1 mask vstate))
652
-
653
- ;; Helper for emitting the `sll.vx` instruction.
654
- (decl rv_vsll_vx (VReg XReg VecOpMasking VState) VReg)
655
- (rule (rv_vsll_vx vs2 vs1 mask vstate)
656
- (vec_alu_rrr (VecAluOpRRR.VsllVX) vs2 vs1 mask vstate))
657
-
658
- ;; Helper for emitting the `vsll.vi` instruction.
659
- (decl rv_vsll_vi (VReg UImm5 VecOpMasking VState) VReg)
660
- (rule (rv_vsll_vi vs2 imm mask vstate)
661
- (vec_alu_rr_uimm5 (VecAluOpRRImm5.VsllVI) vs2 imm mask vstate))
662
-
663
- ;; Helper for emitting the `srl.vv` instruction.
664
- (decl rv_vsrl_vv (VReg VReg VecOpMasking VState) VReg)
665
- (rule (rv_vsrl_vv vs2 vs1 mask vstate)
666
- (vec_alu_rrr (VecAluOpRRR.VsrlVV) vs2 vs1 mask vstate))
667
-
668
- ;; Helper for emitting the `srl.vx` instruction.
669
- (decl rv_vsrl_vx (VReg XReg VecOpMasking VState) VReg)
670
- (rule (rv_vsrl_vx vs2 vs1 mask vstate)
671
- (vec_alu_rrr (VecAluOpRRR.VsrlVX) vs2 vs1 mask vstate))
672
-
673
- ;; Helper for emitting the `vsrl.vi` instruction.
674
- (decl rv_vsrl_vi (VReg UImm5 VecOpMasking VState) VReg)
675
- (rule (rv_vsrl_vi vs2 imm mask vstate)
676
- (vec_alu_rr_uimm5 (VecAluOpRRImm5.VsrlVI) vs2 imm mask vstate))
677
-
678
- ;; Helper for emitting the `sra.vv` instruction.
679
- (decl rv_vsra_vv (VReg VReg VecOpMasking VState) VReg)
680
- (rule (rv_vsra_vv vs2 vs1 mask vstate)
681
- (vec_alu_rrr (VecAluOpRRR.VsraVV) vs2 vs1 mask vstate))
682
-
683
- ;; Helper for emitting the `sra.vx` instruction.
684
- (decl rv_vsra_vx (VReg XReg VecOpMasking VState) VReg)
685
- (rule (rv_vsra_vx vs2 vs1 mask vstate)
686
- (vec_alu_rrr (VecAluOpRRR.VsraVX) vs2 vs1 mask vstate))
687
-
688
- ;; Helper for emitting the `vsra.vi` instruction.
689
- (decl rv_vsra_vi (VReg UImm5 VecOpMasking VState) VReg)
690
- (rule (rv_vsra_vi vs2 imm mask vstate)
691
- (vec_alu_rr_uimm5 (VecAluOpRRImm5.VsraVI) vs2 imm mask vstate))
692
-
693
- ;; Helper for emitting the `vand.vv` instruction.
694
- (decl rv_vand_vv (VReg VReg VecOpMasking VState) VReg)
695
- (rule (rv_vand_vv vs2 vs1 mask vstate)
696
- (vec_alu_rrr (VecAluOpRRR.VandVV) vs2 vs1 mask vstate))
697
-
698
- ;; Helper for emitting the `vand.vx` instruction.
699
- (decl rv_vand_vx (VReg XReg VecOpMasking VState) VReg)
700
- (rule (rv_vand_vx vs2 vs1 mask vstate)
701
- (vec_alu_rrr (VecAluOpRRR.VandVX) vs2 vs1 mask vstate))
702
-
703
- ;; Helper for emitting the `vand.vi` instruction.
704
- (decl rv_vand_vi (VReg Imm5 VecOpMasking VState) VReg)
705
- (rule (rv_vand_vi vs2 imm mask vstate)
706
- (vec_alu_rr_imm5 (VecAluOpRRImm5.VandVI) vs2 imm mask vstate))
707
-
708
- ;; Helper for emitting the `vor.vv` instruction.
709
- (decl rv_vor_vv (VReg VReg VecOpMasking VState) VReg)
710
- (rule (rv_vor_vv vs2 vs1 mask vstate)
711
- (vec_alu_rrr (VecAluOpRRR.VorVV) vs2 vs1 mask vstate))
712
-
713
- ;; Helper for emitting the `vor.vx` instruction.
714
- (decl rv_vor_vx (VReg XReg VecOpMasking VState) VReg)
715
- (rule (rv_vor_vx vs2 vs1 mask vstate)
716
- (vec_alu_rrr (VecAluOpRRR.VorVX) vs2 vs1 mask vstate))
717
-
718
- ;; Helper for emitting the `vor.vi` instruction.
719
- (decl rv_vor_vi (VReg Imm5 VecOpMasking VState) VReg)
720
- (rule (rv_vor_vi vs2 imm mask vstate)
721
- (vec_alu_rr_imm5 (VecAluOpRRImm5.VorVI) vs2 imm mask vstate))
722
-
723
- ;; Helper for emitting the `vxor.vv` instruction.
724
- (decl rv_vxor_vv (VReg VReg VecOpMasking VState) VReg)
725
- (rule (rv_vxor_vv vs2 vs1 mask vstate)
726
- (vec_alu_rrr (VecAluOpRRR.VxorVV) vs2 vs1 mask vstate))
727
-
728
- ;; Helper for emitting the `vxor.vx` instruction.
729
- (decl rv_vxor_vx (VReg XReg VecOpMasking VState) VReg)
730
- (rule (rv_vxor_vx vs2 vs1 mask vstate)
731
- (vec_alu_rrr (VecAluOpRRR.VxorVX) vs2 vs1 mask vstate))
732
-
733
- ;; Helper for emitting the `vxor.vi` instruction.
734
- (decl rv_vxor_vi (VReg Imm5 VecOpMasking VState) VReg)
735
- (rule (rv_vxor_vi vs2 imm mask vstate)
736
- (vec_alu_rr_imm5 (VecAluOpRRImm5.VxorVI) vs2 imm mask vstate))
737
-
738
- ;; Helper for emitting the `vssrl.vi` instruction.
739
- ;;
740
- ;; vd[i] = (unsigned(vs2[i]) >> imm) + r
741
- ;;
742
- ;; `r` here is the rounding mode currently selected.
743
- (decl rv_vssrl_vi (VReg UImm5 VecOpMasking VState) VReg)
744
- (rule (rv_vssrl_vi vs2 imm mask vstate)
745
- (vec_alu_rr_uimm5 (VecAluOpRRImm5.VssrlVI) vs2 imm mask vstate))
746
-
747
- ;; Helper for emitting the `vnot.v` instruction.
748
- ;; This is just a mnemonic for `vxor.vi vd, vs, -1`
749
- (decl rv_vnot_v (VReg VecOpMasking VState) VReg)
750
- (rule (rv_vnot_v vs2 mask vstate)
751
- (if-let neg1 (imm5_from_i8 -1))
752
- (rv_vxor_vi vs2 neg1 mask vstate))
753
-
754
- ;; Helper for emitting the `vmax.vv` instruction.
755
- (decl rv_vmax_vv (VReg VReg VecOpMasking VState) VReg)
756
- (rule (rv_vmax_vv vs2 vs1 mask vstate)
757
- (vec_alu_rrr (VecAluOpRRR.VmaxVV) vs2 vs1 mask vstate))
758
-
759
- ;; Helper for emitting the `vmax.vx` instruction.
760
- (decl rv_vmax_vx (VReg XReg VecOpMasking VState) VReg)
761
- (rule (rv_vmax_vx vs2 vs1 mask vstate)
762
- (vec_alu_rrr (VecAluOpRRR.VmaxVX) vs2 vs1 mask vstate))
763
-
764
- ;; Helper for emitting the `vmin.vv` instruction.
765
- (decl rv_vmin_vv (VReg VReg VecOpMasking VState) VReg)
766
- (rule (rv_vmin_vv vs2 vs1 mask vstate)
767
- (vec_alu_rrr (VecAluOpRRR.VminVV) vs2 vs1 mask vstate))
768
-
769
- ;; Helper for emitting the `vmin.vx` instruction.
770
- (decl rv_vmin_vx (VReg XReg VecOpMasking VState) VReg)
771
- (rule (rv_vmin_vx vs2 vs1 mask vstate)
772
- (vec_alu_rrr (VecAluOpRRR.VminVX) vs2 vs1 mask vstate))
773
-
774
- ;; Helper for emitting the `vmaxu.vv` instruction.
775
- (decl rv_vmaxu_vv (VReg VReg VecOpMasking VState) VReg)
776
- (rule (rv_vmaxu_vv vs2 vs1 mask vstate)
777
- (vec_alu_rrr (VecAluOpRRR.VmaxuVV) vs2 vs1 mask vstate))
778
-
779
- ;; Helper for emitting the `vmaxu.vx` instruction.
780
- (decl rv_vmaxu_vx (VReg XReg VecOpMasking VState) VReg)
781
- (rule (rv_vmaxu_vx vs2 vs1 mask vstate)
782
- (vec_alu_rrr (VecAluOpRRR.VmaxuVX) vs2 vs1 mask vstate))
783
-
784
- ;; Helper for emitting the `vminu.vv` instruction.
785
- (decl rv_vminu_vv (VReg VReg VecOpMasking VState) VReg)
786
- (rule (rv_vminu_vv vs2 vs1 mask vstate)
787
- (vec_alu_rrr (VecAluOpRRR.VminuVV) vs2 vs1 mask vstate))
788
-
789
- ;; Helper for emitting the `vminu.vx` instruction.
790
- (decl rv_vminu_vx (VReg XReg VecOpMasking VState) VReg)
791
- (rule (rv_vminu_vx vs2 vs1 mask vstate)
792
- (vec_alu_rrr (VecAluOpRRR.VminuVX) vs2 vs1 mask vstate))
793
-
794
- ;; Helper for emitting the `vfadd.vv` instruction.
795
- (decl rv_vfadd_vv (VReg VReg VecOpMasking VState) VReg)
796
- (rule (rv_vfadd_vv vs2 vs1 mask vstate)
797
- (vec_alu_rrr (VecAluOpRRR.VfaddVV) vs2 vs1 mask vstate))
798
-
799
- ;; Helper for emitting the `vfadd.vf` instruction.
800
- (decl rv_vfadd_vf (VReg FReg VecOpMasking VState) VReg)
801
- (rule (rv_vfadd_vf vs2 vs1 mask vstate)
802
- (vec_alu_rrr (VecAluOpRRR.VfaddVF) vs2 vs1 mask vstate))
803
-
804
- ;; Helper for emitting the `vfsub.vv` instruction.
805
- (decl rv_vfsub_vv (VReg VReg VecOpMasking VState) VReg)
806
- (rule (rv_vfsub_vv vs2 vs1 mask vstate)
807
- (vec_alu_rrr (VecAluOpRRR.VfsubVV) vs2 vs1 mask vstate))
808
-
809
- ;; Helper for emitting the `vfsub.vf` instruction.
810
- (decl rv_vfsub_vf (VReg FReg VecOpMasking VState) VReg)
811
- (rule (rv_vfsub_vf vs2 vs1 mask vstate)
812
- (vec_alu_rrr (VecAluOpRRR.VfsubVF) vs2 vs1 mask vstate))
813
-
814
- ;; Helper for emitting the `vfrsub.vf` instruction.
815
- (decl rv_vfrsub_vf (VReg FReg VecOpMasking VState) VReg)
816
- (rule (rv_vfrsub_vf vs2 vs1 mask vstate)
817
- (vec_alu_rrr (VecAluOpRRR.VfrsubVF) vs2 vs1 mask vstate))
818
-
819
- ;; Helper for emitting the `vfmul.vv` instruction.
820
- (decl rv_vfmul_vv (VReg VReg VecOpMasking VState) VReg)
821
- (rule (rv_vfmul_vv vs2 vs1 mask vstate)
822
- (vec_alu_rrr (VecAluOpRRR.VfmulVV) vs2 vs1 mask vstate))
823
-
824
- ;; Helper for emitting the `vfmul.vf` instruction.
825
- (decl rv_vfmul_vf (VReg FReg VecOpMasking VState) VReg)
826
- (rule (rv_vfmul_vf vs2 vs1 mask vstate)
827
- (vec_alu_rrr (VecAluOpRRR.VfmulVF) vs2 vs1 mask vstate))
828
-
829
- ;; Helper for emitting the `vfdiv.vv` instruction.
830
- (decl rv_vfdiv_vv (VReg VReg VecOpMasking VState) VReg)
831
- (rule (rv_vfdiv_vv vs2 vs1 mask vstate)
832
- (vec_alu_rrr (VecAluOpRRR.VfdivVV) vs2 vs1 mask vstate))
833
-
834
- ;; Helper for emitting the `vfdiv.vf` instruction.
835
- (decl rv_vfdiv_vf (VReg FReg VecOpMasking VState) VReg)
836
- (rule (rv_vfdiv_vf vs2 vs1 mask vstate)
837
- (vec_alu_rrr (VecAluOpRRR.VfdivVF) vs2 vs1 mask vstate))
838
-
839
- ;; Helper for emitting the `vfrdiv.vf` instruction.
840
- (decl rv_vfrdiv_vf (VReg FReg VecOpMasking VState) VReg)
841
- (rule (rv_vfrdiv_vf vs2 vs1 mask vstate)
842
- (vec_alu_rrr (VecAluOpRRR.VfrdivVF) vs2 vs1 mask vstate))
843
-
844
- ;; Helper for emitting the `vfmin.vv` instruction.
845
- (decl rv_vfmin_vv (VReg VReg VecOpMasking VState) VReg)
846
- (rule (rv_vfmin_vv vs2 vs1 mask vstate)
847
- (vec_alu_rrr (VecAluOpRRR.VfminVV) vs2 vs1 mask vstate))
848
-
849
- ;; Helper for emitting the `vfmax.vv` instruction.
850
- (decl rv_vfmax_vv (VReg VReg VecOpMasking VState) VReg)
851
- (rule (rv_vfmax_vv vs2 vs1 mask vstate)
852
- (vec_alu_rrr (VecAluOpRRR.VfmaxVV) vs2 vs1 mask vstate))
853
-
854
- ;; Helper for emitting the `vfsgnj.vv` ("Floating Point Sign Injection") instruction.
855
- ;; The output of this instruction is `vs2` with the sign bit from `vs1`
856
- (decl rv_vfsgnj_vv (VReg VReg VecOpMasking VState) VReg)
857
- (rule (rv_vfsgnj_vv vs2 vs1 mask vstate)
858
- (vec_alu_rrr (VecAluOpRRR.VfsgnjVV) vs2 vs1 mask vstate))
859
-
860
- ;; Helper for emitting the `vfsgnj.vf` ("Floating Point Sign Injection") instruction.
861
- (decl rv_vfsgnj_vf (VReg FReg VecOpMasking VState) VReg)
862
- (rule (rv_vfsgnj_vf vs2 vs1 mask vstate)
863
- (vec_alu_rrr (VecAluOpRRR.VfsgnjVF) vs2 vs1 mask vstate))
864
-
865
- ;; Helper for emitting the `vfsgnjn.vv` ("Floating Point Sign Injection Negated") instruction.
866
- ;; The output of this instruction is `vs2` with the negated sign bit from `vs1`
867
- (decl rv_vfsgnjn_vv (VReg VReg VecOpMasking VState) VReg)
868
- (rule (rv_vfsgnjn_vv vs2 vs1 mask vstate)
869
- (vec_alu_rrr (VecAluOpRRR.VfsgnjnVV) vs2 vs1 mask vstate))
870
-
871
- ;; Helper for emitting the `vfneg.v` instruction.
872
- ;; This instruction is a mnemonic for `vfsgnjn.vv vd, vs, vs`
873
- (decl rv_vfneg_v (VReg VecOpMasking VState) VReg)
874
- (rule (rv_vfneg_v vs mask vstate) (rv_vfsgnjn_vv vs vs mask vstate))
875
-
876
- ;; Helper for emitting the `vfsgnjx.vv` ("Floating Point Sign Injection Exclusive") instruction.
877
- ;; The output of this instruction is `vs2` with the XOR of the sign bits from `vs2` and `vs1`.
878
- ;; When `vs2 == vs1` this implements `fabs`
879
- (decl rv_vfsgnjx_vv (VReg VReg VecOpMasking VState) VReg)
880
- (rule (rv_vfsgnjx_vv vs2 vs1 mask vstate)
881
- (vec_alu_rrr (VecAluOpRRR.VfsgnjxVV) vs2 vs1 mask vstate))
882
-
883
- ;; Helper for emitting the `vfabs.v` instruction.
884
- ;; This instruction is a mnemonic for `vfsgnjx.vv vd, vs, vs`
885
- (decl rv_vfabs_v (VReg VecOpMasking VState) VReg)
886
- (rule (rv_vfabs_v vs mask vstate) (rv_vfsgnjx_vv vs vs mask vstate))
887
-
888
- ;; Helper for emitting the `vfsqrt.v` instruction.
889
- ;; This instruction splats the F regsiter into all elements of the destination vector.
890
- (decl rv_vfsqrt_v (VReg VecOpMasking VState) VReg)
891
- (rule (rv_vfsqrt_v vs mask vstate)
892
- (vec_alu_rr (VecAluOpRR.VfsqrtV) vs mask vstate))
893
-
894
- ;; Helper for emitting the `vslidedown.vx` instruction.
895
- ;; `vslidedown` moves all elements in the vector down by n elements.
896
- ;; The top most elements are up to the tail policy.
897
- (decl rv_vslidedown_vx (VReg XReg VecOpMasking VState) VReg)
898
- (rule (rv_vslidedown_vx vs2 vs1 mask vstate)
899
- (vec_alu_rrr (VecAluOpRRR.VslidedownVX) vs2 vs1 mask vstate))
900
-
901
- ;; Helper for emitting the `vslidedown.vi` instruction.
902
- ;; Unlike other `vi` instructions the immediate is zero extended.
903
- (decl rv_vslidedown_vi (VReg UImm5 VecOpMasking VState) VReg)
904
- (rule (rv_vslidedown_vi vs2 imm mask vstate)
905
- (vec_alu_rr_uimm5 (VecAluOpRRImm5.VslidedownVI) vs2 imm mask vstate))
906
-
907
- ;; Helper for emitting the `vslideup.vi` instruction.
908
- ;; Unlike other `vi` instructions the immediate is zero extended.
909
- ;; This is implemented as a 2 source operand instruction, since it only
910
- ;; partially modifies the destination register.
911
- (decl rv_vslideup_vvi (VReg VReg UImm5 VecOpMasking VState) VReg)
912
- (rule (rv_vslideup_vvi vd vs2 imm mask vstate)
913
- (vec_alu_rrr_uimm5 (VecAluOpRRRImm5.VslideupVI) vd vs2 imm mask vstate))
914
-
915
- ;; Helper for emitting the `vmv.x.s` instruction.
916
- ;; This instruction copies the first element of the source vector to the destination X register.
917
- ;; Masked versions of this instuction are not supported.
918
- (decl rv_vmv_xs (VReg VState) XReg)
919
- (rule (rv_vmv_xs vs vstate)
920
- (vec_alu_rr (VecAluOpRR.VmvXS) vs (unmasked) vstate))
921
-
922
- ;; Helper for emitting the `vfmv.f.s` instruction.
923
- ;; This instruction copies the first element of the source vector to the destination F register.
924
- ;; Masked versions of this instuction are not supported.
925
- (decl rv_vfmv_fs (VReg VState) FReg)
926
- (rule (rv_vfmv_fs vs vstate)
927
- (vec_alu_rr (VecAluOpRR.VfmvFS) vs (unmasked) vstate))
928
-
929
- ;; Helper for emitting the `vmv.s.x` instruction.
930
- ;; This instruction copies the source X register into first element of the source vector.
931
- ;; Masked versions of this instuction are not supported.
932
- (decl rv_vmv_sx (XReg VState) VReg)
933
- (rule (rv_vmv_sx vs vstate)
934
- (vec_alu_rr (VecAluOpRR.VmvSX) vs (unmasked) vstate))
935
-
936
- ;; Helper for emitting the `vfmv.s.f` instruction.
937
- ;; This instruction copies the source F register into first element of the source vector.
938
- ;; Masked versions of this instuction are not supported.
939
- (decl rv_vfmv_sf (FReg VState) VReg)
940
- (rule (rv_vfmv_sf vs vstate)
941
- (vec_alu_rr (VecAluOpRR.VfmvSF) vs (unmasked) vstate))
942
-
943
- ;; Helper for emitting the `vmv.v.x` instruction.
944
- ;; This instruction splats the X regsiter into all elements of the destination vector.
945
- ;; Masked versions of this instruction are called `vmerge`
946
- (decl rv_vmv_vx (XReg VState) VReg)
947
- (rule (rv_vmv_vx vs vstate)
948
- (vec_alu_rr (VecAluOpRR.VmvVX) vs (unmasked) vstate))
949
-
950
- ;; Helper for emitting the `vfmv.v.f` instruction.
951
- ;; This instruction splats the F regsiter into all elements of the destination vector.
952
- ;; Masked versions of this instruction are called `vmerge`
953
- (decl rv_vfmv_vf (FReg VState) VReg)
954
- (rule (rv_vfmv_vf vs vstate)
955
- (vec_alu_rr (VecAluOpRR.VfmvVF) vs (unmasked) vstate))
956
-
957
- ;; Helper for emitting the `vmv.v.i` instruction.
958
- ;; This instruction splat's the immediate value into all elements of the destination vector.
959
- ;; Masked versions of this instruction are called `vmerge`
960
- (decl rv_vmv_vi (Imm5 VState) VReg)
961
- (rule (rv_vmv_vi imm vstate)
962
- (vec_alu_r_imm5 (VecAluOpRImm5.VmvVI) imm (unmasked) vstate))
963
-
964
- ;; Helper for emitting the `vmerge.vvm` instruction.
965
- ;; This instruction merges the elements of the two source vectors into the destination vector
966
- ;; based on a mask. Elements are taken from the first source vector if the mask bit is clear,
967
- ;; and from the second source vector if the mask bit is set. This instruction is always masked.
968
- ;;
969
- ;; vd[i] = v0.mask[i] ? vs1[i] : vs2[i]
970
- (decl rv_vmerge_vvm (VReg VReg VReg VState) VReg)
971
- (rule (rv_vmerge_vvm vs2 vs1 mask vstate)
972
- (vec_alu_rrr (VecAluOpRRR.VmergeVVM) vs2 vs1 (masked mask) vstate))
973
-
974
- ;; Helper for emitting the `vmerge.vxm` instruction.
975
- ;; Elements are taken from the first source vector if the mask bit is clear, and from the X
976
- ;; register if the mask bit is set. This instruction is always masked.
977
- ;;
978
- ;; vd[i] = v0.mask[i] ? x[rs1] : vs2[i]
979
- (decl rv_vmerge_vxm (VReg XReg VReg VState) VReg)
980
- (rule (rv_vmerge_vxm vs2 vs1 mask vstate)
981
- (vec_alu_rrr (VecAluOpRRR.VmergeVXM) vs2 vs1 (masked mask) vstate))
982
-
983
- ;; Helper for emitting the `vfmerge.vfm` instruction.
984
- ;; Elements are taken from the first source vector if the mask bit is clear, and from the F
985
- ;; register if the mask bit is set. This instruction is always masked.
986
- ;;
987
- ;; vd[i] = v0.mask[i] ? f[rs1] : vs2[i]
988
- (decl rv_vfmerge_vfm (VReg FReg VReg VState) VReg)
989
- (rule (rv_vfmerge_vfm vs2 vs1 mask vstate)
990
- (vec_alu_rrr (VecAluOpRRR.VfmergeVFM) vs2 vs1 (masked mask) vstate))
991
-
992
- ;; Helper for emitting the `vmerge.vim` instruction.
993
- ;; Elements are taken from the first source vector if the mask bit is clear, and from the
994
- ;; immediate value if the mask bit is set. This instruction is always masked.
995
- ;;
996
- ;; vd[i] = v0.mask[i] ? imm : vs2[i]
997
- (decl rv_vmerge_vim (VReg Imm5 VReg VState) VReg)
998
- (rule (rv_vmerge_vim vs2 imm mask vstate)
999
- (vec_alu_rr_imm5 (VecAluOpRRImm5.VmergeVIM) vs2 imm (masked mask) vstate))
1000
-
1001
-
1002
- ;; Helper for emitting the `vredminu.vs` instruction.
1003
- ;;
1004
- ;; vd[0] = minu( vs1[0] , vs2[*] )
1005
- (decl rv_vredminu_vs (VReg VReg VecOpMasking VState) VReg)
1006
- (rule (rv_vredminu_vs vs2 vs1 mask vstate)
1007
- (vec_alu_rrr (VecAluOpRRR.VredminuVS) vs2 vs1 mask vstate))
1008
-
1009
- ;; Helper for emitting the `vredmaxu.vs` instruction.
1010
- ;;
1011
- ;; vd[0] = maxu( vs1[0] , vs2[*] )
1012
- (decl rv_vredmaxu_vs (VReg VReg VecOpMasking VState) VReg)
1013
- (rule (rv_vredmaxu_vs vs2 vs1 mask vstate)
1014
- (vec_alu_rrr (VecAluOpRRR.VredmaxuVS) vs2 vs1 mask vstate))
1015
-
1016
- ;; Helper for emitting the `vrgather.vv` instruction.
1017
- ;;
1018
- ;; vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]];
1019
- (decl rv_vrgather_vv (VReg VReg VecOpMasking VState) VReg)
1020
- (rule (rv_vrgather_vv vs2 vs1 mask vstate)
1021
- (vec_alu_rrr (VecAluOpRRR.VrgatherVV) vs2 vs1 mask vstate))
1022
-
1023
- ;; Helper for emitting the `vrgather.vx` instruction.
1024
- ;;
1025
- ;; vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[x[rs1]]
1026
- (decl rv_vrgather_vx (VReg XReg VecOpMasking VState) VReg)
1027
- (rule (rv_vrgather_vx vs2 vs1 mask vstate)
1028
- (vec_alu_rrr (VecAluOpRRR.VrgatherVX) vs2 vs1 mask vstate))
1029
-
1030
- ;; Helper for emitting the `vrgather.vi` instruction.
1031
- (decl rv_vrgather_vi (VReg UImm5 VecOpMasking VState) VReg)
1032
- (rule (rv_vrgather_vi vs2 imm mask vstate)
1033
- (vec_alu_rr_uimm5 (VecAluOpRRImm5.VrgatherVI) vs2 imm mask vstate))
1034
-
1035
- ;; Helper for emitting the `vcompress.vm` instruction.
1036
- ;;
1037
- ;; The vector compress instruction allows elements selected by a vector mask
1038
- ;; register from a source vector register group to be packed into contiguous
1039
- ;; elements at the start of the destination vector register group.
1040
- ;;
1041
- ;; The mask register is specified through vs1
1042
- (decl rv_vcompress_vm (VReg VReg VState) VReg)
1043
- (rule (rv_vcompress_vm vs2 vs1 vstate)
1044
- (vec_alu_rrr (VecAluOpRRR.VcompressVM) vs2 vs1 (unmasked) vstate))
1045
-
1046
- ;; Helper for emitting the `vmseq.vv` (Vector Mask Set If Equal) instruction.
1047
- (decl rv_vmseq_vv (VReg VReg VecOpMasking VState) VReg)
1048
- (rule (rv_vmseq_vv vs2 vs1 mask vstate)
1049
- (vec_alu_rrr (VecAluOpRRR.VmseqVV) vs2 vs1 mask vstate))
1050
-
1051
- ;; Helper for emitting the `vmseq.vx` (Vector Mask Set If Equal) instruction.
1052
- (decl rv_vmseq_vx (VReg XReg VecOpMasking VState) VReg)
1053
- (rule (rv_vmseq_vx vs2 vs1 mask vstate)
1054
- (vec_alu_rrr (VecAluOpRRR.VmseqVX) vs2 vs1 mask vstate))
1055
-
1056
- ;; Helper for emitting the `vmseq.vi` (Vector Mask Set If Equal) instruction.
1057
- (decl rv_vmseq_vi (VReg Imm5 VecOpMasking VState) VReg)
1058
- (rule (rv_vmseq_vi vs2 imm mask vstate)
1059
- (vec_alu_rr_imm5 (VecAluOpRRImm5.VmseqVI) vs2 imm mask vstate))
1060
-
1061
- ;; Helper for emitting the `vmsne.vv` (Vector Mask Set If Not Equal) instruction.
1062
- (decl rv_vmsne_vv (VReg VReg VecOpMasking VState) VReg)
1063
- (rule (rv_vmsne_vv vs2 vs1 mask vstate)
1064
- (vec_alu_rrr (VecAluOpRRR.VmsneVV) vs2 vs1 mask vstate))
1065
-
1066
- ;; Helper for emitting the `vmsne.vx` (Vector Mask Set If Not Equal) instruction.
1067
- (decl rv_vmsne_vx (VReg XReg VecOpMasking VState) VReg)
1068
- (rule (rv_vmsne_vx vs2 vs1 mask vstate)
1069
- (vec_alu_rrr (VecAluOpRRR.VmsneVX) vs2 vs1 mask vstate))
1070
-
1071
- ;; Helper for emitting the `vmsne.vi` (Vector Mask Set If Not Equal) instruction.
1072
- (decl rv_vmsne_vi (VReg Imm5 VecOpMasking VState) VReg)
1073
- (rule (rv_vmsne_vi vs2 imm mask vstate)
1074
- (vec_alu_rr_imm5 (VecAluOpRRImm5.VmsneVI) vs2 imm mask vstate))
1075
-
1076
- ;; Helper for emitting the `vmsltu.vv` (Vector Mask Set If Less Than, Unsigned) instruction.
1077
- (decl rv_vmsltu_vv (VReg VReg VecOpMasking VState) VReg)
1078
- (rule (rv_vmsltu_vv vs2 vs1 mask vstate)
1079
- (vec_alu_rrr (VecAluOpRRR.VmsltuVV) vs2 vs1 mask vstate))
1080
-
1081
- ;; Helper for emitting the `vmsltu.vx` (Vector Mask Set If Less Than, Unsigned) instruction.
1082
- (decl rv_vmsltu_vx (VReg XReg VecOpMasking VState) VReg)
1083
- (rule (rv_vmsltu_vx vs2 vs1 mask vstate)
1084
- (vec_alu_rrr (VecAluOpRRR.VmsltuVX) vs2 vs1 mask vstate))
1085
-
1086
- ;; Helper for emitting the `vmslt.vv` (Vector Mask Set If Less Than) instruction.
1087
- (decl rv_vmslt_vv (VReg VReg VecOpMasking VState) VReg)
1088
- (rule (rv_vmslt_vv vs2 vs1 mask vstate)
1089
- (vec_alu_rrr (VecAluOpRRR.VmsltVV) vs2 vs1 mask vstate))
1090
-
1091
- ;; Helper for emitting the `vmslt.vx` (Vector Mask Set If Less Than) instruction.
1092
- (decl rv_vmslt_vx (VReg XReg VecOpMasking VState) VReg)
1093
- (rule (rv_vmslt_vx vs2 vs1 mask vstate)
1094
- (vec_alu_rrr (VecAluOpRRR.VmsltVX) vs2 vs1 mask vstate))
1095
-
1096
- ;; Helper for emitting the `vmsleu.vv` (Vector Mask Set If Less Than or Equal, Unsigned) instruction.
1097
- (decl rv_vmsleu_vv (VReg VReg VecOpMasking VState) VReg)
1098
- (rule (rv_vmsleu_vv vs2 vs1 mask vstate)
1099
- (vec_alu_rrr (VecAluOpRRR.VmsleuVV) vs2 vs1 mask vstate))
1100
-
1101
- ;; Helper for emitting the `vmsleu.vx` (Vector Mask Set If Less Than or Equal, Unsigned) instruction.
1102
- (decl rv_vmsleu_vx (VReg XReg VecOpMasking VState) VReg)
1103
- (rule (rv_vmsleu_vx vs2 vs1 mask vstate)
1104
- (vec_alu_rrr (VecAluOpRRR.VmsleuVX) vs2 vs1 mask vstate))
1105
-
1106
- ;; Helper for emitting the `vmsleu.vi` (Vector Mask Set If Less Than or Equal, Unsigned) instruction.
1107
- (decl rv_vmsleu_vi (VReg Imm5 VecOpMasking VState) VReg)
1108
- (rule (rv_vmsleu_vi vs2 imm mask vstate)
1109
- (vec_alu_rr_imm5 (VecAluOpRRImm5.VmsleuVI) vs2 imm mask vstate))
1110
-
1111
- ;; Helper for emitting the `vmsle.vv` (Vector Mask Set If Less Than or Equal) instruction.
1112
- (decl rv_vmsle_vv (VReg VReg VecOpMasking VState) VReg)
1113
- (rule (rv_vmsle_vv vs2 vs1 mask vstate)
1114
- (vec_alu_rrr (VecAluOpRRR.VmsleVV) vs2 vs1 mask vstate))
1115
-
1116
- ;; Helper for emitting the `vmsle.vx` (Vector Mask Set If Less Than or Equal) instruction.
1117
- (decl rv_vmsle_vx (VReg XReg VecOpMasking VState) VReg)
1118
- (rule (rv_vmsle_vx vs2 vs1 mask vstate)
1119
- (vec_alu_rrr (VecAluOpRRR.VmsleVX) vs2 vs1 mask vstate))
1120
-
1121
- ;; Helper for emitting the `vmsle.vi` (Vector Mask Set If Less Than or Equal) instruction.
1122
- (decl rv_vmsle_vi (VReg Imm5 VecOpMasking VState) VReg)
1123
- (rule (rv_vmsle_vi vs2 imm mask vstate)
1124
- (vec_alu_rr_imm5 (VecAluOpRRImm5.VmsleVI) vs2 imm mask vstate))
1125
-
1126
- ;; Helper for emitting the `vmsgt.vv` (Vector Mask Set If Greater Than, Unsigned) instruction.
1127
- ;; This is an alias for `vmsltu.vv` with the operands inverted.
1128
- (decl rv_vmsgtu_vv (VReg VReg VecOpMasking VState) VReg)
1129
- (rule (rv_vmsgtu_vv vs2 vs1 mask vstate) (rv_vmsltu_vv vs1 vs2 mask vstate))
1130
-
1131
- ;; Helper for emitting the `vmsgtu.vx` (Vector Mask Set If Greater Than, Unsigned) instruction.
1132
- (decl rv_vmsgtu_vx (VReg XReg VecOpMasking VState) VReg)
1133
- (rule (rv_vmsgtu_vx vs2 vs1 mask vstate)
1134
- (vec_alu_rrr (VecAluOpRRR.VmsgtuVX) vs2 vs1 mask vstate))
1135
-
1136
- ;; Helper for emitting the `vmsgtu.vi` (Vector Mask Set If Greater Than, Unsigned) instruction.
1137
- (decl rv_vmsgtu_vi (VReg Imm5 VecOpMasking VState) VReg)
1138
- (rule (rv_vmsgtu_vi vs2 imm mask vstate)
1139
- (vec_alu_rr_imm5 (VecAluOpRRImm5.VmsgtuVI) vs2 imm mask vstate))
1140
-
1141
- ;; Helper for emitting the `vmsgt.vv` (Vector Mask Set If Greater Than) instruction.
1142
- ;; This is an alias for `vmslt.vv` with the operands inverted.
1143
- (decl rv_vmsgt_vv (VReg VReg VecOpMasking VState) VReg)
1144
- (rule (rv_vmsgt_vv vs2 vs1 mask vstate) (rv_vmslt_vv vs1 vs2 mask vstate))
1145
-
1146
- ;; Helper for emitting the `vmsgt.vx` (Vector Mask Set If Greater Than) instruction.
1147
- (decl rv_vmsgt_vx (VReg XReg VecOpMasking VState) VReg)
1148
- (rule (rv_vmsgt_vx vs2 vs1 mask vstate)
1149
- (vec_alu_rrr (VecAluOpRRR.VmsgtVX) vs2 vs1 mask vstate))
1150
-
1151
- ;; Helper for emitting the `vmsgt.vi` (Vector Mask Set If Greater Than) instruction.
1152
- (decl rv_vmsgt_vi (VReg Imm5 VecOpMasking VState) VReg)
1153
- (rule (rv_vmsgt_vi vs2 imm mask vstate)
1154
- (vec_alu_rr_imm5 (VecAluOpRRImm5.VmsgtVI) vs2 imm mask vstate))
1155
-
1156
- ;; Helper for emitting the `vmsgeu.vv` (Vector Mask Set If Greater Than or Equal, Unsigned) instruction.
1157
- ;; This is an alias for `vmsleu.vv` with the operands inverted.
1158
- (decl rv_vmsgeu_vv (VReg VReg VecOpMasking VState) VReg)
1159
- (rule (rv_vmsgeu_vv vs2 vs1 mask vstate) (rv_vmsleu_vv vs1 vs2 mask vstate))
1160
-
1161
- ;; Helper for emitting the `vmsge.vv` (Vector Mask Set If Greater Than or Equal) instruction.
1162
- ;; This is an alias for `vmsle.vv` with the operands inverted.
1163
- (decl rv_vmsge_vv (VReg VReg VecOpMasking VState) VReg)
1164
- (rule (rv_vmsge_vv vs2 vs1 mask vstate) (rv_vmsle_vv vs1 vs2 mask vstate))
1165
-
1166
- ;; Helper for emitting the `vmfeq.vv` (Vector Mask Set If Float Equal) instruction.
1167
- (decl rv_vmfeq_vv (VReg VReg VecOpMasking VState) VReg)
1168
- (rule (rv_vmfeq_vv vs2 vs1 mask vstate)
1169
- (vec_alu_rrr (VecAluOpRRR.VmfeqVV) vs2 vs1 mask vstate))
1170
-
1171
- ;; Helper for emitting the `vmfeq.vf` (Vector Mask Set If Float Equal) instruction.
1172
- (decl rv_vmfeq_vf (VReg FReg VecOpMasking VState) VReg)
1173
- (rule (rv_vmfeq_vf vs2 vs1 mask vstate)
1174
- (vec_alu_rrr (VecAluOpRRR.VmfeqVF) vs2 vs1 mask vstate))
1175
-
1176
- ;; Helper for emitting the `vmfne.vv` (Vector Mask Set If Float Not Equal) instruction.
1177
- (decl rv_vmfne_vv (VReg VReg VecOpMasking VState) VReg)
1178
- (rule (rv_vmfne_vv vs2 vs1 mask vstate)
1179
- (vec_alu_rrr (VecAluOpRRR.VmfneVV) vs2 vs1 mask vstate))
1180
-
1181
- ;; Helper for emitting the `vmfne.vf` (Vector Mask Set If Float Not Equal) instruction.
1182
- (decl rv_vmfne_vf (VReg FReg VecOpMasking VState) VReg)
1183
- (rule (rv_vmfne_vf vs2 vs1 mask vstate)
1184
- (vec_alu_rrr (VecAluOpRRR.VmfneVF) vs2 vs1 mask vstate))
1185
-
1186
- ;; Helper for emitting the `vmflt.vv` (Vector Mask Set If Float Less Than) instruction.
1187
- (decl rv_vmflt_vv (VReg VReg VecOpMasking VState) VReg)
1188
- (rule (rv_vmflt_vv vs2 vs1 mask vstate)
1189
- (vec_alu_rrr (VecAluOpRRR.VmfltVV) vs2 vs1 mask vstate))
1190
-
1191
- ;; Helper for emitting the `vmflt.vf` (Vector Mask Set If Float Less Than) instruction.
1192
- (decl rv_vmflt_vf (VReg FReg VecOpMasking VState) VReg)
1193
- (rule (rv_vmflt_vf vs2 vs1 mask vstate)
1194
- (vec_alu_rrr (VecAluOpRRR.VmfltVF) vs2 vs1 mask vstate))
1195
-
1196
- ;; Helper for emitting the `vmfle.vv` (Vector Mask Set If Float Less Than Or Equal) instruction.
1197
- (decl rv_vmfle_vv (VReg VReg VecOpMasking VState) VReg)
1198
- (rule (rv_vmfle_vv vs2 vs1 mask vstate)
1199
- (vec_alu_rrr (VecAluOpRRR.VmfleVV) vs2 vs1 mask vstate))
1200
-
1201
- ;; Helper for emitting the `vmfle.vf` (Vector Mask Set If Float Less Than Or Equal) instruction.
1202
- (decl rv_vmfle_vf (VReg FReg VecOpMasking VState) VReg)
1203
- (rule (rv_vmfle_vf vs2 vs1 mask vstate)
1204
- (vec_alu_rrr (VecAluOpRRR.VmfleVF) vs2 vs1 mask vstate))
1205
-
1206
- ;; Helper for emitting the `vmfgt.vv` (Vector Mask Set If Float Greater Than) instruction.
1207
- ;; This is an alias for `vmflt.vv` with the operands inverted.
1208
- (decl rv_vmfgt_vv (VReg VReg VecOpMasking VState) VReg)
1209
- (rule (rv_vmfgt_vv vs2 vs1 mask vstate) (rv_vmflt_vv vs1 vs2 mask vstate))
1210
-
1211
- ;; Helper for emitting the `vmfgt.vf` (Vector Mask Set If Float Greater Than) instruction.
1212
- (decl rv_vmfgt_vf (VReg FReg VecOpMasking VState) VReg)
1213
- (rule (rv_vmfgt_vf vs2 vs1 mask vstate)
1214
- (vec_alu_rrr (VecAluOpRRR.VmfgtVF) vs2 vs1 mask vstate))
1215
-
1216
- ;; Helper for emitting the `vmfge.vv` (Vector Mask Set If Float Greater Than Or Equal) instruction.
1217
- ;; This is an alias for `vmfle.vv` with the operands inverted.
1218
- (decl rv_vmfge_vv (VReg VReg VecOpMasking VState) VReg)
1219
- (rule (rv_vmfge_vv vs2 vs1 mask vstate) (rv_vmfle_vv vs1 vs2 mask vstate))
1220
-
1221
- ;; Helper for emitting the `vmfge.vf` (Vector Mask Set If Float Greater Than Or Equal) instruction.
1222
- (decl rv_vmfge_vf (VReg FReg VecOpMasking VState) VReg)
1223
- (rule (rv_vmfge_vf vs2 vs1 mask vstate)
1224
- (vec_alu_rrr (VecAluOpRRR.VmfgeVF) vs2 vs1 mask vstate))
1225
-
1226
- ;; Helper for emitting the `vzext.vf2` instruction.
1227
- ;; Zero-extend SEW/2 source to SEW destination
1228
- (decl rv_vzext_vf2 (VReg VecOpMasking VState) VReg)
1229
- (rule (rv_vzext_vf2 vs mask vstate)
1230
- (vec_alu_rr (VecAluOpRR.VzextVF2) vs mask vstate))
1231
-
1232
- ;; Helper for emitting the `vzext.vf4` instruction.
1233
- ;; Zero-extend SEW/4 source to SEW destination
1234
- (decl rv_vzext_vf4 (VReg VecOpMasking VState) VReg)
1235
- (rule (rv_vzext_vf4 vs mask vstate)
1236
- (vec_alu_rr (VecAluOpRR.VzextVF4) vs mask vstate))
1237
-
1238
- ;; Helper for emitting the `vzext.vf8` instruction.
1239
- ;; Zero-extend SEW/8 source to SEW destination
1240
- (decl rv_vzext_vf8 (VReg VecOpMasking VState) VReg)
1241
- (rule (rv_vzext_vf8 vs mask vstate)
1242
- (vec_alu_rr (VecAluOpRR.VzextVF8) vs mask vstate))
1243
-
1244
- ;; Helper for emitting the `vsext.vf2` instruction.
1245
- ;; Sign-extend SEW/2 source to SEW destination
1246
- (decl rv_vsext_vf2 (VReg VecOpMasking VState) VReg)
1247
- (rule (rv_vsext_vf2 vs mask vstate)
1248
- (vec_alu_rr (VecAluOpRR.VsextVF2) vs mask vstate))
1249
-
1250
- ;; Helper for emitting the `vsext.vf4` instruction.
1251
- ;; Sign-extend SEW/4 source to SEW destination
1252
- (decl rv_vsext_vf4 (VReg VecOpMasking VState) VReg)
1253
- (rule (rv_vsext_vf4 vs mask vstate)
1254
- (vec_alu_rr (VecAluOpRR.VsextVF4) vs mask vstate))
1255
-
1256
- ;; Helper for emitting the `vsext.vf8` instruction.
1257
- ;; Sign-extend SEW/8 source to SEW destination
1258
- (decl rv_vsext_vf8 (VReg VecOpMasking VState) VReg)
1259
- (rule (rv_vsext_vf8 vs mask vstate)
1260
- (vec_alu_rr (VecAluOpRR.VsextVF8) vs mask vstate))
1261
-
1262
- ;; Helper for emitting the `vnclip.wi` instruction.
1263
- ;;
1264
- ;; vd[i] = clip(roundoff_signed(vs2[i], uimm))
1265
- (decl rv_vnclip_wi (VReg UImm5 VecOpMasking VState) VReg)
1266
- (rule (rv_vnclip_wi vs2 imm mask vstate)
1267
- (vec_alu_rr_uimm5 (VecAluOpRRImm5.VnclipWI) vs2 imm mask vstate))
1268
-
1269
- ;; Helper for emitting the `vnclipu.wi` instruction.
1270
- ;;
1271
- ;; vd[i] = clip(roundoff_unsigned(vs2[i], uimm))
1272
- (decl rv_vnclipu_wi (VReg UImm5 VecOpMasking VState) VReg)
1273
- (rule (rv_vnclipu_wi vs2 imm mask vstate)
1274
- (vec_alu_rr_uimm5 (VecAluOpRRImm5.VnclipuWI) vs2 imm mask vstate))
1275
-
1276
- ;; Helper for emitting the `vmand.mm` (Mask Bitwise AND) instruction.
1277
- ;;
1278
- ;; vd.mask[i] = vs2.mask[i] && vs1.mask[i]
1279
- (decl rv_vmand_mm (VReg VReg VState) VReg)
1280
- (rule (rv_vmand_mm vs2 vs1 vstate)
1281
- (vec_alu_rrr (VecAluOpRRR.VmandMM) vs2 vs1 (unmasked) vstate))
1282
-
1283
- ;; Helper for emitting the `vmor.mm` (Mask Bitwise OR) instruction.
1284
- ;;
1285
- ;; vd.mask[i] = vs2.mask[i] || vs1.mask[i]
1286
- (decl rv_vmor_mm (VReg VReg VState) VReg)
1287
- (rule (rv_vmor_mm vs2 vs1 vstate)
1288
- (vec_alu_rrr (VecAluOpRRR.VmorMM) vs2 vs1 (unmasked) vstate))
1289
-
1290
- ;; Helper for emitting the `vmnand.mm` (Mask Bitwise NAND) instruction.
1291
- ;;
1292
- ;; vd.mask[i] = !(vs2.mask[i] && vs1.mask[i])
1293
- (decl rv_vmnand_mm (VReg VReg VState) VReg)
1294
- (rule (rv_vmnand_mm vs2 vs1 vstate)
1295
- (vec_alu_rrr (VecAluOpRRR.VmnandMM) vs2 vs1 (unmasked) vstate))
1296
-
1297
- ;; Helper for emitting the `vmnot.m` (Mask Bitwise NOT) instruction.
1298
- ;; This is an alias for `vmnand.mm vd, vs, vs`
1299
- ;;
1300
- ;; vd.mask[i] = !vs.mask[i]
1301
- (decl rv_vmnot_m (VReg VState) VReg)
1302
- (rule (rv_vmnot_m vs vstate) (rv_vmnand_mm vs vs vstate))
1303
-
1304
- ;; Helper for emitting the `vmnor.mm` (Mask Bitwise NOR) instruction.
1305
- ;;
1306
- ;; vd.mask[i] = !(vs2.mask[i] || vs1.mask[i])
1307
- (decl rv_vmnor_mm (VReg VReg VState) VReg)
1308
- (rule (rv_vmnor_mm vs2 vs1 vstate)
1309
- (vec_alu_rrr (VecAluOpRRR.VmnorMM) vs2 vs1 (unmasked) vstate))
1310
-
1311
- ;;;; Multi-Instruction Helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1312
-
1313
- (decl gen_extractlane (Type VReg u8) Reg)
1314
-
1315
- ;; When extracting lane 0 for floats, we can use `vfmv.f.s` directly.
1316
- (rule 3 (gen_extractlane (ty_vec_fits_in_register ty) src 0)
1317
- (if (ty_vector_float ty))
1318
- (rv_vfmv_fs src ty))
1319
-
1320
- ;; When extracting lane 0 for integers, we can use `vmv.x.s` directly.
1321
- (rule 2 (gen_extractlane (ty_vec_fits_in_register ty) src 0)
1322
- (if (ty_vector_not_float ty))
1323
- (rv_vmv_xs src ty))
1324
-
1325
- ;; In the general case, we must first use a `vslidedown` to place the correct lane
1326
- ;; in index 0, and then use the appropriate `vmv` instruction.
1327
- ;; If the index fits into a 5-bit immediate, we can emit a `vslidedown.vi`.
1328
- (rule 1 (gen_extractlane (ty_vec_fits_in_register ty) src (uimm5_from_u8 idx))
1329
- (gen_extractlane ty (rv_vslidedown_vi src idx (unmasked) ty) 0))
1330
-
1331
- ;; Otherwise lower it into an X register.
1332
- (rule 0 (gen_extractlane (ty_vec_fits_in_register ty) src idx)
1333
- (gen_extractlane ty (rv_vslidedown_vx src (imm $I64 idx) (unmasked) ty) 0))
1334
-
1335
-
1336
- ;; Build a vector mask from a u64
1337
- ;; TODO(#6571): We should merge this with the `vconst` rules, and take advantage of
1338
- ;; the other existing `vconst` rules.
1339
- (decl gen_vec_mask (u64) VReg)
1340
-
1341
- ;; When the immediate fits in a 5-bit immediate, we can use `vmv.v.i` directly.
1342
- (rule 1 (gen_vec_mask (imm5_from_u64 imm))
1343
- (rv_vmv_vi imm (vstate_from_type $I64X2)))
1344
-
1345
- ;; Materialize the mask into an X register, and move it into the bottom of
1346
- ;; the vector register.
1347
- (rule 0 (gen_vec_mask mask)
1348
- (rv_vmv_sx (imm $I64 mask) (vstate_from_type $I64X2)))
1349
-
1350
-
1351
- ;; Loads a `VCodeConstant` value into a vector register. For some special `VCodeConstant`s
1352
- ;; we can use a dedicated instruction, otherwise we load the value from the pool.
1353
- ;;
1354
- ;; Type is the preferred type to use when loading the constant.
1355
- (decl gen_constant (Type VCodeConstant) VReg)
1356
-
1357
- ;; The fallback case is to load the constant from the pool.
1358
- (rule (gen_constant ty n)
1359
- (vec_load
1360
- (element_width_from_type ty)
1361
- (VecAMode.UnitStride (gen_const_amode n))
1362
- (mem_flags_trusted)
1363
- (unmasked)
1364
- ty))
1365
-
1366
-
1367
- ;; Emits a vslidedown instruction that moves half the lanes down.
1368
- (decl gen_slidedown_half (Type VReg) VReg)
1369
-
1370
- ;; If the lane count can fit in a 5-bit immediate, we can use `vslidedown.vi`.
1371
- (rule 1 (gen_slidedown_half (ty_vec_fits_in_register ty) src)
1372
- (if-let (uimm5_from_u64 amt) (u64_udiv (ty_lane_count ty) 2))
1373
- (rv_vslidedown_vi src amt (unmasked) ty))
1374
-
1375
- ;; Otherwise lower it into an X register.
1376
- (rule 0 (gen_slidedown_half (ty_vec_fits_in_register ty) src)
1377
- (if-let amt (u64_udiv (ty_lane_count ty) 2))
1378
- (rv_vslidedown_vx src (imm $I64 amt) (unmasked) ty))
1379
-
1380
-
1381
- ;; Expands a mask into SEW wide lanes. Enabled lanes are set to all ones, disabled
1382
- ;; lanes are set to all zeros.
1383
- (decl gen_expand_mask (Type VReg) VReg)
1384
- (rule (gen_expand_mask ty mask)
1385
- (if-let zero (imm5_from_i8 0))
1386
- (if-let neg1 (imm5_from_i8 -1))
1387
- (rv_vmerge_vim (rv_vmv_vi zero ty) neg1 mask ty))
1388
-
1389
-
1390
- ;; Builds a vector mask corresponding to the IntCC operation.
1391
- ;; TODO: We are still missing some rules here for immediates. See #6623
1392
- (decl gen_icmp_mask (Type IntCC Value Value) VReg)
1393
-
1394
- ;; IntCC.Equal
1395
-
1396
- (rule 0 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.Equal) x y)
1397
- (rv_vmseq_vv x y (unmasked) ty))
1398
-
1399
- (rule 1 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.Equal) x (splat y))
1400
- (rv_vmseq_vx x y (unmasked) ty))
1401
-
1402
- (rule 2 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.Equal) (splat x) y)
1403
- (rv_vmseq_vx y x (unmasked) ty))
1404
-
1405
- (rule 3 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.Equal) x (replicated_imm5 y))
1406
- (rv_vmseq_vi x y (unmasked) ty))
1407
-
1408
- (rule 4 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.Equal) (replicated_imm5 x) y)
1409
- (rv_vmseq_vi y x (unmasked) ty))
1410
-
1411
- ;; IntCC.NotEqual
1412
-
1413
- (rule 0 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.NotEqual) x y)
1414
- (rv_vmsne_vv x y (unmasked) ty))
1415
-
1416
- (rule 1 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.NotEqual) x (splat y))
1417
- (rv_vmsne_vx x y (unmasked) ty))
1418
-
1419
- (rule 2 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.NotEqual) (splat x) y)
1420
- (rv_vmsne_vx y x (unmasked) ty))
1421
-
1422
- (rule 3 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.NotEqual) x (replicated_imm5 y))
1423
- (rv_vmsne_vi x y (unmasked) ty))
1424
-
1425
- (rule 4 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.NotEqual) (replicated_imm5 x) y)
1426
- (rv_vmsne_vi y x (unmasked) ty))
1427
-
1428
- ;; IntCC.UnsignedLessThan
1429
-
1430
- (rule 0 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.UnsignedLessThan) x y)
1431
- (rv_vmsltu_vv x y (unmasked) ty))
1432
-
1433
- (rule 1 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.UnsignedLessThan) x (splat y))
1434
- (rv_vmsltu_vx x y (unmasked) ty))
1435
-
1436
- (rule 2 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.UnsignedLessThan) (splat x) y)
1437
- (rv_vmsgtu_vx y x (unmasked) ty))
1438
-
1439
- (rule 4 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.UnsignedLessThan) (replicated_imm5 x) y)
1440
- (rv_vmsgtu_vi y x (unmasked) ty))
1441
-
1442
- ;; IntCC.SignedLessThan
1443
-
1444
- (rule 0 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.SignedLessThan) x y)
1445
- (rv_vmslt_vv x y (unmasked) ty))
1446
-
1447
- (rule 1 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.SignedLessThan) x (splat y))
1448
- (rv_vmslt_vx x y (unmasked) ty))
1449
-
1450
- (rule 2 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.SignedLessThan) (splat x) y)
1451
- (rv_vmsgt_vx y x (unmasked) ty))
1452
-
1453
- (rule 4 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.SignedLessThan) (replicated_imm5 x) y)
1454
- (rv_vmsgt_vi y x (unmasked) ty))
1455
-
1456
- ;; IntCC.UnsignedLessThanOrEqual
1457
-
1458
- (rule 0 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.UnsignedLessThanOrEqual) x y)
1459
- (rv_vmsleu_vv x y (unmasked) ty))
1460
-
1461
- (rule 1 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.UnsignedLessThanOrEqual) x (splat y))
1462
- (rv_vmsleu_vx x y (unmasked) ty))
1463
-
1464
- (rule 3 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.UnsignedLessThanOrEqual) x (replicated_imm5 y))
1465
- (rv_vmsleu_vi x y (unmasked) ty))
1466
-
1467
- ;; IntCC.SignedLessThanOrEqual
1468
-
1469
- (rule 0 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.SignedLessThanOrEqual) x y)
1470
- (rv_vmsle_vv x y (unmasked) ty))
1471
-
1472
- (rule 1 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.SignedLessThanOrEqual) x (splat y))
1473
- (rv_vmsle_vx x y (unmasked) ty))
1474
-
1475
- (rule 3 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.SignedLessThanOrEqual) x (replicated_imm5 y))
1476
- (rv_vmsle_vi x y (unmasked) ty))
1477
-
1478
- ;; IntCC.UnsignedGreaterThan
1479
-
1480
- (rule 0 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.UnsignedGreaterThan) x y)
1481
- (rv_vmsgtu_vv x y (unmasked) ty))
1482
-
1483
- (rule 1 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.UnsignedGreaterThan) x (splat y))
1484
- (rv_vmsgtu_vx x y (unmasked) ty))
1485
-
1486
- (rule 2 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.UnsignedGreaterThan) (splat x) y)
1487
- (rv_vmsltu_vx y x (unmasked) ty))
1488
-
1489
- (rule 3 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.UnsignedGreaterThan) x (replicated_imm5 y))
1490
- (rv_vmsgtu_vi x y (unmasked) ty))
1491
-
1492
- ;; IntCC.SignedGreaterThan
1493
-
1494
- (rule 0 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.SignedGreaterThan) x y)
1495
- (rv_vmsgt_vv x y (unmasked) ty))
1496
-
1497
- (rule 1 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.SignedGreaterThan) x (splat y))
1498
- (rv_vmsgt_vx x y (unmasked) ty))
1499
-
1500
- (rule 2 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.SignedGreaterThan) (splat x) y)
1501
- (rv_vmslt_vx y x (unmasked) ty))
1502
-
1503
- (rule 3 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.SignedGreaterThan) x (replicated_imm5 y))
1504
- (rv_vmsgt_vi x y (unmasked) ty))
1505
-
1506
- ;; IntCC.UnsignedGreaterThanOrEqual
1507
-
1508
- (rule 0 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.UnsignedGreaterThanOrEqual) x y)
1509
- (rv_vmsgeu_vv x y (unmasked) ty))
1510
-
1511
- (rule 2 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.UnsignedGreaterThanOrEqual) (splat x) y)
1512
- (rv_vmsleu_vx y x (unmasked) ty))
1513
-
1514
- (rule 4 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.UnsignedGreaterThanOrEqual) (replicated_imm5 x) y)
1515
- (rv_vmsleu_vi y x (unmasked) ty))
1516
-
1517
- ;; IntCC.SignedGreaterThanOrEqual
1518
-
1519
- (rule 0 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.SignedGreaterThanOrEqual) x y)
1520
- (rv_vmsge_vv x y (unmasked) ty))
1521
-
1522
- (rule 2 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.SignedGreaterThanOrEqual) (splat x) y)
1523
- (rv_vmsle_vx y x (unmasked) ty))
1524
-
1525
- (rule 4 (gen_icmp_mask (ty_vec_fits_in_register ty) (IntCC.SignedGreaterThanOrEqual) (replicated_imm5 x) y)
1526
- (rv_vmsle_vi y x (unmasked) ty))
1527
-
1528
-
1529
-
1530
- ;; Builds a vector mask corresponding to the FloatCC operation.
1531
- (decl gen_fcmp_mask (Type FloatCC Value Value) VReg)
1532
-
1533
- ;; FloatCC.Equal
1534
-
1535
- (rule 0 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.Equal) x y)
1536
- (rv_vmfeq_vv x y (unmasked) ty))
1537
-
1538
- (rule 1 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.Equal) x (splat y))
1539
- (rv_vmfeq_vf x y (unmasked) ty))
1540
-
1541
- (rule 2 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.Equal) (splat x) y)
1542
- (rv_vmfeq_vf y x (unmasked) ty))
1543
-
1544
- ;; FloatCC.NotEqual
1545
- ;; Note: This is UnorderedNotEqual. It is the only unoredered comparison that is not named as such.
1546
-
1547
- (rule 0 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.NotEqual) x y)
1548
- (rv_vmfne_vv x y (unmasked) ty))
1549
-
1550
- (rule 1 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.NotEqual) x (splat y))
1551
- (rv_vmfne_vf x y (unmasked) ty))
1552
-
1553
- (rule 2 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.NotEqual) (splat x) y)
1554
- (rv_vmfne_vf y x (unmasked) ty))
1555
-
1556
- ;; FloatCC.LessThan
1557
-
1558
- (rule 0 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.LessThan) x y)
1559
- (rv_vmflt_vv x y (unmasked) ty))
1560
-
1561
- (rule 1 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.LessThan) x (splat y))
1562
- (rv_vmflt_vf x y (unmasked) ty))
1563
-
1564
- (rule 2 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.LessThan) (splat x) y)
1565
- (rv_vmfgt_vf y x (unmasked) ty))
1566
-
1567
- ;; FloatCC.LessThanOrEqual
1568
-
1569
- (rule 0 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.LessThanOrEqual) x y)
1570
- (rv_vmfle_vv x y (unmasked) ty))
1571
-
1572
- (rule 1 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.LessThanOrEqual) x (splat y))
1573
- (rv_vmfle_vf x y (unmasked) ty))
1574
-
1575
- (rule 2 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.LessThanOrEqual) (splat x) y)
1576
- (rv_vmfge_vf y x (unmasked) ty))
1577
-
1578
- ;; FloatCC.GreaterThan
1579
-
1580
- (rule 0 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.GreaterThan) x y)
1581
- (rv_vmfgt_vv x y (unmasked) ty))
1582
-
1583
- (rule 1 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.GreaterThan) x (splat y))
1584
- (rv_vmfgt_vf x y (unmasked) ty))
1585
-
1586
- (rule 2 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.GreaterThan) (splat x) y)
1587
- (rv_vmflt_vf y x (unmasked) ty))
1588
-
1589
- ;; FloatCC.GreaterThanOrEqual
1590
-
1591
- (rule 0 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.GreaterThanOrEqual) x y)
1592
- (rv_vmfge_vv x y (unmasked) ty))
1593
-
1594
- (rule 1 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.GreaterThanOrEqual) x (splat y))
1595
- (rv_vmfge_vf x y (unmasked) ty))
1596
-
1597
- (rule 2 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.GreaterThanOrEqual) (splat x) y)
1598
- (rv_vmfle_vf y x (unmasked) ty))
1599
-
1600
- ;; FloatCC.Ordered
1601
-
1602
- (rule 0 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.Ordered) x y)
1603
- (rv_vmand_mm
1604
- (gen_fcmp_mask ty (FloatCC.Equal) x x)
1605
- (gen_fcmp_mask ty (FloatCC.Equal) y y)
1606
- ty))
1607
-
1608
- ;; FloatCC.Unordered
1609
-
1610
- (rule 0 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.Unordered) x y)
1611
- (rv_vmor_mm
1612
- (gen_fcmp_mask ty (FloatCC.NotEqual) x x)
1613
- (gen_fcmp_mask ty (FloatCC.NotEqual) y y)
1614
- ty))
1615
-
1616
- ;; FloatCC.OrderedNotEqual
1617
-
1618
- (rule 0 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.OrderedNotEqual) x y)
1619
- (rv_vmor_mm
1620
- (gen_fcmp_mask ty (FloatCC.LessThan) x y)
1621
- (gen_fcmp_mask ty (FloatCC.LessThan) y x)
1622
- ty))
1623
-
1624
- ;; FloatCC.UnorderedOrEqual
1625
-
1626
- (rule 0 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.UnorderedOrEqual) x y)
1627
- (rv_vmnor_mm
1628
- (gen_fcmp_mask ty (FloatCC.LessThan) x y)
1629
- (gen_fcmp_mask ty (FloatCC.LessThan) y x)
1630
- ty))
1631
-
1632
- ;; FloatCC.UnorderedOrGreaterThan
1633
-
1634
- (rule 0 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.UnorderedOrGreaterThan) x y)
1635
- (rv_vmnot_m (gen_fcmp_mask ty (FloatCC.LessThanOrEqual) x y) ty))
1636
-
1637
- ;; FloatCC.UnorderedOrGreaterThanOrEqual
1638
-
1639
- (rule 0 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.UnorderedOrGreaterThanOrEqual) x y)
1640
- (rv_vmnot_m (gen_fcmp_mask ty (FloatCC.LessThan) x y) ty))
1641
-
1642
- ;; FloatCC.UnorderedOrLessThan
1643
-
1644
- (rule 0 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.UnorderedOrLessThan) x y)
1645
- (rv_vmnot_m (gen_fcmp_mask ty (FloatCC.GreaterThanOrEqual) x y) ty))
1646
-
1647
- ;; FloatCC.UnorderedOrLessThanOrEqual
1648
-
1649
- (rule 0 (gen_fcmp_mask (ty_vec_fits_in_register ty) (FloatCC.UnorderedOrLessThanOrEqual) x y)
1650
- (rv_vmnot_m (gen_fcmp_mask ty (FloatCC.GreaterThan) x y) ty))