wasmtime 12.0.1 → 13.0.0

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Files changed (2318) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +176 -221
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/cargo-vendor/cap-net-ext-2.0.0/.cargo-checksum.json +1 -0
  5. data/ext/cargo-vendor/cap-net-ext-2.0.0/COPYRIGHT +29 -0
  6. data/ext/cargo-vendor/cap-net-ext-2.0.0/Cargo.toml +38 -0
  7. data/ext/cargo-vendor/cap-net-ext-2.0.0/README.md +24 -0
  8. data/ext/cargo-vendor/cap-net-ext-2.0.0/src/lib.rs +771 -0
  9. data/ext/cargo-vendor/cranelift-bforest-0.100.0/.cargo-checksum.json +1 -0
  10. data/ext/cargo-vendor/cranelift-bforest-0.100.0/Cargo.toml +31 -0
  11. data/ext/cargo-vendor/cranelift-bforest-0.100.0/src/lib.rs +184 -0
  12. data/ext/cargo-vendor/cranelift-bforest-0.100.0/src/map.rs +922 -0
  13. data/ext/cargo-vendor/cranelift-bforest-0.100.0/src/pool.rs +219 -0
  14. data/ext/cargo-vendor/cranelift-bforest-0.100.0/src/set.rs +597 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.100.0/.cargo-checksum.json +1 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.100.0/Cargo.toml +164 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/binemit/mod.rs +141 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/binemit/stack_map.rs +155 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/bitset.rs +166 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/context.rs +372 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/incremental_cache.rs +256 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/atomic_rmw_op.rs +104 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/condcodes.rs +404 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/constant.rs +463 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/dfg.rs +1686 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/dynamic_type.rs +55 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/entities.rs +567 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/extfunc.rs +411 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/extname.rs +333 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/function.rs +475 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/globalvalue.rs +155 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/immediates.rs +1615 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/instructions.rs +1000 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/jumptable.rs +168 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/known_symbol.rs +47 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/libcall.rs +232 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/memflags.rs +279 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/mod.rs +106 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/sourceloc.rs +117 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/stackslot.rs +216 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/table.rs +40 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/trapcode.rs +144 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/ir/types.rs +630 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/abi.rs +1573 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/inst/args.rs +747 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/inst/emit.rs +3911 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/inst/emit_tests.rs +7951 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/inst/mod.rs +3049 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/inst.isle +4173 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/lower/isle.rs +871 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/lower.isle +2889 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/lower.rs +132 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/aarch64/lower_dynamic_neon.isle +98 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/call_conv.rs +119 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/abi.rs +981 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst/args.rs +1900 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst/emit.rs +3203 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst/encode.rs +326 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst/imms.rs +236 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst/mod.rs +2162 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst/vector.rs +1059 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst.isle +3092 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/inst_vector.isle +1887 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/lower/isle.rs +620 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/riscv64/lower.isle +2119 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/s390x/abi.rs +949 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/s390x/inst/mod.rs +3430 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/s390x/inst.isle +5043 -0
  69. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/s390x/lower.isle +3982 -0
  70. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/unwind/systemv.rs +272 -0
  71. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/unwind/winx64.rs +334 -0
  72. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/unwind.rs +182 -0
  73. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/abi.rs +1200 -0
  74. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/encoding/evex.rs +749 -0
  75. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/encoding/rex.rs +589 -0
  76. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/inst/args.rs +2188 -0
  77. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/inst/emit.rs +4300 -0
  78. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/inst/emit_tests.rs +5474 -0
  79. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/inst/mod.rs +2763 -0
  80. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/inst.isle +5110 -0
  81. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/lower/isle.rs +1096 -0
  82. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/lower.isle +4675 -0
  83. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isa/x64/lower.rs +340 -0
  84. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/isle_prelude.rs +899 -0
  85. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/legalizer/mod.rs +356 -0
  86. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/lib.rs +107 -0
  87. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/machinst/abi.rs +2644 -0
  88. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/machinst/buffer.rs +2362 -0
  89. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/machinst/isle.rs +846 -0
  90. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/machinst/mod.rs +553 -0
  91. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/machinst/reg.rs +556 -0
  92. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/machinst/vcode.rs +1646 -0
  93. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/opts/bitops.isle +147 -0
  94. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/opts/cprop.isle +200 -0
  95. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/opts/extends.isle +34 -0
  96. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/opts/icmp.isle +177 -0
  97. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/opts/selects.isle +59 -0
  98. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/opts/vector.isle +88 -0
  99. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/prelude.isle +603 -0
  100. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/prelude_lower.isle +1029 -0
  101. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/value_label.rs +32 -0
  102. data/ext/cargo-vendor/cranelift-codegen-0.100.0/src/verifier/mod.rs +1986 -0
  103. data/ext/cargo-vendor/cranelift-codegen-meta-0.100.0/.cargo-checksum.json +1 -0
  104. data/ext/cargo-vendor/cranelift-codegen-meta-0.100.0/Cargo.toml +26 -0
  105. data/ext/cargo-vendor/cranelift-codegen-meta-0.100.0/src/constant_hash.rs +63 -0
  106. data/ext/cargo-vendor/cranelift-codegen-meta-0.100.0/src/gen_inst.rs +1784 -0
  107. data/ext/cargo-vendor/cranelift-codegen-meta-0.100.0/src/shared/instructions.rs +3810 -0
  108. data/ext/cargo-vendor/cranelift-codegen-shared-0.100.0/.cargo-checksum.json +1 -0
  109. data/ext/cargo-vendor/cranelift-codegen-shared-0.100.0/Cargo.toml +22 -0
  110. data/ext/cargo-vendor/cranelift-codegen-shared-0.100.0/src/lib.rs +12 -0
  111. data/ext/cargo-vendor/cranelift-control-0.100.0/.cargo-checksum.json +1 -0
  112. data/ext/cargo-vendor/cranelift-control-0.100.0/Cargo.toml +30 -0
  113. data/ext/cargo-vendor/cranelift-entity-0.100.0/.cargo-checksum.json +1 -0
  114. data/ext/cargo-vendor/cranelift-entity-0.100.0/Cargo.toml +41 -0
  115. data/ext/cargo-vendor/cranelift-entity-0.100.0/src/lib.rs +316 -0
  116. data/ext/cargo-vendor/cranelift-entity-0.100.0/src/list.rs +955 -0
  117. data/ext/cargo-vendor/cranelift-entity-0.100.0/src/packed_option.rs +171 -0
  118. data/ext/cargo-vendor/cranelift-entity-0.100.0/src/primary.rs +456 -0
  119. data/ext/cargo-vendor/cranelift-entity-0.100.0/src/sparse.rs +368 -0
  120. data/ext/cargo-vendor/cranelift-frontend-0.100.0/.cargo-checksum.json +1 -0
  121. data/ext/cargo-vendor/cranelift-frontend-0.100.0/Cargo.toml +54 -0
  122. data/ext/cargo-vendor/cranelift-frontend-0.100.0/src/lib.rs +191 -0
  123. data/ext/cargo-vendor/cranelift-isle-0.100.0/.cargo-checksum.json +1 -0
  124. data/ext/cargo-vendor/cranelift-isle-0.100.0/Cargo.toml +37 -0
  125. data/ext/cargo-vendor/cranelift-native-0.100.0/.cargo-checksum.json +1 -0
  126. data/ext/cargo-vendor/cranelift-native-0.100.0/Cargo.toml +38 -0
  127. data/ext/cargo-vendor/cranelift-native-0.100.0/src/lib.rs +190 -0
  128. data/ext/cargo-vendor/cranelift-wasm-0.100.0/.cargo-checksum.json +1 -0
  129. data/ext/cargo-vendor/cranelift-wasm-0.100.0/Cargo.toml +92 -0
  130. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/code_translator.rs +3641 -0
  131. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/environ/dummy.rs +942 -0
  132. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/environ/spec.rs +949 -0
  133. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/func_translator.rs +432 -0
  134. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/heap.rs +108 -0
  135. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/lib.rs +64 -0
  136. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/sections_translator.rs +408 -0
  137. data/ext/cargo-vendor/cranelift-wasm-0.100.0/src/translation_utils.rs +97 -0
  138. data/ext/cargo-vendor/fallible-iterator-0.3.0/.cargo-checksum.json +1 -0
  139. data/ext/cargo-vendor/fallible-iterator-0.3.0/CHANGELOG.md +39 -0
  140. data/ext/cargo-vendor/fallible-iterator-0.3.0/Cargo.toml +29 -0
  141. data/ext/cargo-vendor/fallible-iterator-0.3.0/README.md +16 -0
  142. data/ext/cargo-vendor/fallible-iterator-0.3.0/src/lib.rs +2808 -0
  143. data/ext/cargo-vendor/fallible-iterator-0.3.0/src/test.rs +477 -0
  144. data/ext/cargo-vendor/serde-1.0.188/.cargo-checksum.json +1 -0
  145. data/ext/cargo-vendor/serde-1.0.188/Cargo.toml +69 -0
  146. data/ext/cargo-vendor/serde-1.0.188/build.rs +90 -0
  147. data/ext/cargo-vendor/serde-1.0.188/src/de/ignored_any.rs +238 -0
  148. data/ext/cargo-vendor/serde-1.0.188/src/de/impls.rs +2966 -0
  149. data/ext/cargo-vendor/serde-1.0.188/src/de/mod.rs +2290 -0
  150. data/ext/cargo-vendor/serde-1.0.188/src/de/value.rs +1708 -0
  151. data/ext/cargo-vendor/serde-1.0.188/src/integer128.rs +9 -0
  152. data/ext/cargo-vendor/serde-1.0.188/src/lib.rs +327 -0
  153. data/ext/cargo-vendor/serde-1.0.188/src/macros.rs +231 -0
  154. data/ext/cargo-vendor/serde-1.0.188/src/ser/fmt.rs +170 -0
  155. data/ext/cargo-vendor/serde-1.0.188/src/ser/impls.rs +998 -0
  156. data/ext/cargo-vendor/serde-1.0.188/src/ser/mod.rs +1952 -0
  157. data/ext/cargo-vendor/serde_derive-1.0.188/.cargo-checksum.json +1 -0
  158. data/ext/cargo-vendor/serde_derive-1.0.188/Cargo.toml +59 -0
  159. data/ext/cargo-vendor/serde_derive-1.0.188/src/lib.rs +102 -0
  160. data/ext/cargo-vendor/serde_derive-1.0.188/src/ser.rs +1359 -0
  161. data/ext/cargo-vendor/wasi-cap-std-sync-13.0.0/.cargo-checksum.json +1 -0
  162. data/ext/cargo-vendor/wasi-cap-std-sync-13.0.0/Cargo.toml +96 -0
  163. data/ext/cargo-vendor/wasi-cap-std-sync-13.0.0/src/lib.rs +161 -0
  164. data/ext/cargo-vendor/wasi-common-13.0.0/.cargo-checksum.json +1 -0
  165. data/ext/cargo-vendor/wasi-common-13.0.0/Cargo.toml +87 -0
  166. data/ext/cargo-vendor/wasm-encoder-0.32.0/.cargo-checksum.json +1 -0
  167. data/ext/cargo-vendor/wasm-encoder-0.32.0/Cargo.toml +33 -0
  168. data/ext/cargo-vendor/wasm-encoder-0.32.0/src/component/types.rs +769 -0
  169. data/ext/cargo-vendor/wasm-encoder-0.33.1/.cargo-checksum.json +1 -0
  170. data/ext/cargo-vendor/wasm-encoder-0.33.1/Cargo.toml +33 -0
  171. data/ext/cargo-vendor/wasm-encoder-0.33.1/README.md +80 -0
  172. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/aliases.rs +160 -0
  173. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/builder.rs +449 -0
  174. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/canonicals.rs +159 -0
  175. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/components.rs +29 -0
  176. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/exports.rs +127 -0
  177. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/imports.rs +200 -0
  178. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/instances.rs +200 -0
  179. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/modules.rs +29 -0
  180. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/names.rs +149 -0
  181. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/start.rs +52 -0
  182. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component/types.rs +769 -0
  183. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/component.rs +168 -0
  184. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/code.rs +2913 -0
  185. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/custom.rs +73 -0
  186. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/data.rs +185 -0
  187. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/dump.rs +627 -0
  188. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/elements.rs +220 -0
  189. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/exports.rs +85 -0
  190. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/functions.rs +63 -0
  191. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/globals.rs +90 -0
  192. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/imports.rs +142 -0
  193. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/linking.rs +263 -0
  194. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/memories.rs +99 -0
  195. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/names.rs +265 -0
  196. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/producers.rs +180 -0
  197. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/start.rs +39 -0
  198. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/tables.rs +104 -0
  199. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/tags.rs +85 -0
  200. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core/types.rs +372 -0
  201. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/core.rs +168 -0
  202. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/lib.rs +215 -0
  203. data/ext/cargo-vendor/wasm-encoder-0.33.1/src/raw.rs +30 -0
  204. data/ext/cargo-vendor/wasmparser-0.112.0/.cargo-checksum.json +1 -0
  205. data/ext/cargo-vendor/wasmparser-0.112.0/Cargo.lock +644 -0
  206. data/ext/cargo-vendor/wasmparser-0.112.0/Cargo.toml +54 -0
  207. data/ext/cargo-vendor/wasmparser-0.112.0/src/limits.rs +58 -0
  208. data/ext/cargo-vendor/wasmparser-0.112.0/src/readers/component/types.rs +542 -0
  209. data/ext/cargo-vendor/wasmparser-0.112.0/src/readers/core/types.rs +1303 -0
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  1253. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/s390x/settings.rs +0 -0
  1254. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/encoding/mod.rs +0 -0
  1255. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/encoding/vex.rs +0 -0
  1256. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/inst/emit_state.rs +0 -0
  1257. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/inst/regs.rs +0 -0
  1258. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1259. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1260. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/inst/unwind.rs +0 -0
  1261. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1262. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/mod.rs +0 -0
  1263. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/isa/x64/settings.rs +0 -0
  1264. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/iterators.rs +0 -0
  1265. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/legalizer/globalvalue.rs +0 -0
  1266. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/legalizer/table.rs +0 -0
  1267. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/loop_analysis.rs +0 -0
  1268. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/machinst/blockorder.rs +0 -0
  1269. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/machinst/compile.rs +0 -0
  1270. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/machinst/helpers.rs +0 -0
  1271. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/machinst/inst_common.rs +0 -0
  1272. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/machinst/lower.rs +0 -0
  1273. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/machinst/valueregs.rs +0 -0
  1274. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/nan_canonicalization.rs +0 -0
  1275. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/opts/README.md +0 -0
  1276. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/opts/arithmetic.isle +0 -0
  1277. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/opts/generated_code.rs +0 -0
  1278. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/opts/remat.isle +0 -0
  1279. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/opts/shifts.isle +0 -0
  1280. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/opts.rs +0 -0
  1281. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/prelude_opt.isle +0 -0
  1282. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/print_errors.rs +0 -0
  1283. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/remove_constant_phis.rs +0 -0
  1284. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/result.rs +0 -0
  1285. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/scoped_hash_map.rs +0 -0
  1286. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/settings.rs +0 -0
  1287. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/souper_harvest.rs +0 -0
  1288. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/timing.rs +0 -0
  1289. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/unionfind.rs +0 -0
  1290. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/unreachable_code.rs +0 -0
  1291. /data/ext/cargo-vendor/{cranelift-codegen-0.99.1 → cranelift-codegen-0.100.0}/src/write.rs +0 -0
  1292. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.99.1 → cranelift-codegen-meta-0.100.0}/LICENSE +0 -0
  1293. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/README.md +0 -0
  1294. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/formats.rs +0 -0
  1295. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/instructions.rs +0 -0
  1296. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/isa.rs +0 -0
  1297. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/mod.rs +0 -0
  1298. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/operands.rs +0 -0
  1299. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/settings.rs +0 -0
  1300. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/types.rs +0 -0
  1301. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/cdsl/typevar.rs +0 -0
  1302. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/error.rs +0 -0
  1303. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/gen_settings.rs +0 -0
  1304. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/gen_types.rs +0 -0
  1305. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/isa/arm64.rs +0 -0
  1306. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/isa/mod.rs +0 -0
  1307. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/isa/riscv64.rs +0 -0
  1308. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/isa/s390x.rs +0 -0
  1309. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/isa/x86.rs +0 -0
  1310. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/lib.rs +0 -0
  1311. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/shared/entities.rs +0 -0
  1312. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/shared/formats.rs +0 -0
  1313. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/shared/immediates.rs +0 -0
  1314. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/shared/mod.rs +0 -0
  1315. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/shared/settings.rs +0 -0
  1316. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/shared/types.rs +0 -0
  1317. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/srcgen.rs +0 -0
  1318. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.99.1 → cranelift-codegen-meta-0.100.0}/src/unique_table.rs +0 -0
  1319. /data/ext/cargo-vendor/{cranelift-control-0.99.1 → cranelift-codegen-shared-0.100.0}/LICENSE +0 -0
  1320. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.99.1 → cranelift-codegen-shared-0.100.0}/README.md +0 -0
  1321. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.99.1 → cranelift-codegen-shared-0.100.0}/src/constant_hash.rs +0 -0
  1322. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.99.1 → cranelift-codegen-shared-0.100.0}/src/constants.rs +0 -0
  1323. /data/ext/cargo-vendor/{cranelift-entity-0.99.1 → cranelift-control-0.100.0}/LICENSE +0 -0
  1324. /data/ext/cargo-vendor/{cranelift-control-0.99.1 → cranelift-control-0.100.0}/README.md +0 -0
  1325. /data/ext/cargo-vendor/{cranelift-control-0.99.1 → cranelift-control-0.100.0}/src/chaos.rs +0 -0
  1326. /data/ext/cargo-vendor/{cranelift-control-0.99.1 → cranelift-control-0.100.0}/src/lib.rs +0 -0
  1327. /data/ext/cargo-vendor/{cranelift-control-0.99.1 → cranelift-control-0.100.0}/src/zero_sized.rs +0 -0
  1328. /data/ext/cargo-vendor/{cranelift-frontend-0.99.1 → cranelift-entity-0.100.0}/LICENSE +0 -0
  1329. /data/ext/cargo-vendor/{cranelift-entity-0.99.1 → cranelift-entity-0.100.0}/README.md +0 -0
  1330. /data/ext/cargo-vendor/{cranelift-entity-0.99.1 → cranelift-entity-0.100.0}/src/boxed_slice.rs +0 -0
  1331. /data/ext/cargo-vendor/{cranelift-entity-0.99.1 → cranelift-entity-0.100.0}/src/iter.rs +0 -0
  1332. /data/ext/cargo-vendor/{cranelift-entity-0.99.1 → cranelift-entity-0.100.0}/src/keys.rs +0 -0
  1333. /data/ext/cargo-vendor/{cranelift-entity-0.99.1 → cranelift-entity-0.100.0}/src/map.rs +0 -0
  1334. /data/ext/cargo-vendor/{cranelift-entity-0.99.1 → cranelift-entity-0.100.0}/src/set.rs +0 -0
  1335. /data/ext/cargo-vendor/{cranelift-native-0.99.1 → cranelift-frontend-0.100.0}/LICENSE +0 -0
  1336. /data/ext/cargo-vendor/{cranelift-frontend-0.99.1 → cranelift-frontend-0.100.0}/README.md +0 -0
  1337. /data/ext/cargo-vendor/{cranelift-frontend-0.99.1 → cranelift-frontend-0.100.0}/src/frontend.rs +0 -0
  1338. /data/ext/cargo-vendor/{cranelift-frontend-0.99.1 → cranelift-frontend-0.100.0}/src/ssa.rs +0 -0
  1339. /data/ext/cargo-vendor/{cranelift-frontend-0.99.1 → cranelift-frontend-0.100.0}/src/switch.rs +0 -0
  1340. /data/ext/cargo-vendor/{cranelift-frontend-0.99.1 → cranelift-frontend-0.100.0}/src/variable.rs +0 -0
  1341. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/README.md +0 -0
  1342. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/build.rs +0 -0
  1343. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/bad_converters.isle +0 -0
  1344. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1345. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1346. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/error1.isle +0 -0
  1347. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/extra_parens.isle +0 -0
  1348. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/impure_expression.isle +0 -0
  1349. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/impure_rhs.isle +0 -0
  1350. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1351. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/fail/multi_prio.isle +0 -0
  1352. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/borrows.isle +0 -0
  1353. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/borrows_main.rs +0 -0
  1354. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/iflets.isle +0 -0
  1355. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/iflets_main.rs +0 -0
  1356. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/multi_constructor.isle +0 -0
  1357. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/multi_constructor_main.rs +0 -0
  1358. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/multi_extractor.isle +0 -0
  1359. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/multi_extractor_main.rs +0 -0
  1360. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/test.isle +0 -0
  1361. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/link/test_main.rs +0 -0
  1362. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/bound_var.isle +0 -0
  1363. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/construct_and_extract.isle +0 -0
  1364. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/conversions.isle +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/conversions_extern.isle +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/let.isle +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/nodebug.isle +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/prio_trie_bug.isle +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/test2.isle +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/test3.isle +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/test4.isle +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/pass/tutorial.isle +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/run/iconst.isle +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/run/iconst_main.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/run/let_shadowing.isle +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/isle_examples/run/let_shadowing_main.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/ast.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/codegen.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/compile.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/error.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/lexer.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/lib.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/log.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/overlap.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/parser.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/sema.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/serialize.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/src/trie_again.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-isle-0.99.1 → cranelift-isle-0.100.0}/tests/run_tests.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-wasm-0.99.1 → cranelift-native-0.100.0}/LICENSE +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-native-0.99.1 → cranelift-native-0.100.0}/README.md +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-native-0.99.1 → cranelift-native-0.100.0}/src/riscv.rs +0 -0
  1393. /data/ext/cargo-vendor/{wasi-cap-std-sync-12.0.1 → cranelift-wasm-0.100.0}/LICENSE +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-wasm-0.99.1 → cranelift-wasm-0.100.0}/README.md +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-wasm-0.99.1 → cranelift-wasm-0.100.0}/src/code_translator/bounds_checks.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-wasm-0.99.1 → cranelift-wasm-0.100.0}/src/environ/mod.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-wasm-0.99.1 → cranelift-wasm-0.100.0}/src/module_translator.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-wasm-0.99.1 → cranelift-wasm-0.100.0}/src/state.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-wasm-0.99.1 → cranelift-wasm-0.100.0}/tests/wasm_testsuite.rs +0 -0
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  1492. /data/ext/cargo-vendor/{wasi-cap-std-sync-12.0.1 → wasi-cap-std-sync-13.0.0}/src/net.rs +0 -0
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  1496. /data/ext/cargo-vendor/{wasi-cap-std-sync-12.0.1 → wasi-cap-std-sync-13.0.0}/src/stdio.rs +0 -0
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  1551. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/component/modules.rs +0 -0
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  1557. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/data.rs +0 -0
  1558. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/dump.rs +0 -0
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  1564. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/linking.rs +0 -0
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  1567. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/producers.rs +0 -0
  1568. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/start.rs +0 -0
  1569. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/tables.rs +0 -0
  1570. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/tags.rs +0 -0
  1571. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core/types.rs +0 -0
  1572. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/core.rs +0 -0
  1573. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/lib.rs +0 -0
  1574. /data/ext/cargo-vendor/{wasm-encoder-0.31.1 → wasm-encoder-0.32.0}/src/raw.rs +0 -0
  1575. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasm-encoder-0.33.1}/LICENSE +0 -0
  1576. /data/ext/cargo-vendor/{wasmprinter-0.2.63 → wasmparser-0.112.0}/LICENSE +0 -0
  1577. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/README.md +0 -0
  1578. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/benches/benchmark.rs +0 -0
  1579. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/examples/simple.rs +0 -0
  1580. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/binary_reader.rs +0 -0
  1581. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/lib.rs +0 -0
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  1584. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/component/canonicals.rs +0 -0
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  1590. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/component.rs +0 -0
  1591. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/code.rs +0 -0
  1592. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/coredumps.rs +0 -0
  1593. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/custom.rs +0 -0
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  1595. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.112.0}/src/readers/core/dylink0.rs +0 -0
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  1598. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/functions.rs +0 -0
  1599. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/globals.rs +0 -0
  1600. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/imports.rs +0 -0
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  1604. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/operators.rs +0 -0
  1605. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/readers/core/producers.rs +0 -0
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  1613. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/src/validator/operators.rs +0 -0
  1614. /data/ext/cargo-vendor/{wasmparser-0.110.0 → wasmparser-0.112.0}/tests/big-module.rs +0 -0
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  1617. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/benches/benchmark.rs +0 -0
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  1623. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/component/imports.rs +0 -0
  1624. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/component/instances.rs +0 -0
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  1629. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/coredumps.rs +0 -0
  1630. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/custom.rs +0 -0
  1631. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/data.rs +0 -0
  1632. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/elements.rs +0 -0
  1633. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/exports.rs +0 -0
  1634. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/functions.rs +0 -0
  1635. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/globals.rs +0 -0
  1636. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/imports.rs +0 -0
  1637. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/init.rs +0 -0
  1638. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/memories.rs +0 -0
  1639. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/names.rs +0 -0
  1640. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/operators.rs +0 -0
  1641. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/producers.rs +0 -0
  1642. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/tables.rs +0 -0
  1643. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/readers/core/tags.rs +0 -0
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  1647. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/src/validator/names.rs +0 -0
  1648. /data/ext/cargo-vendor/{wasmparser-0.111.0 → wasmparser-0.113.1}/tests/big-module.rs +0 -0
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  1651. /data/ext/cargo-vendor/{wasmprinter-0.2.63 → wasmprinter-0.2.66}/tests/all.rs +0 -0
  1652. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-13.0.0}/LICENSE +0 -0
  1653. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/README.md +0 -0
  1654. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/code.rs +0 -0
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  1657. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/component/func/options.rs +0 -0
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  1661. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/component/storage.rs +0 -0
  1662. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/component/store.rs +0 -0
  1663. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/coredump.rs +0 -0
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  1665. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/func/typed.rs +0 -0
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  1668. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/linker.rs +0 -0
  1669. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/memory.rs +0 -0
  1670. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/module/registry.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/profiling.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/ref.rs +0 -0
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  1675. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/store/context.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/store/data.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/store/func_refs.rs +0 -0
  1678. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/trampoline/func.rs +0 -0
  1679. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/trampoline/global.rs +0 -0
  1680. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/trampoline/table.rs +0 -0
  1681. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/trap.rs +0 -0
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  1684. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/unix.rs +0 -0
  1685. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/values.rs +0 -0
  1686. /data/ext/cargo-vendor/{wasmtime-12.0.1 → wasmtime-13.0.0}/src/windows.rs +0 -0
  1687. /data/ext/cargo-vendor/{wasmtime-asm-macros-12.0.1 → wasmtime-asm-macros-13.0.0}/src/lib.rs +0 -0
  1688. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-cache-13.0.0}/LICENSE +0 -0
  1689. /data/ext/cargo-vendor/{wasmtime-cache-12.0.1 → wasmtime-cache-13.0.0}/build.rs +0 -0
  1690. /data/ext/cargo-vendor/{wasmtime-cache-12.0.1 → wasmtime-cache-13.0.0}/src/config/tests.rs +0 -0
  1691. /data/ext/cargo-vendor/{wasmtime-cache-12.0.1 → wasmtime-cache-13.0.0}/src/lib.rs +0 -0
  1692. /data/ext/cargo-vendor/{wasmtime-cache-12.0.1 → wasmtime-cache-13.0.0}/src/tests.rs +0 -0
  1693. /data/ext/cargo-vendor/{wasmtime-cache-12.0.1 → wasmtime-cache-13.0.0}/src/worker/tests/system_time_stub.rs +0 -0
  1694. /data/ext/cargo-vendor/{wasmtime-cache-12.0.1 → wasmtime-cache-13.0.0}/tests/cache_write_default_config.rs +0 -0
  1695. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/src/lib.rs +0 -0
  1696. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/char.wit +0 -0
  1697. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/conventions.wit +0 -0
  1698. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/direct-import.wit +0 -0
  1699. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/empty.wit +0 -0
  1700. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/flags.wit +0 -0
  1701. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/floats.wit +0 -0
  1702. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/function-new.wit +0 -0
  1703. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/integers.wit +0 -0
  1704. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/lists.wit +0 -0
  1705. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/many-arguments.wit +0 -0
  1706. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/multi-return.wit +0 -0
  1707. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/records.wit +0 -0
  1708. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/rename.wit +0 -0
  1709. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/share-types.wit +0 -0
  1710. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/simple-functions.wit +0 -0
  1711. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/simple-lists.wit +0 -0
  1712. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/simple-wasi.wit +0 -0
  1713. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/small-anonymous.wit +0 -0
  1714. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/smoke-default.wit +0 -0
  1715. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/smoke-export.wit +0 -0
  1716. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/smoke.wit +0 -0
  1717. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/strings.wit +0 -0
  1718. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/use-paths.wit +0 -0
  1719. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen/worlds-with-types.wit +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-component-macro-12.0.1 → wasmtime-component-macro-13.0.0}/tests/codegen.rs +0 -0
  1721. /data/ext/cargo-vendor/{wasmtime-component-util-12.0.1 → wasmtime-component-util-13.0.0}/src/lib.rs +0 -0
  1722. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-cranelift-13.0.0}/LICENSE +0 -0
  1723. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/SECURITY.md +0 -0
  1724. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/compiler/component.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/gc.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/address_transform.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/expression.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/line_program.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/mod.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/range_info_builder.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/refs.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/simulate.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/unit.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/transform/utils.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/debug/write_debuginfo.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmtime-cranelift-12.0.1 → wasmtime-cranelift-13.0.0}/src/lib.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-12.0.1 → wasmtime-cranelift-shared-13.0.0}/src/compiled_function.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-12.0.1 → wasmtime-cranelift-shared-13.0.0}/src/isa_builder.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-12.0.1 → wasmtime-cranelift-shared-13.0.0}/src/lib.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-12.0.1 → wasmtime-cranelift-shared-13.0.0}/src/obj.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-environ-13.0.0}/LICENSE +0 -0
  1742. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/examples/factc.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/component/dfg.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/component/translate/adapt.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/component/translate/inline.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/component/translate.rs +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/component/types/resources.rs +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/component/vmcomponent_offsets.rs +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/component.rs +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/fact/core_types.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/fact/signature.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/fact/traps.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/fact.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/obj.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/ref_bits.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/scopevec.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-environ-12.0.1 → wasmtime-environ-13.0.0}/src/trap_encoding.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-fiber-13.0.0}/LICENSE +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/build.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/lib.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/unix/aarch64.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/unix/arm.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/unix/riscv64.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/unix/s390x.S +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/unix/x86.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/unix/x86_64.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/unix.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/windows.c +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-fiber-12.0.1 → wasmtime-fiber-13.0.0}/src/windows.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-types-12.0.1 → wasmtime-jit-13.0.0}/LICENSE +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/code_memory.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/debug.rs +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/demangling.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/profiling/jitdump.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/profiling/perfmap.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/profiling/vtune.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/profiling.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-jit-12.0.1 → wasmtime-jit-13.0.0}/src/unwind.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-jit-debug-12.0.1 → wasmtime-jit-debug-13.0.0}/README.md +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-jit-debug-12.0.1 → wasmtime-jit-debug-13.0.0}/src/gdb_jit_int.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-jit-debug-12.0.1 → wasmtime-jit-debug-13.0.0}/src/lib.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-jit-debug-12.0.1 → wasmtime-jit-debug-13.0.0}/src/perf_jitdump.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-12.0.1 → wasmtime-jit-icache-coherence-13.0.0}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-12.0.1 → wasmtime-jit-icache-coherence-13.0.0}/src/libc.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-12.0.1 → wasmtime-jit-icache-coherence-13.0.0}/src/miri.rs +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-12.0.1 → wasmtime-jit-icache-coherence-13.0.0}/src/win.rs +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-runtime-13.0.0}/LICENSE +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/build.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/component/libcalls.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/component/resources.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/component.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/cow.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/debug_builtins.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/export.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/externref.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/helpers.c +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/imports.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/instance/allocator/pooling/unix.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/instance/allocator/pooling/windows.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/mmap/miri.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/mmap/unix.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/mmap/windows.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/mmap.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/mmap_vec.rs +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/module_id.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/send_sync_ptr.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/store_box.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/trampolines/aarch64.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/trampolines/riscv64.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/trampolines/s390x.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/trampolines/x86_64.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/trampolines.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/backtrace/s390x.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/backtrace.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/coredump.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/unix.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/traphandlers/windows.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-runtime-12.0.1 → wasmtime-runtime-13.0.0}/src/vmcontext/vm_host_func_context.rs +0 -0
  1822. /data/ext/cargo-vendor/{wast-63.0.0 → wasmtime-types-13.0.0}/LICENSE +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-types-12.0.1 → wasmtime-types-13.0.0}/src/error.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-versioned-export-macros-12.0.1 → wasmtime-versioned-export-macros-13.0.0}/src/lib.rs +0 -0
  1825. /data/ext/cargo-vendor/{wat-1.0.70 → wasmtime-wasi-13.0.0}/LICENSE +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/README.md +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/build.rs +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/src/preview2/clocks/host.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/src/preview2/clocks.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/src/preview2/error.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1/src/preview2/preview2 → wasmtime-wasi-13.0.0/src/preview2/host}/random.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/src/preview2/poll.rs +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/src/preview2/random.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1/wit/deps/wasi-cli-base → wasmtime-wasi-13.0.0/wit/deps/cli}/stdio.wit +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/clocks/monotonic-clock.wit +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/clocks/timezone.wit +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/clocks/wall-clock.wit +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/http/incoming-handler.wit +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/http/outgoing-handler.wit +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/poll/poll.wit +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/random/insecure-seed.wit +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/random/insecure.wit +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/random/random.wit +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/wit/deps/sockets/instance-network.wit +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/witx/typenames.witx +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-wasi-12.0.1 → wasmtime-wasi-13.0.0}/witx/wasi_snapshot_preview1.witx +0 -0
  1847. /data/ext/cargo-vendor/{file-per-thread-logger-0.2.0 → wasmtime-winch-13.0.0}/LICENSE +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-winch-12.0.1 → wasmtime-winch-13.0.0}/src/builder.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-winch-12.0.1 → wasmtime-winch-13.0.0}/src/compiler.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-winch-12.0.1 → wasmtime-winch-13.0.0}/src/lib.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-12.0.1 → wasmtime-wit-bindgen-13.0.0}/src/source.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-12.0.1 → wast-65.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/README.md +0 -0
  1854. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/alias.rs +0 -0
  1855. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/component.rs +0 -0
  1856. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/custom.rs +0 -0
  1857. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/export.rs +0 -0
  1858. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/func.rs +0 -0
  1859. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/import.rs +0 -0
  1860. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/instance.rs +0 -0
  1861. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/item_ref.rs +0 -0
  1862. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component/module.rs +0 -0
  1863. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/component.rs +0 -0
  1864. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/custom.rs +0 -0
  1865. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/export.rs +0 -0
  1866. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/func.rs +0 -0
  1867. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/global.rs +0 -0
  1868. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/import.rs +0 -0
  1869. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/memory.rs +0 -0
  1870. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/module.rs +0 -0
  1871. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/resolve/deinline_import_export.rs +0 -0
  1872. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/resolve/mod.rs +0 -0
  1873. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/resolve/names.rs +0 -0
  1874. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/resolve/types.rs +0 -0
  1875. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core/tag.rs +0 -0
  1876. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/core.rs +0 -0
  1877. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/encode.rs +0 -0
  1878. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/error.rs +0 -0
  1879. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/gensym.rs +0 -0
  1880. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/lexer.rs +0 -0
  1881. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/names.rs +0 -0
  1882. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/parser.rs +0 -0
  1883. /data/ext/cargo-vendor/{wast-63.0.0 → wast-65.0.1}/src/token.rs +0 -0
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  2009. /data/ext/cargo-vendor/{wiggle-12.0.1 → wiggle-13.0.0}/src/wasmtime.rs +0 -0
  2010. /data/ext/cargo-vendor/{wiggle-generate-12.0.1 → wiggle-generate-13.0.0}/README.md +0 -0
  2011. /data/ext/cargo-vendor/{wiggle-generate-12.0.1 → wiggle-generate-13.0.0}/src/codegen_settings.rs +0 -0
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  2017. /data/ext/cargo-vendor/{wiggle-generate-12.0.1 → wiggle-generate-13.0.0}/src/types/error.rs +0 -0
  2018. /data/ext/cargo-vendor/{wiggle-generate-12.0.1 → wiggle-generate-13.0.0}/src/types/flags.rs +0 -0
  2019. /data/ext/cargo-vendor/{wiggle-generate-12.0.1 → wiggle-generate-13.0.0}/src/types/handle.rs +0 -0
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  2022. /data/ext/cargo-vendor/{wiggle-macro-12.0.1 → wiggle-macro-13.0.0}/src/lib.rs +0 -0
  2023. /data/ext/cargo-vendor/{wasmtime-winch-12.0.1 → winch-codegen-0.11.0}/LICENSE +0 -0
  2024. /data/ext/cargo-vendor/{winch-codegen-0.10.1 → winch-codegen-0.11.0}/build.rs +0 -0
  2025. /data/ext/cargo-vendor/{winch-codegen-0.10.1 → winch-codegen-0.11.0}/src/abi/local.rs +0 -0
  2026. /data/ext/cargo-vendor/{winch-codegen-0.10.1 → winch-codegen-0.11.0}/src/codegen/env.rs +0 -0
  2027. /data/ext/cargo-vendor/{winch-codegen-0.10.1 → winch-codegen-0.11.0}/src/frame/mod.rs +0 -0
  2028. /data/ext/cargo-vendor/{winch-codegen-0.10.1 → winch-codegen-0.11.0}/src/isa/aarch64/mod.rs +0 -0
  2029. /data/ext/cargo-vendor/{winch-codegen-0.10.1 → winch-codegen-0.11.0}/src/isa/mod.rs +0 -0
  2030. /data/ext/cargo-vendor/{winch-codegen-0.10.1 → winch-codegen-0.11.0}/src/lib.rs +0 -0
  2031. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/README.md +0 -0
  2032. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/src/ast/toposort.rs +0 -0
  2033. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/comments.wit +0 -0
  2034. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/complex-include/deps/bar/root.wit +0 -0
  2035. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/complex-include/deps/baz/root.wit +0 -0
  2036. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/complex-include/root.wit +0 -0
  2037. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/cross-package-resource/deps/foo/foo.wit +0 -0
  2038. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/cross-package-resource/foo.wit +0 -0
  2039. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/diamond1/deps/dep1/types.wit +0 -0
  2040. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/diamond1/deps/dep2/types.wit +0 -0
  2041. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/diamond1/join.wit +0 -0
  2042. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/disambiguate-diamond/shared1.wit +0 -0
  2043. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/disambiguate-diamond/shared2.wit +0 -0
  2044. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/disambiguate-diamond/world.wit +0 -0
  2045. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/embedded.wit.md +0 -0
  2046. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/empty.wit +0 -0
  2047. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/deps/another-pkg/other-doc.wit +0 -0
  2048. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/deps/corp/saas.wit +0 -0
  2049. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/deps/different-pkg/the-doc.wit +0 -0
  2050. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/deps/foreign-pkg/the-doc.wit +0 -0
  2051. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/deps/some-pkg/some-doc.wit +0 -0
  2052. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/deps/wasi/clocks.wit +0 -0
  2053. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/deps/wasi/filesystem.wit +0 -0
  2054. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps/root.wit +0 -0
  2055. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/another-pkg/other-doc.wit +0 -0
  2056. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/corp/saas.wit +0 -0
  2057. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/different-pkg/the-doc.wit +0 -0
  2058. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/foreign-pkg/the-doc.wit +0 -0
  2059. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/some-pkg/some-doc.wit +0 -0
  2060. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/wasi/clocks.wit +0 -0
  2061. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/wasi/filesystem.wit +0 -0
  2062. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/deps/wasi/wasi.wit +0 -0
  2063. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/foreign-deps-union/root.wit +0 -0
  2064. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/functions.wit +0 -0
  2065. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/ignore-files-deps/deps/bar/types.wit +0 -0
  2066. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/ignore-files-deps/deps/ignore-me.txt +0 -0
  2067. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/ignore-files-deps/world.wit +0 -0
  2068. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/include-reps.wit +0 -0
  2069. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/kebab-name-include-with.wit +0 -0
  2070. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/many-names/a.wit +0 -0
  2071. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/many-names/b.wit +0 -0
  2072. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/multi-file/bar.wit +0 -0
  2073. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/multi-file/cycle-a.wit +0 -0
  2074. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/multi-file/cycle-b.wit +0 -0
  2075. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/multi-file/foo.wit +0 -0
  2076. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/name-both-resource-and-type/deps/dep/foo.wit +0 -0
  2077. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/name-both-resource-and-type/foo.wit +0 -0
  2078. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/package-syntax1.wit +0 -0
  2079. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/package-syntax3.wit +0 -0
  2080. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/package-syntax4.wit +0 -0
  2081. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  2082. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/alias-no-type.wit.result +0 -0
  2083. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/async.wit.result +0 -0
  2084. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/async1.wit.result +0 -0
  2085. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-function.wit +0 -0
  2086. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-function.wit.result +0 -0
  2087. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-function2.wit +0 -0
  2088. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-function2.wit.result +0 -0
  2089. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-include1.wit +0 -0
  2090. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-include1.wit.result +0 -0
  2091. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-include2.wit +0 -0
  2092. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-include2.wit.result +0 -0
  2093. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-include3.wit +0 -0
  2094. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-include3.wit.result +0 -0
  2095. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-list.wit +0 -0
  2096. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  2097. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg1/root.wit +0 -0
  2098. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg1.wit.result +0 -0
  2099. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg2/deps/bar/empty.wit +0 -0
  2100. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg2/root.wit +0 -0
  2101. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg2.wit.result +0 -0
  2102. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg3/deps/bar/baz.wit +0 -0
  2103. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg3/root.wit +0 -0
  2104. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg3.wit.result +0 -0
  2105. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg4/deps/bar/baz.wit +0 -0
  2106. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg4/root.wit +0 -0
  2107. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg4.wit.result +0 -0
  2108. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg5/deps/bar/baz.wit +0 -0
  2109. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg5/root.wit +0 -0
  2110. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg5.wit.result +0 -0
  2111. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg6/deps/bar/baz.wit +0 -0
  2112. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg6/root.wit +0 -0
  2113. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-pkg6.wit.result +0 -0
  2114. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource1.wit +0 -0
  2115. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource1.wit.result +0 -0
  2116. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource10.wit +0 -0
  2117. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource10.wit.result +0 -0
  2118. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource11.wit +0 -0
  2119. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource11.wit.result +0 -0
  2120. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource12.wit +0 -0
  2121. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource12.wit.result +0 -0
  2122. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource13.wit +0 -0
  2123. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource13.wit.result +0 -0
  2124. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource14.wit +0 -0
  2125. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource14.wit.result +0 -0
  2126. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource15/deps/foo/foo.wit +0 -0
  2127. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource15/foo.wit +0 -0
  2128. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource15.wit.result +0 -0
  2129. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource2.wit +0 -0
  2130. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource2.wit.result +0 -0
  2131. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource3.wit +0 -0
  2132. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource3.wit.result +0 -0
  2133. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource4.wit +0 -0
  2134. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource4.wit.result +0 -0
  2135. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource5.wit +0 -0
  2136. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource5.wit.result +0 -0
  2137. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource6.wit +0 -0
  2138. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource6.wit.result +0 -0
  2139. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource7.wit +0 -0
  2140. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource7.wit.result +0 -0
  2141. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource8.wit +0 -0
  2142. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource8.wit.result +0 -0
  2143. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource9.wit +0 -0
  2144. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-resource9.wit.result +0 -0
  2145. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-world-type1.wit +0 -0
  2146. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/bad-world-type1.wit.result +0 -0
  2147. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/conflicting-package/a.wit +0 -0
  2148. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/conflicting-package/b.wit +0 -0
  2149. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/conflicting-package.wit.result +0 -0
  2150. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle.wit +0 -0
  2151. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle.wit.result +0 -0
  2152. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle2.wit +0 -0
  2153. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle2.wit.result +0 -0
  2154. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle3.wit +0 -0
  2155. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle3.wit.result +0 -0
  2156. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle4.wit +0 -0
  2157. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle4.wit.result +0 -0
  2158. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle5.wit +0 -0
  2159. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/cycle5.wit.result +0 -0
  2160. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/dangling-type.wit +0 -0
  2161. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  2162. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-functions.wit +0 -0
  2163. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-functions.wit.result +0 -0
  2164. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-interface.wit +0 -0
  2165. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-interface.wit.result +0 -0
  2166. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-interface2/foo.wit +0 -0
  2167. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-interface2/foo2.wit +0 -0
  2168. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-interface2.wit.result +0 -0
  2169. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-type.wit +0 -0
  2170. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/duplicate-type.wit.result +0 -0
  2171. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/empty-enum.wit +0 -0
  2172. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/empty-enum.wit.result +0 -0
  2173. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/empty-variant1.wit +0 -0
  2174. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/empty-variant1.wit.result +0 -0
  2175. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/export-twice.wit +0 -0
  2176. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/export-twice.wit.result +0 -0
  2177. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export1.wit +0 -0
  2178. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export1.wit.result +0 -0
  2179. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export2.wit +0 -0
  2180. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export2.wit.result +0 -0
  2181. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export3.wit +0 -0
  2182. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export3.wit.result +0 -0
  2183. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export4.wit +0 -0
  2184. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export4.wit.result +0 -0
  2185. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export5.wit +0 -0
  2186. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-and-export5.wit.result +0 -0
  2187. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-export-overlap1.wit +0 -0
  2188. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-export-overlap1.wit.result +0 -0
  2189. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-export-overlap2.wit +0 -0
  2190. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-export-overlap2.wit.result +0 -0
  2191. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-twice.wit +0 -0
  2192. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/import-twice.wit.result +0 -0
  2193. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-cycle.wit +0 -0
  2194. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-cycle.wit.result +0 -0
  2195. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-foreign/deps/bar/empty.wit +0 -0
  2196. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-foreign/root.wit +0 -0
  2197. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-foreign.wit.result +0 -0
  2198. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-with-id.wit +0 -0
  2199. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-with-id.wit.result +0 -0
  2200. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-with-on-id.wit +0 -0
  2201. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/include-with-on-id.wit.result +0 -0
  2202. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-md.md +0 -0
  2203. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-md.wit.result +0 -0
  2204. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  2205. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  2206. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-type-reference.wit +0 -0
  2207. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-type-reference.wit.result +0 -0
  2208. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-type-reference2.wit +0 -0
  2209. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/invalid-type-reference2.wit.result +0 -0
  2210. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/kebab-name-include-not-found.wit +0 -0
  2211. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/kebab-name-include-not-found.wit.result +0 -0
  2212. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/kebab-name-include.wit +0 -0
  2213. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/kebab-name-include.wit.result +0 -0
  2214. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/keyword.wit +0 -0
  2215. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/keyword.wit.result +0 -0
  2216. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/missing-package.wit +0 -0
  2217. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/missing-package.wit.result +0 -0
  2218. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/no-access-to-sibling-use/bar.wit +0 -0
  2219. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/no-access-to-sibling-use/foo.wit +0 -0
  2220. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/no-access-to-sibling-use.wit.result +0 -0
  2221. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/non-existance-world-include/deps/bar/baz.wit +0 -0
  2222. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/non-existance-world-include/root.wit +0 -0
  2223. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/non-existance-world-include.wit.result +0 -0
  2224. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/pkg-cycle/deps/a1/root.wit +0 -0
  2225. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/pkg-cycle/root.wit +0 -0
  2226. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/pkg-cycle.wit.result +0 -0
  2227. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/pkg-cycle2/deps/a1/root.wit +0 -0
  2228. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/pkg-cycle2/deps/a2/root.wit +0 -0
  2229. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/pkg-cycle2/root.wit +0 -0
  2230. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/pkg-cycle2.wit.result +0 -0
  2231. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/type-and-resource-same-name/deps/dep/foo.wit +0 -0
  2232. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/type-and-resource-same-name/foo.wit +0 -0
  2233. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/type-and-resource-same-name.wit.result +0 -0
  2234. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/undefined-typed.wit +0 -0
  2235. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/undefined-typed.wit.result +0 -0
  2236. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/union-fuzz-2.wit +0 -0
  2237. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/union-fuzz-2.wit.result +0 -0
  2238. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unknown-interface.wit +0 -0
  2239. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unknown-interface.wit.result +0 -0
  2240. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface1.wit +0 -0
  2241. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface1.wit.result +0 -0
  2242. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface2.wit +0 -0
  2243. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface2.wit.result +0 -0
  2244. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface3.wit +0 -0
  2245. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface3.wit.result +0 -0
  2246. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface4.wit +0 -0
  2247. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-interface4.wit.result +0 -0
  2248. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use1.wit +0 -0
  2249. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use1.wit.result +0 -0
  2250. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use10/bar.wit +0 -0
  2251. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  2252. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use10.wit.result +0 -0
  2253. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use2.wit +0 -0
  2254. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use2.wit.result +0 -0
  2255. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use3.wit +0 -0
  2256. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use3.wit.result +0 -0
  2257. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use7.wit +0 -0
  2258. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use7.wit.result +0 -0
  2259. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use8.wit +0 -0
  2260. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use8.wit.result +0 -0
  2261. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use9.wit +0 -0
  2262. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unresolved-use9.wit.result +0 -0
  2263. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
  2264. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-and-include-world/deps/bar/baz.wit +0 -0
  2265. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-and-include-world/root.wit +0 -0
  2266. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-and-include-world.wit.result +0 -0
  2267. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict.wit +0 -0
  2268. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict.wit.result +0 -0
  2269. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict2.wit +0 -0
  2270. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict2.wit.result +0 -0
  2271. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict3.wit +0 -0
  2272. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-conflict3.wit.result +0 -0
  2273. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-cycle1.wit +0 -0
  2274. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-cycle1.wit.result +0 -0
  2275. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-cycle4.wit +0 -0
  2276. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-cycle4.wit.result +0 -0
  2277. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-shadow1.wit +0 -0
  2278. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-shadow1.wit.result +0 -0
  2279. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-world/deps/bar/baz.wit +0 -0
  2280. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-world/root.wit +0 -0
  2281. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/use-world.wit.result +0 -0
  2282. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-interface-clash.wit +0 -0
  2283. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-interface-clash.wit.result +0 -0
  2284. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-same-fields2.wit +0 -0
  2285. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-same-fields2.wit.result +0 -0
  2286. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-same-fields3.wit +0 -0
  2287. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-same-fields3.wit.result +0 -0
  2288. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-top-level-func.wit +0 -0
  2289. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-top-level-func.wit.result +0 -0
  2290. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-top-level-func2.wit +0 -0
  2291. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/parse-fail/world-top-level-func2.wit.result +0 -0
  2292. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-empty.wit +0 -0
  2293. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-multiple-returns-borrow.wit +0 -0
  2294. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-multiple-returns-own.wit +0 -0
  2295. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-multiple.wit +0 -0
  2296. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-return-borrow.wit +0 -0
  2297. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources-return-own.wit +0 -0
  2298. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources.wit +0 -0
  2299. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/resources1.wit +0 -0
  2300. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/shared-types.wit +0 -0
  2301. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/stress-export-elaborate.wit +0 -0
  2302. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/type-then-eof.wit +0 -0
  2303. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/union-fuzz-1.wit +0 -0
  2304. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/use-chain.wit +0 -0
  2305. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/use.wit +0 -0
  2306. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/versions/deps/a1/foo.wit +0 -0
  2307. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/versions/deps/a2/foo.wit +0 -0
  2308. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/versions/foo.wit +0 -0
  2309. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/wasi.wit +0 -0
  2310. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/world-iface-no-collide.wit +0 -0
  2311. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/world-implicit-import1.wit +0 -0
  2312. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/world-implicit-import2.wit +0 -0
  2313. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/world-implicit-import3.wit +0 -0
  2314. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/world-same-fields4.wit +0 -0
  2315. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/world-top-level-funcs.wit +0 -0
  2316. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/world-top-level-resources.wit +0 -0
  2317. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/worlds-union-dedup.wit +0 -0
  2318. /data/ext/cargo-vendor/{wit-parser-0.9.2 → wit-parser-0.11.1}/tests/ui/worlds-with-types.wit +0 -0
@@ -1,4048 +0,0 @@
1
- ;; Instruction formats.
2
- (type MInst
3
- (enum
4
- ;; A no-op of zero size.
5
- (Nop0)
6
-
7
- ;; A no-op that is one instruction large.
8
- (Nop4)
9
-
10
- ;; An ALU operation with two register sources and a register destination.
11
- (AluRRR
12
- (alu_op ALUOp)
13
- (size OperandSize)
14
- (rd WritableReg)
15
- (rn Reg)
16
- (rm Reg))
17
-
18
- ;; An ALU operation with three register sources and a register destination.
19
- (AluRRRR
20
- (alu_op ALUOp3)
21
- (size OperandSize)
22
- (rd WritableReg)
23
- (rn Reg)
24
- (rm Reg)
25
- (ra Reg))
26
-
27
- ;; An ALU operation with a register source and an immediate-12 source, and a register
28
- ;; destination.
29
- (AluRRImm12
30
- (alu_op ALUOp)
31
- (size OperandSize)
32
- (rd WritableReg)
33
- (rn Reg)
34
- (imm12 Imm12))
35
-
36
- ;; An ALU operation with a register source and an immediate-logic source, and a register destination.
37
- (AluRRImmLogic
38
- (alu_op ALUOp)
39
- (size OperandSize)
40
- (rd WritableReg)
41
- (rn Reg)
42
- (imml ImmLogic))
43
-
44
- ;; An ALU operation with a register source and an immediate-shiftamt source, and a register destination.
45
- (AluRRImmShift
46
- (alu_op ALUOp)
47
- (size OperandSize)
48
- (rd WritableReg)
49
- (rn Reg)
50
- (immshift ImmShift))
51
-
52
- ;; An ALU operation with two register sources, one of which can be shifted, and a register
53
- ;; destination.
54
- (AluRRRShift
55
- (alu_op ALUOp)
56
- (size OperandSize)
57
- (rd WritableReg)
58
- (rn Reg)
59
- (rm Reg)
60
- (shiftop ShiftOpAndAmt))
61
-
62
- ;; An ALU operation with two register sources, one of which can be {zero,sign}-extended and
63
- ;; shifted, and a register destination.
64
- (AluRRRExtend
65
- (alu_op ALUOp)
66
- (size OperandSize)
67
- (rd WritableReg)
68
- (rn Reg)
69
- (rm Reg)
70
- (extendop ExtendOp))
71
-
72
- ;; A bit op instruction with a single register source.
73
- (BitRR
74
- (op BitOp)
75
- (size OperandSize)
76
- (rd WritableReg)
77
- (rn Reg))
78
-
79
- ;; An unsigned (zero-extending) 8-bit load.
80
- (ULoad8
81
- (rd WritableReg)
82
- (mem AMode)
83
- (flags MemFlags))
84
-
85
- ;; A signed (sign-extending) 8-bit load.
86
- (SLoad8
87
- (rd WritableReg)
88
- (mem AMode)
89
- (flags MemFlags))
90
-
91
- ;; An unsigned (zero-extending) 16-bit load.
92
- (ULoad16
93
- (rd WritableReg)
94
- (mem AMode)
95
- (flags MemFlags))
96
-
97
- ;; A signed (sign-extending) 16-bit load.
98
- (SLoad16
99
- (rd WritableReg)
100
- (mem AMode)
101
- (flags MemFlags))
102
-
103
- ;; An unsigned (zero-extending) 32-bit load.
104
- (ULoad32
105
- (rd WritableReg)
106
- (mem AMode)
107
- (flags MemFlags))
108
-
109
- ;; A signed (sign-extending) 32-bit load.
110
- (SLoad32
111
- (rd WritableReg)
112
- (mem AMode)
113
- (flags MemFlags))
114
-
115
- ;; A 64-bit load.
116
- (ULoad64
117
- (rd WritableReg)
118
- (mem AMode)
119
- (flags MemFlags))
120
-
121
- ;; An 8-bit store.
122
- (Store8
123
- (rd Reg)
124
- (mem AMode)
125
- (flags MemFlags))
126
-
127
- ;; A 16-bit store.
128
- (Store16
129
- (rd Reg)
130
- (mem AMode)
131
- (flags MemFlags))
132
-
133
- ;; A 32-bit store.
134
- (Store32
135
- (rd Reg)
136
- (mem AMode)
137
- (flags MemFlags))
138
-
139
- ;; A 64-bit store.
140
- (Store64
141
- (rd Reg)
142
- (mem AMode)
143
- (flags MemFlags))
144
-
145
- ;; A store of a pair of registers.
146
- (StoreP64
147
- (rt Reg)
148
- (rt2 Reg)
149
- (mem PairAMode)
150
- (flags MemFlags))
151
-
152
- ;; A load of a pair of registers.
153
- (LoadP64
154
- (rt WritableReg)
155
- (rt2 WritableReg)
156
- (mem PairAMode)
157
- (flags MemFlags))
158
-
159
- ;; A MOV instruction. These are encoded as ORR's (AluRRR form).
160
- ;; The 32-bit version zeroes the top 32 bits of the
161
- ;; destination, which is effectively an alias for an unsigned
162
- ;; 32-to-64-bit extension.
163
- (Mov
164
- (size OperandSize)
165
- (rd WritableReg)
166
- (rm Reg))
167
-
168
- ;; Like `Move` but with a particular `PReg` source (for implementing CLIF
169
- ;; instructions like `get_stack_pointer`).
170
- (MovFromPReg
171
- (rd WritableReg)
172
- (rm PReg))
173
-
174
- ;; Like `Move` but with a particular `PReg` destination (for
175
- ;; implementing CLIF instructions like `set_pinned_reg`).
176
- (MovToPReg
177
- (rd PReg)
178
- (rm Reg))
179
-
180
- ;; A MOV[Z,N] with a 16-bit immediate.
181
- (MovWide
182
- (op MoveWideOp)
183
- (rd WritableReg)
184
- (imm MoveWideConst)
185
- (size OperandSize))
186
-
187
- ;; A MOVK with a 16-bit immediate. Modifies its register; we
188
- ;; model this with a seprate input `rn` and output `rd` virtual
189
- ;; register, with a regalloc constraint to tie them together.
190
- (MovK
191
- (rd WritableReg)
192
- (rn Reg)
193
- (imm MoveWideConst)
194
- (size OperandSize))
195
-
196
-
197
- ;; A sign- or zero-extend operation.
198
- (Extend
199
- (rd WritableReg)
200
- (rn Reg)
201
- (signed bool)
202
- (from_bits u8)
203
- (to_bits u8))
204
-
205
- ;; A conditional-select operation.
206
- (CSel
207
- (rd WritableReg)
208
- (cond Cond)
209
- (rn Reg)
210
- (rm Reg))
211
-
212
- ;; A conditional-select negation operation.
213
- (CSNeg
214
- (rd WritableReg)
215
- (cond Cond)
216
- (rn Reg)
217
- (rm Reg))
218
-
219
- ;; A conditional-set operation.
220
- (CSet
221
- (rd WritableReg)
222
- (cond Cond))
223
-
224
- ;; A conditional-set-mask operation.
225
- (CSetm
226
- (rd WritableReg)
227
- (cond Cond))
228
-
229
- ;; A conditional comparison with a second register.
230
- (CCmp
231
- (size OperandSize)
232
- (rn Reg)
233
- (rm Reg)
234
- (nzcv NZCV)
235
- (cond Cond))
236
-
237
- ;; A conditional comparison with an immediate.
238
- (CCmpImm
239
- (size OperandSize)
240
- (rn Reg)
241
- (imm UImm5)
242
- (nzcv NZCV)
243
- (cond Cond))
244
-
245
- ;; A synthetic insn, which is a load-linked store-conditional loop, that has the overall
246
- ;; effect of atomically modifying a memory location in a particular way. Because we have
247
- ;; no way to explain to the regalloc about earlyclobber registers, this instruction has
248
- ;; completely fixed operand registers, and we rely on the RA's coalescing to remove copies
249
- ;; in the surrounding code to the extent it can. Load- and store-exclusive instructions,
250
- ;; with acquire-release semantics, are used to access memory. The operand conventions are:
251
- ;;
252
- ;; x25 (rd) address
253
- ;; x26 (rd) second operand for `op`
254
- ;; x27 (wr) old value
255
- ;; x24 (wr) scratch reg; value afterwards has no meaning
256
- ;; x28 (wr) scratch reg; value afterwards has no meaning
257
- (AtomicRMWLoop
258
- (ty Type) ;; I8, I16, I32 or I64
259
- (op AtomicRMWLoopOp)
260
- (flags MemFlags)
261
- (addr Reg)
262
- (operand Reg)
263
- (oldval WritableReg)
264
- (scratch1 WritableReg)
265
- (scratch2 WritableReg))
266
-
267
- ;; Similar to AtomicRMWLoop, a compare-and-swap operation implemented using a load-linked
268
- ;; store-conditional loop, with acquire-release semantics.
269
- ;; Note that the operand conventions, although very similar to AtomicRMWLoop, are different:
270
- ;;
271
- ;; x25 (rd) address
272
- ;; x26 (rd) expected value
273
- ;; x28 (rd) replacement value
274
- ;; x27 (wr) old value
275
- ;; x24 (wr) scratch reg; value afterwards has no meaning
276
- (AtomicCASLoop
277
- (ty Type) ;; I8, I16, I32 or I64
278
- (flags MemFlags)
279
- (addr Reg)
280
- (expected Reg)
281
- (replacement Reg)
282
- (oldval WritableReg)
283
- (scratch WritableReg))
284
-
285
- ;; An atomic read-modify-write operation. These instructions require the
286
- ;; Large System Extension (LSE) ISA support (FEAT_LSE). The instructions have
287
- ;; acquire-release semantics.
288
- (AtomicRMW
289
- (op AtomicRMWOp)
290
- (rs Reg)
291
- (rt WritableReg)
292
- (rn Reg)
293
- (ty Type)
294
- (flags MemFlags))
295
-
296
- ;; An atomic compare-and-swap operation. These instructions require the
297
- ;; Large System Extension (LSE) ISA support (FEAT_LSE). The instructions have
298
- ;; acquire-release semantics.
299
- (AtomicCAS
300
- ;; `rd` is really `rs` in the encoded instruction (so `rd` == `rs`); we separate
301
- ;; them here to have separate use and def vregs for regalloc.
302
- (rd WritableReg)
303
- (rs Reg)
304
- (rt Reg)
305
- (rn Reg)
306
- (ty Type)
307
- (flags MemFlags))
308
-
309
- ;; Read `access_ty` bits from address `rt`, either 8, 16, 32 or 64-bits, and put
310
- ;; it in `rn`, optionally zero-extending to fill a word or double word result.
311
- ;; This instruction is sequentially consistent.
312
- (LoadAcquire
313
- (access_ty Type) ;; I8, I16, I32 or I64
314
- (rt WritableReg)
315
- (rn Reg)
316
- (flags MemFlags))
317
-
318
- ;; Write the lowest `ty` bits of `rt` to address `rn`.
319
- ;; This instruction is sequentially consistent.
320
- (StoreRelease
321
- (access_ty Type) ;; I8, I16, I32 or I64
322
- (rt Reg)
323
- (rn Reg)
324
- (flags MemFlags))
325
-
326
- ;; A memory fence. This must provide ordering to ensure that, at a minimum, neither loads
327
- ;; nor stores may move forwards or backwards across the fence. Currently emitted as "dmb
328
- ;; ish". This instruction is sequentially consistent.
329
- (Fence)
330
-
331
- ;; Consumption of speculative data barrier.
332
- (Csdb)
333
-
334
- ;; FPU move. Note that this is distinct from a vector-register
335
- ;; move; moving just 64 bits seems to be significantly faster.
336
- (FpuMove64
337
- (rd WritableReg)
338
- (rn Reg))
339
-
340
- ;; Vector register move.
341
- (FpuMove128
342
- (rd WritableReg)
343
- (rn Reg))
344
-
345
- ;; Move to scalar from a vector element.
346
- (FpuMoveFromVec
347
- (rd WritableReg)
348
- (rn Reg)
349
- (idx u8)
350
- (size VectorSize))
351
-
352
- ;; Zero-extend a SIMD & FP scalar to the full width of a vector register.
353
- ;; 16-bit scalars require half-precision floating-point support (FEAT_FP16).
354
- (FpuExtend
355
- (rd WritableReg)
356
- (rn Reg)
357
- (size ScalarSize))
358
-
359
- ;; 1-op FPU instruction.
360
- (FpuRR
361
- (fpu_op FPUOp1)
362
- (size ScalarSize)
363
- (rd WritableReg)
364
- (rn Reg))
365
-
366
- ;; 2-op FPU instruction.
367
- (FpuRRR
368
- (fpu_op FPUOp2)
369
- (size ScalarSize)
370
- (rd WritableReg)
371
- (rn Reg)
372
- (rm Reg))
373
-
374
- (FpuRRI
375
- (fpu_op FPUOpRI)
376
- (rd WritableReg)
377
- (rn Reg))
378
-
379
- ;; Variant of FpuRRI that modifies its `rd`, and so we name the
380
- ;; input state `ri` (for "input") and constrain the two
381
- ;; together.
382
- (FpuRRIMod
383
- (fpu_op FPUOpRIMod)
384
- (rd WritableReg)
385
- (ri Reg)
386
- (rn Reg))
387
-
388
-
389
- ;; 3-op FPU instruction.
390
- ;; 16-bit scalars require half-precision floating-point support (FEAT_FP16).
391
- (FpuRRRR
392
- (fpu_op FPUOp3)
393
- (size ScalarSize)
394
- (rd WritableReg)
395
- (rn Reg)
396
- (rm Reg)
397
- (ra Reg))
398
-
399
- ;; FPU comparison.
400
- (FpuCmp
401
- (size ScalarSize)
402
- (rn Reg)
403
- (rm Reg))
404
-
405
- ;; Floating-point load, single-precision (32 bit).
406
- (FpuLoad32
407
- (rd WritableReg)
408
- (mem AMode)
409
- (flags MemFlags))
410
-
411
- ;; Floating-point store, single-precision (32 bit).
412
- (FpuStore32
413
- (rd Reg)
414
- (mem AMode)
415
- (flags MemFlags))
416
-
417
- ;; Floating-point load, double-precision (64 bit).
418
- (FpuLoad64
419
- (rd WritableReg)
420
- (mem AMode)
421
- (flags MemFlags))
422
-
423
- ;; Floating-point store, double-precision (64 bit).
424
- (FpuStore64
425
- (rd Reg)
426
- (mem AMode)
427
- (flags MemFlags))
428
-
429
- ;; Floating-point/vector load, 128 bit.
430
- (FpuLoad128
431
- (rd WritableReg)
432
- (mem AMode)
433
- (flags MemFlags))
434
-
435
- ;; Floating-point/vector store, 128 bit.
436
- (FpuStore128
437
- (rd Reg)
438
- (mem AMode)
439
- (flags MemFlags))
440
-
441
- ;; A load of a pair of floating-point registers, double precision (64-bit).
442
- (FpuLoadP64
443
- (rt WritableReg)
444
- (rt2 WritableReg)
445
- (mem PairAMode)
446
- (flags MemFlags))
447
-
448
- ;; A store of a pair of floating-point registers, double precision (64-bit).
449
- (FpuStoreP64
450
- (rt Reg)
451
- (rt2 Reg)
452
- (mem PairAMode)
453
- (flags MemFlags))
454
-
455
- ;; A load of a pair of floating-point registers, 128-bit.
456
- (FpuLoadP128
457
- (rt WritableReg)
458
- (rt2 WritableReg)
459
- (mem PairAMode)
460
- (flags MemFlags))
461
-
462
- ;; A store of a pair of floating-point registers, 128-bit.
463
- (FpuStoreP128
464
- (rt Reg)
465
- (rt2 Reg)
466
- (mem PairAMode)
467
- (flags MemFlags))
468
-
469
- ;; Conversion: FP -> integer.
470
- (FpuToInt
471
- (op FpuToIntOp)
472
- (rd WritableReg)
473
- (rn Reg))
474
-
475
- ;; Conversion: integer -> FP.
476
- (IntToFpu
477
- (op IntToFpuOp)
478
- (rd WritableReg)
479
- (rn Reg))
480
-
481
- ;; FP conditional select, 32 bit.
482
- (FpuCSel32
483
- (rd WritableReg)
484
- (rn Reg)
485
- (rm Reg)
486
- (cond Cond))
487
-
488
- ;; FP conditional select, 64 bit.
489
- (FpuCSel64
490
- (rd WritableReg)
491
- (rn Reg)
492
- (rm Reg)
493
- (cond Cond))
494
-
495
- ;; Round to integer.
496
- (FpuRound
497
- (op FpuRoundMode)
498
- (rd WritableReg)
499
- (rn Reg))
500
-
501
- ;; Move from a GPR to a vector register. The scalar value is parked in the lowest lane
502
- ;; of the destination, and all other lanes are zeroed out. Currently only 32- and 64-bit
503
- ;; transactions are supported.
504
- (MovToFpu
505
- (rd WritableReg)
506
- (rn Reg)
507
- (size ScalarSize))
508
-
509
- ;; Loads a floating-point immediate.
510
- (FpuMoveFPImm
511
- (rd WritableReg)
512
- (imm ASIMDFPModImm)
513
- (size ScalarSize))
514
-
515
- ;; Move to a vector element from a GPR.
516
- (MovToVec
517
- (rd WritableReg)
518
- (ri Reg)
519
- (rn Reg)
520
- (idx u8)
521
- (size VectorSize))
522
-
523
- ;; Unsigned move from a vector element to a GPR.
524
- (MovFromVec
525
- (rd WritableReg)
526
- (rn Reg)
527
- (idx u8)
528
- (size ScalarSize))
529
-
530
- ;; Signed move from a vector element to a GPR.
531
- (MovFromVecSigned
532
- (rd WritableReg)
533
- (rn Reg)
534
- (idx u8)
535
- (size VectorSize)
536
- (scalar_size OperandSize))
537
-
538
- ;; Duplicate general-purpose register to vector.
539
- (VecDup
540
- (rd WritableReg)
541
- (rn Reg)
542
- (size VectorSize))
543
-
544
- ;; Duplicate scalar to vector.
545
- (VecDupFromFpu
546
- (rd WritableReg)
547
- (rn Reg)
548
- (size VectorSize)
549
- (lane u8))
550
-
551
- ;; Duplicate FP immediate to vector.
552
- (VecDupFPImm
553
- (rd WritableReg)
554
- (imm ASIMDFPModImm)
555
- (size VectorSize))
556
-
557
- ;; Duplicate immediate to vector.
558
- (VecDupImm
559
- (rd WritableReg)
560
- (imm ASIMDMovModImm)
561
- (invert bool)
562
- (size VectorSize))
563
-
564
- ;; Vector extend.
565
- (VecExtend
566
- (t VecExtendOp)
567
- (rd WritableReg)
568
- (rn Reg)
569
- (high_half bool)
570
- (lane_size ScalarSize))
571
-
572
- ;; Move vector element to another vector element.
573
- (VecMovElement
574
- (rd WritableReg)
575
- (ri Reg)
576
- (rn Reg)
577
- (dest_idx u8)
578
- (src_idx u8)
579
- (size VectorSize))
580
-
581
- ;; Vector widening operation.
582
- (VecRRLong
583
- (op VecRRLongOp)
584
- (rd WritableReg)
585
- (rn Reg)
586
- (high_half bool))
587
-
588
- ;; Vector narrowing operation -- low half.
589
- (VecRRNarrowLow
590
- (op VecRRNarrowOp)
591
- (rd WritableReg)
592
- (rn Reg)
593
- (lane_size ScalarSize))
594
-
595
- ;; Vector narrowing operation -- high half.
596
- (VecRRNarrowHigh
597
- (op VecRRNarrowOp)
598
- (rd WritableReg)
599
- (ri Reg)
600
- (rn Reg)
601
- (lane_size ScalarSize))
602
-
603
- ;; 1-operand vector instruction that operates on a pair of elements.
604
- (VecRRPair
605
- (op VecPairOp)
606
- (rd WritableReg)
607
- (rn Reg))
608
-
609
- ;; 2-operand vector instruction that produces a result with twice the
610
- ;; lane width and half the number of lanes.
611
- (VecRRRLong
612
- (alu_op VecRRRLongOp)
613
- (rd WritableReg)
614
- (rn Reg)
615
- (rm Reg)
616
- (high_half bool))
617
-
618
- ;; 2-operand vector instruction that produces a result with
619
- ;; twice the lane width and half the number of lanes. Variant
620
- ;; that modifies `rd` (so takes its initial state as `ri`).
621
- (VecRRRLongMod
622
- (alu_op VecRRRLongModOp)
623
- (rd WritableReg)
624
- (ri Reg)
625
- (rn Reg)
626
- (rm Reg)
627
- (high_half bool))
628
-
629
- ;; 1-operand vector instruction that extends elements of the input
630
- ;; register and operates on a pair of elements. The output lane width
631
- ;; is double that of the input.
632
- (VecRRPairLong
633
- (op VecRRPairLongOp)
634
- (rd WritableReg)
635
- (rn Reg))
636
-
637
- ;; A vector ALU op.
638
- (VecRRR
639
- (alu_op VecALUOp)
640
- (rd WritableReg)
641
- (rn Reg)
642
- (rm Reg)
643
- (size VectorSize))
644
-
645
- ;; A vector ALU op modifying a source register.
646
- (VecRRRMod
647
- (alu_op VecALUModOp)
648
- (rd WritableReg)
649
- (ri Reg)
650
- (rn Reg)
651
- (rm Reg)
652
- (size VectorSize))
653
-
654
- ;; A vector ALU op modifying a source register.
655
- (VecFmlaElem
656
- (alu_op VecALUModOp)
657
- (rd WritableReg)
658
- (ri Reg)
659
- (rn Reg)
660
- (rm Reg)
661
- (size VectorSize)
662
- (idx u8))
663
-
664
- ;; Vector two register miscellaneous instruction.
665
- (VecMisc
666
- (op VecMisc2)
667
- (rd WritableReg)
668
- (rn Reg)
669
- (size VectorSize))
670
-
671
- ;; Vector instruction across lanes.
672
- (VecLanes
673
- (op VecLanesOp)
674
- (rd WritableReg)
675
- (rn Reg)
676
- (size VectorSize))
677
-
678
- ;; Vector shift by immediate Shift Left (immediate), Unsigned Shift Right (immediate)
679
- ;; Signed Shift Right (immediate). These are somewhat unusual in that, for right shifts,
680
- ;; the allowed range of `imm` values is 1 to lane-size-in-bits, inclusive. A zero
681
- ;; right-shift cannot be encoded. Left shifts are "normal", though, having valid `imm`
682
- ;; values from 0 to lane-size-in-bits - 1 inclusive.
683
- (VecShiftImm
684
- (op VecShiftImmOp)
685
- (rd WritableReg)
686
- (rn Reg)
687
- (size VectorSize)
688
- (imm u8))
689
-
690
- ;; Destructive vector shift by immediate.
691
- (VecShiftImmMod
692
- (op VecShiftImmModOp)
693
- (rd WritableReg)
694
- (ri Reg)
695
- (rn Reg)
696
- (size VectorSize)
697
- (imm u8))
698
-
699
- ;; Vector extract - create a new vector, being the concatenation of the lowest `imm4` bytes
700
- ;; of `rm` followed by the uppermost `16 - imm4` bytes of `rn`.
701
- (VecExtract
702
- (rd WritableReg)
703
- (rn Reg)
704
- (rm Reg)
705
- (imm4 u8))
706
-
707
- ;; Table vector lookup - single register table. The table
708
- ;; consists of 8-bit elements and is stored in `rn`, while `rm`
709
- ;; contains 8-bit element indices. This variant emits `TBL`,
710
- ;; which sets elements that correspond to out-of-range indices
711
- ;; (greater than 15) to 0.
712
- (VecTbl
713
- (rd WritableReg)
714
- (rn Reg)
715
- (rm Reg))
716
-
717
- ;; Table vector lookup - single register table. The table
718
- ;; consists of 8-bit elements and is stored in `rn`, while `rm`
719
- ;; contains 8-bit element indices. This variant emits `TBX`,
720
- ;; which leaves elements that correspond to out-of-range indices
721
- ;; (greater than 15) unmodified. Hence, it takes an input vreg in
722
- ;; `ri` that is constrained to the same allocation as `rd`.
723
- (VecTblExt
724
- (rd WritableReg)
725
- (ri Reg)
726
- (rn Reg)
727
- (rm Reg))
728
-
729
- ;; Table vector lookup - two register table. The table consists
730
- ;; of 8-bit elements and is stored in `rn` and `rn2`, while
731
- ;; `rm` contains 8-bit element indices. The table registers
732
- ;; `rn` and `rn2` must have consecutive numbers modulo 32, that
733
- ;; is v31 and v0 (in that order) are consecutive registers.
734
- ;; This variant emits `TBL`, which sets out-of-range results to
735
- ;; 0.
736
- (VecTbl2
737
- (rd WritableReg)
738
- (rn Reg)
739
- (rn2 Reg)
740
- (rm Reg))
741
-
742
- ;; Table vector lookup - two register table. The table consists
743
- ;; of 8-bit elements and is stored in `rn` and `rn2`, while
744
- ;; `rm` contains 8-bit element indices. The table registers
745
- ;; `rn` and `rn2` must have consecutive numbers modulo 32, that
746
- ;; is v31 and v0 (in that order) are consecutive registers.
747
- ;; This variant emits `TBX`, which leaves out-of-range results
748
- ;; unmodified, hence takes the initial state of the result
749
- ;; register in vreg `ri`.
750
- (VecTbl2Ext
751
- (rd WritableReg)
752
- (ri Reg)
753
- (rn Reg)
754
- (rn2 Reg)
755
- (rm Reg))
756
-
757
- ;; Load an element and replicate to all lanes of a vector.
758
- (VecLoadReplicate
759
- (rd WritableReg)
760
- (rn Reg)
761
- (size VectorSize)
762
- (flags MemFlags))
763
-
764
- ;; Vector conditional select, 128 bit. A synthetic instruction, which generates a 4-insn
765
- ;; control-flow diamond.
766
- (VecCSel
767
- (rd WritableReg)
768
- (rn Reg)
769
- (rm Reg)
770
- (cond Cond))
771
-
772
- ;; Move to the NZCV flags (actually a `MSR NZCV, Xn` insn).
773
- (MovToNZCV
774
- (rn Reg))
775
-
776
- ;; Move from the NZCV flags (actually a `MRS Xn, NZCV` insn).
777
- (MovFromNZCV
778
- (rd WritableReg))
779
-
780
- ;; A machine call instruction. N.B.: this allows only a +/- 128MB offset (it uses a relocation
781
- ;; of type `Reloc::Arm64Call`); if the destination distance is not `RelocDistance::Near`, the
782
- ;; code should use a `LoadExtName` / `CallInd` sequence instead, allowing an arbitrary 64-bit
783
- ;; target.
784
- (Call
785
- (info BoxCallInfo))
786
-
787
- ;; A machine indirect-call instruction.
788
- (CallInd
789
- (info BoxCallIndInfo))
790
-
791
- ;; A return-call macro instruction.
792
- (ReturnCall
793
- (callee BoxExternalName)
794
- (info BoxReturnCallInfo))
795
-
796
- ;; An indirect return-call macro instruction.
797
- (ReturnCallInd
798
- (callee Reg)
799
- (info BoxReturnCallInfo))
800
-
801
- ;; A pseudo-instruction that captures register arguments in vregs.
802
- (Args
803
- (args VecArgPair))
804
-
805
- ;; ---- branches (exactly one must appear at end of BB) ----
806
-
807
- ;; A machine return instruction.
808
- (Ret
809
- (rets VecRetPair)
810
- (stack_bytes_to_pop u32))
811
-
812
- ;; A machine return instruction with pointer authentication using SP as the
813
- ;; modifier. This instruction requires pointer authentication support
814
- ;; (FEAT_PAuth) unless `is_hint` is true, in which case it is equivalent to
815
- ;; the combination of a no-op and a return instruction on platforms without
816
- ;; the relevant support.
817
- (AuthenticatedRet
818
- (key APIKey)
819
- (is_hint bool)
820
- (rets VecRetPair)
821
- (stack_bytes_to_pop u32))
822
-
823
- ;; An unconditional branch.
824
- (Jump
825
- (dest BranchTarget))
826
-
827
- ;; A conditional branch. Contains two targets; at emission time, both are emitted, but
828
- ;; the MachBuffer knows to truncate the trailing branch if fallthrough. We optimize the
829
- ;; choice of taken/not_taken (inverting the branch polarity as needed) based on the
830
- ;; fallthrough at the time of lowering.
831
- (CondBr
832
- (taken BranchTarget)
833
- (not_taken BranchTarget)
834
- (kind CondBrKind))
835
-
836
- ;; A conditional trap: execute a `udf` if the condition is true. This is
837
- ;; one VCode instruction because it uses embedded control flow; it is
838
- ;; logically a single-in, single-out region, but needs to appear as one
839
- ;; unit to the register allocator.
840
- ;;
841
- ;; The `CondBrKind` gives the conditional-branch condition that will
842
- ;; *execute* the embedded `Inst`. (In the emitted code, we use the inverse
843
- ;; of this condition in a branch that skips the trap instruction.)
844
- (TrapIf
845
- (kind CondBrKind)
846
- (trap_code TrapCode))
847
-
848
- ;; An indirect branch through a register, augmented with set of all
849
- ;; possible successors.
850
- (IndirectBr
851
- (rn Reg)
852
- (targets VecMachLabel))
853
-
854
- ;; A "break" instruction, used for e.g. traps and debug breakpoints.
855
- (Brk)
856
-
857
- ;; An instruction guaranteed to always be undefined and to trigger an illegal instruction at
858
- ;; runtime.
859
- (Udf
860
- (trap_code TrapCode))
861
-
862
- ;; Compute the address (using a PC-relative offset) of a memory location, using the `ADR`
863
- ;; instruction. Note that we take a simple offset, not a `MemLabel`, here, because `Adr` is
864
- ;; only used for now in fixed lowering sequences with hardcoded offsets. In the future we may
865
- ;; need full `MemLabel` support.
866
- (Adr
867
- (rd WritableReg)
868
- ;; Offset in range -2^20 .. 2^20.
869
- (off i32))
870
-
871
- ;; Compute the address (using a PC-relative offset) of a 4KB page.
872
- (Adrp
873
- (rd WritableReg)
874
- (off i32))
875
-
876
- ;; Raw 32-bit word, used for inline constants and jump-table entries.
877
- (Word4
878
- (data u32))
879
-
880
- ;; Raw 64-bit word, used for inline constants.
881
- (Word8
882
- (data u64))
883
-
884
- ;; Jump-table sequence, as one compound instruction (see note in lower_inst.rs for rationale).
885
- (JTSequence
886
- (info BoxJTSequenceInfo)
887
- (ridx Reg)
888
- (rtmp1 WritableReg)
889
- (rtmp2 WritableReg))
890
-
891
- ;; Load an inline symbol reference.
892
- (LoadExtName
893
- (rd WritableReg)
894
- (name BoxExternalName)
895
- (offset i64))
896
-
897
- ;; Load address referenced by `mem` into `rd`.
898
- (LoadAddr
899
- (rd WritableReg)
900
- (mem AMode))
901
-
902
- ;; Pointer authentication code for instruction address with modifier in SP;
903
- ;; equivalent to a no-op if Pointer authentication (FEAT_PAuth) is not
904
- ;; supported.
905
- (Pacisp
906
- (key APIKey))
907
-
908
- ;; Strip pointer authentication code from instruction address in LR;
909
- ;; equivalent to a no-op if Pointer authentication (FEAT_PAuth) is not
910
- ;; supported.
911
- (Xpaclri)
912
-
913
- ;; Branch target identification; equivalent to a no-op if Branch Target
914
- ;; Identification (FEAT_BTI) is not supported.
915
- (Bti
916
- (targets BranchTargetType))
917
-
918
- ;; Marker, no-op in generated code: SP "virtual offset" is adjusted. This
919
- ;; controls how AMode::NominalSPOffset args are lowered.
920
- (VirtualSPOffsetAdj
921
- (offset i64))
922
-
923
- ;; Meta-insn, no-op in generated code: emit constant/branch veneer island
924
- ;; at this point (with a guard jump around it) if less than the needed
925
- ;; space is available before the next branch deadline. See the `MachBuffer`
926
- ;; implementation in `machinst/buffer.rs` for the overall algorithm. In
927
- ;; brief, we retain a set of "pending/unresolved label references" from
928
- ;; branches as we scan forward through instructions to emit machine code;
929
- ;; if we notice we're about to go out of range on an unresolved reference,
930
- ;; we stop, emit a bunch of "veneers" (branches in a form that has a longer
931
- ;; range, e.g. a 26-bit-offset unconditional jump), and point the original
932
- ;; label references to those. This is an "island" because it comes in the
933
- ;; middle of the code.
934
- ;;
935
- ;; This meta-instruction is a necessary part of the logic that determines
936
- ;; where to place islands. Ordinarily, we want to place them between basic
937
- ;; blocks, so we compute the worst-case size of each block, and emit the
938
- ;; island before starting a block if we would exceed a deadline before the
939
- ;; end of the block. However, some sequences (such as an inline jumptable)
940
- ;; are variable-length and not accounted for by this logic; so these
941
- ;; lowered sequences include an `EmitIsland` to trigger island generation
942
- ;; where necessary.
943
- (EmitIsland
944
- ;; The needed space before the next deadline.
945
- (needed_space CodeOffset))
946
-
947
- ;; A call to the `ElfTlsGetAddr` libcall. Returns address of TLS symbol in x0.
948
- (ElfTlsGetAddr
949
- (symbol ExternalName)
950
- (rd WritableReg))
951
-
952
- (MachOTlsGetAddr
953
- (symbol ExternalName)
954
- (rd WritableReg))
955
-
956
- ;; An unwind pseudo-instruction.
957
- (Unwind
958
- (inst UnwindInst))
959
-
960
- ;; A dummy use, useful to keep a value alive.
961
- (DummyUse
962
- (reg Reg))
963
-
964
- ;; Emits an inline stack probe loop.
965
- ;;
966
- ;; Note that this is emitted post-regalloc so `start` and `end` can be
967
- ;; temporary registers such as the spilltmp and tmp2 registers. This also
968
- ;; means that the internal codegen can't use these registers.
969
- (StackProbeLoop (start WritableReg)
970
- (end Reg)
971
- (step Imm12))))
972
-
973
- ;; An ALU operation. This can be paired with several instruction formats
974
- ;; below (see `Inst`) in any combination.
975
- (type ALUOp
976
- (enum
977
- (Add)
978
- (Sub)
979
- (Orr)
980
- (OrrNot)
981
- (And)
982
- (AndS)
983
- (AndNot)
984
- ;; XOR (AArch64 calls this "EOR")
985
- (Eor)
986
- ;; XNOR (AArch64 calls this "EOR-NOT")
987
- (EorNot)
988
- ;; Add, setting flags
989
- (AddS)
990
- ;; Sub, setting flags
991
- (SubS)
992
- ;; Signed multiply, high-word result
993
- (SMulH)
994
- ;; Unsigned multiply, high-word result
995
- (UMulH)
996
- (SDiv)
997
- (UDiv)
998
- (RotR)
999
- (Lsr)
1000
- (Asr)
1001
- (Lsl)
1002
- ;; Add with carry
1003
- (Adc)
1004
- ;; Add with carry, settings flags
1005
- (AdcS)
1006
- ;; Subtract with carry
1007
- (Sbc)
1008
- ;; Subtract with carry, settings flags
1009
- (SbcS)
1010
- ))
1011
-
1012
- ;; An ALU operation with three arguments.
1013
- (type ALUOp3
1014
- (enum
1015
- ;; Multiply-add
1016
- (MAdd)
1017
- ;; Multiply-sub
1018
- (MSub)
1019
- ;; Unsigned-Multiply-add
1020
- (UMAddL)
1021
- ;; Signed-Multiply-add
1022
- (SMAddL)
1023
- ))
1024
-
1025
- (type MoveWideOp
1026
- (enum
1027
- (MovZ)
1028
- (MovN)
1029
- ))
1030
-
1031
- (type UImm5 (primitive UImm5))
1032
- (type Imm12 (primitive Imm12))
1033
- (type ImmLogic (primitive ImmLogic))
1034
- (type ImmShift (primitive ImmShift))
1035
- (type ShiftOpAndAmt (primitive ShiftOpAndAmt))
1036
- (type MoveWideConst (primitive MoveWideConst))
1037
- (type NZCV (primitive NZCV))
1038
- (type ASIMDFPModImm (primitive ASIMDFPModImm))
1039
- (type ASIMDMovModImm (primitive ASIMDMovModImm))
1040
-
1041
- (type BoxCallInfo (primitive BoxCallInfo))
1042
- (type BoxCallIndInfo (primitive BoxCallIndInfo))
1043
- (type BoxReturnCallInfo (primitive BoxReturnCallInfo))
1044
- (type CondBrKind (primitive CondBrKind))
1045
- (type BranchTarget (primitive BranchTarget))
1046
- (type BoxJTSequenceInfo (primitive BoxJTSequenceInfo))
1047
- (type CodeOffset (primitive CodeOffset))
1048
- (type VecMachLabel extern (enum))
1049
-
1050
- (type ExtendOp extern
1051
- (enum
1052
- (UXTB)
1053
- (UXTH)
1054
- (UXTW)
1055
- (UXTX)
1056
- (SXTB)
1057
- (SXTH)
1058
- (SXTW)
1059
- (SXTX)
1060
- ))
1061
-
1062
- ;; An operation on the bits of a register. This can be paired with several instruction formats
1063
- ;; below (see `Inst`) in any combination.
1064
- (type BitOp
1065
- (enum
1066
- ;; Bit reverse
1067
- (RBit)
1068
- (Clz)
1069
- (Cls)
1070
- ;; Byte reverse
1071
- (Rev16)
1072
- (Rev32)
1073
- (Rev64)
1074
- ))
1075
-
1076
- (type MemLabel extern (enum))
1077
- (type SImm9 extern (enum))
1078
- (type UImm12Scaled extern (enum))
1079
-
1080
- ;; An addressing mode specified for a load/store operation.
1081
- (type AMode
1082
- (enum
1083
- ;;
1084
- ;; Real ARM64 addressing modes:
1085
- ;;
1086
- ;; "post-indexed" mode as per AArch64 docs: postincrement reg after
1087
- ;; address computation.
1088
- ;; Specialized here to SP so we don't have to emit regalloc metadata.
1089
- (SPPostIndexed
1090
- (simm9 SImm9))
1091
-
1092
- ;; "pre-indexed" mode as per AArch64 docs: preincrement reg before
1093
- ;; address computation.
1094
- ;; Specialized here to SP so we don't have to emit regalloc metadata.
1095
- (SPPreIndexed
1096
- (simm9 SImm9))
1097
-
1098
- ;; N.B.: RegReg, RegScaled, and RegScaledExtended all correspond to
1099
- ;; what the ISA calls the "register offset" addressing mode. We split
1100
- ;; out several options here for more ergonomic codegen.
1101
- ;;
1102
- ;; Register plus register offset.
1103
- (RegReg
1104
- (rn Reg)
1105
- (rm Reg))
1106
-
1107
- ;; Register plus register offset, scaled by type's size.
1108
- (RegScaled
1109
- (rn Reg)
1110
- (rm Reg)
1111
- (ty Type))
1112
-
1113
- ;; Register plus register offset, scaled by type's size, with index
1114
- ;; sign- or zero-extended first.
1115
- (RegScaledExtended
1116
- (rn Reg)
1117
- (rm Reg)
1118
- (ty Type)
1119
- (extendop ExtendOp))
1120
-
1121
- ;; Register plus register offset, with index sign- or zero-extended
1122
- ;; first.
1123
- (RegExtended
1124
- (rn Reg)
1125
- (rm Reg)
1126
- (extendop ExtendOp))
1127
-
1128
- ;; Unscaled signed 9-bit immediate offset from reg.
1129
- (Unscaled
1130
- (rn Reg)
1131
- (simm9 SImm9))
1132
-
1133
- ;; Scaled (by size of a type) unsigned 12-bit immediate offset from reg.
1134
- (UnsignedOffset
1135
- (rn Reg)
1136
- (uimm12 UImm12Scaled))
1137
-
1138
- ;; virtual addressing modes that are lowered at emission time:
1139
- ;;
1140
- ;; Reference to a "label": e.g., a symbol.
1141
- (Label
1142
- (label MemLabel))
1143
-
1144
- ;; Arbitrary offset from a register. Converted to generation of large
1145
- ;; offsets with multiple instructions as necessary during code emission.
1146
- (RegOffset
1147
- (rn Reg)
1148
- (off i64)
1149
- (ty Type))
1150
-
1151
- ;; Offset from the stack pointer.
1152
- (SPOffset
1153
- (off i64)
1154
- (ty Type))
1155
-
1156
- ;; Offset from the frame pointer.
1157
- (FPOffset
1158
- (off i64)
1159
- (ty Type))
1160
-
1161
- ;; A reference to a constant which is placed outside of the function's
1162
- ;; body, typically at the end.
1163
- (Const
1164
- (addr VCodeConstant))
1165
-
1166
- ;; Offset from the "nominal stack pointer", which is where the real SP is
1167
- ;; just after stack and spill slots are allocated in the function prologue.
1168
- ;; At emission time, this is converted to `SPOffset` with a fixup added to
1169
- ;; the offset constant. The fixup is a running value that is tracked as
1170
- ;; emission iterates through instructions in linear order, and can be
1171
- ;; adjusted up and down with [Inst::VirtualSPOffsetAdj].
1172
- ;;
1173
- ;; The standard ABI is in charge of handling this (by emitting the
1174
- ;; adjustment meta-instructions). It maintains the invariant that "nominal
1175
- ;; SP" is where the actual SP is after the function prologue and before
1176
- ;; clobber pushes. See the diagram in the documentation for
1177
- ;; [crate::isa::aarch64::abi](the ABI module) for more details.
1178
- (NominalSPOffset
1179
- (off i64)
1180
- (ty Type))))
1181
-
1182
- (type PairAMode extern (enum))
1183
- (type FPUOpRI extern (enum))
1184
- (type FPUOpRIMod extern (enum))
1185
-
1186
- (type OperandSize extern
1187
- (enum Size32
1188
- Size64))
1189
-
1190
- ;; Helper for calculating the `OperandSize` corresponding to a type
1191
- (decl operand_size (Type) OperandSize)
1192
- (rule 1 (operand_size (fits_in_32 _ty)) (OperandSize.Size32))
1193
- (rule (operand_size (fits_in_64 _ty)) (OperandSize.Size64))
1194
-
1195
- (type ScalarSize extern
1196
- (enum Size8
1197
- Size16
1198
- Size32
1199
- Size64
1200
- Size128))
1201
-
1202
- ;; Helper for calculating the `ScalarSize` corresponding to a type
1203
- (decl scalar_size (Type) ScalarSize)
1204
-
1205
- (rule (scalar_size $I8) (ScalarSize.Size8))
1206
- (rule (scalar_size $I16) (ScalarSize.Size16))
1207
- (rule (scalar_size $I32) (ScalarSize.Size32))
1208
- (rule (scalar_size $I64) (ScalarSize.Size64))
1209
- (rule (scalar_size $I128) (ScalarSize.Size128))
1210
-
1211
- (rule (scalar_size $F32) (ScalarSize.Size32))
1212
- (rule (scalar_size $F64) (ScalarSize.Size64))
1213
-
1214
- ;; Helper for calculating the `ScalarSize` lane type from vector type
1215
- (decl lane_size (Type) ScalarSize)
1216
- (rule 1 (lane_size (multi_lane 8 _)) (ScalarSize.Size8))
1217
- (rule 1 (lane_size (multi_lane 16 _)) (ScalarSize.Size16))
1218
- (rule 1 (lane_size (multi_lane 32 _)) (ScalarSize.Size32))
1219
- (rule 1 (lane_size (multi_lane 64 _)) (ScalarSize.Size64))
1220
- (rule (lane_size (dynamic_lane 8 _)) (ScalarSize.Size8))
1221
- (rule (lane_size (dynamic_lane 16 _)) (ScalarSize.Size16))
1222
- (rule (lane_size (dynamic_lane 32 _)) (ScalarSize.Size32))
1223
- (rule (lane_size (dynamic_lane 64 _)) (ScalarSize.Size64))
1224
-
1225
- ;; Helper for extracting the size of a lane from the input `VectorSize`
1226
- (decl pure vector_lane_size (VectorSize) ScalarSize)
1227
- (rule (vector_lane_size (VectorSize.Size8x16)) (ScalarSize.Size8))
1228
- (rule (vector_lane_size (VectorSize.Size8x8)) (ScalarSize.Size8))
1229
- (rule (vector_lane_size (VectorSize.Size16x8)) (ScalarSize.Size16))
1230
- (rule (vector_lane_size (VectorSize.Size16x4)) (ScalarSize.Size16))
1231
- (rule (vector_lane_size (VectorSize.Size32x4)) (ScalarSize.Size32))
1232
- (rule (vector_lane_size (VectorSize.Size32x2)) (ScalarSize.Size32))
1233
- (rule (vector_lane_size (VectorSize.Size64x2)) (ScalarSize.Size64))
1234
-
1235
- (type Cond extern
1236
- (enum
1237
- (Eq)
1238
- (Ne)
1239
- (Hs)
1240
- (Lo)
1241
- (Mi)
1242
- (Pl)
1243
- (Vs)
1244
- (Vc)
1245
- (Hi)
1246
- (Ls)
1247
- (Ge)
1248
- (Lt)
1249
- (Gt)
1250
- (Le)
1251
- (Al)
1252
- (Nv)
1253
- ))
1254
-
1255
- (type VectorSize extern
1256
- (enum
1257
- (Size8x8)
1258
- (Size8x16)
1259
- (Size16x4)
1260
- (Size16x8)
1261
- (Size32x2)
1262
- (Size32x4)
1263
- (Size64x2)
1264
- ))
1265
-
1266
- ;; Helper for calculating the `VectorSize` corresponding to a type
1267
- (decl vector_size (Type) VectorSize)
1268
- (rule 1 (vector_size (multi_lane 8 8)) (VectorSize.Size8x8))
1269
- (rule 1 (vector_size (multi_lane 8 16)) (VectorSize.Size8x16))
1270
- (rule 1 (vector_size (multi_lane 16 4)) (VectorSize.Size16x4))
1271
- (rule 1 (vector_size (multi_lane 16 8)) (VectorSize.Size16x8))
1272
- (rule 1 (vector_size (multi_lane 32 2)) (VectorSize.Size32x2))
1273
- (rule 1 (vector_size (multi_lane 32 4)) (VectorSize.Size32x4))
1274
- (rule 1 (vector_size (multi_lane 64 2)) (VectorSize.Size64x2))
1275
- (rule (vector_size (dynamic_lane 8 8)) (VectorSize.Size8x8))
1276
- (rule (vector_size (dynamic_lane 8 16)) (VectorSize.Size8x16))
1277
- (rule (vector_size (dynamic_lane 16 4)) (VectorSize.Size16x4))
1278
- (rule (vector_size (dynamic_lane 16 8)) (VectorSize.Size16x8))
1279
- (rule (vector_size (dynamic_lane 32 2)) (VectorSize.Size32x2))
1280
- (rule (vector_size (dynamic_lane 32 4)) (VectorSize.Size32x4))
1281
- (rule (vector_size (dynamic_lane 64 2)) (VectorSize.Size64x2))
1282
-
1283
- ;; A floating-point unit (FPU) operation with one arg.
1284
- (type FPUOp1
1285
- (enum
1286
- (Abs)
1287
- (Neg)
1288
- (Sqrt)
1289
- (Cvt32To64)
1290
- (Cvt64To32)
1291
- ))
1292
-
1293
- ;; A floating-point unit (FPU) operation with two args.
1294
- (type FPUOp2
1295
- (enum
1296
- (Add)
1297
- (Sub)
1298
- (Mul)
1299
- (Div)
1300
- (Max)
1301
- (Min)
1302
- ))
1303
-
1304
- ;; A floating-point unit (FPU) operation with three args.
1305
- (type FPUOp3
1306
- (enum
1307
- (MAdd)
1308
- ))
1309
-
1310
- ;; A conversion from an FP to an integer value.
1311
- (type FpuToIntOp
1312
- (enum
1313
- (F32ToU32)
1314
- (F32ToI32)
1315
- (F32ToU64)
1316
- (F32ToI64)
1317
- (F64ToU32)
1318
- (F64ToI32)
1319
- (F64ToU64)
1320
- (F64ToI64)
1321
- ))
1322
-
1323
- ;; A conversion from an integer to an FP value.
1324
- (type IntToFpuOp
1325
- (enum
1326
- (U32ToF32)
1327
- (I32ToF32)
1328
- (U32ToF64)
1329
- (I32ToF64)
1330
- (U64ToF32)
1331
- (I64ToF32)
1332
- (U64ToF64)
1333
- (I64ToF64)
1334
- ))
1335
-
1336
- ;; Modes for FP rounding ops: round down (floor) or up (ceil), or toward zero (trunc), or to
1337
- ;; nearest, and for 32- or 64-bit FP values.
1338
- (type FpuRoundMode
1339
- (enum
1340
- (Minus32)
1341
- (Minus64)
1342
- (Plus32)
1343
- (Plus64)
1344
- (Zero32)
1345
- (Zero64)
1346
- (Nearest32)
1347
- (Nearest64)
1348
- ))
1349
-
1350
- ;; Type of vector element extensions.
1351
- (type VecExtendOp
1352
- (enum
1353
- ;; Signed extension
1354
- (Sxtl)
1355
- ;; Unsigned extension
1356
- (Uxtl)
1357
- ))
1358
-
1359
- ;; A vector ALU operation.
1360
- (type VecALUOp
1361
- (enum
1362
- ;; Signed saturating add
1363
- (Sqadd)
1364
- ;; Unsigned saturating add
1365
- (Uqadd)
1366
- ;; Signed saturating subtract
1367
- (Sqsub)
1368
- ;; Unsigned saturating subtract
1369
- (Uqsub)
1370
- ;; Compare bitwise equal
1371
- (Cmeq)
1372
- ;; Compare signed greater than or equal
1373
- (Cmge)
1374
- ;; Compare signed greater than
1375
- (Cmgt)
1376
- ;; Compare unsigned higher
1377
- (Cmhs)
1378
- ;; Compare unsigned higher or same
1379
- (Cmhi)
1380
- ;; Floating-point compare equal
1381
- (Fcmeq)
1382
- ;; Floating-point compare greater than
1383
- (Fcmgt)
1384
- ;; Floating-point compare greater than or equal
1385
- (Fcmge)
1386
- ;; Bitwise and
1387
- (And)
1388
- ;; Bitwise bit clear
1389
- (Bic)
1390
- ;; Bitwise inclusive or
1391
- (Orr)
1392
- ;; Bitwise exclusive or
1393
- (Eor)
1394
- ;; Unsigned maximum pairwise
1395
- (Umaxp)
1396
- ;; Add
1397
- (Add)
1398
- ;; Subtract
1399
- (Sub)
1400
- ;; Multiply
1401
- (Mul)
1402
- ;; Signed shift left
1403
- (Sshl)
1404
- ;; Unsigned shift left
1405
- (Ushl)
1406
- ;; Unsigned minimum
1407
- (Umin)
1408
- ;; Signed minimum
1409
- (Smin)
1410
- ;; Unsigned maximum
1411
- (Umax)
1412
- ;; Signed maximum
1413
- (Smax)
1414
- ;; Unsigned rounding halving add
1415
- (Urhadd)
1416
- ;; Floating-point add
1417
- (Fadd)
1418
- ;; Floating-point subtract
1419
- (Fsub)
1420
- ;; Floating-point divide
1421
- (Fdiv)
1422
- ;; Floating-point maximum
1423
- (Fmax)
1424
- ;; Floating-point minimum
1425
- (Fmin)
1426
- ;; Floating-point multiply
1427
- (Fmul)
1428
- ;; Add pairwise
1429
- (Addp)
1430
- ;; Zip vectors (primary) [meaning, high halves]
1431
- (Zip1)
1432
- ;; Zip vectors (secondary)
1433
- (Zip2)
1434
- ;; Signed saturating rounding doubling multiply returning high half
1435
- (Sqrdmulh)
1436
- ;; Unzip vectors (primary)
1437
- (Uzp1)
1438
- ;; Unzip vectors (secondary)
1439
- (Uzp2)
1440
- ;; Transpose vectors (primary)
1441
- (Trn1)
1442
- ;; Transpose vectors (secondary)
1443
- (Trn2)
1444
- ))
1445
-
1446
- ;; A Vector ALU operation which modifies a source register.
1447
- (type VecALUModOp
1448
- (enum
1449
- ;; Bitwise select
1450
- (Bsl)
1451
- ;; Floating-point fused multiply-add vectors
1452
- (Fmla)
1453
- ;; Floating-point fused multiply-subtract vectors
1454
- (Fmls)
1455
- ))
1456
-
1457
- ;; A Vector miscellaneous operation with two registers.
1458
- (type VecMisc2
1459
- (enum
1460
- ;; Bitwise NOT
1461
- (Not)
1462
- ;; Negate
1463
- (Neg)
1464
- ;; Absolute value
1465
- (Abs)
1466
- ;; Floating-point absolute value
1467
- (Fabs)
1468
- ;; Floating-point negate
1469
- (Fneg)
1470
- ;; Floating-point square root
1471
- (Fsqrt)
1472
- ;; Reverse elements in 16-bit lanes
1473
- (Rev16)
1474
- ;; Reverse elements in 32-bit lanes
1475
- (Rev32)
1476
- ;; Reverse elements in 64-bit doublewords
1477
- (Rev64)
1478
- ;; Floating-point convert to signed integer, rounding toward zero
1479
- (Fcvtzs)
1480
- ;; Floating-point convert to unsigned integer, rounding toward zero
1481
- (Fcvtzu)
1482
- ;; Signed integer convert to floating-point
1483
- (Scvtf)
1484
- ;; Unsigned integer convert to floating-point
1485
- (Ucvtf)
1486
- ;; Floating point round to integral, rounding towards nearest
1487
- (Frintn)
1488
- ;; Floating point round to integral, rounding towards zero
1489
- (Frintz)
1490
- ;; Floating point round to integral, rounding towards minus infinity
1491
- (Frintm)
1492
- ;; Floating point round to integral, rounding towards plus infinity
1493
- (Frintp)
1494
- ;; Population count per byte
1495
- (Cnt)
1496
- ;; Compare bitwise equal to 0
1497
- (Cmeq0)
1498
- ;; Compare signed greater than or equal to 0
1499
- (Cmge0)
1500
- ;; Compare signed greater than 0
1501
- (Cmgt0)
1502
- ;; Compare signed less than or equal to 0
1503
- (Cmle0)
1504
- ;; Compare signed less than 0
1505
- (Cmlt0)
1506
- ;; Floating point compare equal to 0
1507
- (Fcmeq0)
1508
- ;; Floating point compare greater than or equal to 0
1509
- (Fcmge0)
1510
- ;; Floating point compare greater than 0
1511
- (Fcmgt0)
1512
- ;; Floating point compare less than or equal to 0
1513
- (Fcmle0)
1514
- ;; Floating point compare less than 0
1515
- (Fcmlt0)
1516
- ))
1517
-
1518
- ;; A vector widening operation with one argument.
1519
- (type VecRRLongOp
1520
- (enum
1521
- ;; Floating-point convert to higher precision long, 16-bit elements
1522
- (Fcvtl16)
1523
- ;; Floating-point convert to higher precision long, 32-bit elements
1524
- (Fcvtl32)
1525
- ;; Shift left long (by element size), 8-bit elements
1526
- (Shll8)
1527
- ;; Shift left long (by element size), 16-bit elements
1528
- (Shll16)
1529
- ;; Shift left long (by element size), 32-bit elements
1530
- (Shll32)
1531
- ))
1532
-
1533
- ;; A vector narrowing operation with one argument.
1534
- (type VecRRNarrowOp
1535
- (enum
1536
- ;; Extract narrow.
1537
- (Xtn)
1538
- ;; Signed saturating extract narrow.
1539
- (Sqxtn)
1540
- ;; Signed saturating extract unsigned narrow.
1541
- (Sqxtun)
1542
- ;; Unsigned saturating extract narrow.
1543
- (Uqxtn)
1544
- ;; Floating-point convert to lower precision narrow.
1545
- (Fcvtn)
1546
- ))
1547
-
1548
- (type VecRRRLongOp
1549
- (enum
1550
- ;; Signed multiply long.
1551
- (Smull8)
1552
- (Smull16)
1553
- (Smull32)
1554
- ;; Unsigned multiply long.
1555
- (Umull8)
1556
- (Umull16)
1557
- (Umull32)
1558
- ))
1559
-
1560
- (type VecRRRLongModOp
1561
- (enum
1562
- ;; Unsigned multiply add long
1563
- (Umlal8)
1564
- (Umlal16)
1565
- (Umlal32)
1566
- ))
1567
-
1568
- ;; A vector operation on a pair of elements with one register.
1569
- (type VecPairOp
1570
- (enum
1571
- ;; Add pair of elements
1572
- (Addp)
1573
- ))
1574
-
1575
- ;; 1-operand vector instruction that extends elements of the input register
1576
- ;; and operates on a pair of elements.
1577
- (type VecRRPairLongOp
1578
- (enum
1579
- ;; Sign extend and add pair of elements
1580
- (Saddlp8)
1581
- (Saddlp16)
1582
- ;; Unsigned extend and add pair of elements
1583
- (Uaddlp8)
1584
- (Uaddlp16)
1585
- ))
1586
-
1587
- ;; An operation across the lanes of vectors.
1588
- (type VecLanesOp
1589
- (enum
1590
- ;; Integer addition across a vector
1591
- (Addv)
1592
- ;; Unsigned minimum across a vector
1593
- (Uminv)
1594
- ))
1595
-
1596
- ;; A shift-by-immediate operation on each lane of a vector.
1597
- (type VecShiftImmOp
1598
- (enum
1599
- ;; Unsigned shift left
1600
- (Shl)
1601
- ;; Unsigned shift right
1602
- (Ushr)
1603
- ;; Signed shift right
1604
- (Sshr)
1605
- ))
1606
-
1607
- ;; Destructive shift-by-immediate operation on each lane of a vector.
1608
- (type VecShiftImmModOp
1609
- (enum
1610
- ;; Shift left and insert
1611
- (Sli)
1612
- ))
1613
-
1614
- ;; Atomic read-modify-write operations with acquire-release semantics
1615
- (type AtomicRMWOp
1616
- (enum
1617
- (Add)
1618
- (Clr)
1619
- (Eor)
1620
- (Set)
1621
- (Smax)
1622
- (Smin)
1623
- (Umax)
1624
- (Umin)
1625
- (Swp)
1626
- ))
1627
-
1628
- ;; Atomic read-modify-write operations, with acquire-release semantics,
1629
- ;; implemented with a loop.
1630
- (type AtomicRMWLoopOp
1631
- (enum
1632
- (Add)
1633
- (Sub)
1634
- (And)
1635
- (Nand)
1636
- (Eor)
1637
- (Orr)
1638
- (Smax)
1639
- (Smin)
1640
- (Umax)
1641
- (Umin)
1642
- (Xchg)
1643
- ))
1644
-
1645
- ;; Keys for instruction address PACs
1646
- (type APIKey
1647
- (enum
1648
- (A)
1649
- (B)
1650
- ))
1651
-
1652
- ;; Branch target types
1653
- (type BranchTargetType
1654
- (enum
1655
- (None)
1656
- (C)
1657
- (J)
1658
- (JC)
1659
- ))
1660
-
1661
- ;; Extractors for target features ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1662
- (decl pure partial sign_return_address_disabled () Unit)
1663
- (extern constructor sign_return_address_disabled sign_return_address_disabled)
1664
-
1665
- (decl use_lse () Inst)
1666
- (extern extractor use_lse use_lse)
1667
-
1668
- ;; Extractor helpers for various immmediate constants ;;;;;;;;;;;;;;;;;;;;;;;;;;
1669
-
1670
- (decl pure partial move_wide_const_from_u64 (Type u64) MoveWideConst)
1671
- (extern constructor move_wide_const_from_u64 move_wide_const_from_u64)
1672
-
1673
- (decl pure partial move_wide_const_from_inverted_u64 (Type u64) MoveWideConst)
1674
- (extern constructor move_wide_const_from_inverted_u64 move_wide_const_from_inverted_u64)
1675
-
1676
- (decl pure partial imm_logic_from_u64 (Type u64) ImmLogic)
1677
- (extern constructor imm_logic_from_u64 imm_logic_from_u64)
1678
-
1679
- (decl pure partial imm_logic_from_imm64 (Type Imm64) ImmLogic)
1680
- (extern constructor imm_logic_from_imm64 imm_logic_from_imm64)
1681
-
1682
- (decl pure partial imm_shift_from_imm64 (Type Imm64) ImmShift)
1683
- (extern constructor imm_shift_from_imm64 imm_shift_from_imm64)
1684
-
1685
- (decl imm_shift_from_u8 (u8) ImmShift)
1686
- (extern constructor imm_shift_from_u8 imm_shift_from_u8)
1687
-
1688
- (decl imm12_from_u64 (Imm12) u64)
1689
- (extern extractor imm12_from_u64 imm12_from_u64)
1690
-
1691
- (decl u8_into_uimm5 (u8) UImm5)
1692
- (extern constructor u8_into_uimm5 u8_into_uimm5)
1693
-
1694
- (decl u8_into_imm12 (u8) Imm12)
1695
- (extern constructor u8_into_imm12 u8_into_imm12)
1696
-
1697
- (decl u64_into_imm_logic (Type u64) ImmLogic)
1698
- (extern constructor u64_into_imm_logic u64_into_imm_logic)
1699
-
1700
- (decl branch_target (VecMachLabel u8) BranchTarget)
1701
- (extern constructor branch_target branch_target)
1702
-
1703
- (decl targets_jt_size (VecMachLabel) u32)
1704
- (extern constructor targets_jt_size targets_jt_size)
1705
-
1706
- (decl targets_jt_space (VecMachLabel) CodeOffset)
1707
- (extern constructor targets_jt_space targets_jt_space)
1708
-
1709
- (decl targets_jt_info (VecMachLabel) BoxJTSequenceInfo)
1710
- (extern constructor targets_jt_info targets_jt_info)
1711
-
1712
- ;; Calculate the minimum floating-point bound for a conversion to floating
1713
- ;; point from an integer type.
1714
- ;; Accepts whether the output is signed, the size of the input
1715
- ;; floating point type in bits, and the size of the output integer type
1716
- ;; in bits.
1717
- (decl min_fp_value (bool u8 u8) Reg)
1718
- (extern constructor min_fp_value min_fp_value)
1719
-
1720
- ;; Calculate the maximum floating-point bound for a conversion to floating
1721
- ;; point from an integer type.
1722
- ;; Accepts whether the output is signed, the size of the input
1723
- ;; floating point type in bits, and the size of the output integer type
1724
- ;; in bits.
1725
- (decl max_fp_value (bool u8 u8) Reg)
1726
- (extern constructor max_fp_value max_fp_value)
1727
-
1728
- ;; Constructs an FPUOpRI.Ushr* given the size in bits of the value (or lane)
1729
- ;; and the amount to shift by.
1730
- (decl fpu_op_ri_ushr (u8 u8) FPUOpRI)
1731
- (extern constructor fpu_op_ri_ushr fpu_op_ri_ushr)
1732
-
1733
- ;; Constructs an FPUOpRIMod.Sli* given the size in bits of the value (or lane)
1734
- ;; and the amount to shift by.
1735
- (decl fpu_op_ri_sli (u8 u8) FPUOpRIMod)
1736
- (extern constructor fpu_op_ri_sli fpu_op_ri_sli)
1737
-
1738
- (decl pure partial lshr_from_u64 (Type u64) ShiftOpAndAmt)
1739
- (extern constructor lshr_from_u64 lshr_from_u64)
1740
-
1741
- (decl pure partial lshl_from_imm64 (Type Imm64) ShiftOpAndAmt)
1742
- (extern constructor lshl_from_imm64 lshl_from_imm64)
1743
-
1744
- (decl pure partial lshl_from_u64 (Type u64) ShiftOpAndAmt)
1745
- (extern constructor lshl_from_u64 lshl_from_u64)
1746
-
1747
- (decl pure partial ashr_from_u64 (Type u64) ShiftOpAndAmt)
1748
- (extern constructor ashr_from_u64 ashr_from_u64)
1749
-
1750
- (decl integral_ty (Type) Type)
1751
- (extern extractor integral_ty integral_ty)
1752
-
1753
- (decl valid_atomic_transaction (Type) Type)
1754
- (extern extractor valid_atomic_transaction valid_atomic_transaction)
1755
-
1756
- (decl pure partial is_zero_simm9 (SImm9) Unit)
1757
- (extern constructor is_zero_simm9 is_zero_simm9)
1758
-
1759
- (decl pure partial is_zero_uimm12 (UImm12Scaled) Unit)
1760
- (extern constructor is_zero_uimm12 is_zero_uimm12)
1761
-
1762
- ;; Helper to go directly from a `Value`, when it's an `iconst`, to an `Imm12`.
1763
- (decl imm12_from_value (Imm12) Value)
1764
- (extractor
1765
- (imm12_from_value n)
1766
- (iconst (u64_from_imm64 (imm12_from_u64 n))))
1767
-
1768
- ;; Conceptually the same as `imm12_from_value`, but tries negating the constant
1769
- ;; value (first sign-extending to handle narrow widths).
1770
- (decl pure partial imm12_from_negated_value (Value) Imm12)
1771
- (rule
1772
- (imm12_from_negated_value (has_type ty (iconst n)))
1773
- (if-let (imm12_from_u64 imm) (i64_as_u64 (i64_neg (i64_sextend_imm64 ty n))))
1774
- imm)
1775
-
1776
- ;; Helper type to represent a value and an extend operation fused together.
1777
- (type ExtendedValue extern (enum))
1778
- (decl extended_value_from_value (ExtendedValue) Value)
1779
- (extern extractor extended_value_from_value extended_value_from_value)
1780
-
1781
- ;; Constructors used to poke at the fields of an `ExtendedValue`.
1782
- (decl put_extended_in_reg (ExtendedValue) Reg)
1783
- (extern constructor put_extended_in_reg put_extended_in_reg)
1784
- (decl get_extended_op (ExtendedValue) ExtendOp)
1785
- (extern constructor get_extended_op get_extended_op)
1786
-
1787
- (decl nzcv (bool bool bool bool) NZCV)
1788
- (extern constructor nzcv nzcv)
1789
-
1790
- (decl cond_br_zero (Reg) CondBrKind)
1791
- (extern constructor cond_br_zero cond_br_zero)
1792
-
1793
- (decl cond_br_not_zero (Reg) CondBrKind)
1794
- (extern constructor cond_br_not_zero cond_br_not_zero)
1795
-
1796
- (decl cond_br_cond (Cond) CondBrKind)
1797
- (extern constructor cond_br_cond cond_br_cond)
1798
-
1799
- (decl pair_amode (Value u32) PairAMode)
1800
- (extern constructor pair_amode pair_amode)
1801
-
1802
- ;; Instruction creation helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1803
-
1804
- ;; Helper for creating the zero register.
1805
- (decl zero_reg () Reg)
1806
- (extern constructor zero_reg zero_reg)
1807
-
1808
- (decl fp_reg () Reg)
1809
- (extern constructor fp_reg fp_reg)
1810
-
1811
- (decl stack_reg () Reg)
1812
- (extern constructor stack_reg stack_reg)
1813
-
1814
- (decl writable_link_reg () WritableReg)
1815
- (extern constructor writable_link_reg writable_link_reg)
1816
-
1817
- (decl writable_zero_reg () WritableReg)
1818
- (extern constructor writable_zero_reg writable_zero_reg)
1819
-
1820
- (decl value_regs_zero () ValueRegs)
1821
- (rule (value_regs_zero)
1822
- (value_regs
1823
- (imm $I64 (ImmExtend.Zero) 0)
1824
- (imm $I64 (ImmExtend.Zero) 0)))
1825
-
1826
-
1827
- ;; Helper for emitting `MInst.Mov` instructions.
1828
- (decl mov (Reg Type) Reg)
1829
- (rule (mov src ty)
1830
- (let ((dst WritableReg (temp_writable_reg $I64))
1831
- (_ Unit (emit (MInst.Mov (operand_size ty) dst src))))
1832
- dst))
1833
-
1834
- ;; Helper for emitting `MInst.MovZ` instructions.
1835
- (decl movz (MoveWideConst OperandSize) Reg)
1836
- (rule (movz imm size)
1837
- (let ((dst WritableReg (temp_writable_reg $I64))
1838
- (_ Unit (emit (MInst.MovWide (MoveWideOp.MovZ) dst imm size))))
1839
- dst))
1840
-
1841
- ;; Helper for emitting `MInst.MovN` instructions.
1842
- (decl movn (MoveWideConst OperandSize) Reg)
1843
- (rule (movn imm size)
1844
- (let ((dst WritableReg (temp_writable_reg $I64))
1845
- (_ Unit (emit (MInst.MovWide (MoveWideOp.MovN) dst imm size))))
1846
- dst))
1847
-
1848
- ;; Helper for emitting `MInst.AluRRImmLogic` instructions.
1849
- (decl alu_rr_imm_logic (ALUOp Type Reg ImmLogic) Reg)
1850
- (rule (alu_rr_imm_logic op ty src imm)
1851
- (let ((dst WritableReg (temp_writable_reg $I64))
1852
- (_ Unit (emit (MInst.AluRRImmLogic op (operand_size ty) dst src imm))))
1853
- dst))
1854
-
1855
- ;; Helper for emitting `MInst.AluRRImmShift` instructions.
1856
- (decl alu_rr_imm_shift (ALUOp Type Reg ImmShift) Reg)
1857
- (rule (alu_rr_imm_shift op ty src imm)
1858
- (let ((dst WritableReg (temp_writable_reg $I64))
1859
- (_ Unit (emit (MInst.AluRRImmShift op (operand_size ty) dst src imm))))
1860
- dst))
1861
-
1862
- ;; Helper for emitting `MInst.AluRRR` instructions.
1863
- (decl alu_rrr (ALUOp Type Reg Reg) Reg)
1864
- (rule (alu_rrr op ty src1 src2)
1865
- (let ((dst WritableReg (temp_writable_reg $I64))
1866
- (_ Unit (emit (MInst.AluRRR op (operand_size ty) dst src1 src2))))
1867
- dst))
1868
-
1869
- ;; Helper for emitting `MInst.VecRRR` instructions.
1870
- (decl vec_rrr (VecALUOp Reg Reg VectorSize) Reg)
1871
- (rule (vec_rrr op src1 src2 size)
1872
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1873
- (_ Unit (emit (MInst.VecRRR op dst src1 src2 size))))
1874
- dst))
1875
-
1876
- ;; Helper for emitting `MInst.FpuRR` instructions.
1877
- (decl fpu_rr (FPUOp1 Reg ScalarSize) Reg)
1878
- (rule (fpu_rr op src size)
1879
- (let ((dst WritableReg (temp_writable_reg $F64))
1880
- (_ Unit (emit (MInst.FpuRR op size dst src))))
1881
- dst))
1882
-
1883
- ;; Helper for emitting `MInst.VecRRRMod` instructions which use three registers,
1884
- ;; one of which is both source and output.
1885
- (decl vec_rrr_mod (VecALUModOp Reg Reg Reg VectorSize) Reg)
1886
- (rule (vec_rrr_mod op src1 src2 src3 size)
1887
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1888
- (_1 Unit (emit (MInst.VecRRRMod op dst src1 src2 src3 size))))
1889
- dst))
1890
-
1891
- ;; Helper for emitting `MInst.VecFmlaElem` instructions which use three registers,
1892
- ;; one of which is both source and output.
1893
- (decl vec_fmla_elem (VecALUModOp Reg Reg Reg VectorSize u8) Reg)
1894
- (rule (vec_fmla_elem op src1 src2 src3 size idx)
1895
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1896
- (_1 Unit (emit (MInst.VecFmlaElem op dst src1 src2 src3 size idx))))
1897
- dst))
1898
-
1899
- (decl fpu_rri (FPUOpRI Reg) Reg)
1900
- (rule (fpu_rri op src)
1901
- (let ((dst WritableReg (temp_writable_reg $F64))
1902
- (_ Unit (emit (MInst.FpuRRI op dst src))))
1903
- dst))
1904
-
1905
- (decl fpu_rri_mod (FPUOpRIMod Reg Reg) Reg)
1906
- (rule (fpu_rri_mod op dst_src src)
1907
- (let ((dst WritableReg (temp_writable_reg $F64))
1908
- (_ Unit (emit (MInst.FpuRRIMod op dst dst_src src))))
1909
- dst))
1910
-
1911
- ;; Helper for emitting `MInst.FpuRRR` instructions.
1912
- (decl fpu_rrr (FPUOp2 Reg Reg ScalarSize) Reg)
1913
- (rule (fpu_rrr op src1 src2 size)
1914
- (let ((dst WritableReg (temp_writable_reg $F64))
1915
- (_ Unit (emit (MInst.FpuRRR op size dst src1 src2))))
1916
- dst))
1917
-
1918
- ;; Helper for emitting `MInst.FpuRRRR` instructions.
1919
- (decl fpu_rrrr (FPUOp3 ScalarSize Reg Reg Reg) Reg)
1920
- (rule (fpu_rrrr size op src1 src2 src3)
1921
- (let ((dst WritableReg (temp_writable_reg $F64))
1922
- (_ Unit (emit (MInst.FpuRRRR size op dst src1 src2 src3))))
1923
- dst))
1924
-
1925
- ;; Helper for emitting `MInst.FpuCmp` instructions.
1926
- (decl fpu_cmp (ScalarSize Reg Reg) ProducesFlags)
1927
- (rule (fpu_cmp size rn rm)
1928
- (ProducesFlags.ProducesFlagsSideEffect
1929
- (MInst.FpuCmp size rn rm)))
1930
-
1931
- ;; Helper for emitting `MInst.VecLanes` instructions.
1932
- (decl vec_lanes (VecLanesOp Reg VectorSize) Reg)
1933
- (rule (vec_lanes op src size)
1934
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1935
- (_ Unit (emit (MInst.VecLanes op dst src size))))
1936
- dst))
1937
-
1938
- ;; Helper for emitting `MInst.VecShiftImm` instructions.
1939
- (decl vec_shift_imm (VecShiftImmOp u8 Reg VectorSize) Reg)
1940
- (rule (vec_shift_imm op imm src size)
1941
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1942
- (_ Unit (emit (MInst.VecShiftImm op dst src size imm))))
1943
- dst))
1944
-
1945
- ;; Helper for emitting `MInst.VecDup` instructions.
1946
- (decl vec_dup (Reg VectorSize) Reg)
1947
- (rule (vec_dup src size)
1948
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1949
- (_ Unit (emit (MInst.VecDup dst src size))))
1950
- dst))
1951
-
1952
- ;; Helper for emitting `MInst.VecDupFromFpu` instructions.
1953
- (decl vec_dup_from_fpu (Reg VectorSize u8) Reg)
1954
- (rule (vec_dup_from_fpu src size lane)
1955
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1956
- (_ Unit (emit (MInst.VecDupFromFpu dst src size lane))))
1957
- dst))
1958
-
1959
- ;; Helper for emitting `MInst.VecDupImm` instructions.
1960
- (decl vec_dup_imm (ASIMDMovModImm bool VectorSize) Reg)
1961
- (rule (vec_dup_imm imm invert size)
1962
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1963
- (_ Unit (emit (MInst.VecDupImm dst imm invert size))))
1964
- dst))
1965
-
1966
- ;; Helper for emitting `MInst.AluRRImm12` instructions.
1967
- (decl alu_rr_imm12 (ALUOp Type Reg Imm12) Reg)
1968
- (rule (alu_rr_imm12 op ty src imm)
1969
- (let ((dst WritableReg (temp_writable_reg $I64))
1970
- (_ Unit (emit (MInst.AluRRImm12 op (operand_size ty) dst src imm))))
1971
- dst))
1972
-
1973
- ;; Helper for emitting `MInst.AluRRRShift` instructions.
1974
- (decl alu_rrr_shift (ALUOp Type Reg Reg ShiftOpAndAmt) Reg)
1975
- (rule (alu_rrr_shift op ty src1 src2 shift)
1976
- (let ((dst WritableReg (temp_writable_reg $I64))
1977
- (_ Unit (emit (MInst.AluRRRShift op (operand_size ty) dst src1 src2 shift))))
1978
- dst))
1979
-
1980
- ;; Helper for emitting `cmp` instructions, setting flags, with a right-shifted
1981
- ;; second operand register.
1982
- (decl cmp_rr_shift (OperandSize Reg Reg u64) ProducesFlags)
1983
- (rule (cmp_rr_shift size src1 src2 shift_amount)
1984
- (if-let shift (lshr_from_u64 $I64 shift_amount))
1985
- (ProducesFlags.ProducesFlagsSideEffect
1986
- (MInst.AluRRRShift (ALUOp.SubS) size (writable_zero_reg)
1987
- src1 src2 shift)))
1988
-
1989
- ;; Helper for emitting `cmp` instructions, setting flags, with an arithmetic right-shifted
1990
- ;; second operand register.
1991
- (decl cmp_rr_shift_asr (OperandSize Reg Reg u64) ProducesFlags)
1992
- (rule (cmp_rr_shift_asr size src1 src2 shift_amount)
1993
- (if-let shift (ashr_from_u64 $I64 shift_amount))
1994
- (ProducesFlags.ProducesFlagsSideEffect
1995
- (MInst.AluRRRShift (ALUOp.SubS) size (writable_zero_reg)
1996
- src1 src2 shift)))
1997
-
1998
- ;; Helper for emitting `MInst.AluRRRExtend` instructions.
1999
- (decl alu_rrr_extend (ALUOp Type Reg Reg ExtendOp) Reg)
2000
- (rule (alu_rrr_extend op ty src1 src2 extend)
2001
- (let ((dst WritableReg (temp_writable_reg $I64))
2002
- (_ Unit (emit (MInst.AluRRRExtend op (operand_size ty) dst src1 src2 extend))))
2003
- dst))
2004
-
2005
- ;; Same as `alu_rrr_extend`, but takes an `ExtendedValue` packed "pair" instead
2006
- ;; of a `Reg` and an `ExtendOp`.
2007
- (decl alu_rr_extend_reg (ALUOp Type Reg ExtendedValue) Reg)
2008
- (rule (alu_rr_extend_reg op ty src1 extended_reg)
2009
- (let ((src2 Reg (put_extended_in_reg extended_reg))
2010
- (extend ExtendOp (get_extended_op extended_reg)))
2011
- (alu_rrr_extend op ty src1 src2 extend)))
2012
-
2013
- ;; Helper for emitting `MInst.AluRRRR` instructions.
2014
- (decl alu_rrrr (ALUOp3 Type Reg Reg Reg) Reg)
2015
- (rule (alu_rrrr op ty src1 src2 src3)
2016
- (let ((dst WritableReg (temp_writable_reg $I64))
2017
- (_ Unit (emit (MInst.AluRRRR op (operand_size ty) dst src1 src2 src3))))
2018
- dst))
2019
-
2020
- ;; Helper for emitting paired `MInst.AluRRR` instructions
2021
- (decl alu_rrr_with_flags_paired (Type Reg Reg ALUOp) ProducesFlags)
2022
- (rule (alu_rrr_with_flags_paired ty src1 src2 alu_op)
2023
- (let ((dst WritableReg (temp_writable_reg $I64)))
2024
- (ProducesFlags.ProducesFlagsReturnsResultWithConsumer
2025
- (MInst.AluRRR alu_op (operand_size ty) dst src1 src2)
2026
- dst)))
2027
-
2028
- ;; Should only be used for AdcS and SbcS
2029
- (decl alu_rrr_with_flags_chained (Type Reg Reg ALUOp) ConsumesAndProducesFlags)
2030
- (rule (alu_rrr_with_flags_chained ty src1 src2 alu_op)
2031
- (let ((dst WritableReg (temp_writable_reg $I64)))
2032
- (ConsumesAndProducesFlags.ReturnsReg
2033
- (MInst.AluRRR alu_op (operand_size ty) dst src1 src2)
2034
- dst)))
2035
-
2036
- ;; Helper for emitting `MInst.BitRR` instructions.
2037
- (decl bit_rr (BitOp Type Reg) Reg)
2038
- (rule (bit_rr op ty src)
2039
- (let ((dst WritableReg (temp_writable_reg $I64))
2040
- (_ Unit (emit (MInst.BitRR op (operand_size ty) dst src))))
2041
- dst))
2042
-
2043
- ;; Helper for emitting `adds` instructions.
2044
- (decl add_with_flags_paired (Type Reg Reg) ProducesFlags)
2045
- (rule (add_with_flags_paired ty src1 src2)
2046
- (let ((dst WritableReg (temp_writable_reg $I64)))
2047
- (ProducesFlags.ProducesFlagsReturnsResultWithConsumer
2048
- (MInst.AluRRR (ALUOp.AddS) (operand_size ty) dst src1 src2)
2049
- dst)))
2050
-
2051
- ;; Helper for emitting `adc` instructions.
2052
- (decl adc_paired (Type Reg Reg) ConsumesFlags)
2053
- (rule (adc_paired ty src1 src2)
2054
- (let ((dst WritableReg (temp_writable_reg $I64)))
2055
- (ConsumesFlags.ConsumesFlagsReturnsResultWithProducer
2056
- (MInst.AluRRR (ALUOp.Adc) (operand_size ty) dst src1 src2)
2057
- dst)))
2058
-
2059
- ;; Helper for emitting `subs` instructions.
2060
- (decl sub_with_flags_paired (Type Reg Reg) ProducesFlags)
2061
- (rule (sub_with_flags_paired ty src1 src2)
2062
- (let ((dst WritableReg (temp_writable_reg $I64)))
2063
- (ProducesFlags.ProducesFlagsReturnsResultWithConsumer
2064
- (MInst.AluRRR (ALUOp.SubS) (operand_size ty) dst src1 src2)
2065
- dst)))
2066
-
2067
- ;; Helper for materializing a boolean value into a register from
2068
- ;; flags.
2069
- (decl materialize_bool_result (Cond) ConsumesFlags)
2070
- (rule (materialize_bool_result cond)
2071
- (let ((dst WritableReg (temp_writable_reg $I64)))
2072
- (ConsumesFlags.ConsumesFlagsReturnsReg
2073
- (MInst.CSet dst cond)
2074
- dst)))
2075
-
2076
- (decl cmn_imm (OperandSize Reg Imm12) ProducesFlags)
2077
- (rule (cmn_imm size src1 src2)
2078
- (ProducesFlags.ProducesFlagsSideEffect
2079
- (MInst.AluRRImm12 (ALUOp.AddS) size (writable_zero_reg)
2080
- src1 src2)))
2081
-
2082
- (decl cmp (OperandSize Reg Reg) ProducesFlags)
2083
- (rule (cmp size src1 src2)
2084
- (ProducesFlags.ProducesFlagsSideEffect
2085
- (MInst.AluRRR (ALUOp.SubS) size (writable_zero_reg)
2086
- src1 src2)))
2087
-
2088
- (decl cmp_imm (OperandSize Reg Imm12) ProducesFlags)
2089
- (rule (cmp_imm size src1 src2)
2090
- (ProducesFlags.ProducesFlagsSideEffect
2091
- (MInst.AluRRImm12 (ALUOp.SubS) size (writable_zero_reg)
2092
- src1 src2)))
2093
-
2094
- (decl cmp64_imm (Reg Imm12) ProducesFlags)
2095
- (rule (cmp64_imm src1 src2)
2096
- (cmp_imm (OperandSize.Size64) src1 src2))
2097
-
2098
- (decl cmp_extend (OperandSize Reg Reg ExtendOp) ProducesFlags)
2099
- (rule (cmp_extend size src1 src2 extend)
2100
- (ProducesFlags.ProducesFlagsSideEffect
2101
- (MInst.AluRRRExtend (ALUOp.SubS) size (writable_zero_reg)
2102
- src1 src2 extend)))
2103
-
2104
- ;; Helper for emitting `sbc` instructions.
2105
- (decl sbc_paired (Type Reg Reg) ConsumesFlags)
2106
- (rule (sbc_paired ty src1 src2)
2107
- (let ((dst WritableReg (temp_writable_reg $I64)))
2108
- (ConsumesFlags.ConsumesFlagsReturnsResultWithProducer
2109
- (MInst.AluRRR (ALUOp.Sbc) (operand_size ty) dst src1 src2)
2110
- dst)))
2111
-
2112
- ;; Helper for emitting `MInst.VecMisc` instructions.
2113
- (decl vec_misc (VecMisc2 Reg VectorSize) Reg)
2114
- (rule (vec_misc op src size)
2115
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2116
- (_ Unit (emit (MInst.VecMisc op dst src size))))
2117
- dst))
2118
-
2119
- ;; Helper for emitting `MInst.VecTbl` instructions.
2120
- (decl vec_tbl (Reg Reg) Reg)
2121
- (rule (vec_tbl rn rm)
2122
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2123
- (_ Unit (emit (MInst.VecTbl dst rn rm))))
2124
- dst))
2125
-
2126
- (decl vec_tbl_ext (Reg Reg Reg) Reg)
2127
- (rule (vec_tbl_ext ri rn rm)
2128
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2129
- (_ Unit (emit (MInst.VecTblExt dst ri rn rm))))
2130
- dst))
2131
-
2132
- ;; Helper for emitting `MInst.VecTbl2` instructions.
2133
- (decl vec_tbl2 (Reg Reg Reg Type) Reg)
2134
- (rule (vec_tbl2 rn rn2 rm ty)
2135
- (let (
2136
- (dst WritableReg (temp_writable_reg $I8X16))
2137
- (_ Unit (emit (MInst.VecTbl2 dst rn rn2 rm)))
2138
- )
2139
- dst))
2140
-
2141
- ;; Helper for emitting `MInst.VecTbl2Ext` instructions.
2142
- (decl vec_tbl2_ext (Reg Reg Reg Reg Type) Reg)
2143
- (rule (vec_tbl2_ext ri rn rn2 rm ty)
2144
- (let (
2145
- (dst WritableReg (temp_writable_reg $I8X16))
2146
- (_ Unit (emit (MInst.VecTbl2Ext dst ri rn rn2 rm)))
2147
- )
2148
- dst))
2149
-
2150
- ;; Helper for emitting `MInst.VecRRRLong` instructions.
2151
- (decl vec_rrr_long (VecRRRLongOp Reg Reg bool) Reg)
2152
- (rule (vec_rrr_long op src1 src2 high_half)
2153
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2154
- (_ Unit (emit (MInst.VecRRRLong op dst src1 src2 high_half))))
2155
- dst))
2156
-
2157
- ;; Helper for emitting `MInst.VecRRPairLong` instructions.
2158
- (decl vec_rr_pair_long (VecRRPairLongOp Reg) Reg)
2159
- (rule (vec_rr_pair_long op src)
2160
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2161
- (_ Unit (emit (MInst.VecRRPairLong op dst src))))
2162
- dst))
2163
-
2164
- ;; Helper for emitting `MInst.VecRRRLongMod` instructions.
2165
- (decl vec_rrrr_long (VecRRRLongModOp Reg Reg Reg bool) Reg)
2166
- (rule (vec_rrrr_long op src1 src2 src3 high_half)
2167
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2168
- (_ Unit (emit (MInst.VecRRRLongMod op dst src1 src2 src3 high_half))))
2169
- dst))
2170
-
2171
- ;; Helper for emitting `MInst.VecRRNarrow` instructions.
2172
- (decl vec_rr_narrow_low (VecRRNarrowOp Reg ScalarSize) Reg)
2173
- (rule (vec_rr_narrow_low op src size)
2174
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2175
- (_ Unit (emit (MInst.VecRRNarrowLow op dst src size))))
2176
- dst))
2177
-
2178
- ;; Helper for emitting `MInst.VecRRNarrow` instructions which update the
2179
- ;; high half of the destination register.
2180
- (decl vec_rr_narrow_high (VecRRNarrowOp Reg Reg ScalarSize) Reg)
2181
- (rule (vec_rr_narrow_high op mod src size)
2182
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2183
- (_ Unit (emit (MInst.VecRRNarrowHigh op dst mod src size))))
2184
- dst))
2185
-
2186
- ;; Helper for emitting `MInst.VecRRLong` instructions.
2187
- (decl vec_rr_long (VecRRLongOp Reg bool) Reg)
2188
- (rule (vec_rr_long op src high_half)
2189
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2190
- (_ Unit (emit (MInst.VecRRLong op dst src high_half))))
2191
- dst))
2192
-
2193
- ;; Helper for emitting `MInst.FpuCSel32` / `MInst.FpuCSel64`
2194
- ;; instructions.
2195
- (decl fpu_csel (Type Cond Reg Reg) ConsumesFlags)
2196
- (rule (fpu_csel $F32 cond if_true if_false)
2197
- (let ((dst WritableReg (temp_writable_reg $F32)))
2198
- (ConsumesFlags.ConsumesFlagsReturnsReg
2199
- (MInst.FpuCSel32 dst if_true if_false cond)
2200
- dst)))
2201
-
2202
- (rule (fpu_csel $F64 cond if_true if_false)
2203
- (let ((dst WritableReg (temp_writable_reg $F64)))
2204
- (ConsumesFlags.ConsumesFlagsReturnsReg
2205
- (MInst.FpuCSel64 dst if_true if_false cond)
2206
- dst)))
2207
-
2208
- ;; Helper for emitting `MInst.VecCSel` instructions.
2209
- (decl vec_csel (Cond Reg Reg) ConsumesFlags)
2210
- (rule (vec_csel cond if_true if_false)
2211
- (let ((dst WritableReg (temp_writable_reg $I8X16)))
2212
- (ConsumesFlags.ConsumesFlagsReturnsReg
2213
- (MInst.VecCSel dst if_true if_false cond)
2214
- dst)))
2215
-
2216
- ;; Helper for emitting `MInst.FpuRound` instructions.
2217
- (decl fpu_round (FpuRoundMode Reg) Reg)
2218
- (rule (fpu_round op rn)
2219
- (let ((dst WritableReg (temp_writable_reg $F64))
2220
- (_ Unit (emit (MInst.FpuRound op dst rn))))
2221
- dst))
2222
-
2223
- ;; Helper for emitting `MInst.FpuMove64` and `MInst.FpuMove128` instructions.
2224
- (decl fpu_move (Type Reg) Reg)
2225
- (rule (fpu_move _ src)
2226
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2227
- (_ Unit (emit (MInst.FpuMove128 dst src))))
2228
- dst))
2229
- (rule 1 (fpu_move (fits_in_64 _) src)
2230
- (let ((dst WritableReg (temp_writable_reg $F64))
2231
- (_ Unit (emit (MInst.FpuMove64 dst src))))
2232
- dst))
2233
-
2234
- ;; Helper for emitting `MInst.MovToFpu` instructions.
2235
- (decl mov_to_fpu (Reg ScalarSize) Reg)
2236
- (rule (mov_to_fpu x size)
2237
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2238
- (_ Unit (emit (MInst.MovToFpu dst x size))))
2239
- dst))
2240
-
2241
- ;; Helper for emitting `MInst.FpuMoveFPImm` instructions.
2242
- (decl fpu_move_fp_imm (ASIMDFPModImm ScalarSize) Reg)
2243
- (rule (fpu_move_fp_imm imm size)
2244
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2245
- (_ Unit (emit (MInst.FpuMoveFPImm dst imm size))))
2246
- dst))
2247
-
2248
- ;; Helper for emitting `MInst.MovToVec` instructions.
2249
- (decl mov_to_vec (Reg Reg u8 VectorSize) Reg)
2250
- (rule (mov_to_vec src1 src2 lane size)
2251
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2252
- (_ Unit (emit (MInst.MovToVec dst src1 src2 lane size))))
2253
- dst))
2254
-
2255
- ;; Helper for emitting `MInst.VecMovElement` instructions.
2256
- (decl mov_vec_elem (Reg Reg u8 u8 VectorSize) Reg)
2257
- (rule (mov_vec_elem src1 src2 dst_idx src_idx size)
2258
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2259
- (_ Unit (emit (MInst.VecMovElement dst src1 src2 dst_idx src_idx size))))
2260
- dst))
2261
-
2262
- ;; Helper for emitting `MInst.MovFromVec` instructions.
2263
- (decl mov_from_vec (Reg u8 ScalarSize) Reg)
2264
- (rule (mov_from_vec rn idx size)
2265
- (let ((dst WritableReg (temp_writable_reg $I64))
2266
- (_ Unit (emit (MInst.MovFromVec dst rn idx size))))
2267
- dst))
2268
-
2269
- ;; Helper for emitting `MInst.MovFromVecSigned` instructions.
2270
- (decl mov_from_vec_signed (Reg u8 VectorSize OperandSize) Reg)
2271
- (rule (mov_from_vec_signed rn idx size scalar_size)
2272
- (let ((dst WritableReg (temp_writable_reg $I64))
2273
- (_ Unit (emit (MInst.MovFromVecSigned dst rn idx size scalar_size))))
2274
- dst))
2275
-
2276
- (decl fpu_move_from_vec (Reg u8 VectorSize) Reg)
2277
- (rule (fpu_move_from_vec rn idx size)
2278
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2279
- (_ Unit (emit (MInst.FpuMoveFromVec dst rn idx size))))
2280
- dst))
2281
-
2282
- ;; Helper for emitting `MInst.Extend` instructions.
2283
- (decl extend (Reg bool u8 u8) Reg)
2284
- (rule (extend rn signed from_bits to_bits)
2285
- (let ((dst WritableReg (temp_writable_reg $I64))
2286
- (_ Unit (emit (MInst.Extend dst rn signed from_bits to_bits))))
2287
- dst))
2288
-
2289
- ;; Helper for emitting `MInst.FpuExtend` instructions.
2290
- (decl fpu_extend (Reg ScalarSize) Reg)
2291
- (rule (fpu_extend src size)
2292
- (let ((dst WritableReg (temp_writable_reg $F32X4))
2293
- (_ Unit (emit (MInst.FpuExtend dst src size))))
2294
- dst))
2295
-
2296
- ;; Helper for emitting `MInst.VecExtend` instructions.
2297
- (decl vec_extend (VecExtendOp Reg bool ScalarSize) Reg)
2298
- (rule (vec_extend op src high_half size)
2299
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2300
- (_ Unit (emit (MInst.VecExtend op dst src high_half size))))
2301
- dst))
2302
-
2303
- ;; Helper for emitting `MInst.VecExtract` instructions.
2304
- (decl vec_extract (Reg Reg u8) Reg)
2305
- (rule (vec_extract src1 src2 idx)
2306
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2307
- (_ Unit (emit (MInst.VecExtract dst src1 src2 idx))))
2308
- dst))
2309
-
2310
- ;; Helper for emitting `MInst.LoadAcquire` instructions.
2311
- (decl load_acquire (Type MemFlags Reg) Reg)
2312
- (rule (load_acquire ty flags addr)
2313
- (let ((dst WritableReg (temp_writable_reg $I64))
2314
- (_ Unit (emit (MInst.LoadAcquire ty dst addr flags))))
2315
- dst))
2316
-
2317
- ;; Helper for emitting `MInst.StoreRelease` instructions.
2318
- (decl store_release (Type MemFlags Reg Reg) SideEffectNoResult)
2319
- (rule (store_release ty flags src addr)
2320
- (SideEffectNoResult.Inst (MInst.StoreRelease ty src addr flags)))
2321
-
2322
- ;; Helper for generating a `tst` instruction.
2323
- ;;
2324
- ;; Produces a `ProducesFlags` rather than a register or emitted instruction
2325
- ;; which must be paired with `with_flags*` helpers.
2326
- (decl tst_imm (Type Reg ImmLogic) ProducesFlags)
2327
- (rule (tst_imm ty reg imm)
2328
- (ProducesFlags.ProducesFlagsSideEffect
2329
- (MInst.AluRRImmLogic (ALUOp.AndS)
2330
- (operand_size ty)
2331
- (writable_zero_reg)
2332
- reg
2333
- imm)))
2334
-
2335
- ;; Helper for generating a `CSel` instruction.
2336
- ;;
2337
- ;; Note that this doesn't actually emit anything, instead it produces a
2338
- ;; `ConsumesFlags` instruction which must be consumed with `with_flags*`
2339
- ;; helpers.
2340
- (decl csel (Cond Reg Reg) ConsumesFlags)
2341
- (rule (csel cond if_true if_false)
2342
- (let ((dst WritableReg (temp_writable_reg $I64)))
2343
- (ConsumesFlags.ConsumesFlagsReturnsReg
2344
- (MInst.CSel dst cond if_true if_false)
2345
- dst)))
2346
-
2347
- ;; Helper for constructing `cset` instructions.
2348
- (decl cset (Cond) ConsumesFlags)
2349
- (rule (cset cond)
2350
- (let ((dst WritableReg (temp_writable_reg $I64)))
2351
- (ConsumesFlags.ConsumesFlagsReturnsReg (MInst.CSet dst cond) dst)))
2352
-
2353
- ;; Helper for constructing `cset` instructions, when the flags producer will
2354
- ;; also return a value.
2355
- (decl cset_paired (Cond) ConsumesFlags)
2356
- (rule (cset_paired cond)
2357
- (let ((dst WritableReg (temp_writable_reg $I64)))
2358
- (ConsumesFlags.ConsumesFlagsReturnsResultWithProducer (MInst.CSet dst cond) dst)))
2359
-
2360
- ;; Helper for constructing `csetm` instructions.
2361
- (decl csetm (Cond) ConsumesFlags)
2362
- (rule (csetm cond)
2363
- (let ((dst WritableReg (temp_writable_reg $I64)))
2364
- (ConsumesFlags.ConsumesFlagsReturnsReg (MInst.CSetm dst cond) dst)))
2365
-
2366
- ;; Helper for generating a `CSNeg` instruction.
2367
- ;;
2368
- ;; Note that this doesn't actually emit anything, instead it produces a
2369
- ;; `ConsumesFlags` instruction which must be consumed with `with_flags*`
2370
- ;; helpers.
2371
- (decl csneg (Cond Reg Reg) ConsumesFlags)
2372
- (rule (csneg cond if_true if_false)
2373
- (let ((dst WritableReg (temp_writable_reg $I64)))
2374
- (ConsumesFlags.ConsumesFlagsReturnsReg
2375
- (MInst.CSNeg dst cond if_true if_false)
2376
- dst)))
2377
-
2378
- ;; Helper for generating `MInst.CCmp` instructions.
2379
- ;; Creates a new `ProducesFlags` from the supplied `ProducesFlags` followed
2380
- ;; immediately by the `MInst.CCmp` instruction.
2381
- (decl ccmp (OperandSize Reg Reg NZCV Cond ProducesFlags) ProducesFlags)
2382
- (rule (ccmp size rn rm nzcv cond inst_input)
2383
- (produces_flags_concat inst_input (ProducesFlags.ProducesFlagsSideEffect (MInst.CCmp size rn rm nzcv cond))))
2384
-
2385
- ;; Helper for generating `MInst.CCmpImm` instructions.
2386
- (decl ccmp_imm (OperandSize Reg UImm5 NZCV Cond) ConsumesFlags)
2387
- (rule 1 (ccmp_imm size rn imm nzcv cond)
2388
- (let ((dst WritableReg (temp_writable_reg $I64)))
2389
- (ConsumesFlags.ConsumesFlagsTwiceReturnsValueRegs
2390
- (MInst.CCmpImm size rn imm nzcv cond)
2391
- (MInst.CSet dst cond)
2392
- (value_reg dst))))
2393
-
2394
- ;; Helpers for generating `add` instructions.
2395
-
2396
- (decl add (Type Reg Reg) Reg)
2397
- (rule (add ty x y) (alu_rrr (ALUOp.Add) ty x y))
2398
-
2399
- (decl add_imm (Type Reg Imm12) Reg)
2400
- (rule (add_imm ty x y) (alu_rr_imm12 (ALUOp.Add) ty x y))
2401
-
2402
- (decl add_extend (Type Reg ExtendedValue) Reg)
2403
- (rule (add_extend ty x y) (alu_rr_extend_reg (ALUOp.Add) ty x y))
2404
-
2405
- (decl add_extend_op (Type Reg Reg ExtendOp) Reg)
2406
- (rule (add_extend_op ty x y extend) (alu_rrr_extend (ALUOp.Add) ty x y extend))
2407
-
2408
- (decl add_shift (Type Reg Reg ShiftOpAndAmt) Reg)
2409
- (rule (add_shift ty x y z) (alu_rrr_shift (ALUOp.Add) ty x y z))
2410
-
2411
- (decl add_vec (Reg Reg VectorSize) Reg)
2412
- (rule (add_vec x y size) (vec_rrr (VecALUOp.Add) x y size))
2413
-
2414
- ;; Helpers for generating `sub` instructions.
2415
-
2416
- (decl sub (Type Reg Reg) Reg)
2417
- (rule (sub ty x y) (alu_rrr (ALUOp.Sub) ty x y))
2418
-
2419
- (decl sub_imm (Type Reg Imm12) Reg)
2420
- (rule (sub_imm ty x y) (alu_rr_imm12 (ALUOp.Sub) ty x y))
2421
-
2422
- (decl sub_extend (Type Reg ExtendedValue) Reg)
2423
- (rule (sub_extend ty x y) (alu_rr_extend_reg (ALUOp.Sub) ty x y))
2424
-
2425
- (decl sub_shift (Type Reg Reg ShiftOpAndAmt) Reg)
2426
- (rule (sub_shift ty x y z) (alu_rrr_shift (ALUOp.Sub) ty x y z))
2427
-
2428
- (decl sub_vec (Reg Reg VectorSize) Reg)
2429
- (rule (sub_vec x y size) (vec_rrr (VecALUOp.Sub) x y size))
2430
-
2431
- (decl sub_i128 (ValueRegs ValueRegs) ValueRegs)
2432
- (rule (sub_i128 x y)
2433
- (let
2434
- ;; Get the high/low registers for `x`.
2435
- ((x_regs ValueRegs x)
2436
- (x_lo Reg (value_regs_get x_regs 0))
2437
- (x_hi Reg (value_regs_get x_regs 1))
2438
-
2439
- ;; Get the high/low registers for `y`.
2440
- (y_regs ValueRegs y)
2441
- (y_lo Reg (value_regs_get y_regs 0))
2442
- (y_hi Reg (value_regs_get y_regs 1)))
2443
- ;; the actual subtraction is `subs` followed by `sbc` which comprises
2444
- ;; the low/high bits of the result
2445
- (with_flags
2446
- (sub_with_flags_paired $I64 x_lo y_lo)
2447
- (sbc_paired $I64 x_hi y_hi))))
2448
-
2449
- ;; Helpers for generating `madd` instructions.
2450
-
2451
- (decl madd (Type Reg Reg Reg) Reg)
2452
- (rule (madd ty x y z) (alu_rrrr (ALUOp3.MAdd) ty x y z))
2453
-
2454
- ;; Helpers for generating `msub` instructions.
2455
-
2456
- (decl msub (Type Reg Reg Reg) Reg)
2457
- (rule (msub ty x y z) (alu_rrrr (ALUOp3.MSub) ty x y z))
2458
-
2459
- ;; Helpers for generating `umaddl` instructions
2460
- (decl umaddl (Reg Reg Reg) Reg)
2461
- (rule (umaddl x y z) (alu_rrrr (ALUOp3.UMAddL) $I32 x y z))
2462
-
2463
- ;; Helpers for generating `smaddl` instructions
2464
- (decl smaddl (Reg Reg Reg) Reg)
2465
- (rule (smaddl x y z) (alu_rrrr (ALUOp3.SMAddL) $I32 x y z))
2466
-
2467
- ;; Helper for generating `uqadd` instructions.
2468
- (decl uqadd (Reg Reg VectorSize) Reg)
2469
- (rule (uqadd x y size) (vec_rrr (VecALUOp.Uqadd) x y size))
2470
-
2471
- ;; Helper for generating `sqadd` instructions.
2472
- (decl sqadd (Reg Reg VectorSize) Reg)
2473
- (rule (sqadd x y size) (vec_rrr (VecALUOp.Sqadd) x y size))
2474
-
2475
- ;; Helper for generating `uqsub` instructions.
2476
- (decl uqsub (Reg Reg VectorSize) Reg)
2477
- (rule (uqsub x y size) (vec_rrr (VecALUOp.Uqsub) x y size))
2478
-
2479
- ;; Helper for generating `sqsub` instructions.
2480
- (decl sqsub (Reg Reg VectorSize) Reg)
2481
- (rule (sqsub x y size) (vec_rrr (VecALUOp.Sqsub) x y size))
2482
-
2483
- ;; Helper for generating `umulh` instructions.
2484
- (decl umulh (Type Reg Reg) Reg)
2485
- (rule (umulh ty x y) (alu_rrr (ALUOp.UMulH) ty x y))
2486
-
2487
- ;; Helper for generating `smulh` instructions.
2488
- (decl smulh (Type Reg Reg) Reg)
2489
- (rule (smulh ty x y) (alu_rrr (ALUOp.SMulH) ty x y))
2490
-
2491
- ;; Helper for generating `mul` instructions.
2492
- (decl mul (Reg Reg VectorSize) Reg)
2493
- (rule (mul x y size) (vec_rrr (VecALUOp.Mul) x y size))
2494
-
2495
- ;; Helper for generating `neg` instructions.
2496
- (decl neg (Reg VectorSize) Reg)
2497
- (rule (neg x size) (vec_misc (VecMisc2.Neg) x size))
2498
-
2499
- ;; Helper for generating `rev16` instructions.
2500
- (decl rev16 (Reg VectorSize) Reg)
2501
- (rule (rev16 x size) (vec_misc (VecMisc2.Rev16) x size))
2502
-
2503
- ;; Helper for generating `rev32` instructions.
2504
- (decl rev32 (Reg VectorSize) Reg)
2505
- (rule (rev32 x size) (vec_misc (VecMisc2.Rev32) x size))
2506
-
2507
- ;; Helper for generating `rev64` instructions.
2508
- (decl rev64 (Reg VectorSize) Reg)
2509
- (rule (rev64 x size) (vec_misc (VecMisc2.Rev64) x size))
2510
-
2511
- ;; Helper for generating `xtn` instructions.
2512
- (decl xtn (Reg ScalarSize) Reg)
2513
- (rule (xtn x size) (vec_rr_narrow_low (VecRRNarrowOp.Xtn) x size))
2514
-
2515
- ;; Helper for generating `fcvtn` instructions.
2516
- (decl fcvtn (Reg ScalarSize) Reg)
2517
- (rule (fcvtn x size) (vec_rr_narrow_low (VecRRNarrowOp.Fcvtn) x size))
2518
-
2519
- ;; Helper for generating `sqxtn` instructions.
2520
- (decl sqxtn (Reg ScalarSize) Reg)
2521
- (rule (sqxtn x size) (vec_rr_narrow_low (VecRRNarrowOp.Sqxtn) x size))
2522
-
2523
- ;; Helper for generating `sqxtn2` instructions.
2524
- (decl sqxtn2 (Reg Reg ScalarSize) Reg)
2525
- (rule (sqxtn2 x y size) (vec_rr_narrow_high (VecRRNarrowOp.Sqxtn) x y size))
2526
-
2527
- ;; Helper for generating `sqxtun` instructions.
2528
- (decl sqxtun (Reg ScalarSize) Reg)
2529
- (rule (sqxtun x size) (vec_rr_narrow_low (VecRRNarrowOp.Sqxtun) x size))
2530
-
2531
- ;; Helper for generating `sqxtun2` instructions.
2532
- (decl sqxtun2 (Reg Reg ScalarSize) Reg)
2533
- (rule (sqxtun2 x y size) (vec_rr_narrow_high (VecRRNarrowOp.Sqxtun) x y size))
2534
-
2535
- ;; Helper for generating `uqxtn` instructions.
2536
- (decl uqxtn (Reg ScalarSize) Reg)
2537
- (rule (uqxtn x size) (vec_rr_narrow_low (VecRRNarrowOp.Uqxtn) x size))
2538
-
2539
- ;; Helper for generating `uqxtn2` instructions.
2540
- (decl uqxtn2 (Reg Reg ScalarSize) Reg)
2541
- (rule (uqxtn2 x y size) (vec_rr_narrow_high (VecRRNarrowOp.Uqxtn) x y size))
2542
-
2543
- ;; Helper for generating `fence` instructions.
2544
- (decl aarch64_fence () SideEffectNoResult)
2545
- (rule (aarch64_fence)
2546
- (SideEffectNoResult.Inst (MInst.Fence)))
2547
-
2548
- ;; Helper for generating `csdb` instructions.
2549
- (decl csdb () SideEffectNoResult)
2550
- (rule (csdb)
2551
- (SideEffectNoResult.Inst (MInst.Csdb)))
2552
-
2553
- ;; Helper for generating `brk` instructions.
2554
- (decl brk () SideEffectNoResult)
2555
- (rule (brk)
2556
- (SideEffectNoResult.Inst (MInst.Brk)))
2557
-
2558
- ;; Helper for generating `addp` instructions.
2559
- (decl addp (Reg Reg VectorSize) Reg)
2560
- (rule (addp x y size) (vec_rrr (VecALUOp.Addp) x y size))
2561
-
2562
- ;; Helper for generating `zip1` instructions.
2563
- (decl zip1 (Reg Reg VectorSize) Reg)
2564
- (rule (zip1 x y size) (vec_rrr (VecALUOp.Zip1) x y size))
2565
-
2566
- ;; Helper for generating vector `abs` instructions.
2567
- (decl vec_abs (Reg VectorSize) Reg)
2568
- (rule (vec_abs x size) (vec_misc (VecMisc2.Abs) x size))
2569
-
2570
- ;; Helper for generating instruction sequences to calculate a scalar absolute
2571
- ;; value.
2572
- (decl abs (OperandSize Reg) Reg)
2573
- (rule (abs size x)
2574
- (value_regs_get (with_flags (cmp_imm size x (u8_into_imm12 0))
2575
- (csneg (Cond.Gt) x x)) 0))
2576
-
2577
- ;; Helper for generating `addv` instructions.
2578
- (decl addv (Reg VectorSize) Reg)
2579
- (rule (addv x size) (vec_lanes (VecLanesOp.Addv) x size))
2580
-
2581
- ;; Helper for generating `shll32` instructions.
2582
- (decl shll32 (Reg bool) Reg)
2583
- (rule (shll32 x high_half) (vec_rr_long (VecRRLongOp.Shll32) x high_half))
2584
-
2585
- ;; Helpers for generating `addlp` instructions.
2586
-
2587
- (decl saddlp8 (Reg) Reg)
2588
- (rule (saddlp8 x) (vec_rr_pair_long (VecRRPairLongOp.Saddlp8) x))
2589
-
2590
- (decl saddlp16 (Reg) Reg)
2591
- (rule (saddlp16 x) (vec_rr_pair_long (VecRRPairLongOp.Saddlp16) x))
2592
-
2593
- (decl uaddlp8 (Reg) Reg)
2594
- (rule (uaddlp8 x) (vec_rr_pair_long (VecRRPairLongOp.Uaddlp8) x))
2595
-
2596
- (decl uaddlp16 (Reg) Reg)
2597
- (rule (uaddlp16 x) (vec_rr_pair_long (VecRRPairLongOp.Uaddlp16) x))
2598
-
2599
- ;; Helper for generating `umlal32` instructions.
2600
- (decl umlal32 (Reg Reg Reg bool) Reg)
2601
- (rule (umlal32 x y z high_half) (vec_rrrr_long (VecRRRLongModOp.Umlal32) x y z high_half))
2602
-
2603
- ;; Helper for generating `smull8` instructions.
2604
- (decl smull8 (Reg Reg bool) Reg)
2605
- (rule (smull8 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull8) x y high_half))
2606
-
2607
- ;; Helper for generating `umull8` instructions.
2608
- (decl umull8 (Reg Reg bool) Reg)
2609
- (rule (umull8 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull8) x y high_half))
2610
-
2611
- ;; Helper for generating `smull16` instructions.
2612
- (decl smull16 (Reg Reg bool) Reg)
2613
- (rule (smull16 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull16) x y high_half))
2614
-
2615
- ;; Helper for generating `umull16` instructions.
2616
- (decl umull16 (Reg Reg bool) Reg)
2617
- (rule (umull16 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull16) x y high_half))
2618
-
2619
- ;; Helper for generating `smull32` instructions.
2620
- (decl smull32 (Reg Reg bool) Reg)
2621
- (rule (smull32 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull32) x y high_half))
2622
-
2623
- ;; Helper for generating `umull32` instructions.
2624
- (decl umull32 (Reg Reg bool) Reg)
2625
- (rule (umull32 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull32) x y high_half))
2626
-
2627
- ;; Helper for generating `asr` instructions.
2628
- (decl asr (Type Reg Reg) Reg)
2629
- (rule (asr ty x y) (alu_rrr (ALUOp.Asr) ty x y))
2630
-
2631
- (decl asr_imm (Type Reg ImmShift) Reg)
2632
- (rule (asr_imm ty x imm) (alu_rr_imm_shift (ALUOp.Asr) ty x imm))
2633
-
2634
- ;; Helper for generating `lsr` instructions.
2635
- (decl lsr (Type Reg Reg) Reg)
2636
- (rule (lsr ty x y) (alu_rrr (ALUOp.Lsr) ty x y))
2637
-
2638
- (decl lsr_imm (Type Reg ImmShift) Reg)
2639
- (rule (lsr_imm ty x imm) (alu_rr_imm_shift (ALUOp.Lsr) ty x imm))
2640
-
2641
- ;; Helper for generating `lsl` instructions.
2642
- (decl lsl (Type Reg Reg) Reg)
2643
- (rule (lsl ty x y) (alu_rrr (ALUOp.Lsl) ty x y))
2644
-
2645
- (decl lsl_imm (Type Reg ImmShift) Reg)
2646
- (rule (lsl_imm ty x imm) (alu_rr_imm_shift (ALUOp.Lsl) ty x imm))
2647
-
2648
- ;; Helper for generating `udiv` instructions.
2649
- (decl a64_udiv (Type Reg Reg) Reg)
2650
- (rule (a64_udiv ty x y) (alu_rrr (ALUOp.UDiv) ty x y))
2651
-
2652
- ;; Helper for generating `sdiv` instructions.
2653
- (decl a64_sdiv (Type Reg Reg) Reg)
2654
- (rule (a64_sdiv ty x y) (alu_rrr (ALUOp.SDiv) ty x y))
2655
-
2656
- ;; Helper for generating `not` instructions.
2657
- (decl not (Reg VectorSize) Reg)
2658
- (rule (not x size) (vec_misc (VecMisc2.Not) x size))
2659
-
2660
- ;; Helpers for generating `orr_not` instructions.
2661
-
2662
- (decl orr_not (Type Reg Reg) Reg)
2663
- (rule (orr_not ty x y) (alu_rrr (ALUOp.OrrNot) ty x y))
2664
-
2665
- (decl orr_not_shift (Type Reg Reg ShiftOpAndAmt) Reg)
2666
- (rule (orr_not_shift ty x y shift) (alu_rrr_shift (ALUOp.OrrNot) ty x y shift))
2667
-
2668
- ;; Helpers for generating `orr` instructions.
2669
-
2670
- (decl orr (Type Reg Reg) Reg)
2671
- (rule (orr ty x y) (alu_rrr (ALUOp.Orr) ty x y))
2672
-
2673
- (decl orr_imm (Type Reg ImmLogic) Reg)
2674
- (rule (orr_imm ty x y) (alu_rr_imm_logic (ALUOp.Orr) ty x y))
2675
-
2676
- (decl orr_shift (Type Reg Reg ShiftOpAndAmt) Reg)
2677
- (rule (orr_shift ty x y shift) (alu_rrr_shift (ALUOp.Orr) ty x y shift))
2678
-
2679
- (decl orr_vec (Reg Reg VectorSize) Reg)
2680
- (rule (orr_vec x y size) (vec_rrr (VecALUOp.Orr) x y size))
2681
-
2682
- ;; Helpers for generating `and` instructions.
2683
-
2684
- (decl and_reg (Type Reg Reg) Reg)
2685
- (rule (and_reg ty x y) (alu_rrr (ALUOp.And) ty x y))
2686
-
2687
- (decl and_imm (Type Reg ImmLogic) Reg)
2688
- (rule (and_imm ty x y) (alu_rr_imm_logic (ALUOp.And) ty x y))
2689
-
2690
- (decl and_vec (Reg Reg VectorSize) Reg)
2691
- (rule (and_vec x y size) (vec_rrr (VecALUOp.And) x y size))
2692
-
2693
- ;; Helpers for generating `eor` instructions.
2694
- (decl eor_vec (Reg Reg VectorSize) Reg)
2695
- (rule (eor_vec x y size) (vec_rrr (VecALUOp.Eor) x y size))
2696
-
2697
- ;; Helpers for generating `bic` instructions.
2698
-
2699
- (decl bic (Type Reg Reg) Reg)
2700
- (rule (bic ty x y) (alu_rrr (ALUOp.AndNot) ty x y))
2701
-
2702
- (decl bic_vec (Reg Reg VectorSize) Reg)
2703
- (rule (bic_vec x y size) (vec_rrr (VecALUOp.Bic) x y size))
2704
-
2705
- ;; Helpers for generating `sshl` instructions.
2706
- (decl sshl (Reg Reg VectorSize) Reg)
2707
- (rule (sshl x y size) (vec_rrr (VecALUOp.Sshl) x y size))
2708
-
2709
- ;; Helpers for generating `ushl` instructions.
2710
- (decl ushl (Reg Reg VectorSize) Reg)
2711
- (rule (ushl x y size) (vec_rrr (VecALUOp.Ushl) x y size))
2712
-
2713
- ;; Helpers for generating `ushl` instructions.
2714
- (decl ushl_vec_imm (Reg u8 VectorSize) Reg)
2715
- (rule (ushl_vec_imm x amt size) (vec_shift_imm (VecShiftImmOp.Shl) amt x size))
2716
-
2717
- ;; Helpers for generating `ushr` instructions.
2718
- (decl ushr_vec_imm (Reg u8 VectorSize) Reg)
2719
- (rule (ushr_vec_imm x amt size) (vec_shift_imm (VecShiftImmOp.Ushr) amt x size))
2720
-
2721
- ;; Helpers for generating `sshr` instructions.
2722
- (decl sshr_vec_imm (Reg u8 VectorSize) Reg)
2723
- (rule (sshr_vec_imm x amt size) (vec_shift_imm (VecShiftImmOp.Sshr) amt x size))
2724
-
2725
- ;; Helpers for generating `rotr` instructions.
2726
-
2727
- (decl a64_rotr (Type Reg Reg) Reg)
2728
- (rule (a64_rotr ty x y) (alu_rrr (ALUOp.RotR) ty x y))
2729
-
2730
- (decl a64_rotr_imm (Type Reg ImmShift) Reg)
2731
- (rule (a64_rotr_imm ty x y) (alu_rr_imm_shift (ALUOp.RotR) ty x y))
2732
-
2733
- ;; Helpers for generating `rbit` instructions.
2734
-
2735
- (decl rbit (Type Reg) Reg)
2736
- (rule (rbit ty x) (bit_rr (BitOp.RBit) ty x))
2737
-
2738
- ;; Helpers for generating `clz` instructions.
2739
-
2740
- (decl a64_clz (Type Reg) Reg)
2741
- (rule (a64_clz ty x) (bit_rr (BitOp.Clz) ty x))
2742
-
2743
- ;; Helpers for generating `cls` instructions.
2744
-
2745
- (decl a64_cls (Type Reg) Reg)
2746
- (rule (a64_cls ty x) (bit_rr (BitOp.Cls) ty x))
2747
-
2748
- ;; Helpers for generating `rev` instructions
2749
-
2750
- (decl a64_rev16 (Type Reg) Reg)
2751
- (rule (a64_rev16 ty x) (bit_rr (BitOp.Rev16) ty x))
2752
-
2753
- (decl a64_rev32 (Type Reg) Reg)
2754
- (rule (a64_rev32 ty x) (bit_rr (BitOp.Rev32) ty x))
2755
-
2756
- (decl a64_rev64 (Type Reg) Reg)
2757
- (rule (a64_rev64 ty x) (bit_rr (BitOp.Rev64) ty x))
2758
-
2759
- ;; Helpers for generating `eon` instructions.
2760
-
2761
- (decl eon (Type Reg Reg) Reg)
2762
- (rule (eon ty x y) (alu_rrr (ALUOp.EorNot) ty x y))
2763
-
2764
- ;; Helpers for generating `cnt` instructions.
2765
-
2766
- (decl vec_cnt (Reg VectorSize) Reg)
2767
- (rule (vec_cnt x size) (vec_misc (VecMisc2.Cnt) x size))
2768
-
2769
- ;; Helpers for generating a `bsl` instruction.
2770
-
2771
- (decl bsl (Type Reg Reg Reg) Reg)
2772
- (rule (bsl ty c x y)
2773
- (vec_rrr_mod (VecALUModOp.Bsl) c x y (vector_size ty)))
2774
-
2775
- ;; Helper for generating a `udf` instruction.
2776
-
2777
- (decl udf (TrapCode) SideEffectNoResult)
2778
- (rule (udf trap_code)
2779
- (SideEffectNoResult.Inst (MInst.Udf trap_code)))
2780
-
2781
- ;; Helpers for generating various load instructions, with varying
2782
- ;; widths and sign/zero-extending properties.
2783
- (decl aarch64_uload8 (AMode MemFlags) Reg)
2784
- (rule (aarch64_uload8 amode flags)
2785
- (let ((dst WritableReg (temp_writable_reg $I64))
2786
- (_ Unit (emit (MInst.ULoad8 dst amode flags))))
2787
- dst))
2788
- (decl aarch64_sload8 (AMode MemFlags) Reg)
2789
- (rule (aarch64_sload8 amode flags)
2790
- (let ((dst WritableReg (temp_writable_reg $I64))
2791
- (_ Unit (emit (MInst.SLoad8 dst amode flags))))
2792
- dst))
2793
- (decl aarch64_uload16 (AMode MemFlags) Reg)
2794
- (rule (aarch64_uload16 amode flags)
2795
- (let ((dst WritableReg (temp_writable_reg $I64))
2796
- (_ Unit (emit (MInst.ULoad16 dst amode flags))))
2797
- dst))
2798
- (decl aarch64_sload16 (AMode MemFlags) Reg)
2799
- (rule (aarch64_sload16 amode flags)
2800
- (let ((dst WritableReg (temp_writable_reg $I64))
2801
- (_ Unit (emit (MInst.SLoad16 dst amode flags))))
2802
- dst))
2803
- (decl aarch64_uload32 (AMode MemFlags) Reg)
2804
- (rule (aarch64_uload32 amode flags)
2805
- (let ((dst WritableReg (temp_writable_reg $I64))
2806
- (_ Unit (emit (MInst.ULoad32 dst amode flags))))
2807
- dst))
2808
- (decl aarch64_sload32 (AMode MemFlags) Reg)
2809
- (rule (aarch64_sload32 amode flags)
2810
- (let ((dst WritableReg (temp_writable_reg $I64))
2811
- (_ Unit (emit (MInst.SLoad32 dst amode flags))))
2812
- dst))
2813
- (decl aarch64_uload64 (AMode MemFlags) Reg)
2814
- (rule (aarch64_uload64 amode flags)
2815
- (let ((dst WritableReg (temp_writable_reg $I64))
2816
- (_ Unit (emit (MInst.ULoad64 dst amode flags))))
2817
- dst))
2818
- (decl aarch64_fpuload32 (AMode MemFlags) Reg)
2819
- (rule (aarch64_fpuload32 amode flags)
2820
- (let ((dst WritableReg (temp_writable_reg $F64))
2821
- (_ Unit (emit (MInst.FpuLoad32 dst amode flags))))
2822
- dst))
2823
- (decl aarch64_fpuload64 (AMode MemFlags) Reg)
2824
- (rule (aarch64_fpuload64 amode flags)
2825
- (let ((dst WritableReg (temp_writable_reg $F64))
2826
- (_ Unit (emit (MInst.FpuLoad64 dst amode flags))))
2827
- dst))
2828
- (decl aarch64_fpuload128 (AMode MemFlags) Reg)
2829
- (rule (aarch64_fpuload128 amode flags)
2830
- (let ((dst WritableReg (temp_writable_reg $F64X2))
2831
- (_ Unit (emit (MInst.FpuLoad128 dst amode flags))))
2832
- dst))
2833
- (decl aarch64_loadp64 (PairAMode MemFlags) ValueRegs)
2834
- (rule (aarch64_loadp64 amode flags)
2835
- (let ((dst1 WritableReg (temp_writable_reg $I64))
2836
- (dst2 WritableReg (temp_writable_reg $I64))
2837
- (_ Unit (emit (MInst.LoadP64 dst1 dst2 amode flags))))
2838
- (value_regs dst1 dst2)))
2839
-
2840
- ;; Helpers for generating various store instructions with varying
2841
- ;; widths.
2842
- (decl aarch64_store8 (AMode MemFlags Reg) SideEffectNoResult)
2843
- (rule (aarch64_store8 amode flags val)
2844
- (SideEffectNoResult.Inst (MInst.Store8 val amode flags)))
2845
- (decl aarch64_store16 (AMode MemFlags Reg) SideEffectNoResult)
2846
- (rule (aarch64_store16 amode flags val)
2847
- (SideEffectNoResult.Inst (MInst.Store16 val amode flags)))
2848
- (decl aarch64_store32 (AMode MemFlags Reg) SideEffectNoResult)
2849
- (rule (aarch64_store32 amode flags val)
2850
- (SideEffectNoResult.Inst (MInst.Store32 val amode flags)))
2851
- (decl aarch64_store64 (AMode MemFlags Reg) SideEffectNoResult)
2852
- (rule (aarch64_store64 amode flags val)
2853
- (SideEffectNoResult.Inst (MInst.Store64 val amode flags)))
2854
- (decl aarch64_fpustore32 (AMode MemFlags Reg) SideEffectNoResult)
2855
- (rule (aarch64_fpustore32 amode flags val)
2856
- (SideEffectNoResult.Inst (MInst.FpuStore32 val amode flags)))
2857
- (decl aarch64_fpustore64 (AMode MemFlags Reg) SideEffectNoResult)
2858
- (rule (aarch64_fpustore64 amode flags val)
2859
- (SideEffectNoResult.Inst (MInst.FpuStore64 val amode flags)))
2860
- (decl aarch64_fpustore128 (AMode MemFlags Reg) SideEffectNoResult)
2861
- (rule (aarch64_fpustore128 amode flags val)
2862
- (SideEffectNoResult.Inst (MInst.FpuStore128 val amode flags)))
2863
- (decl aarch64_storep64 (PairAMode MemFlags Reg Reg) SideEffectNoResult)
2864
- (rule (aarch64_storep64 amode flags val1 val2)
2865
- (SideEffectNoResult.Inst (MInst.StoreP64 val1 val2 amode flags)))
2866
-
2867
- ;; Helper for generating a `trapif` instruction.
2868
-
2869
- (decl trap_if (ProducesFlags TrapCode Cond) InstOutput)
2870
- (rule (trap_if flags trap_code cond)
2871
- (side_effect
2872
- (with_flags_side_effect flags
2873
- (ConsumesFlags.ConsumesFlagsSideEffect
2874
- (MInst.TrapIf (cond_br_cond cond) trap_code)))))
2875
-
2876
- ;; Immediate value helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2877
-
2878
- ;; Type of extension performed by an immediate helper
2879
- (type ImmExtend
2880
- (enum
2881
- (Sign)
2882
- (Zero)))
2883
-
2884
- ;; Arguments:
2885
- ;; * Immediate type
2886
- ;; * Way to extend the immediate value to the full width of the destination
2887
- ;; register
2888
- ;; * Immediate value - only the bits that fit within the type are used and
2889
- ;; extended, while the rest are ignored
2890
- ;;
2891
- ;; Note that, unlike the convention in the AArch64 backend, this helper leaves
2892
- ;; all bits in the destination register in a defined state, i.e. smaller types
2893
- ;; such as `I8` are either sign- or zero-extended.
2894
- (decl imm (Type ImmExtend u64) Reg)
2895
-
2896
- ;; Move wide immediate instructions; to simplify, we only match when we
2897
- ;; are zero-extending the value.
2898
- (rule 3 (imm (integral_ty ty) (ImmExtend.Zero) k)
2899
- (if-let n (move_wide_const_from_u64 ty k))
2900
- (movz n (operand_size ty)))
2901
- (rule 2 (imm (integral_ty (ty_32_or_64 ty)) (ImmExtend.Zero) k)
2902
- (if-let n (move_wide_const_from_inverted_u64 ty k))
2903
- (movn n (operand_size ty)))
2904
-
2905
- ;; Weird logical-instruction immediate in ORI using zero register; to simplify,
2906
- ;; we only match when we are zero-extending the value.
2907
- (rule 1 (imm (integral_ty ty) (ImmExtend.Zero) k)
2908
- (if-let n (imm_logic_from_u64 ty k))
2909
- (orr_imm ty (zero_reg) n))
2910
-
2911
- (decl load_constant64_full (Type ImmExtend u64) Reg)
2912
- (extern constructor load_constant64_full load_constant64_full)
2913
-
2914
- ;; Fallback for integral 64-bit constants
2915
- (rule (imm (integral_ty ty) extend n)
2916
- (load_constant64_full ty extend n))
2917
-
2918
- ;; Sign extension helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2919
-
2920
- ;; Place a `Value` into a register, sign extending it to 32-bits
2921
- (decl put_in_reg_sext32 (Value) Reg)
2922
- (rule -1 (put_in_reg_sext32 val @ (value_type (fits_in_32 ty)))
2923
- (extend val $true (ty_bits ty) 32))
2924
-
2925
- ;; 32/64-bit passthrough.
2926
- (rule (put_in_reg_sext32 val @ (value_type $I32)) val)
2927
- (rule (put_in_reg_sext32 val @ (value_type $I64)) val)
2928
-
2929
- ;; Place a `Value` into a register, zero extending it to 32-bits
2930
- (decl put_in_reg_zext32 (Value) Reg)
2931
- (rule -1 (put_in_reg_zext32 val @ (value_type (fits_in_32 ty)))
2932
- (extend val $false (ty_bits ty) 32))
2933
-
2934
- ;; 32/64-bit passthrough.
2935
- (rule (put_in_reg_zext32 val @ (value_type $I32)) val)
2936
- (rule (put_in_reg_zext32 val @ (value_type $I64)) val)
2937
-
2938
- ;; Place a `Value` into a register, sign extending it to 64-bits
2939
- (decl put_in_reg_sext64 (Value) Reg)
2940
- (rule 1 (put_in_reg_sext64 val @ (value_type (fits_in_32 ty)))
2941
- (extend val $true (ty_bits ty) 64))
2942
-
2943
- ;; 64-bit passthrough.
2944
- (rule (put_in_reg_sext64 val @ (value_type $I64)) val)
2945
-
2946
- ;; Place a `Value` into a register, zero extending it to 64-bits
2947
- (decl put_in_reg_zext64 (Value) Reg)
2948
- (rule 1 (put_in_reg_zext64 val @ (value_type (fits_in_32 ty)))
2949
- (extend val $false (ty_bits ty) 64))
2950
-
2951
- ;; 64-bit passthrough.
2952
- (rule (put_in_reg_zext64 val @ (value_type $I64)) val)
2953
-
2954
- ;; Misc instruction helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2955
-
2956
- (decl trap_if_zero_divisor (Reg) Reg)
2957
- (rule (trap_if_zero_divisor reg)
2958
- (let ((_ Unit (emit (MInst.TrapIf (cond_br_zero reg) (trap_code_division_by_zero)))))
2959
- reg))
2960
-
2961
- (decl size_from_ty (Type) OperandSize)
2962
- (rule 1 (size_from_ty (fits_in_32 _ty)) (OperandSize.Size32))
2963
- (rule (size_from_ty $I64) (OperandSize.Size64))
2964
-
2965
- ;; Check for signed overflow. The only case is min_value / -1.
2966
- ;; The following checks must be done in 32-bit or 64-bit, depending
2967
- ;; on the input type.
2968
- (decl trap_if_div_overflow (Type Reg Reg) Reg)
2969
- (rule (trap_if_div_overflow ty x y)
2970
- (let (
2971
- ;; Check RHS is -1.
2972
- (_ Unit (emit (MInst.AluRRImm12 (ALUOp.AddS) (operand_size ty) (writable_zero_reg) y (u8_into_imm12 1))))
2973
-
2974
- ;; Check LHS is min_value, by subtracting 1 and branching if
2975
- ;; there is overflow.
2976
- (_ Unit (emit (MInst.CCmpImm (size_from_ty ty)
2977
- x
2978
- (u8_into_uimm5 1)
2979
- (nzcv $false $false $false $false)
2980
- (Cond.Eq))))
2981
- (_ Unit (emit (MInst.TrapIf (cond_br_cond (Cond.Vs))
2982
- (trap_code_integer_overflow))))
2983
- )
2984
- x))
2985
-
2986
- ;; Check for unsigned overflow.
2987
- (decl trap_if_overflow (ProducesFlags TrapCode) Reg)
2988
- (rule (trap_if_overflow producer tc)
2989
- (with_flags_reg
2990
- producer
2991
- (ConsumesFlags.ConsumesFlagsSideEffect
2992
- (MInst.TrapIf (cond_br_cond (Cond.Hs)) tc))))
2993
-
2994
- (decl sink_atomic_load (Inst) Reg)
2995
- (rule (sink_atomic_load x @ (atomic_load _ addr))
2996
- (let ((_ Unit (sink_inst x)))
2997
- (put_in_reg addr)))
2998
-
2999
- ;; Helper for generating either an `AluRRR`, `AluRRRShift`, or `AluRRImmLogic`
3000
- ;; instruction depending on the input. Note that this requires that the `ALUOp`
3001
- ;; specified is commutative.
3002
- (decl alu_rs_imm_logic_commutative (ALUOp Type Value Value) Reg)
3003
-
3004
- ;; Base case of operating on registers.
3005
- (rule -1 (alu_rs_imm_logic_commutative op ty x y)
3006
- (alu_rrr op ty x y))
3007
-
3008
- ;; Special cases for when one operand is a constant.
3009
- (rule (alu_rs_imm_logic_commutative op ty x (iconst k))
3010
- (if-let imm (imm_logic_from_imm64 ty k))
3011
- (alu_rr_imm_logic op ty x imm))
3012
- (rule 1 (alu_rs_imm_logic_commutative op ty (iconst k) x)
3013
- (if-let imm (imm_logic_from_imm64 ty k))
3014
- (alu_rr_imm_logic op ty x imm))
3015
-
3016
- ;; Special cases for when one operand is shifted left by a constant.
3017
- (rule (alu_rs_imm_logic_commutative op ty x (ishl y (iconst k)))
3018
- (if-let amt (lshl_from_imm64 ty k))
3019
- (alu_rrr_shift op ty x y amt))
3020
- (rule 1 (alu_rs_imm_logic_commutative op ty (ishl x (iconst k)) y)
3021
- (if-let amt (lshl_from_imm64 ty k))
3022
- (alu_rrr_shift op ty y x amt))
3023
-
3024
- ;; Same as `alu_rs_imm_logic_commutative` above, except that it doesn't require
3025
- ;; that the operation is commutative.
3026
- (decl alu_rs_imm_logic (ALUOp Type Value Value) Reg)
3027
- (rule -1 (alu_rs_imm_logic op ty x y)
3028
- (alu_rrr op ty x y))
3029
- (rule (alu_rs_imm_logic op ty x (iconst k))
3030
- (if-let imm (imm_logic_from_imm64 ty k))
3031
- (alu_rr_imm_logic op ty x imm))
3032
- (rule (alu_rs_imm_logic op ty x (ishl y (iconst k)))
3033
- (if-let amt (lshl_from_imm64 ty k))
3034
- (alu_rrr_shift op ty x y amt))
3035
-
3036
- ;; Helper for generating i128 bitops which simply do the same operation to the
3037
- ;; hi/lo registers.
3038
- ;;
3039
- ;; TODO: Support immlogic here
3040
- (decl i128_alu_bitop (ALUOp Type Value Value) ValueRegs)
3041
- (rule (i128_alu_bitop op ty x y)
3042
- (let (
3043
- (x_regs ValueRegs (put_in_regs x))
3044
- (x_lo Reg (value_regs_get x_regs 0))
3045
- (x_hi Reg (value_regs_get x_regs 1))
3046
- (y_regs ValueRegs (put_in_regs y))
3047
- (y_lo Reg (value_regs_get y_regs 0))
3048
- (y_hi Reg (value_regs_get y_regs 1))
3049
- )
3050
- (value_regs
3051
- (alu_rrr op ty x_lo y_lo)
3052
- (alu_rrr op ty x_hi y_hi))))
3053
-
3054
- ;; Helper for emitting `MInst.VecLoadReplicate` instructions.
3055
- (decl ld1r (Reg VectorSize MemFlags) Reg)
3056
- (rule (ld1r src size flags)
3057
- (let ((dst WritableReg (temp_writable_reg $I8X16))
3058
- (_ Unit (emit (MInst.VecLoadReplicate dst src size flags))))
3059
- dst))
3060
-
3061
- ;; Helper for emitting `MInst.LoadExtName` instructions.
3062
- (decl load_ext_name (BoxExternalName i64) Reg)
3063
- (rule (load_ext_name extname offset)
3064
- (let ((dst WritableReg (temp_writable_reg $I64))
3065
- (_ Unit (emit (MInst.LoadExtName dst extname offset))))
3066
- dst))
3067
-
3068
- ;; Lower the address of a load or a store.
3069
- (decl amode (Type Value u32) AMode)
3070
- ;; TODO: Port lower_address() to ISLE.
3071
- (extern constructor amode amode)
3072
-
3073
- (decl sink_load_into_addr (Type Inst) Reg)
3074
- (rule (sink_load_into_addr ty x @ (load _ addr (offset32 offset)))
3075
- (let ((_ Unit (sink_inst x)))
3076
- (add_imm_to_addr addr offset)))
3077
-
3078
- (decl add_imm_to_addr (Reg u64) Reg)
3079
- (rule 2 (add_imm_to_addr val 0) val)
3080
- (rule 1 (add_imm_to_addr val (imm12_from_u64 imm)) (add_imm $I64 val imm))
3081
- (rule 0 (add_imm_to_addr val offset) (add $I64 val (imm $I64 (ImmExtend.Zero) offset)))
3082
-
3083
- ;; Lower a constant f32.
3084
- ;;
3085
- ;; Note that we must make sure that all bits outside the lowest 32 are set to 0
3086
- ;; because this function is also used to load wider constants (that have zeros
3087
- ;; in their most significant bits).
3088
- (decl constant_f32 (u32) Reg)
3089
- (rule 2 (constant_f32 0)
3090
- (vec_dup_imm (asimd_mov_mod_imm_zero (ScalarSize.Size32))
3091
- $false
3092
- (VectorSize.Size32x2)))
3093
- (rule 1 (constant_f32 n)
3094
- (if-let imm (asimd_fp_mod_imm_from_u64 n (ScalarSize.Size32)))
3095
- (fpu_move_fp_imm imm (ScalarSize.Size32)))
3096
- (rule (constant_f32 n)
3097
- (mov_to_fpu (imm $I32 (ImmExtend.Zero) n) (ScalarSize.Size32)))
3098
-
3099
- ;; Lower a constant f64.
3100
- ;;
3101
- ;; Note that we must make sure that all bits outside the lowest 64 are set to 0
3102
- ;; because this function is also used to load wider constants (that have zeros
3103
- ;; in their most significant bits).
3104
- ;; TODO: Treat as half of a 128 bit vector and consider replicated patterns.
3105
- ;; Scalar MOVI might also be an option.
3106
- (decl constant_f64 (u64) Reg)
3107
- (rule 4 (constant_f64 0)
3108
- (vec_dup_imm (asimd_mov_mod_imm_zero (ScalarSize.Size32))
3109
- $false
3110
- (VectorSize.Size32x2)))
3111
- (rule 3 (constant_f64 n)
3112
- (if-let imm (asimd_fp_mod_imm_from_u64 n (ScalarSize.Size64)))
3113
- (fpu_move_fp_imm imm (ScalarSize.Size64)))
3114
- (rule 2 (constant_f64 (u64_as_u32 n))
3115
- (constant_f32 n))
3116
- (rule 1 (constant_f64 (u64_low32_bits_unset n))
3117
- (mov_to_fpu (imm $I64 (ImmExtend.Zero) n) (ScalarSize.Size64)))
3118
- (rule (constant_f64 n)
3119
- (fpu_load64 (AMode.Const (emit_u64_le_const n)) (mem_flags_trusted)))
3120
-
3121
- ;; Tests whether the low 32 bits in the input are all zero.
3122
- (decl u64_low32_bits_unset (u64) u64)
3123
- (extern extractor u64_low32_bits_unset u64_low32_bits_unset)
3124
-
3125
- ;; Lower a constant f128.
3126
- (decl constant_f128 (u128) Reg)
3127
- (rule 3 (constant_f128 0)
3128
- (vec_dup_imm (asimd_mov_mod_imm_zero (ScalarSize.Size8))
3129
- $false
3130
- (VectorSize.Size8x16)))
3131
-
3132
- ;; If the upper 64-bits are all zero then defer to `constant_f64`.
3133
- (rule 2 (constant_f128 (u128_as_u64 n)) (constant_f64 n))
3134
-
3135
- ;; If the low half of the u128 equals the high half then delegate to the splat
3136
- ;; logic as a splat of a 64-bit value.
3137
- (rule 1 (constant_f128 (u128_replicated_u64 n))
3138
- (splat_const n (VectorSize.Size64x2)))
3139
-
3140
- ;; Base case is to load the constant from memory.
3141
- (rule (constant_f128 n)
3142
- (fpu_load128 (AMode.Const (emit_u128_le_const n)) (mem_flags_trusted)))
3143
-
3144
- ;; Lower a vector splat with a constant parameter.
3145
- ;;
3146
- ;; The 64-bit input here only uses the low bits for the lane size in
3147
- ;; `VectorSize` and all other bits are ignored.
3148
- (decl splat_const (u64 VectorSize) Reg)
3149
-
3150
- ;; If the splat'd constant can itself be reduced in size then attempt to do so
3151
- ;; as it will make it easier to create the immediates in the instructions below.
3152
- (rule 5 (splat_const (u64_replicated_u32 n) (VectorSize.Size64x2))
3153
- (splat_const n (VectorSize.Size32x4)))
3154
- (rule 5 (splat_const (u32_replicated_u16 n) (VectorSize.Size32x4))
3155
- (splat_const n (VectorSize.Size16x8)))
3156
- (rule 5 (splat_const (u32_replicated_u16 n) (VectorSize.Size32x2))
3157
- (splat_const n (VectorSize.Size16x4)))
3158
- (rule 5 (splat_const (u16_replicated_u8 n) (VectorSize.Size16x8))
3159
- (splat_const n (VectorSize.Size8x16)))
3160
- (rule 5 (splat_const (u16_replicated_u8 n) (VectorSize.Size16x4))
3161
- (splat_const n (VectorSize.Size8x8)))
3162
-
3163
- ;; Special cases for `vec_dup_imm` instructions where the input is either
3164
- ;; negated or not.
3165
- (rule 4 (splat_const n size)
3166
- (if-let imm (asimd_mov_mod_imm_from_u64 n (vector_lane_size size)))
3167
- (vec_dup_imm imm $false size))
3168
- (rule 3 (splat_const n size)
3169
- (if-let imm (asimd_mov_mod_imm_from_u64 (u64_not n) (vector_lane_size size)))
3170
- (vec_dup_imm imm $true size))
3171
-
3172
- ;; Special case a 32-bit splat where an immediate can be created by
3173
- ;; concatenating the 32-bit constant into a 64-bit value
3174
- (rule 2 (splat_const n (VectorSize.Size32x4))
3175
- (if-let imm (asimd_mov_mod_imm_from_u64 (u64_or n (u64_shl n 32)) (ScalarSize.Size64)))
3176
- (vec_dup_imm imm $false (VectorSize.Size64x2)))
3177
- (rule 2 (splat_const n (VectorSize.Size32x2))
3178
- (if-let imm (asimd_mov_mod_imm_from_u64 (u64_or n (u64_shl n 32)) (ScalarSize.Size64)))
3179
- (fpu_extend (vec_dup_imm imm $false (VectorSize.Size64x2)) (ScalarSize.Size64)))
3180
-
3181
- (rule 1 (splat_const n size)
3182
- (if-let imm (asimd_fp_mod_imm_from_u64 n (vector_lane_size size)))
3183
- (vec_dup_fp_imm imm size))
3184
-
3185
- ;; The base case for splat is to use `vec_dup` with the immediate loaded into a
3186
- ;; register.
3187
- (rule (splat_const n size)
3188
- (vec_dup (imm $I64 (ImmExtend.Zero) n) size))
3189
-
3190
- ;; Each of these extractors tests whether the upper half of the input equals the
3191
- ;; lower half of the input
3192
- (decl u128_replicated_u64 (u64) u128)
3193
- (extern extractor u128_replicated_u64 u128_replicated_u64)
3194
- (decl u64_replicated_u32 (u64) u64)
3195
- (extern extractor u64_replicated_u32 u64_replicated_u32)
3196
- (decl u32_replicated_u16 (u64) u64)
3197
- (extern extractor u32_replicated_u16 u32_replicated_u16)
3198
- (decl u16_replicated_u8 (u64) u64)
3199
- (extern extractor u16_replicated_u8 u16_replicated_u8)
3200
-
3201
- ;; Lower a FloatCC to a Cond.
3202
- (decl fp_cond_code (FloatCC) Cond)
3203
- ;; TODO: Port lower_fp_condcode() to ISLE.
3204
- (extern constructor fp_cond_code fp_cond_code)
3205
-
3206
- ;; Lower an integer cond code.
3207
- (decl cond_code (IntCC) Cond)
3208
- ;; TODO: Port lower_condcode() to ISLE.
3209
- (extern constructor cond_code cond_code)
3210
-
3211
- ;; Invert a condition code.
3212
- (decl invert_cond (Cond) Cond)
3213
- ;; TODO: Port cond.invert() to ISLE.
3214
- (extern constructor invert_cond invert_cond)
3215
-
3216
- ;; Generate comparison to zero operator from input condition code
3217
- (decl float_cc_cmp_zero_to_vec_misc_op (FloatCC) VecMisc2)
3218
- (extern constructor float_cc_cmp_zero_to_vec_misc_op float_cc_cmp_zero_to_vec_misc_op)
3219
-
3220
- (decl float_cc_cmp_zero_to_vec_misc_op_swap (FloatCC) VecMisc2)
3221
- (extern constructor float_cc_cmp_zero_to_vec_misc_op_swap float_cc_cmp_zero_to_vec_misc_op_swap)
3222
-
3223
- ;; Match valid generic compare to zero cases
3224
- (decl fcmp_zero_cond (FloatCC) FloatCC)
3225
- (extern extractor fcmp_zero_cond fcmp_zero_cond)
3226
-
3227
- ;; Match not equal compare to zero separately as it requires two output instructions
3228
- (decl fcmp_zero_cond_not_eq (FloatCC) FloatCC)
3229
- (extern extractor fcmp_zero_cond_not_eq fcmp_zero_cond_not_eq)
3230
-
3231
- ;; Helper for generating float compare to zero instructions where 2nd argument is zero
3232
- (decl float_cmp_zero (FloatCC Reg VectorSize) Reg)
3233
- (rule (float_cmp_zero cond rn size)
3234
- (vec_misc (float_cc_cmp_zero_to_vec_misc_op cond) rn size))
3235
-
3236
- ;; Helper for generating float compare to zero instructions in case where 1st argument is zero
3237
- (decl float_cmp_zero_swap (FloatCC Reg VectorSize) Reg)
3238
- (rule (float_cmp_zero_swap cond rn size)
3239
- (vec_misc (float_cc_cmp_zero_to_vec_misc_op_swap cond) rn size))
3240
-
3241
- ;; Helper for generating float compare equal to zero instruction
3242
- (decl fcmeq0 (Reg VectorSize) Reg)
3243
- (rule (fcmeq0 rn size)
3244
- (vec_misc (VecMisc2.Fcmeq0) rn size))
3245
-
3246
- ;; Generate comparison to zero operator from input condition code
3247
- (decl int_cc_cmp_zero_to_vec_misc_op (IntCC) VecMisc2)
3248
- (extern constructor int_cc_cmp_zero_to_vec_misc_op int_cc_cmp_zero_to_vec_misc_op)
3249
-
3250
- (decl int_cc_cmp_zero_to_vec_misc_op_swap (IntCC) VecMisc2)
3251
- (extern constructor int_cc_cmp_zero_to_vec_misc_op_swap int_cc_cmp_zero_to_vec_misc_op_swap)
3252
-
3253
- ;; Match valid generic compare to zero cases
3254
- (decl icmp_zero_cond (IntCC) IntCC)
3255
- (extern extractor icmp_zero_cond icmp_zero_cond)
3256
-
3257
- ;; Match not equal compare to zero separately as it requires two output instructions
3258
- (decl icmp_zero_cond_not_eq (IntCC) IntCC)
3259
- (extern extractor icmp_zero_cond_not_eq icmp_zero_cond_not_eq)
3260
-
3261
- ;; Helper for generating int compare to zero instructions where 2nd argument is zero
3262
- (decl int_cmp_zero (IntCC Reg VectorSize) Reg)
3263
- (rule (int_cmp_zero cond rn size)
3264
- (vec_misc (int_cc_cmp_zero_to_vec_misc_op cond) rn size))
3265
-
3266
- ;; Helper for generating int compare to zero instructions in case where 1st argument is zero
3267
- (decl int_cmp_zero_swap (IntCC Reg VectorSize) Reg)
3268
- (rule (int_cmp_zero_swap cond rn size)
3269
- (vec_misc (int_cc_cmp_zero_to_vec_misc_op_swap cond) rn size))
3270
-
3271
- ;; Helper for generating int compare equal to zero instruction
3272
- (decl cmeq0 (Reg VectorSize) Reg)
3273
- (rule (cmeq0 rn size)
3274
- (vec_misc (VecMisc2.Cmeq0) rn size))
3275
-
3276
- ;; Helper for emitting `MInst.AtomicRMW` instructions.
3277
- (decl lse_atomic_rmw (AtomicRMWOp Value Reg Type MemFlags) Reg)
3278
- (rule (lse_atomic_rmw op p r_arg2 ty flags)
3279
- (let (
3280
- (r_addr Reg p)
3281
- (dst WritableReg (temp_writable_reg ty))
3282
- (_ Unit (emit (MInst.AtomicRMW op r_arg2 dst r_addr ty flags)))
3283
- )
3284
- dst))
3285
-
3286
- ;; Helper for emitting `MInst.AtomicCAS` instructions.
3287
- (decl lse_atomic_cas (Reg Reg Reg Type MemFlags) Reg)
3288
- (rule (lse_atomic_cas addr expect replace ty flags)
3289
- (let (
3290
- (dst WritableReg (temp_writable_reg ty))
3291
- (_ Unit (emit (MInst.AtomicCAS dst expect replace addr ty flags)))
3292
- )
3293
- dst))
3294
-
3295
- ;; Helper for emitting `MInst.AtomicRMWLoop` instructions.
3296
- ;; - Make sure that both args are in virtual regs, since in effect
3297
- ;; we have to do a parallel copy to get them safely to the AtomicRMW input
3298
- ;; regs, and that's not guaranteed safe if either is in a real reg.
3299
- ;; - Move the args to the preordained AtomicRMW input regs
3300
- ;; - And finally, copy the preordained AtomicRMW output reg to its destination.
3301
- (decl atomic_rmw_loop (AtomicRMWLoopOp Reg Reg Type MemFlags) Reg)
3302
- (rule (atomic_rmw_loop op addr operand ty flags)
3303
- (let ((dst WritableReg (temp_writable_reg $I64))
3304
- (scratch1 WritableReg (temp_writable_reg $I64))
3305
- (scratch2 WritableReg (temp_writable_reg $I64))
3306
- (_ Unit (emit (MInst.AtomicRMWLoop ty op flags addr operand dst scratch1 scratch2))))
3307
- dst))
3308
-
3309
- ;; Helper for emitting `MInst.AtomicCASLoop` instructions.
3310
- ;; This is very similar to, but not identical to, the AtomicRmw case. Note
3311
- ;; that the AtomicCASLoop sequence does its own masking, so we don't need to worry
3312
- ;; about zero-extending narrow (I8/I16/I32) values here.
3313
- ;; Make sure that all three args are in virtual regs. See corresponding comment
3314
- ;; for `atomic_rmw_loop` above.
3315
- (decl atomic_cas_loop (Reg Reg Reg Type MemFlags) Reg)
3316
- (rule (atomic_cas_loop addr expect replace ty flags)
3317
- (let ((dst WritableReg (temp_writable_reg $I64))
3318
- (scratch WritableReg (temp_writable_reg $I64))
3319
- (_ Unit (emit (MInst.AtomicCASLoop ty flags addr expect replace dst scratch))))
3320
- dst))
3321
-
3322
- ;; Helper for emitting `MInst.MovPReg` instructions.
3323
- (decl mov_from_preg (PReg) Reg)
3324
- (rule (mov_from_preg src)
3325
- (let ((dst WritableReg (temp_writable_reg $I64))
3326
- (_ Unit (emit (MInst.MovFromPReg dst src))))
3327
- dst))
3328
-
3329
- (decl mov_to_preg (PReg Reg) SideEffectNoResult)
3330
- (rule (mov_to_preg dst src)
3331
- (SideEffectNoResult.Inst (MInst.MovToPReg dst src)))
3332
-
3333
- (decl preg_sp () PReg)
3334
- (extern constructor preg_sp preg_sp)
3335
-
3336
- (decl preg_fp () PReg)
3337
- (extern constructor preg_fp preg_fp)
3338
-
3339
- (decl preg_link () PReg)
3340
- (extern constructor preg_link preg_link)
3341
-
3342
- (decl preg_pinned () PReg)
3343
- (extern constructor preg_pinned preg_pinned)
3344
-
3345
- (decl aarch64_sp () Reg)
3346
- (rule (aarch64_sp)
3347
- (mov_from_preg (preg_sp)))
3348
-
3349
- (decl aarch64_fp () Reg)
3350
- (rule (aarch64_fp)
3351
- (mov_from_preg (preg_fp)))
3352
-
3353
- (decl aarch64_link () Reg)
3354
- (rule 1 (aarch64_link)
3355
- (if (preserve_frame_pointers))
3356
- (if (sign_return_address_disabled))
3357
- (let ((dst WritableReg (temp_writable_reg $I64))
3358
- ;; Even though LR is not an allocatable register, whether it
3359
- ;; contains the return address for the current function is
3360
- ;; unknown at this point. For example, this operation may come
3361
- ;; immediately after a call, in which case LR would not have a
3362
- ;; valid value. That's why we must obtain the return address from
3363
- ;; the frame record that corresponds to the current subroutine on
3364
- ;; the stack; the presence of the record is guaranteed by the
3365
- ;; `preserve_frame_pointers` setting.
3366
- (addr AMode (AMode.FPOffset 8 $I64))
3367
- (_ Unit (emit (MInst.ULoad64 dst addr (mem_flags_trusted)))))
3368
- dst))
3369
-
3370
- (rule (aarch64_link)
3371
- (if (preserve_frame_pointers))
3372
- ;; Similarly to the rule above, we must load the return address from the
3373
- ;; the frame record. Furthermore, we can use LR as a scratch register
3374
- ;; because the function will set it to the return address immediately
3375
- ;; before returning.
3376
- (let ((addr AMode (AMode.FPOffset 8 $I64))
3377
- (lr WritableReg (writable_link_reg))
3378
- (_ Unit (emit (MInst.ULoad64 lr addr (mem_flags_trusted))))
3379
- (_ Unit (emit (MInst.Xpaclri))))
3380
- (mov_from_preg (preg_link))))
3381
-
3382
- ;; Helper for getting the maximum shift amount for a type.
3383
-
3384
- (decl max_shift (Type) u8)
3385
- (rule (max_shift $F64) 63)
3386
- (rule (max_shift $F32) 31)
3387
-
3388
- ;; Helper for generating `fcopysign` instruction sequences.
3389
-
3390
- (decl fcopy_sign (Reg Reg Type) Reg)
3391
- (rule 1 (fcopy_sign x y (ty_scalar_float ty))
3392
- (let ((dst WritableReg (temp_writable_reg $F64))
3393
- (tmp Reg (fpu_rri (fpu_op_ri_ushr (ty_bits ty) (max_shift ty)) y))
3394
- (_ Unit (emit (MInst.FpuRRIMod (fpu_op_ri_sli (ty_bits ty) (max_shift ty)) dst x tmp))))
3395
- dst))
3396
- (rule (fcopy_sign x y ty @ (multi_lane _ _))
3397
- (let ((dst WritableReg (temp_writable_reg $I8X16))
3398
- (tmp Reg (ushr_vec_imm y (max_shift (lane_type ty)) (vector_size ty)))
3399
- (_ Unit (emit (MInst.VecShiftImmMod (VecShiftImmModOp.Sli) dst x tmp (vector_size ty) (max_shift (lane_type ty))))))
3400
- dst))
3401
-
3402
- ;; Helpers for generating `MInst.FpuToInt` instructions.
3403
-
3404
- (decl fpu_to_int_nan_check (ScalarSize Reg) Reg)
3405
- (rule (fpu_to_int_nan_check size src)
3406
- (let ((r ValueRegs
3407
- (with_flags (fpu_cmp size src src)
3408
- (ConsumesFlags.ConsumesFlagsReturnsReg
3409
- (MInst.TrapIf (cond_br_cond (Cond.Vs))
3410
- (trap_code_bad_conversion_to_integer))
3411
- src))))
3412
- (value_regs_get r 0)))
3413
-
3414
- ;; Checks that the value is not less than the minimum bound,
3415
- ;; accepting a boolean (whether the type is signed), input type,
3416
- ;; output type, and registers containing the source and minimum bound.
3417
- (decl fpu_to_int_underflow_check (bool Type Type Reg Reg) Reg)
3418
- (rule (fpu_to_int_underflow_check $true $F32 (fits_in_16 out_ty) src min)
3419
- (let ((r ValueRegs
3420
- (with_flags (fpu_cmp (ScalarSize.Size32) src min)
3421
- (ConsumesFlags.ConsumesFlagsReturnsReg
3422
- (MInst.TrapIf (cond_br_cond (Cond.Le))
3423
- (trap_code_integer_overflow))
3424
- src))))
3425
- (value_regs_get r 0)))
3426
- (rule (fpu_to_int_underflow_check $true $F64 (fits_in_32 out_ty) src min)
3427
- (let ((r ValueRegs
3428
- (with_flags (fpu_cmp (ScalarSize.Size64) src min)
3429
- (ConsumesFlags.ConsumesFlagsReturnsReg
3430
- (MInst.TrapIf (cond_br_cond (Cond.Le))
3431
- (trap_code_integer_overflow))
3432
- src))))
3433
- (value_regs_get r 0)))
3434
- (rule -1 (fpu_to_int_underflow_check $true in_ty _out_ty src min)
3435
- (let ((r ValueRegs
3436
- (with_flags (fpu_cmp (scalar_size in_ty) src min)
3437
- (ConsumesFlags.ConsumesFlagsReturnsReg
3438
- (MInst.TrapIf (cond_br_cond (Cond.Lt))
3439
- (trap_code_integer_overflow))
3440
- src))))
3441
- (value_regs_get r 0)))
3442
- (rule (fpu_to_int_underflow_check $false in_ty _out_ty src min)
3443
- (let ((r ValueRegs
3444
- (with_flags (fpu_cmp (scalar_size in_ty) src min)
3445
- (ConsumesFlags.ConsumesFlagsReturnsReg
3446
- (MInst.TrapIf (cond_br_cond (Cond.Le))
3447
- (trap_code_integer_overflow))
3448
- src))))
3449
- (value_regs_get r 0)))
3450
-
3451
- (decl fpu_to_int_overflow_check (ScalarSize Reg Reg) Reg)
3452
- (rule (fpu_to_int_overflow_check size src max)
3453
- (let ((r ValueRegs
3454
- (with_flags (fpu_cmp size src max)
3455
- (ConsumesFlags.ConsumesFlagsReturnsReg
3456
- (MInst.TrapIf (cond_br_cond (Cond.Ge))
3457
- (trap_code_integer_overflow))
3458
- src))))
3459
- (value_regs_get r 0)))
3460
-
3461
- ;; Emits the appropriate instruction sequence to convert a
3462
- ;; floating-point value to an integer, trapping if the value
3463
- ;; is a NaN or does not fit in the target type.
3464
- ;; Accepts the specific conversion op, the source register,
3465
- ;; whether the input is signed, and finally the input and output
3466
- ;; types.
3467
- (decl fpu_to_int_cvt (FpuToIntOp Reg bool Type Type) Reg)
3468
- (rule (fpu_to_int_cvt op src signed in_ty out_ty)
3469
- (let ((size ScalarSize (scalar_size in_ty))
3470
- (in_bits u8 (ty_bits in_ty))
3471
- (out_bits u8 (ty_bits out_ty))
3472
- (src Reg (fpu_to_int_nan_check size src))
3473
- (min Reg (min_fp_value signed in_bits out_bits))
3474
- (src Reg (fpu_to_int_underflow_check signed in_ty out_ty src min))
3475
- (max Reg (max_fp_value signed in_bits out_bits))
3476
- (src Reg (fpu_to_int_overflow_check size src max)))
3477
- (fpu_to_int op src)))
3478
-
3479
- ;; Emits the appropriate instruction sequence to convert a
3480
- ;; floating-point value to an integer, saturating if the value
3481
- ;; does not fit in the target type.
3482
- ;; Accepts the specific conversion op, the source register,
3483
- ;; whether the input is signed, and finally the output type.
3484
- (decl fpu_to_int_cvt_sat (FpuToIntOp Reg bool Type) Reg)
3485
- (rule 1 (fpu_to_int_cvt_sat op src _ $I64)
3486
- (fpu_to_int op src))
3487
- (rule 1 (fpu_to_int_cvt_sat op src _ $I32)
3488
- (fpu_to_int op src))
3489
- (rule (fpu_to_int_cvt_sat op src $false (fits_in_16 out_ty))
3490
- (let ((result Reg (fpu_to_int op src))
3491
- (max Reg (imm out_ty (ImmExtend.Zero) (ty_mask out_ty))))
3492
- (with_flags_reg
3493
- (cmp (OperandSize.Size32) result max)
3494
- (csel (Cond.Hi) max result))))
3495
- (rule (fpu_to_int_cvt_sat op src $true (fits_in_16 out_ty))
3496
- (let ((result Reg (fpu_to_int op src))
3497
- (max Reg (signed_max out_ty))
3498
- (min Reg (signed_min out_ty))
3499
- (result Reg (with_flags_reg
3500
- (cmp (operand_size out_ty) result max)
3501
- (csel (Cond.Gt) max result)))
3502
- (result Reg (with_flags_reg
3503
- (cmp (operand_size out_ty) result min)
3504
- (csel (Cond.Lt) min result))))
3505
- result))
3506
-
3507
- (decl signed_min (Type) Reg)
3508
- (rule (signed_min $I8) (imm $I8 (ImmExtend.Sign) 0x80))
3509
- (rule (signed_min $I16) (imm $I16 (ImmExtend.Sign) 0x8000))
3510
-
3511
- (decl signed_max (Type) Reg)
3512
- (rule (signed_max $I8) (imm $I8 (ImmExtend.Sign) 0x7F))
3513
- (rule (signed_max $I16) (imm $I16 (ImmExtend.Sign) 0x7FFF))
3514
-
3515
- (decl fpu_to_int (FpuToIntOp Reg) Reg)
3516
- (rule (fpu_to_int op src)
3517
- (let ((dst WritableReg (temp_writable_reg $I64))
3518
- (_ Unit (emit (MInst.FpuToInt op dst src))))
3519
- dst))
3520
-
3521
- ;; Helper for generating `MInst.IntToFpu` instructions.
3522
-
3523
- (decl int_to_fpu (IntToFpuOp Reg) Reg)
3524
- (rule (int_to_fpu op src)
3525
- (let ((dst WritableReg (temp_writable_reg $I8X16))
3526
- (_ Unit (emit (MInst.IntToFpu op dst src))))
3527
- dst))
3528
-
3529
- ;;;; Helpers for Emitting Calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3530
-
3531
- (decl gen_call (SigRef ExternalName RelocDistance ValueSlice) InstOutput)
3532
- (extern constructor gen_call gen_call)
3533
-
3534
- (decl gen_call_indirect (SigRef Value ValueSlice) InstOutput)
3535
- (extern constructor gen_call_indirect gen_call_indirect)
3536
-
3537
- ;; Helpers for pinned register manipulation.
3538
-
3539
- (decl write_pinned_reg (Reg) SideEffectNoResult)
3540
- (rule (write_pinned_reg val)
3541
- (mov_to_preg (preg_pinned) val))
3542
-
3543
- ;; Helpers for stackslot effective address generation.
3544
-
3545
- (decl compute_stack_addr (StackSlot Offset32) Reg)
3546
- (rule (compute_stack_addr stack_slot offset)
3547
- (let ((dst WritableReg (temp_writable_reg $I64))
3548
- (_ Unit (emit (abi_stackslot_addr dst stack_slot offset))))
3549
- dst))
3550
-
3551
- ;; Helper for emitting instruction sequences to perform a vector comparison.
3552
-
3553
- (decl vec_cmp_vc (Reg Reg VectorSize) Reg)
3554
- (rule (vec_cmp_vc rn rm size)
3555
- (let ((dst Reg (vec_rrr (VecALUOp.Fcmeq) rn rn size))
3556
- (tmp Reg (vec_rrr (VecALUOp.Fcmeq) rm rm size))
3557
- (dst Reg (vec_rrr (VecALUOp.And) dst tmp size)))
3558
- dst))
3559
-
3560
- (decl vec_cmp (Reg Reg Type Cond) Reg)
3561
-
3562
- ;; Floating point Vs / Vc
3563
- (rule (vec_cmp rn rm ty (Cond.Vc))
3564
- (if (ty_vector_float ty))
3565
- (vec_cmp_vc rn rm (vector_size ty)))
3566
- (rule (vec_cmp rn rm ty (Cond.Vs))
3567
- (if (ty_vector_float ty))
3568
- (let ((tmp Reg (vec_cmp_vc rn rm (vector_size ty))))
3569
- (vec_misc (VecMisc2.Not) tmp (vector_size ty))))
3570
-
3571
- ;; 'Less than' operations are implemented by swapping the order of
3572
- ;; operands and using the 'greater than' instructions.
3573
- ;; 'Not equal' is implemented with 'equal' and inverting the result.
3574
-
3575
- ;; Floating-point
3576
- (rule (vec_cmp rn rm ty (Cond.Eq))
3577
- (if (ty_vector_float ty))
3578
- (vec_rrr (VecALUOp.Fcmeq) rn rm (vector_size ty)))
3579
- (rule (vec_cmp rn rm ty (Cond.Ne))
3580
- (if (ty_vector_float ty))
3581
- (let ((tmp Reg (vec_rrr (VecALUOp.Fcmeq) rn rm (vector_size ty))))
3582
- (vec_misc (VecMisc2.Not) tmp (vector_size ty))))
3583
- (rule (vec_cmp rn rm ty (Cond.Ge))
3584
- (if (ty_vector_float ty))
3585
- (vec_rrr (VecALUOp.Fcmge) rn rm (vector_size ty)))
3586
- (rule (vec_cmp rn rm ty (Cond.Gt))
3587
- (if (ty_vector_float ty))
3588
- (vec_rrr (VecALUOp.Fcmgt) rn rm (vector_size ty)))
3589
- ;; Floating-point swapped-operands
3590
- (rule (vec_cmp rn rm ty (Cond.Mi))
3591
- (if (ty_vector_float ty))
3592
- (vec_rrr (VecALUOp.Fcmgt) rm rn (vector_size ty)))
3593
- (rule (vec_cmp rn rm ty (Cond.Ls))
3594
- (if (ty_vector_float ty))
3595
- (vec_rrr (VecALUOp.Fcmge) rm rn (vector_size ty)))
3596
-
3597
- ;; Integer
3598
- (rule 1 (vec_cmp rn rm ty (Cond.Eq))
3599
- (if (ty_vector_not_float ty))
3600
- (vec_rrr (VecALUOp.Cmeq) rn rm (vector_size ty)))
3601
- (rule 1 (vec_cmp rn rm ty (Cond.Ne))
3602
- (if (ty_vector_not_float ty))
3603
- (let ((tmp Reg (vec_rrr (VecALUOp.Cmeq) rn rm (vector_size ty))))
3604
- (vec_misc (VecMisc2.Not) tmp (vector_size ty))))
3605
- (rule 1 (vec_cmp rn rm ty (Cond.Ge))
3606
- (if (ty_vector_not_float ty))
3607
- (vec_rrr (VecALUOp.Cmge) rn rm (vector_size ty)))
3608
- (rule 1 (vec_cmp rn rm ty (Cond.Gt))
3609
- (if (ty_vector_not_float ty))
3610
- (vec_rrr (VecALUOp.Cmgt) rn rm (vector_size ty)))
3611
- (rule (vec_cmp rn rm ty (Cond.Hs))
3612
- (if (ty_vector_not_float ty))
3613
- (vec_rrr (VecALUOp.Cmhs) rn rm (vector_size ty)))
3614
- (rule (vec_cmp rn rm ty (Cond.Hi))
3615
- (if (ty_vector_not_float ty))
3616
- (vec_rrr (VecALUOp.Cmhi) rn rm (vector_size ty)))
3617
- ;; Integer swapped-operands
3618
- (rule (vec_cmp rn rm ty (Cond.Le))
3619
- (if (ty_vector_not_float ty))
3620
- (vec_rrr (VecALUOp.Cmge) rm rn (vector_size ty)))
3621
- (rule (vec_cmp rn rm ty (Cond.Lt))
3622
- (if (ty_vector_not_float ty))
3623
- (vec_rrr (VecALUOp.Cmgt) rm rn (vector_size ty)))
3624
- (rule 1 (vec_cmp rn rm ty (Cond.Ls))
3625
- (if (ty_vector_not_float ty))
3626
- (vec_rrr (VecALUOp.Cmhs) rm rn (vector_size ty)))
3627
- (rule (vec_cmp rn rm ty (Cond.Lo))
3628
- (if (ty_vector_not_float ty))
3629
- (vec_rrr (VecALUOp.Cmhi) rm rn (vector_size ty)))
3630
-
3631
- ;; Helper for determining if any value in a vector is true.
3632
- ;; This operation is implemented by using umaxp to create a scalar value, which
3633
- ;; is then compared against zero.
3634
- ;;
3635
- ;; umaxp vn.4s, vm.4s, vm.4s
3636
- ;; mov xm, vn.d[0]
3637
- ;; cmp xm, #0
3638
- (decl vanytrue (Reg Type) ProducesFlags)
3639
- (rule 1 (vanytrue src (ty_vec128 ty))
3640
- (let ((src Reg (vec_rrr (VecALUOp.Umaxp) src src (VectorSize.Size32x4)))
3641
- (src Reg (mov_from_vec src 0 (ScalarSize.Size64))))
3642
- (cmp_imm (OperandSize.Size64) src (u8_into_imm12 0))))
3643
- (rule (vanytrue src ty)
3644
- (if (ty_vec64 ty))
3645
- (let ((src Reg (mov_from_vec src 0 (ScalarSize.Size64))))
3646
- (cmp_imm (OperandSize.Size64) src (u8_into_imm12 0))))
3647
-
3648
- ;;;; TLS Values ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3649
-
3650
- ;; Helper for emitting ElfTlsGetAddr.
3651
- (decl elf_tls_get_addr (ExternalName) Reg)
3652
- (rule (elf_tls_get_addr name)
3653
- (let ((dst WritableReg (temp_writable_reg $I64))
3654
- (_ Unit (emit (MInst.ElfTlsGetAddr name dst))))
3655
- dst))
3656
-
3657
- (decl macho_tls_get_addr (ExternalName) Reg)
3658
- (rule (macho_tls_get_addr name)
3659
- (let ((dst WritableReg (temp_writable_reg $I64))
3660
- (_ Unit (emit (MInst.MachOTlsGetAddr name dst))))
3661
- dst))
3662
-
3663
- ;; A tuple of `ProducesFlags` and `IntCC`.
3664
- (type FlagsAndCC (enum (FlagsAndCC (flags ProducesFlags)
3665
- (cc IntCC))))
3666
-
3667
- ;; Helper constructor for `FlagsAndCC`.
3668
- (decl flags_and_cc (ProducesFlags IntCC) FlagsAndCC)
3669
- (rule (flags_and_cc flags cc) (FlagsAndCC.FlagsAndCC flags cc))
3670
-
3671
- ;; Materialize a `FlagsAndCC` into a boolean `ValueRegs`.
3672
- (decl flags_and_cc_to_bool (FlagsAndCC) ValueRegs)
3673
- (rule (flags_and_cc_to_bool (FlagsAndCC.FlagsAndCC flags cc))
3674
- (with_flags flags (materialize_bool_result (cond_code cc))))
3675
-
3676
- ;; Get the `ProducesFlags` out of a `FlagsAndCC`.
3677
- (decl flags_and_cc_flags (FlagsAndCC) ProducesFlags)
3678
- (rule (flags_and_cc_flags (FlagsAndCC.FlagsAndCC flags _cc)) flags)
3679
-
3680
- ;; Get the `IntCC` out of a `FlagsAndCC`.
3681
- (decl flags_and_cc_cc (FlagsAndCC) IntCC)
3682
- (rule (flags_and_cc_cc (FlagsAndCC.FlagsAndCC _flags cc)) cc)
3683
-
3684
- ;; Helpers for lowering `icmp` sequences.
3685
- ;; `lower_icmp` contains shared functionality for lowering `icmp`
3686
- ;; sequences, which `lower_icmp_into_{reg,flags}` extend from.
3687
- (decl lower_icmp (IntCC Value Value Type) FlagsAndCC)
3688
- (decl lower_icmp_into_reg (IntCC Value Value Type Type) ValueRegs)
3689
- (decl lower_icmp_into_flags (IntCC Value Value Type) FlagsAndCC)
3690
- (decl lower_icmp_const (IntCC Value u64 Type) FlagsAndCC)
3691
- ;; For most cases, `lower_icmp_into_flags` is the same as `lower_icmp`,
3692
- ;; except for some I128 cases (see below).
3693
- (rule -1 (lower_icmp_into_flags cond x y ty) (lower_icmp cond x y ty))
3694
-
3695
- ;; Vectors.
3696
- ;; `icmp` into flags for vectors is invalid.
3697
- (rule 1 (lower_icmp_into_reg cond x y in_ty @ (multi_lane _ _) _out_ty)
3698
- (let ((cond Cond (cond_code cond))
3699
- (rn Reg (put_in_reg x))
3700
- (rm Reg (put_in_reg y)))
3701
- (vec_cmp rn rm in_ty cond)))
3702
-
3703
- ;; Determines the appropriate extend op given the value type and the given ArgumentExtension.
3704
- (decl lower_extend_op (Type ArgumentExtension) ExtendOp)
3705
- (rule (lower_extend_op $I8 (ArgumentExtension.Sext)) (ExtendOp.SXTB))
3706
- (rule (lower_extend_op $I16 (ArgumentExtension.Sext)) (ExtendOp.SXTH))
3707
- (rule (lower_extend_op $I8 (ArgumentExtension.Uext)) (ExtendOp.UXTB))
3708
- (rule (lower_extend_op $I16 (ArgumentExtension.Uext)) (ExtendOp.UXTH))
3709
-
3710
- ;; Integers <= 64-bits.
3711
- (rule -2 (lower_icmp_into_reg cond rn rm in_ty out_ty)
3712
- (if (ty_int_ref_scalar_64 in_ty))
3713
- (let ((cc Cond (cond_code cond)))
3714
- (flags_and_cc_to_bool (lower_icmp cond rn rm in_ty))))
3715
-
3716
- (rule 1 (lower_icmp cond rn rm (fits_in_16 ty))
3717
- (if (signed_cond_code cond))
3718
- (let ((rn Reg (put_in_reg_sext32 rn)))
3719
- (flags_and_cc (cmp_extend (operand_size ty) rn rm (lower_extend_op ty (ArgumentExtension.Sext))) cond)))
3720
- (rule -1 (lower_icmp cond rn (imm12_from_value rm) (fits_in_16 ty))
3721
- (let ((rn Reg (put_in_reg_zext32 rn)))
3722
- (flags_and_cc (cmp_imm (operand_size ty) rn rm) cond)))
3723
- (rule -2 (lower_icmp cond rn rm (fits_in_16 ty))
3724
- (let ((rn Reg (put_in_reg_zext32 rn)))
3725
- (flags_and_cc (cmp_extend (operand_size ty) rn rm (lower_extend_op ty (ArgumentExtension.Uext))) cond)))
3726
- (rule -3 (lower_icmp cond rn (u64_from_iconst c) ty)
3727
- (if (ty_int_ref_scalar_64 ty))
3728
- (lower_icmp_const cond rn c ty))
3729
- (rule -4 (lower_icmp cond rn rm ty)
3730
- (if (ty_int_ref_scalar_64 ty))
3731
- (flags_and_cc (cmp (operand_size ty) rn rm) cond))
3732
-
3733
- ;; We get better encodings when testing against an immediate that's even instead
3734
- ;; of odd, so rewrite comparisons to use even immediates:
3735
- ;;
3736
- ;; A >= B + 1
3737
- ;; ==> A - 1 >= B
3738
- ;; ==> A > B
3739
- (rule (lower_icmp_const (IntCC.UnsignedGreaterThanOrEqual) a b ty)
3740
- (if (ty_int_ref_scalar_64 ty))
3741
- (if-let $true (u64_is_odd b))
3742
- (if-let (imm12_from_u64 imm) (u64_sub b 1))
3743
- (flags_and_cc (cmp_imm (operand_size ty) a imm) (IntCC.UnsignedGreaterThan)))
3744
- (rule (lower_icmp_const (IntCC.SignedGreaterThanOrEqual) a b ty)
3745
- (if (ty_int_ref_scalar_64 ty))
3746
- (if-let $true (u64_is_odd b))
3747
- (if-let (imm12_from_u64 imm) (u64_sub b 1))
3748
- (flags_and_cc (cmp_imm (operand_size ty) a imm) (IntCC.SignedGreaterThan)))
3749
-
3750
- (rule -1 (lower_icmp_const cond rn (imm12_from_u64 c) ty)
3751
- (if (ty_int_ref_scalar_64 ty))
3752
- (flags_and_cc (cmp_imm (operand_size ty) rn c) cond))
3753
- (rule -2 (lower_icmp_const cond rn c ty)
3754
- (if (ty_int_ref_scalar_64 ty))
3755
- (flags_and_cc (cmp (operand_size ty) rn (imm ty (ImmExtend.Zero) c)) cond))
3756
-
3757
-
3758
- ;; 128-bit integers.
3759
- (rule (lower_icmp_into_reg cond @ (IntCC.Equal) rn rm $I128 $I8)
3760
- (let ((cc Cond (cond_code cond)))
3761
- (flags_and_cc_to_bool
3762
- (lower_icmp cond rn rm $I128))))
3763
- (rule (lower_icmp_into_reg cond @ (IntCC.NotEqual) rn rm $I128 $I8)
3764
- (let ((cc Cond (cond_code cond)))
3765
- (flags_and_cc_to_bool
3766
- (lower_icmp cond rn rm $I128))))
3767
-
3768
- ;; cmp lhs_lo, rhs_lo
3769
- ;; ccmp lhs_hi, rhs_hi, #0, eq
3770
- (decl lower_icmp_i128_eq_ne (Value Value) ProducesFlags)
3771
- (rule (lower_icmp_i128_eq_ne lhs rhs)
3772
- (let ((lhs ValueRegs (put_in_regs lhs))
3773
- (rhs ValueRegs (put_in_regs rhs))
3774
- (lhs_lo Reg (value_regs_get lhs 0))
3775
- (lhs_hi Reg (value_regs_get lhs 1))
3776
- (rhs_lo Reg (value_regs_get rhs 0))
3777
- (rhs_hi Reg (value_regs_get rhs 1))
3778
- (cmp_inst ProducesFlags (cmp (OperandSize.Size64) lhs_lo rhs_lo)))
3779
- (ccmp (OperandSize.Size64) lhs_hi rhs_hi
3780
- (nzcv $false $false $false $false) (Cond.Eq) cmp_inst)))
3781
-
3782
- (rule (lower_icmp (IntCC.Equal) lhs rhs $I128)
3783
- (flags_and_cc (lower_icmp_i128_eq_ne lhs rhs) (IntCC.Equal)))
3784
- (rule (lower_icmp (IntCC.NotEqual) lhs rhs $I128)
3785
- (flags_and_cc (lower_icmp_i128_eq_ne lhs rhs) (IntCC.NotEqual)))
3786
-
3787
- ;; cmp lhs_lo, rhs_lo
3788
- ;; cset tmp1, unsigned_cond
3789
- ;; cmp lhs_hi, rhs_hi
3790
- ;; cset tmp2, cond
3791
- ;; csel dst, tmp1, tmp2, eq
3792
- (rule -1 (lower_icmp_into_reg cond lhs rhs $I128 $I8)
3793
- (let ((unsigned_cond Cond (cond_code (intcc_unsigned cond)))
3794
- (cond Cond (cond_code cond))
3795
- (lhs ValueRegs (put_in_regs lhs))
3796
- (rhs ValueRegs (put_in_regs rhs))
3797
- (lhs_lo Reg (value_regs_get lhs 0))
3798
- (lhs_hi Reg (value_regs_get lhs 1))
3799
- (rhs_lo Reg (value_regs_get rhs 0))
3800
- (rhs_hi Reg (value_regs_get rhs 1))
3801
- (tmp1 Reg (with_flags_reg (cmp (OperandSize.Size64) lhs_lo rhs_lo)
3802
- (materialize_bool_result unsigned_cond))))
3803
- (with_flags (cmp (OperandSize.Size64) lhs_hi rhs_hi)
3804
- (lower_icmp_i128_consumer cond tmp1))))
3805
-
3806
- (decl lower_icmp_i128_consumer (Cond Reg) ConsumesFlags)
3807
- (rule (lower_icmp_i128_consumer cond tmp1)
3808
- (let ((tmp2 WritableReg (temp_writable_reg $I64))
3809
- (dst WritableReg (temp_writable_reg $I64)))
3810
- (ConsumesFlags.ConsumesFlagsTwiceReturnsValueRegs
3811
- (MInst.CSet tmp2 cond)
3812
- (MInst.CSel dst (Cond.Eq) tmp1 tmp2)
3813
- (value_reg dst))))
3814
-
3815
- (decl lower_bmask (Type Type ValueRegs) ValueRegs)
3816
-
3817
-
3818
- ;; For conversions that exactly fit a register, we can use csetm.
3819
- ;;
3820
- ;; cmp val, #0
3821
- ;; csetm res, ne
3822
- (rule 0
3823
- (lower_bmask (fits_in_64 _) (ty_32_or_64 in_ty) val)
3824
- (with_flags_reg
3825
- (cmp_imm (operand_size in_ty) (value_regs_get val 0) (u8_into_imm12 0))
3826
- (csetm (Cond.Ne))))
3827
-
3828
- ;; For conversions from a 128-bit value into a 64-bit or smaller one, we or the
3829
- ;; two registers of the 128-bit value together, and then recurse with the
3830
- ;; combined value as a 64-bit test.
3831
- ;;
3832
- ;; orr val, lo, hi
3833
- ;; cmp val, #0
3834
- ;; csetm res, ne
3835
- (rule 1
3836
- (lower_bmask (fits_in_64 ty) $I128 val)
3837
- (let ((lo Reg (value_regs_get val 0))
3838
- (hi Reg (value_regs_get val 1))
3839
- (combined Reg (orr $I64 lo hi)))
3840
- (lower_bmask ty $I64 (value_reg combined))))
3841
-
3842
- ;; For converting from any type into i128, duplicate the result of
3843
- ;; converting to i64.
3844
- (rule 2
3845
- (lower_bmask $I128 in_ty val)
3846
- (let ((res ValueRegs (lower_bmask $I64 in_ty val))
3847
- (res Reg (value_regs_get res 0)))
3848
- (value_regs res res)))
3849
-
3850
- ;; For conversions smaller than a register, we need to mask off the high bits, and then
3851
- ;; we can recurse into the general case.
3852
- ;;
3853
- ;; and tmp, val, #ty_mask
3854
- ;; cmp tmp, #0
3855
- ;; csetm res, ne
3856
- (rule 3
3857
- (lower_bmask out_ty (fits_in_16 in_ty) val)
3858
- ; This if-let can't fail due to ty_mask always producing 8/16 consecutive 1s.
3859
- (if-let mask_bits (imm_logic_from_u64 $I32 (ty_mask in_ty)))
3860
- (let ((masked Reg (and_imm $I32 (value_regs_get val 0) mask_bits)))
3861
- (lower_bmask out_ty $I32 masked)))
3862
-
3863
- ;; Exceptional `lower_icmp_into_flags` rules.
3864
- ;; We need to guarantee that the flags for `cond` are correct, so we
3865
- ;; compare `dst` with 1.
3866
- (rule (lower_icmp_into_flags cond @ (IntCC.SignedGreaterThanOrEqual) lhs rhs $I128)
3867
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
3868
- (dst Reg (value_regs_get dst 0))
3869
- (tmp Reg (imm $I64 (ImmExtend.Sign) 1))) ;; mov tmp, #1
3870
- (flags_and_cc (cmp (OperandSize.Size64) dst tmp) cond)))
3871
- (rule (lower_icmp_into_flags cond @ (IntCC.UnsignedGreaterThanOrEqual) lhs rhs $I128)
3872
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
3873
- (dst Reg (value_regs_get dst 0))
3874
- (tmp Reg (imm $I64 (ImmExtend.Zero) 1)))
3875
- (flags_and_cc (cmp (OperandSize.Size64) dst tmp) cond)))
3876
- (rule (lower_icmp_into_flags cond @ (IntCC.SignedLessThanOrEqual) lhs rhs $I128)
3877
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
3878
- (dst Reg (value_regs_get dst 0))
3879
- (tmp Reg (imm $I64 (ImmExtend.Sign) 1)))
3880
- (flags_and_cc (cmp (OperandSize.Size64) tmp dst) cond)))
3881
- (rule (lower_icmp_into_flags cond @ (IntCC.UnsignedLessThanOrEqual) lhs rhs $I128)
3882
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
3883
- (dst Reg (value_regs_get dst 0))
3884
- (tmp Reg (imm $I64 (ImmExtend.Zero) 1)))
3885
- (flags_and_cc (cmp (OperandSize.Size64) tmp dst) cond)))
3886
- ;; For strict comparisons, we compare with 0.
3887
- (rule (lower_icmp_into_flags cond @ (IntCC.SignedGreaterThan) lhs rhs $I128)
3888
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
3889
- (dst Reg (value_regs_get dst 0)))
3890
- (flags_and_cc (cmp (OperandSize.Size64) dst (zero_reg)) cond)))
3891
- (rule (lower_icmp_into_flags cond @ (IntCC.UnsignedGreaterThan) lhs rhs $I128)
3892
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
3893
- (dst Reg (value_regs_get dst 0)))
3894
- (flags_and_cc (cmp (OperandSize.Size64) dst (zero_reg)) cond)))
3895
- (rule (lower_icmp_into_flags cond @ (IntCC.SignedLessThan) lhs rhs $I128)
3896
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
3897
- (dst Reg (value_regs_get dst 0)))
3898
- (flags_and_cc (cmp (OperandSize.Size64) (zero_reg) dst) cond)))
3899
- (rule (lower_icmp_into_flags cond @ (IntCC.UnsignedLessThan) lhs rhs $I128)
3900
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
3901
- (dst Reg (value_regs_get dst 0)))
3902
- (flags_and_cc (cmp (OperandSize.Size64) (zero_reg) dst) cond)))
3903
-
3904
- ;; Helpers for generating select instruction sequences.
3905
- (decl lower_select (ProducesFlags Cond Type Value Value) ValueRegs)
3906
- (rule 2 (lower_select flags cond (ty_scalar_float ty) rn rm)
3907
- (with_flags flags (fpu_csel ty cond rn rm)))
3908
- (rule 3 (lower_select flags cond (ty_vec128 ty) rn rm)
3909
- (with_flags flags (vec_csel cond rn rm)))
3910
- (rule (lower_select flags cond ty rn rm)
3911
- (if (ty_vec64 ty))
3912
- (with_flags flags (fpu_csel $F64 cond rn rm)))
3913
- (rule 4 (lower_select flags cond $I128 rn rm)
3914
- (let ((dst_lo WritableReg (temp_writable_reg $I64))
3915
- (dst_hi WritableReg (temp_writable_reg $I64))
3916
- (rn ValueRegs (put_in_regs rn))
3917
- (rm ValueRegs (put_in_regs rm))
3918
- (rn_lo Reg (value_regs_get rn 0))
3919
- (rn_hi Reg (value_regs_get rn 1))
3920
- (rm_lo Reg (value_regs_get rm 0))
3921
- (rm_hi Reg (value_regs_get rm 1)))
3922
- (with_flags flags
3923
- (ConsumesFlags.ConsumesFlagsTwiceReturnsValueRegs
3924
- (MInst.CSel dst_lo cond rn_lo rm_lo)
3925
- (MInst.CSel dst_hi cond rn_hi rm_hi)
3926
- (value_regs dst_lo dst_hi)))))
3927
- (rule 1 (lower_select flags cond ty rn rm)
3928
- (if (ty_int_ref_scalar_64 ty))
3929
- (with_flags flags (csel cond rn rm)))
3930
-
3931
- ;; Helper for emitting `MInst.Jump` instructions.
3932
- (decl aarch64_jump (BranchTarget) SideEffectNoResult)
3933
- (rule (aarch64_jump target)
3934
- (SideEffectNoResult.Inst (MInst.Jump target)))
3935
-
3936
- ;; Helper for emitting `MInst.JTSequence` instructions.
3937
- ;; Emit the compound instruction that does:
3938
- ;;
3939
- ;; b.hs default
3940
- ;; csel rB, xzr, rIndex, hs
3941
- ;; csdb
3942
- ;; adr rA, jt
3943
- ;; ldrsw rB, [rA, rB, uxtw #2]
3944
- ;; add rA, rA, rB
3945
- ;; br rA
3946
- ;; [jt entries]
3947
- ;;
3948
- ;; This must be *one* instruction in the vcode because
3949
- ;; we cannot allow regalloc to insert any spills/fills
3950
- ;; in the middle of the sequence; otherwise, the ADR's
3951
- ;; PC-rel offset to the jumptable would be incorrect.
3952
- ;; (The alternative is to introduce a relocation pass
3953
- ;; for inlined jumptables, which is much worse, IMHO.)
3954
- (decl jt_sequence (Reg BoxJTSequenceInfo) ConsumesFlags)
3955
- (rule (jt_sequence ridx info)
3956
- (let ((rtmp1 WritableReg (temp_writable_reg $I64))
3957
- (rtmp2 WritableReg (temp_writable_reg $I64)))
3958
- (ConsumesFlags.ConsumesFlagsSideEffect
3959
- (MInst.JTSequence info ridx rtmp1 rtmp2))))
3960
-
3961
- ;; Helper for emitting `MInst.CondBr` instructions.
3962
- (decl cond_br (BranchTarget BranchTarget CondBrKind) ConsumesFlags)
3963
- (rule (cond_br taken not_taken kind)
3964
- (ConsumesFlags.ConsumesFlagsSideEffect
3965
- (MInst.CondBr taken not_taken kind)))
3966
-
3967
- ;; Helper for emitting `MInst.MovToNZCV` instructions.
3968
- (decl mov_to_nzcv (Reg) ProducesFlags)
3969
- (rule (mov_to_nzcv rn)
3970
- (ProducesFlags.ProducesFlagsSideEffect
3971
- (MInst.MovToNZCV rn)))
3972
-
3973
- ;; Helper for emitting `MInst.EmitIsland` instructions.
3974
- (decl emit_island (CodeOffset) SideEffectNoResult)
3975
- (rule (emit_island needed_space)
3976
- (SideEffectNoResult.Inst
3977
- (MInst.EmitIsland needed_space)))
3978
-
3979
- ;; Helper for emitting `br_table` sequences.
3980
- (decl br_table_impl (u64 Reg VecMachLabel) Unit)
3981
- (rule (br_table_impl (imm12_from_u64 jt_size) ridx targets)
3982
- (let ((jt_info BoxJTSequenceInfo (targets_jt_info targets)))
3983
- (emit_side_effect (with_flags_side_effect
3984
- (cmp_imm (OperandSize.Size32) ridx jt_size)
3985
- (jt_sequence ridx jt_info)))))
3986
- (rule -1 (br_table_impl jt_size ridx targets)
3987
- (let ((jt_size Reg (imm $I64 (ImmExtend.Zero) jt_size))
3988
- (jt_info BoxJTSequenceInfo (targets_jt_info targets)))
3989
- (emit_side_effect (with_flags_side_effect
3990
- (cmp (OperandSize.Size32) ridx jt_size)
3991
- (jt_sequence ridx jt_info)))))
3992
-
3993
- ;; Helper for emitting the `uzp1` instruction
3994
- (decl vec_uzp1 (Reg Reg VectorSize) Reg)
3995
- (rule (vec_uzp1 rn rm size) (vec_rrr (VecALUOp.Uzp1) rn rm size))
3996
-
3997
- ;; Helper for emitting the `uzp2` instruction
3998
- (decl vec_uzp2 (Reg Reg VectorSize) Reg)
3999
- (rule (vec_uzp2 rn rm size) (vec_rrr (VecALUOp.Uzp2) rn rm size))
4000
-
4001
- ;; Helper for emitting the `zip1` instruction
4002
- (decl vec_zip1 (Reg Reg VectorSize) Reg)
4003
- (rule (vec_zip1 rn rm size) (vec_rrr (VecALUOp.Zip1) rn rm size))
4004
-
4005
- ;; Helper for emitting the `zip2` instruction
4006
- (decl vec_zip2 (Reg Reg VectorSize) Reg)
4007
- (rule (vec_zip2 rn rm size) (vec_rrr (VecALUOp.Zip2) rn rm size))
4008
-
4009
- ;; Helper for emitting the `trn1` instruction
4010
- (decl vec_trn1 (Reg Reg VectorSize) Reg)
4011
- (rule (vec_trn1 rn rm size) (vec_rrr (VecALUOp.Trn1) rn rm size))
4012
-
4013
- ;; Helper for emitting the `trn2` instruction
4014
- (decl vec_trn2 (Reg Reg VectorSize) Reg)
4015
- (rule (vec_trn2 rn rm size) (vec_rrr (VecALUOp.Trn2) rn rm size))
4016
-
4017
- ;; Helper for creating a zero value `ASIMDMovModImm` immediate.
4018
- (decl asimd_mov_mod_imm_zero (ScalarSize) ASIMDMovModImm)
4019
- (extern constructor asimd_mov_mod_imm_zero asimd_mov_mod_imm_zero)
4020
-
4021
- ;; Helper for fallibly creating an `ASIMDMovModImm` immediate from its parts.
4022
- (decl pure partial asimd_mov_mod_imm_from_u64 (u64 ScalarSize) ASIMDMovModImm)
4023
- (extern constructor asimd_mov_mod_imm_from_u64 asimd_mov_mod_imm_from_u64)
4024
-
4025
- ;; Helper for fallibly creating an `ASIMDFPModImm` immediate from its parts.
4026
- (decl pure partial asimd_fp_mod_imm_from_u64 (u64 ScalarSize) ASIMDFPModImm)
4027
- (extern constructor asimd_fp_mod_imm_from_u64 asimd_fp_mod_imm_from_u64)
4028
-
4029
- ;; Helper for creating a `VecDupFPImm` instruction
4030
- (decl vec_dup_fp_imm (ASIMDFPModImm VectorSize) Reg)
4031
- (rule (vec_dup_fp_imm imm size)
4032
- (let ((dst WritableReg (temp_writable_reg $I8X16))
4033
- (_ Unit (emit (MInst.VecDupFPImm dst imm size))))
4034
- dst))
4035
-
4036
- ;; Helper for creating a `FpuLoad64` instruction
4037
- (decl fpu_load64 (AMode MemFlags) Reg)
4038
- (rule (fpu_load64 amode flags)
4039
- (let ((dst WritableReg (temp_writable_reg $I8X16))
4040
- (_ Unit (emit (MInst.FpuLoad64 dst amode flags))))
4041
- dst))
4042
-
4043
- ;; Helper for creating a `FpuLoad128` instruction
4044
- (decl fpu_load128 (AMode MemFlags) Reg)
4045
- (rule (fpu_load128 amode flags)
4046
- (let ((dst WritableReg (temp_writable_reg $I8X16))
4047
- (_ Unit (emit (MInst.FpuLoad128 dst amode flags))))
4048
- dst))