udb 0.1.9 → 0.1.14

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (414) hide show
  1. checksums.yaml +4 -4
  2. data/.data/cfgs/example_rv64_with_overlay.yaml +20 -20
  3. data/.data/cfgs/mc100-32-full-example.yaml +1 -0
  4. data/.data/cfgs/profile/README.adoc +10 -0
  5. data/.data/cfgs/profile/RVA20S64.yaml +26 -6
  6. data/.data/cfgs/profile/RVA20U64.yaml +18 -4
  7. data/.data/cfgs/profile/RVA22S64.yaml +27 -7
  8. data/.data/cfgs/profile/RVA22U64.yaml +18 -4
  9. data/.data/cfgs/profile/RVA23S64.yaml +61 -7
  10. data/.data/cfgs/profile/RVA23U64.yaml +36 -4
  11. data/.data/cfgs/profile/RVB23S64.yaml +27 -7
  12. data/.data/cfgs/profile/RVB23U64.yaml +18 -4
  13. data/.data/cfgs/profile/RVI20U32.yaml +10 -4
  14. data/.data/cfgs/profile/RVI20U64.yaml +10 -4
  15. data/.data/cfgs/qc_iu.yaml +8 -1
  16. data/.data/cfgs/rv32-riscv-tests.yaml +6 -2
  17. data/.data/cfgs/rv32-vector.yaml +6 -2
  18. data/.data/cfgs/rv64-riscv-tests.yaml +6 -2
  19. data/.data/cfgs/rv64-vector.yaml +6 -2
  20. data/.data/spec/custom/isa/qc_iu/csr/Smrnmi/mnepc.yaml +17 -0
  21. data/.data/spec/custom/isa/qc_iu/csr/Xqccmi/qc.itba.yaml +45 -0
  22. data/.data/spec/custom/isa/qc_iu/csr/Xqccmi/qc.itdec.yaml +39 -0
  23. data/.data/spec/custom/isa/qc_iu/csr/jvt.yaml +11 -0
  24. data/.data/spec/custom/isa/qc_iu/csr/mepc.yaml +16 -0
  25. data/.data/spec/custom/isa/qc_iu/ext/Xqccmi.yaml +290 -0
  26. data/.data/spec/custom/isa/qc_iu/ext/Xqccmt.yaml +127 -0
  27. data/.data/spec/custom/isa/qc_iu/inst/Xqccmi/qc.cm.ilut.yaml +136 -0
  28. data/.data/spec/custom/isa/qc_iu/inst/Xqccmt/qc.cm.jalt.yaml +84 -0
  29. data/.data/spec/custom/isa/qc_iu/inst/Xqccmt/qc.cm.jt.yaml +60 -0
  30. data/.data/spec/custom/isa/qc_iu/isa/globals.isa +134 -0
  31. data/.data/spec/schemas/config_schema.json +220 -27
  32. data/.data/spec/schemas/csr_schema.json +0 -6
  33. data/.data/spec/schemas/ext_schema.json +80 -24
  34. data/.data/spec/schemas/inst_schema.json +0 -3
  35. data/.data/spec/schemas/mmr_schema.json +3 -3
  36. data/.data/spec/schemas/profile_release_schema.json +1 -1
  37. data/.data/spec/schemas/profile_schema.json +0 -3
  38. data/.data/spec/schemas/register_file_schema.json +8 -3
  39. data/.data/spec/schemas/schema_defs.json +13 -27
  40. data/.data/spec/std/isa/csr/H/henvcfg.yaml +25 -0
  41. data/.data/spec/std/isa/csr/I/pmpaddr0.yaml +6 -4
  42. data/.data/spec/std/isa/csr/I/pmpaddr1.yaml +6 -4
  43. data/.data/spec/std/isa/csr/I/pmpaddr10.yaml +6 -4
  44. data/.data/spec/std/isa/csr/I/pmpaddr11.yaml +6 -4
  45. data/.data/spec/std/isa/csr/I/pmpaddr12.yaml +6 -4
  46. data/.data/spec/std/isa/csr/I/pmpaddr13.yaml +6 -4
  47. data/.data/spec/std/isa/csr/I/pmpaddr14.yaml +6 -4
  48. data/.data/spec/std/isa/csr/I/pmpaddr15.yaml +6 -4
  49. data/.data/spec/std/isa/csr/I/pmpaddr16.yaml +6 -4
  50. data/.data/spec/std/isa/csr/I/pmpaddr17.yaml +6 -4
  51. data/.data/spec/std/isa/csr/I/pmpaddr18.yaml +6 -4
  52. data/.data/spec/std/isa/csr/I/pmpaddr19.yaml +6 -4
  53. data/.data/spec/std/isa/csr/I/pmpaddr2.yaml +6 -4
  54. data/.data/spec/std/isa/csr/I/pmpaddr20.yaml +6 -4
  55. data/.data/spec/std/isa/csr/I/pmpaddr21.yaml +6 -4
  56. data/.data/spec/std/isa/csr/I/pmpaddr22.yaml +6 -4
  57. data/.data/spec/std/isa/csr/I/pmpaddr23.yaml +6 -4
  58. data/.data/spec/std/isa/csr/I/pmpaddr24.yaml +6 -4
  59. data/.data/spec/std/isa/csr/I/pmpaddr25.yaml +6 -4
  60. data/.data/spec/std/isa/csr/I/pmpaddr26.yaml +6 -4
  61. data/.data/spec/std/isa/csr/I/pmpaddr27.yaml +6 -4
  62. data/.data/spec/std/isa/csr/I/pmpaddr28.yaml +6 -4
  63. data/.data/spec/std/isa/csr/I/pmpaddr29.yaml +6 -4
  64. data/.data/spec/std/isa/csr/I/pmpaddr3.yaml +6 -4
  65. data/.data/spec/std/isa/csr/I/pmpaddr30.yaml +6 -4
  66. data/.data/spec/std/isa/csr/I/pmpaddr31.yaml +6 -4
  67. data/.data/spec/std/isa/csr/I/pmpaddr32.yaml +6 -4
  68. data/.data/spec/std/isa/csr/I/pmpaddr33.yaml +6 -4
  69. data/.data/spec/std/isa/csr/I/pmpaddr34.yaml +6 -4
  70. data/.data/spec/std/isa/csr/I/pmpaddr35.yaml +6 -4
  71. data/.data/spec/std/isa/csr/I/pmpaddr36.yaml +6 -4
  72. data/.data/spec/std/isa/csr/I/pmpaddr37.yaml +6 -4
  73. data/.data/spec/std/isa/csr/I/pmpaddr38.yaml +6 -4
  74. data/.data/spec/std/isa/csr/I/pmpaddr39.yaml +6 -4
  75. data/.data/spec/std/isa/csr/I/pmpaddr4.yaml +6 -4
  76. data/.data/spec/std/isa/csr/I/pmpaddr40.yaml +6 -4
  77. data/.data/spec/std/isa/csr/I/pmpaddr41.yaml +6 -4
  78. data/.data/spec/std/isa/csr/I/pmpaddr42.yaml +6 -4
  79. data/.data/spec/std/isa/csr/I/pmpaddr43.yaml +6 -4
  80. data/.data/spec/std/isa/csr/I/pmpaddr44.yaml +6 -4
  81. data/.data/spec/std/isa/csr/I/pmpaddr45.yaml +6 -4
  82. data/.data/spec/std/isa/csr/I/pmpaddr46.yaml +6 -4
  83. data/.data/spec/std/isa/csr/I/pmpaddr47.yaml +6 -4
  84. data/.data/spec/std/isa/csr/I/pmpaddr48.yaml +6 -4
  85. data/.data/spec/std/isa/csr/I/pmpaddr49.yaml +6 -4
  86. data/.data/spec/std/isa/csr/I/pmpaddr5.yaml +6 -4
  87. data/.data/spec/std/isa/csr/I/pmpaddr50.yaml +6 -4
  88. data/.data/spec/std/isa/csr/I/pmpaddr51.yaml +6 -4
  89. data/.data/spec/std/isa/csr/I/pmpaddr52.yaml +6 -4
  90. data/.data/spec/std/isa/csr/I/pmpaddr53.yaml +6 -4
  91. data/.data/spec/std/isa/csr/I/pmpaddr54.yaml +6 -4
  92. data/.data/spec/std/isa/csr/I/pmpaddr55.yaml +6 -4
  93. data/.data/spec/std/isa/csr/I/pmpaddr56.yaml +6 -4
  94. data/.data/spec/std/isa/csr/I/pmpaddr57.yaml +6 -4
  95. data/.data/spec/std/isa/csr/I/pmpaddr58.yaml +6 -4
  96. data/.data/spec/std/isa/csr/I/pmpaddr59.yaml +6 -4
  97. data/.data/spec/std/isa/csr/I/pmpaddr6.yaml +6 -4
  98. data/.data/spec/std/isa/csr/I/pmpaddr60.yaml +6 -4
  99. data/.data/spec/std/isa/csr/I/pmpaddr61.yaml +6 -4
  100. data/.data/spec/std/isa/csr/I/pmpaddr62.yaml +6 -4
  101. data/.data/spec/std/isa/csr/I/pmpaddr63.yaml +6 -4
  102. data/.data/spec/std/isa/csr/I/pmpaddr7.yaml +6 -4
  103. data/.data/spec/std/isa/csr/I/pmpaddr8.yaml +6 -4
  104. data/.data/spec/std/isa/csr/I/pmpaddr9.yaml +6 -4
  105. data/.data/spec/std/isa/csr/I/pmpaddrN.layout +6 -4
  106. data/.data/spec/std/isa/csr/I/pmpcfg0.yaml +128 -152
  107. data/.data/spec/std/isa/csr/I/pmpcfg1.yaml +64 -76
  108. data/.data/spec/std/isa/csr/I/pmpcfg10.yaml +128 -152
  109. data/.data/spec/std/isa/csr/I/pmpcfg11.yaml +64 -76
  110. data/.data/spec/std/isa/csr/I/pmpcfg12.yaml +128 -152
  111. data/.data/spec/std/isa/csr/I/pmpcfg13.yaml +64 -76
  112. data/.data/spec/std/isa/csr/I/pmpcfg14.yaml +128 -152
  113. data/.data/spec/std/isa/csr/I/pmpcfg15.yaml +64 -76
  114. data/.data/spec/std/isa/csr/I/pmpcfg2.yaml +128 -152
  115. data/.data/spec/std/isa/csr/I/pmpcfg3.yaml +64 -76
  116. data/.data/spec/std/isa/csr/I/pmpcfg4.yaml +128 -152
  117. data/.data/spec/std/isa/csr/I/pmpcfg5.yaml +64 -76
  118. data/.data/spec/std/isa/csr/I/pmpcfg6.yaml +128 -152
  119. data/.data/spec/std/isa/csr/I/pmpcfg7.yaml +64 -76
  120. data/.data/spec/std/isa/csr/I/pmpcfg8.yaml +128 -152
  121. data/.data/spec/std/isa/csr/I/pmpcfg9.yaml +64 -76
  122. data/.data/spec/std/isa/csr/I/pmpcfgN.layout +16 -19
  123. data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.layout +6 -2
  124. data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.yaml +6 -2
  125. data/.data/spec/std/isa/csr/hstatus.yaml +16 -0
  126. data/.data/spec/std/isa/csr/jvt.yaml +1 -0
  127. data/.data/spec/std/isa/csr/mcycleh.yaml +1 -1
  128. data/.data/spec/std/isa/csr/menvcfg.yaml +20 -0
  129. data/.data/spec/std/isa/csr/misa.yaml +0 -12
  130. data/.data/spec/std/isa/csr/mstatus.yaml +46 -6
  131. data/.data/spec/std/isa/csr/mstatush.yaml +17 -15
  132. data/.data/spec/std/isa/csr/senvcfg.yaml +42 -0
  133. data/.data/spec/std/isa/csr/sstatus.yaml +12 -0
  134. data/.data/spec/std/isa/csr/vsstatus.yaml +24 -0
  135. data/.data/spec/std/isa/ext/A.yaml +5 -7
  136. data/.data/spec/std/isa/ext/S.yaml +12 -0
  137. data/.data/spec/std/isa/ext/Smpmpmt.yaml +52 -0
  138. data/.data/spec/std/isa/ext/Sv32.yaml +7 -19
  139. data/.data/spec/std/isa/ext/Sv39.yaml +7 -19
  140. data/.data/spec/std/isa/ext/Sv48.yaml +4 -20
  141. data/.data/spec/std/isa/ext/Sv57.yaml +4 -20
  142. data/.data/spec/std/isa/ext/Svukte.yaml +71 -0
  143. data/.data/spec/std/isa/ext/Zawrs.yaml +1 -1
  144. data/.data/spec/std/isa/ext/Zihpm.yaml +0 -12
  145. data/.data/spec/std/isa/inst/B/andn.yaml +10 -12
  146. data/.data/spec/std/isa/inst/B/clmul.yaml +9 -11
  147. data/.data/spec/std/isa/inst/B/clmulh.yaml +9 -11
  148. data/.data/spec/std/isa/inst/B/orn.yaml +9 -11
  149. data/.data/spec/std/isa/inst/B/rev8.yaml +1 -1
  150. data/.data/spec/std/isa/inst/B/rol.yaml +9 -11
  151. data/.data/spec/std/isa/inst/B/rolw.yaml +9 -11
  152. data/.data/spec/std/isa/inst/B/ror.yaml +9 -11
  153. data/.data/spec/std/isa/inst/B/rorw.yaml +9 -11
  154. data/.data/spec/std/isa/inst/B/xnor.yaml +9 -11
  155. data/.data/spec/std/isa/inst/C/c.addi.yaml +1 -0
  156. data/.data/spec/std/isa/inst/C/c.addi16sp.yaml +1 -0
  157. data/.data/spec/std/isa/inst/C/c.addiw.yaml +1 -0
  158. data/.data/spec/std/isa/inst/C/c.andi.yaml +1 -0
  159. data/.data/spec/std/isa/inst/C/c.ldsp.yaml +4 -4
  160. data/.data/spec/std/isa/inst/C/c.li.yaml +1 -0
  161. data/.data/spec/std/isa/inst/C/c.lui.yaml +1 -0
  162. data/.data/spec/std/isa/inst/C/c.mv.yaml +1 -1
  163. data/.data/spec/std/isa/inst/C/c.sdsp.yaml +1 -1
  164. data/.data/spec/std/isa/inst/D/fsgnj.d.yaml +3 -0
  165. data/.data/spec/std/isa/inst/D/fsgnjn.d.yaml +3 -0
  166. data/.data/spec/std/isa/inst/D/fsgnjx.d.yaml +3 -0
  167. data/.data/spec/std/isa/inst/F/fadd.s.yaml +5 -5
  168. data/.data/spec/std/isa/inst/F/fclass.s.yaml +2 -2
  169. data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml +1 -1
  170. data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml +1 -1
  171. data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml +1 -1
  172. data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml +1 -1
  173. data/.data/spec/std/isa/inst/F/fcvt.s.w.yaml +1 -1
  174. data/.data/spec/std/isa/inst/F/fcvt.s.wu.yaml +1 -1
  175. data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml +1 -1
  176. data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml +1 -1
  177. data/.data/spec/std/isa/inst/F/fdiv.s.yaml +1 -1
  178. data/.data/spec/std/isa/inst/F/feq.s.yaml +2 -2
  179. data/.data/spec/std/isa/inst/F/fle.s.yaml +2 -2
  180. data/.data/spec/std/isa/inst/F/fleq.s.yaml +2 -2
  181. data/.data/spec/std/isa/inst/F/flt.s.yaml +2 -2
  182. data/.data/spec/std/isa/inst/F/fltq.s.yaml +2 -2
  183. data/.data/spec/std/isa/inst/F/flw.yaml +2 -2
  184. data/.data/spec/std/isa/inst/F/fmadd.s.yaml +1 -1
  185. data/.data/spec/std/isa/inst/F/fmax.s.yaml +6 -6
  186. data/.data/spec/std/isa/inst/F/fmin.s.yaml +6 -6
  187. data/.data/spec/std/isa/inst/F/fmsub.s.yaml +1 -1
  188. data/.data/spec/std/isa/inst/F/fmul.s.yaml +1 -1
  189. data/.data/spec/std/isa/inst/F/fmv.w.x.yaml +2 -2
  190. data/.data/spec/std/isa/inst/F/fmv.x.w.yaml +1 -1
  191. data/.data/spec/std/isa/inst/F/fnmadd.s.yaml +2 -2
  192. data/.data/spec/std/isa/inst/F/fnmsub.s.yaml +1 -1
  193. data/.data/spec/std/isa/inst/F/fsgnj.s.yaml +4 -4
  194. data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml +3 -3
  195. data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml +4 -4
  196. data/.data/spec/std/isa/inst/F/fsqrt.s.yaml +1 -1
  197. data/.data/spec/std/isa/inst/F/fsub.s.yaml +1 -1
  198. data/.data/spec/std/isa/inst/F/fsw.yaml +1 -1
  199. data/.data/spec/std/isa/inst/I/addi.yaml +2 -1
  200. data/.data/spec/std/isa/inst/I/addiw.yaml +2 -1
  201. data/.data/spec/std/isa/inst/I/andi.yaml +2 -1
  202. data/.data/spec/std/isa/inst/I/auipc.yaml +1 -0
  203. data/.data/spec/std/isa/inst/I/beq.yaml +1 -1
  204. data/.data/spec/std/isa/inst/I/bge.yaml +4 -2
  205. data/.data/spec/std/isa/inst/I/bgeu.yaml +3 -0
  206. data/.data/spec/std/isa/inst/I/blt.yaml +4 -2
  207. data/.data/spec/std/isa/inst/I/bltu.yaml +3 -0
  208. data/.data/spec/std/isa/inst/I/bne.yaml +1 -1
  209. data/.data/spec/std/isa/inst/I/lb.yaml +1 -0
  210. data/.data/spec/std/isa/inst/I/lbu.yaml +1 -0
  211. data/.data/spec/std/isa/inst/I/ld.yaml +2 -0
  212. data/.data/spec/std/isa/inst/I/lh.yaml +1 -0
  213. data/.data/spec/std/isa/inst/I/lhu.yaml +1 -0
  214. data/.data/spec/std/isa/inst/I/lui.yaml +1 -0
  215. data/.data/spec/std/isa/inst/I/lw.yaml +1 -0
  216. data/.data/spec/std/isa/inst/I/lwu.yaml +1 -0
  217. data/.data/spec/std/isa/inst/I/ori.yaml +1 -0
  218. data/.data/spec/std/isa/inst/I/sb.yaml +1 -0
  219. data/.data/spec/std/isa/inst/I/sd.yaml +1 -0
  220. data/.data/spec/std/isa/inst/I/sh.yaml +1 -0
  221. data/.data/spec/std/isa/inst/I/slt.yaml +2 -2
  222. data/.data/spec/std/isa/inst/I/slti.yaml +1 -0
  223. data/.data/spec/std/isa/inst/I/sltiu.yaml +2 -1
  224. data/.data/spec/std/isa/inst/I/sltu.yaml +1 -1
  225. data/.data/spec/std/isa/inst/I/sub.yaml +1 -1
  226. data/.data/spec/std/isa/inst/I/subw.yaml +1 -1
  227. data/.data/spec/std/isa/inst/I/sw.yaml +1 -0
  228. data/.data/spec/std/isa/inst/I/xori.yaml +2 -1
  229. data/.data/spec/std/isa/inst/M/mul.yaml +0 -19
  230. data/.data/spec/std/isa/inst/Q/fsgnj.q.yaml +1 -1
  231. data/.data/spec/std/isa/inst/S/sret.yaml +3 -1
  232. data/.data/spec/std/isa/inst/V/vadc.vim.yaml +1 -0
  233. data/.data/spec/std/isa/inst/V/vadd.vi.yaml +1 -0
  234. data/.data/spec/std/isa/inst/V/vadd.vv.yaml +1 -5
  235. data/.data/spec/std/isa/inst/V/vand.vi.yaml +1 -0
  236. data/.data/spec/std/isa/inst/V/vfsgnjn.vv.yaml +3 -0
  237. data/.data/spec/std/isa/inst/V/vfsgnjx.vv.yaml +3 -0
  238. data/.data/spec/std/isa/inst/V/vl1re8.v.yaml +3 -0
  239. data/.data/spec/std/isa/inst/V/vl2re8.v.yaml +3 -0
  240. data/.data/spec/std/isa/inst/V/vl4re8.v.yaml +3 -0
  241. data/.data/spec/std/isa/inst/V/vl8re8.v.yaml +3 -0
  242. data/.data/spec/std/isa/inst/V/vle8.v.yaml +4 -8
  243. data/.data/spec/std/isa/inst/V/vmadc.vi.yaml +1 -0
  244. data/.data/spec/std/isa/inst/V/vmadc.vim.yaml +1 -0
  245. data/.data/spec/std/isa/inst/V/vmand.mm.yaml +3 -0
  246. data/.data/spec/std/isa/inst/V/vmerge.vim.yaml +1 -0
  247. data/.data/spec/std/isa/inst/V/vmfle.vv.yaml +3 -0
  248. data/.data/spec/std/isa/inst/V/vmflt.vv.yaml +3 -0
  249. data/.data/spec/std/isa/inst/V/vmnand.mm.yaml +3 -0
  250. data/.data/spec/std/isa/inst/V/vmseq.vi.yaml +1 -0
  251. data/.data/spec/std/isa/inst/V/vmsgt.vi.yaml +4 -0
  252. data/.data/spec/std/isa/inst/V/vmsgtu.vi.yaml +4 -0
  253. data/.data/spec/std/isa/inst/V/vmsle.vi.yaml +4 -0
  254. data/.data/spec/std/isa/inst/V/vmsle.vv.yaml +3 -0
  255. data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml +4 -0
  256. data/.data/spec/std/isa/inst/V/vmsleu.vv.yaml +3 -0
  257. data/.data/spec/std/isa/inst/V/vmslt.vv.yaml +3 -0
  258. data/.data/spec/std/isa/inst/V/vmsltu.vv.yaml +3 -0
  259. data/.data/spec/std/isa/inst/V/vmsne.vi.yaml +1 -0
  260. data/.data/spec/std/isa/inst/V/vmv.v.i.yaml +2 -13
  261. data/.data/spec/std/isa/inst/V/vmv.x.s.yaml +1 -1
  262. data/.data/spec/std/isa/inst/V/vmxnor.mm.yaml +3 -0
  263. data/.data/spec/std/isa/inst/V/vmxor.mm.yaml +3 -0
  264. data/.data/spec/std/isa/inst/V/vnsrl.wx.yaml +3 -0
  265. data/.data/spec/std/isa/inst/V/vor.vi.yaml +1 -0
  266. data/.data/spec/std/isa/inst/V/vrsub.vi.yaml +1 -0
  267. data/.data/spec/std/isa/inst/V/vrsub.vx.yaml +3 -0
  268. data/.data/spec/std/isa/inst/V/vsadd.vi.yaml +1 -0
  269. data/.data/spec/std/isa/inst/V/vsaddu.vi.yaml +1 -0
  270. data/.data/spec/std/isa/inst/V/vse8.v.yaml +4 -4
  271. data/.data/spec/std/isa/inst/V/vwadd.vx.yaml +3 -0
  272. data/.data/spec/std/isa/inst/V/vwaddu.vx.yaml +3 -0
  273. data/.data/spec/std/isa/inst/V/vxor.vi.yaml +4 -0
  274. data/.data/spec/std/isa/inst/Zalasr/lSIZE.AQRL.layout +40 -5
  275. data/.data/spec/std/isa/inst/Zalasr/lb.aq.yaml +17 -1
  276. data/.data/spec/std/isa/inst/Zalasr/lb.aqrl.yaml +17 -1
  277. data/.data/spec/std/isa/inst/Zalasr/ld.aq.yaml +17 -1
  278. data/.data/spec/std/isa/inst/Zalasr/ld.aqrl.yaml +17 -1
  279. data/.data/spec/std/isa/inst/Zalasr/lh.aq.yaml +17 -1
  280. data/.data/spec/std/isa/inst/Zalasr/lh.aqrl.yaml +17 -1
  281. data/.data/spec/std/isa/inst/Zalasr/lw.aq.yaml +17 -1
  282. data/.data/spec/std/isa/inst/Zalasr/lw.aqrl.yaml +17 -1
  283. data/.data/spec/std/isa/inst/Zalasr/sSIZE.AQRL.layout +46 -5
  284. data/.data/spec/std/isa/inst/Zalasr/sb.aqrl.yaml +16 -1
  285. data/.data/spec/std/isa/inst/Zalasr/sb.rl.yaml +16 -1
  286. data/.data/spec/std/isa/inst/Zalasr/sd.aqrl.yaml +16 -1
  287. data/.data/spec/std/isa/inst/Zalasr/sd.rl.yaml +16 -1
  288. data/.data/spec/std/isa/inst/Zalasr/sh.aqrl.yaml +16 -1
  289. data/.data/spec/std/isa/inst/Zalasr/sh.rl.yaml +16 -1
  290. data/.data/spec/std/isa/inst/Zalasr/sw.aqrl.yaml +16 -1
  291. data/.data/spec/std/isa/inst/Zalasr/sw.rl.yaml +16 -1
  292. data/.data/spec/std/isa/inst/Zawrs/wrs.nto.yaml +4 -2
  293. data/.data/spec/std/isa/inst/Zba/add.uw.yaml +9 -11
  294. data/.data/spec/std/isa/inst/Zbb/orc.b.yaml +1 -1
  295. data/.data/spec/std/isa/inst/Zbkb/brev8.yaml +3 -3
  296. data/.data/spec/std/isa/inst/Zbkb/packw.yaml +1 -1
  297. data/.data/spec/std/isa/inst/Zbkb/unzip.yaml +2 -2
  298. data/.data/spec/std/isa/inst/Zbkb/zip.yaml +2 -2
  299. data/.data/spec/std/isa/inst/Zbkx/xperm4.yaml +2 -2
  300. data/.data/spec/std/isa/inst/Zbkx/xperm8.yaml +2 -2
  301. data/.data/spec/std/isa/inst/Zcd/c.fld.yaml +1 -1
  302. data/.data/spec/std/isa/inst/Zcd/c.fldsp.yaml +1 -1
  303. data/.data/spec/std/isa/inst/Zcd/c.fsdsp.yaml +1 -1
  304. data/.data/spec/std/isa/inst/Zcf/c.flwsp.yaml +1 -1
  305. data/.data/spec/std/isa/inst/Zcf/c.fswsp.yaml +1 -1
  306. data/.data/spec/std/isa/inst/Zcmp/cm.pop.yaml +1 -1
  307. data/.data/spec/std/isa/inst/Zcmp/cm.popret.yaml +1 -1
  308. data/.data/spec/std/isa/inst/Zcmp/cm.popretz.yaml +1 -1
  309. data/.data/spec/std/isa/inst/Zcmp/cm.push.yaml +2 -3
  310. data/.data/spec/std/isa/inst/Zfa/fround.s.yaml +1 -1
  311. data/.data/spec/std/isa/inst/Zfh/fcvt.h.s.yaml +6 -6
  312. data/.data/spec/std/isa/inst/Zfh/fcvt.s.h.yaml +5 -5
  313. data/.data/spec/std/isa/inst/Zfh/flh.yaml +1 -1
  314. data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml +1 -1
  315. data/.data/spec/std/isa/inst/Zfh/fmv.x.h.yaml +1 -1
  316. data/.data/spec/std/isa/inst/Zfh/fsh.yaml +1 -1
  317. data/.data/spec/std/isa/inst/Zicbop/prefetch.i.yaml +2 -0
  318. data/.data/spec/std/isa/inst/Zicbop/prefetch.r.yaml +2 -0
  319. data/.data/spec/std/isa/inst/Zicbop/prefetch.w.yaml +2 -0
  320. data/.data/spec/std/isa/inst/Zicsr/csrrc.yaml +1 -1
  321. data/.data/spec/std/isa/inst/Zicsr/csrrci.yaml +1 -1
  322. data/.data/spec/std/isa/inst/Zicsr/csrrs.yaml +2 -2
  323. data/.data/spec/std/isa/inst/Zicsr/csrrsi.yaml +1 -1
  324. data/.data/spec/std/isa/inst/Zicsr/csrrw.yaml +1 -1
  325. data/.data/spec/std/isa/inst/Zicsr/csrrwi.yaml +1 -1
  326. data/.data/spec/std/isa/inst/Zks/sm3p0.yaml +1 -1
  327. data/.data/spec/std/isa/inst/Zks/sm3p1.yaml +1 -1
  328. data/.data/spec/std/isa/inst/Zks/sm4ed.yaml +1 -1
  329. data/.data/spec/std/isa/inst/Zks/sm4ks.yaml +1 -1
  330. data/.data/spec/std/isa/isa/builtin_functions.idl +18 -0
  331. data/.data/spec/std/isa/isa/fp.idl +1 -5
  332. data/.data/spec/std/isa/isa/globals.isa +72 -21
  333. data/.data/spec/std/isa/isa/interrupts.idl +1 -0
  334. data/.data/spec/std/isa/isa/vec.idl +1 -2
  335. data/.data/spec/std/isa/manual_version/isa/20240411/isa_20240411.yaml +5 -5
  336. data/.data/spec/std/isa/param/COUNTINHIBIT_EN.yaml +8 -2
  337. data/.data/spec/std/isa/param/HSTATEEN_CONTEXT_TYPE.yaml +1 -0
  338. data/.data/spec/std/isa/param/JVT_BASE_MASK.yaml +1 -1
  339. data/.data/spec/std/isa/param/MCOUNTINHIBIT_IMPLEMENTED.yaml +25 -0
  340. data/.data/spec/std/isa/param/MSTATEEN_CONTEXT_TYPE.yaml +1 -0
  341. data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml +1 -0
  342. data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_VECTORED.yaml +1 -0
  343. data/.data/spec/std/isa/param/MTVEC_MODES.yaml +10 -3
  344. data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml +11 -22
  345. data/.data/spec/std/isa/param/NUM_USABLE_PMP_ENTRIES.yaml +35 -0
  346. data/.data/spec/std/isa/param/PMP_NA4_SUPPORTED.yaml +23 -0
  347. data/.data/spec/std/isa/param/PMP_NAPOT_SUPPORTED.yaml +19 -0
  348. data/.data/spec/std/isa/param/{MSTATUS_TVM_IMPLEMENTED.yaml → PMP_TOR_SUPPORTED.yaml} +6 -6
  349. data/.data/spec/std/isa/param/PRECISE_SYNCHRONOUS_EXCEPTIONS.yaml +1 -0
  350. data/.data/spec/std/isa/param/TRAP_ON_EBREAK.yaml +1 -0
  351. data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_M.yaml +1 -0
  352. data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml +1 -0
  353. data/.data/spec/std/isa/param/VLEN.yaml +2 -0
  354. data/.data/spec/std/isa/param/ZAWRS_NTO_IS_NOP.yaml +19 -0
  355. data/.data/spec/std/isa/profile/RVA20S64.yaml +11 -4
  356. data/.data/spec/std/isa/profile/RVA20U64.yaml +14 -5
  357. data/.data/spec/std/isa/profile/RVA22S64.yaml +14 -3
  358. data/.data/spec/std/isa/profile/RVA22U64.yaml +8 -1
  359. data/.data/spec/std/isa/profile/RVA23S64.yaml +13 -0
  360. data/.data/spec/std/isa/profile/RVA23U64.yaml +15 -1
  361. data/.data/spec/std/isa/profile/RVB23S64.yaml +15 -3
  362. data/.data/spec/std/isa/profile/RVB23U64.yaml +8 -1
  363. data/.data/spec/std/isa/profile/RVI20U32.yaml +8 -1
  364. data/.data/spec/std/isa/profile/RVI20U64.yaml +7 -0
  365. data/.data/spec/std/isa/register_file/F.yaml +3 -2
  366. data/.data/spec/std/isa/register_file/V.yaml +2 -2
  367. data/.data/spec/std/isa/register_file/X.yaml +2 -1
  368. data/lib/udb/ESPRESSO_VERSION +1 -1
  369. data/lib/udb/architecture.rb +4 -25
  370. data/lib/udb/cfg_arch.rb +171 -59
  371. data/lib/udb/cli.rb +10 -1
  372. data/lib/udb/condition.rb +38 -37
  373. data/lib/udb/config.rb +86 -8
  374. data/lib/udb/doc_link.rb +3 -4
  375. data/lib/udb/logic.rb +29 -56
  376. data/lib/udb/obj/csr.rb +23 -5
  377. data/lib/udb/obj/csr_field.rb +36 -21
  378. data/lib/udb/obj/database_obj.rb +2 -5
  379. data/lib/udb/obj/extension.rb +0 -3
  380. data/lib/udb/obj/instruction.rb +2 -5
  381. data/lib/udb/obj/non_isa_specification.rb +22 -100
  382. data/lib/udb/obj/portfolio.rb +75 -20
  383. data/lib/udb/obj/profile.rb +0 -4
  384. data/lib/udb/obj/register_file.rb +63 -2
  385. data/lib/udb/portfolio_design.rb +3 -6
  386. data/lib/udb/resolver.rb +84 -23
  387. data/lib/udb/version.rb +1 -1
  388. data/lib/udb/version_spec.rb +8 -0
  389. data/lib/udb/z3.rb +25 -2
  390. data/lib/udb.rb +0 -3
  391. metadata +30 -38
  392. data/.data/cfgs/profile/RVA23M64.yaml +0 -159
  393. data/.data/cfgs/profile/RVB23M64.yaml +0 -149
  394. data/.data/spec/schemas/proc_cert_class_schema.json +0 -35
  395. data/.data/spec/schemas/proc_cert_model_schema.json +0 -336
  396. data/.data/spec/std/isa/proc_cert_class/AC.yaml +0 -13
  397. data/.data/spec/std/isa/proc_cert_class/MC.yaml +0 -13
  398. data/.data/spec/std/isa/proc_cert_class/RVI.yaml +0 -16
  399. data/.data/spec/std/isa/proc_cert_model/AC100.yaml +0 -72
  400. data/.data/spec/std/isa/proc_cert_model/AC200.yaml +0 -58
  401. data/.data/spec/std/isa/proc_cert_model/MC100-32.yaml +0 -155
  402. data/.data/spec/std/isa/proc_cert_model/MC100-64.yaml +0 -21
  403. data/.data/spec/std/isa/proc_cert_model/MC200-32.yaml +0 -60
  404. data/.data/spec/std/isa/proc_cert_model/MC200-64.yaml +0 -21
  405. data/.data/spec/std/isa/proc_cert_model/MC300-32.yaml +0 -40
  406. data/.data/spec/std/isa/proc_cert_model/MC300-64.yaml +0 -21
  407. data/.data/spec/std/isa/proc_cert_model/RVI20-32.yaml +0 -39
  408. data/.data/spec/std/isa/proc_cert_model/RVI20-64.yaml +0 -19
  409. data/.data/spec/std/isa/profile/RVA23M64.yaml +0 -24
  410. data/.data/spec/std/isa/profile/RVB23M64.yaml +0 -86
  411. data/lib/udb/cert_normative_rule.rb +0 -41
  412. data/lib/udb/obj/certifiable_obj.rb +0 -21
  413. data/lib/udb/obj/certificate.rb +0 -230
  414. data/lib/udb/proc_cert_design.rb +0 -77
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 17
31
31
  (or, if `pmp18cfg.A` == TOR, for PMP entry 18).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 17) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 17) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 17) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 17) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 18
31
31
  (or, if `pmp19cfg.A` == TOR, for PMP entry 19).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 18) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 18) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 18) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 18) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 19
31
31
  (or, if `pmp20cfg.A` == TOR, for PMP entry 20).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 19) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 19) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 19) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 19) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 2
31
31
  (or, if `pmp3cfg.A` == TOR, for PMP entry 3).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 2) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 2) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 2) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 2) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 20
31
31
  (or, if `pmp21cfg.A` == TOR, for PMP entry 21).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 20) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 20) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 20) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 20) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 21
31
31
  (or, if `pmp22cfg.A` == TOR, for PMP entry 22).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 21) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 21) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 21) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 21) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 22
31
31
  (or, if `pmp23cfg.A` == TOR, for PMP entry 23).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 22) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 22) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 22) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 22) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 23
31
31
  (or, if `pmp24cfg.A` == TOR, for PMP entry 24).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 23) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 23) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 23) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 23) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 24
31
31
  (or, if `pmp25cfg.A` == TOR, for PMP entry 25).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 24) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 24) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 24) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 24) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 25
31
31
  (or, if `pmp26cfg.A` == TOR, for PMP entry 26).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 25) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 25) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 25) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 25) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 26
31
31
  (or, if `pmp27cfg.A` == TOR, for PMP entry 27).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 26) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 26) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 26) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 26) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 27
31
31
  (or, if `pmp28cfg.A` == TOR, for PMP entry 28).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 27) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 27) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 27) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 27) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 28
31
31
  (or, if `pmp29cfg.A` == TOR, for PMP entry 29).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 28) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 28) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 28) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 28) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 29
31
31
  (or, if `pmp30cfg.A` == TOR, for PMP entry 30).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 29) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 29) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 29) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 29) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 3
31
31
  (or, if `pmp4cfg.A` == TOR, for PMP entry 4).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 3) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 3) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 3) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 3) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 30
31
31
  (or, if `pmp31cfg.A` == TOR, for PMP entry 31).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 30) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 30) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 30) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 30) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 31
31
31
  (or, if `pmp32cfg.A` == TOR, for PMP entry 32).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 31) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 31) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 31) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 31) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 32
31
31
  (or, if `pmp33cfg.A` == TOR, for PMP entry 33).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 32) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 32) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 32) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 32) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 33
31
31
  (or, if `pmp34cfg.A` == TOR, for PMP entry 34).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 33) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 33) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 33) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 33) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 34
31
31
  (or, if `pmp35cfg.A` == TOR, for PMP entry 35).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 34) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 34) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 34) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 34) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 35
31
31
  (or, if `pmp36cfg.A` == TOR, for PMP entry 36).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 35) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 35) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 35) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 35) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 36
31
31
  (or, if `pmp37cfg.A` == TOR, for PMP entry 37).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 36) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 36) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 36) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 36) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 37
31
31
  (or, if `pmp38cfg.A` == TOR, for PMP entry 38).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 37) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 37) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 37) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 37) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 38
31
31
  (or, if `pmp39cfg.A` == TOR, for PMP entry 39).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 38) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 38) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 38) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 38) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 39
31
31
  (or, if `pmp40cfg.A` == TOR, for PMP entry 40).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 39) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 39) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 39) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 39) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;