udb 0.1.9 → 0.1.14

data/.data/cfgs/profile/RVB23U64.yaml

@@ -10,8 +10,7 @@ kind: architecture configuration
 type: partially configured
 name: RVB23U64
 description:
-params:
-  MXLEN: 64
+params: {}
 mandatory_extensions:
 - name: A
   version: "~> 2.1"
@@ -20,9 +19,9 @@ mandatory_extensions:
 - name: C
   version: "~> 2.0"
 - name: D
-  version: "~> 2.2"
+  version: "~> 2.2.0"
 - name: F
-  version: "~> 2.2"
+  version: "~> 2.2.0"
 - name: I
   version: "~> 2.1"
 - name: M
@@ -33,6 +32,10 @@ mandatory_extensions:
   version: "~> 1.0"
 - name: Za64rs
   version: "~> 1.0"
+- name: Zaamo
+  version: "~> 1.0.0"
+- name: Zalrsc
+  version: "~> 1.0.0"
 - name: Zawrs
   version: "~> 1.0"
 - name: Zba
@@ -41,8 +44,12 @@ mandatory_extensions:
   version: "~> 1.0"
 - name: Zbs
   version: "~> 1.0"
+- name: Zca
+  version: "~> 1.0.0"
 - name: Zcb
   version: "~> 1.0"
+- name: Zcd
+  version: "~> 1.0.0"
 - name: Zcmop
   version: "~> 1.0"
 - name: Zfa
@@ -139,3 +146,10 @@ non_mandatory_extensions:
 - name: Zvkt
   version: "~> 1.0"
 additional_extensions: true
+requirements:
+  param:
+    allOf:
+    - name: U_MODE_ENDIANNESS
+      equal: little
+    - name: UXLEN
+      includes: 64

data/.data/cfgs/profile/RVI20U32.yaml

@@ -10,8 +10,7 @@ kind: architecture configuration
 type: partially configured
 name: RVI20U32
 description:
-params:
-  MXLEN: 32
+params: {}
 mandatory_extensions:
 - name: I
   version: "~> 2.1"
@@ -21,9 +20,9 @@ non_mandatory_extensions:
 - name: C
   version: "~> 2.0"
 - name: D
-  version: "~> 2.2"
+  version: "~> 2.2.0"
 - name: F
-  version: "~> 2.2"
+  version: "~> 2.2.0"
 - name: M
   version: "~> 2.0"
 - name: Zca
@@ -39,3 +38,10 @@ non_mandatory_extensions:
 - name: Zihpm
   version: "~> 2.0"
 additional_extensions: true
+requirements:
+  param:
+    allOf:
+    - name: U_MODE_ENDIANNESS
+      equal: little
+    - name: UXLEN
+      includes: 32

data/.data/cfgs/profile/RVI20U64.yaml

@@ -10,8 +10,7 @@ kind: architecture configuration
 type: partially configured
 name: RVI20U64
 description:
-params:
-  MXLEN: 64
+params: {}
 mandatory_extensions:
 - name: I
   version: "~> 2.1"
@@ -21,9 +20,9 @@ non_mandatory_extensions:
 - name: C
   version: "~> 2.0"
 - name: D
-  version: "~> 2.2"
+  version: "~> 2.2.0"
 - name: F
-  version: "~> 2.2"
+  version: "~> 2.2.0"
 - name: M
   version: "~> 2.0"
 - name: Zca
@@ -39,3 +38,10 @@ non_mandatory_extensions:
 - name: Zihpm
   version: "~> 2.0"
 additional_extensions: true
+requirements:
+  param:
+    allOf:
+    - name: U_MODE_ENDIANNESS
+      equal: little
+    - name: UXLEN
+      includes: 64

data/.data/cfgs/qc_iu.yaml

@@ -5,7 +5,7 @@ kind: architecture configuration
 type: fully configured
 name: qc_iu
 arch_overlay: qc_iu
-description: Configuration with the Xqci and Xqccmp custom extensions.
+description: Configuration with the Xqci, Xqccmp, Xqccmt, and Xqccmi custom extensions.
 implemented_extensions:
   - { name: Sm, version: "= 1.13" }
   - { name: Smrnmi, version: "= 1.0" }
@@ -22,6 +22,8 @@ implemented_extensions:
   - { name: Zicsr, version: "= 2.0" }
   - { name: Zihpm, version: "= 2.0" }
   - { name: Xqccmp, version: "= 0.3" }
+  - { name: Xqccmt, version: "= 0.1.0" }
+  - { name: Xqccmi, version: "= 0.2.0" }
   - { name: Xqci, version: "= 0.13" }
   - { name: Xqcia, version: "= 0.7.0" }
   - { name: Xqciac, version: "= 0.3.0" }
@@ -174,9 +176,14 @@ params:
   MTVAL_WIDTH: 32
   PMP_GRANULARITY: 12
   NUM_PMP_ENTRIES: 16
+  NUM_USABLE_PMP_ENTRIES: 16
+  PMP_TOR_SUPPORTED: true
+  PMP_NA4_SUPPORTED: false
+  PMP_NAPOT_SUPPORTED: true
   PMA_GRANULARITY: 12
   M_MODE_ENDIANNESS: little
   MISA_CSR_IMPLEMENTED: true
+  MCOUNTINHIBIT_IMPLEMENTED: true
   MTVEC_ACCESS: rw
   MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
   MTVEC_BASE_ALIGNMENT_DIRECT: 4

data/.data/cfgs/rv32-riscv-tests.yaml

@@ -18,7 +18,7 @@ implemented_extensions:
   - [S, "1.11.0"]
   - [U, "1.0.0"]
   - [Zifencei, "2.0.0"]
-  - [Sv32, "1.11.0"]
+  - [Sv32, "1.0"]
   - [F, "2.2.0"]
   - [Zcf, "1.0"]
 
@@ -55,6 +55,7 @@ params:
   PMA_GRANULARITY: 12
   PHYS_ADDR_WIDTH: 34
   MISA_CSR_IMPLEMENTED: true
+  MCOUNTINHIBIT_IMPLEMENTED: true
   MTVEC_ACCESS: rw
   MTVEC_MODES: [0, 1]
   MTVEC_BASE_ALIGNMENT_DIRECT: 4
@@ -193,8 +194,11 @@ params:
   TRAP_ON_ECALL_FROM_S: true
   MSTATUS_VS_LEGAL_VALUES: [0]
   MSTATUS_FS_LEGAL_VALUES: [3, 2, 1, 0]
-  MSTATUS_TVM_IMPLEMENTED: false
   NUM_PMP_ENTRIES: 16
+  NUM_USABLE_PMP_ENTRIES: 16
+  PMP_TOR_SUPPORTED: true
+  PMP_NA4_SUPPORTED: false
+  PMP_NAPOT_SUPPORTED: true
   PMP_GRANULARITY: 12
   MUTABLE_MISA_U: false
   U_MODE_ENDIANNESS: little

data/.data/cfgs/rv32-vector.yaml

@@ -22,7 +22,7 @@ implemented_extensions:
   - [S, "1.11.0"]
   - [U, "1.0.0"]
   - [Zifencei, "2.0.0"]
-  - [Sv32, "1.11.0"]
+  - [Sv32, "1.0"]
   - [V, "1.0.0"]
   - [Zve64f, "1.0.0"]
   - [Zve64d, "1.0.0"]
@@ -65,6 +65,7 @@ params:
   PMA_GRANULARITY: 12
   PHYS_ADDR_WIDTH: 34
   MISA_CSR_IMPLEMENTED: true
+  MCOUNTINHIBIT_IMPLEMENTED: true
   MTVEC_ACCESS: rw
   MTVEC_MODES: [0, 1]
   MTVEC_BASE_ALIGNMENT_DIRECT: 4
@@ -207,8 +208,11 @@ params:
   MSTATUS_VS_LEGAL_VALUES: [0, 1, 2, 3]
   HW_MSTATUS_FS_DIRTY_UPDATE: precise
   MSTATUS_FS_LEGAL_VALUES: [0, 3]
-  MSTATUS_TVM_IMPLEMENTED: false
   NUM_PMP_ENTRIES: 16
+  NUM_USABLE_PMP_ENTRIES: 16
+  PMP_TOR_SUPPORTED: true
+  PMP_NA4_SUPPORTED: false
+  PMP_NAPOT_SUPPORTED: true
   PMP_GRANULARITY: 12
   MUTABLE_MISA_U: false
   U_MODE_ENDIANNESS: little

data/.data/cfgs/rv64-riscv-tests.yaml

@@ -17,7 +17,7 @@ implemented_extensions:
   - [S, "1.11.0"]
   - [U, "1.0.0"]
   - [Zifencei, "2.0.0"]
-  - [Sv39, "1.11.0"]
+  - [Sv39, "1.0"]
   - [Zca, "1.0.0"]
   - [F, "2.2.0"]
 
@@ -53,6 +53,7 @@ params:
   PMA_GRANULARITY: 12
   PHYS_ADDR_WIDTH: 57
   MISA_CSR_IMPLEMENTED: true
+  MCOUNTINHIBIT_IMPLEMENTED: true
   MTVEC_ACCESS: rw
   MTVEC_MODES: [0, 1]
   MTVEC_BASE_ALIGNMENT_DIRECT: 4
@@ -192,8 +193,11 @@ params:
   TRAP_ON_ECALL_FROM_U: true
   MSTATUS_VS_LEGAL_VALUES: [0]
   MSTATUS_FS_LEGAL_VALUES: [3, 2, 1, 0]
-  MSTATUS_TVM_IMPLEMENTED: false
   NUM_PMP_ENTRIES: 16
+  NUM_USABLE_PMP_ENTRIES: 16
+  PMP_TOR_SUPPORTED: true
+  PMP_NA4_SUPPORTED: false
+  PMP_NAPOT_SUPPORTED: true
   PMP_GRANULARITY: 12
   MUTABLE_MISA_U: false
   U_MODE_ENDIANNESS: little

data/.data/cfgs/rv64-vector.yaml

@@ -19,7 +19,7 @@ implemented_extensions:
   - [S, "1.11.0"]
   - [U, "1.0.0"]
   - [Zifencei, "2.0.0"]
-  - [Sv39, "1.11.0"]
+  - [Sv39, "1.0"]
   - [V, "1.0.0"]
   - [F, "2.2"]
   - [D, "2.2"]
@@ -64,6 +64,7 @@ params:
   PMA_GRANULARITY: 12
   PHYS_ADDR_WIDTH: 57
   MISA_CSR_IMPLEMENTED: true
+  MCOUNTINHIBIT_IMPLEMENTED: true
   MTVEC_ACCESS: rw
   MTVEC_MODES: [0, 1]
   MTVEC_BASE_ALIGNMENT_DIRECT: 4
@@ -204,8 +205,11 @@ params:
   TRAP_ON_ECALL_FROM_U: true
   MSTATUS_VS_LEGAL_VALUES: [0, 1, 2, 3]
   MSTATUS_FS_LEGAL_VALUES: [0, 1, 2, 3]
-  MSTATUS_TVM_IMPLEMENTED: false
   NUM_PMP_ENTRIES: 16
+  NUM_USABLE_PMP_ENTRIES: 16
+  PMP_TOR_SUPPORTED: true
+  PMP_NA4_SUPPORTED: false
+  PMP_NAPOT_SUPPORTED: true
   PMP_GRANULARITY: 12
   MUTABLE_MISA_U: false
   U_MODE_ENDIANNESS: little

data/.data/spec/custom/isa/qc_iu/csr/Smrnmi/mnepc.yaml

@@ -0,0 +1,17 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+---
+# Overlay: allow bit 0 of mnepc.PC to be written and read back unchanged.
+#
+# When Xqccmi is present, qc.cm.ilut sets bit 0 of mepc/mnepc to indicate
+# whether an exception originated from the first (bit 0 = 0) or second
+# (bit 0 = 1) packed instruction in an ILUT entry. The standard mnepc
+# definition forces bit 0 to 0 on write and masks it on read; both
+# behaviours are removed here so that bit 0 is preserved faithfully.
+fields:
+  PC:
+    sw_write(csr_value): |
+      return csr_value.PC;
+sw_read(): |
+  return CSR[mnepc].PC;

data/.data/spec/custom/isa/qc_iu/csr/Xqccmi/qc.itba.yaml

@@ -0,0 +1,45 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
+
+$schema: csr_schema.json#
+kind: csr
+name: qc.itba
+long_name: Instruction Table Base Address Register
+address: 0x800
+priv_mode: U
+length: MXLEN
+writable: true
+description: |
+  The `qc.itba` register holds the base address of the Instruction Lookup Table (ILUT)
+  used by the `qc.cm.ilut` instruction.
+
+  The BASE field specifies bits[XLEN-1:6] of the ILUT base address. The lower 6 bits
+  are implicitly zero, so the ILUT base address is always 64-byte aligned.
+
+  The memory region pointed to by `qc.itba.base` is treated as instruction memory for
+  the purpose of executing ILUT instructions, requiring execute (X) access permission.
+  Read (R) permission is not required.
+
+  `qc.itba` adds architectural state to the system software context and must be
+  saved and restored on context switches.
+definedBy:
+  extension:
+    name: Xqccmi
+fields:
+  base:
+    location_rv32: 31-6
+    location_rv64: 63-6
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      Bits[XLEN-1:6] of the ILUT base address. The full base address is formed by
+      appending 6 implicit zero bits: `base_addr = {base, 6'b000000}`.
+      The base address must be 64-byte aligned.
+  mode:
+    location: 5-0
+    type: RO
+    reset_value: 0
+    description: |
+      Reserved for future use. Always reads as zero. Writes are ignored.

data/.data/spec/custom/isa/qc_iu/csr/Xqccmi/qc.itdec.yaml

@@ -0,0 +1,39 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../../schemas/csr_schema.json
+
+$schema: csr_schema.json#
+kind: csr
+name: qc.itdec
+long_name: Instruction Table Double Entry Count Register
+address: 0x801
+priv_mode: U
+length: MXLEN
+writable: true
+description: |
+  The `qc.itdec` register specifies the number of leading 64-bit double entries
+  in the Instruction Lookup Table (ILUT) used by the `qc.cm.ilut` instruction.
+
+  The DEC field holds an 11-bit count. The first DEC logical ILUT entries
+  (indices 0 through DEC−1) are 64-bit double entries. The remaining entries
+  (indices DEC through 2047) are 32-bit single entries.
+
+  The byte offset from the ILUT base address for logical index i is:
+  - If i < DEC: offset = i × 8
+  - If i ≥ DEC: offset = DEC × 8 + (i − DEC) × 4
+
+  The reset value of 0 selects backward-compatible mode in which all entries
+  are 32-bit single entries.
+definedBy:
+  extension:
+    name: Xqccmi
+fields:
+  dec:
+    location: 13-3
+    type: RW
+    reset_value: 0
+    description: |
+      11-bit double entry count. Specifies the number of leading 64-bit entries
+      in the ILUT. Legal range: 0..2047. A value of 0 means all entries are
+      32-bit (backward-compatible mode).

data/.data/spec/custom/isa/qc_iu/csr/jvt.yaml

@@ -0,0 +1,11 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+---
+# Overlay: extend jvt definedBy to include Xqccmt (custom variant of Zcmt)
+definedBy:
+  extension:
+    name: null
+    anyOf:
+      - name: Zcmt
+      - name: Xqccmt

data/.data/spec/custom/isa/qc_iu/csr/mepc.yaml

@@ -0,0 +1,16 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+---
+# Overlay: allow bit 0 of mepc.PC to be written and read back unchanged.
+#
+# When Xqccmi is present, qc.cm.ilut sets bit 0 of mepc to indicate whether
+# an exception originated from the first (bit 0 = 0) or second (bit 0 = 1)
+# packed instruction in an ILUT entry. The standard mepc definition forces
+# bit 0 to 0 on write and masks it on read; both behaviours are removed here.
+fields:
+  PC:
+    sw_write(csr_value): |
+      return csr_value.PC;
+sw_read(): |
+  return CSR[mepc].PC;