udb 0.1.9 → 0.1.14

data/.data/spec/std/isa/inst/I/ld.yaml

@@ -29,6 +29,7 @@ encoding:
     variables:
       - name: imm
         location: 31-20
+        sign_extend: true
       - name: xs1
         location: 19-15
       - name: xd
@@ -39,6 +40,7 @@ encoding:
     variables:
       - name: imm
         location: 31-20
+        sign_extend: true
       - name: xs1
         location: 19-15
       - name: xd

data/.data/spec/std/isa/inst/I/lh.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/lhu.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/lui.yaml

@@ -18,6 +18,7 @@ encoding:
     - name: imm
       location: 31-12
       left_shift: 12
+      sign_extend: true
     - name: xd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/I/lw.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/lwu.yaml

@@ -22,6 +22,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/ori.yaml

@@ -17,6 +17,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/sb.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: xs2
       location: 24-20
     - name: xs1

data/.data/spec/std/isa/inst/I/sd.yaml

@@ -25,6 +25,7 @@ encoding:
     variables:
       - name: imm
         location: 31-25|11-7
+        sign_extend: true
       - name: xs2
         not: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
         location: 24-20

data/.data/spec/std/isa/inst/I/sh.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: xs2
       location: 24-20
     - name: xs1

data/.data/spec/std/isa/inst/I/slt.yaml

@@ -31,9 +31,9 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: xs2 == 0
-    to: sltz xd,xs1
+    to: sltz xd, xs1
   - when: xs1 == 0
-    to: sgtz xd,xs2
+    to: sgtz xd, xs2
 operation(): |
   XReg src1 = X[xs1];
   XReg src2 = X[xs2];

data/.data/spec/std/isa/inst/I/slti.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/sltiu.yaml

@@ -23,6 +23,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd
@@ -35,7 +36,7 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: imm == 1
-    to: seqz xd,xs1
+    to: seqz xd, xs1
 operation(): |
   Bits<MXLEN> sign_extend_imm = $signed(imm);
   X[xd] = (X[xs1] < sign_extend_imm) ? 1 : 0;

data/.data/spec/std/isa/inst/I/sltu.yaml

@@ -31,6 +31,6 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: xs1 == 0
-    to: snez xd,xs2
+    to: snez xd, xs2
 operation(): |
   X[xd] = (X[xs1] < X[xs2]) ? 1 : 0;

data/.data/spec/std/isa/inst/I/sub.yaml

@@ -29,7 +29,7 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: xs1 == 0
-    to: neg xd,xs2
+    to: neg xd, xs2
 operation(): |
   XReg t0 = X[xs1];
   XReg t1 = X[xs2];

data/.data/spec/std/isa/inst/I/subw.yaml

@@ -33,7 +33,7 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: xs1 == 0
-    to: negw xd,xs2
+    to: negw xd, xs2
 operation(): |
   Bits<32> t0 = X[xs1][31:0];
   Bits<32> t1 = X[xs2][31:0];

data/.data/spec/std/isa/inst/I/sw.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: xs2
       location: 24-20
     - name: xs1

data/.data/spec/std/isa/inst/I/xori.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd
@@ -31,5 +32,5 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: $signed(imm) == -1
-    to: not xd,xs1
+    to: not xd, xs1
 operation(): X[xd] = X[xs1] ^ $signed(imm);

data/.data/spec/std/isa/inst/M/mul.yaml

@@ -50,22 +50,3 @@ operation(): |
   XReg src2 = X[xs2];
 
   X[xd] = (src1 * src2)[MXLEN-1:0];
-
-cert_normative_rules:
-  - id: inst.mul.encoding
-    name: Encoding
-    description: Encoding of `mul` instruction
-    doc_links:
-      - manual:inst:mul:encoding
-  - id: inst.mul.basic_op
-    name: Basic operation
-    description: Basic operation of `mul` instruction
-    doc_links:
-      - manual:inst:mul:operation
-  - id: inst.mul.ill_exc_misa_M_disabled
-    name: Illegal instruction exception when misa.M is 0
-    description: |
-      An illegal instruction exception is raised when the instruction is executed
-      and `misa.M` is 0.
-    doc_links:
-      - manual:csr:misa:disabling-extension

data/.data/spec/std/isa/inst/Q/fsgnj.q.yaml

@@ -32,5 +32,5 @@ access:
 data_independent_timing: false
 pseudoinstructions:
   - when: (fs2 == fs1)
-    to: fmv.q fd,fs1
+    to: fmv.q fd, fs1
 operation(): |

data/.data/spec/std/isa/inst/S/sret.yaml

@@ -133,7 +133,7 @@ operation(): |
     CSR[mstatus].SPIE = 1;
     CSR[mstatus].SPP = 2'b00;
     $pc = $bits(CSR[sepc]);
-  } else {
+  } else if (implemented?(ExtensionName::H)) {
     if (CSR[mstatus].TSR == 1'b1) {
       raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
     }
@@ -141,4 +141,6 @@ operation(): |
     CSR[vsstatus].SIE = CSR[vsstatus].SPIE;
     CSR[vsstatus].SPIE = 1;
     $pc = $bits(CSR[vsepc]);
+  } else {
+    unreachable();
   }

data/.data/spec/std/isa/inst/V/vadc.vim.yaml

@@ -20,6 +20,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vadd.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vadd.vv.yaml

@@ -47,11 +47,7 @@ operation(): |
   for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
     U32 start_bit_pos = i * state.sew;
     U32 end_bit_pos = start_bit_pos + state.sew - 1;
-    v[vd] = {
-      v[vd][VLEN-1:end_bit_pos + 1],
-      (v[vs2])[end_bit_pos:start_bit_pos] + (v[vs1])[end_bit_pos:start_bit_pos],
-      v[vd][start_bit_pos-1:0]
-      };
+    V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] + V[vs1][end_bit_pos:start_bit_pos];
   }
 
   CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/V/vand.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vfsgnjn.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: vs2 == vs1
+    to: vfneg.v vd, vs2
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vfsgnjx.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: vs2 == vs1
+    to: vfabs.v vd, vs2
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vl1re8.v.yaml

@@ -25,5 +25,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vl1r.v vd, (xs1)
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vl2re8.v.yaml

@@ -25,5 +25,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vl2r.v vd, (xs1)
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vl4re8.v.yaml

@@ -25,5 +25,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vl4r.v vd, (xs1)
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vl8re8.v.yaml

@@ -25,5 +25,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vl8r.v vd, (xs1)
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vle8.v.yaml

@@ -31,13 +31,9 @@ data_independent_timing: false
 operation(): |
   XReg virtual_address = X[xs1];
   # "A simple in-order implementation can ignore the settings and simply execute all vector instructions using the undisturbed policy"
-  for (U32 i = 0; i < CSR[vl].VALUE; i++) {
-    U32 start_bit_pos = (CSR[vstart].VALUE + i) * 8;
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 start_bit_pos = i * 8;
     U32 end_bit_pos = start_bit_pos + 7;
-    v[vd] = {
-      v[vd][VLEN-1:end_bit_pos + 1],
-      sext(read_memory(8, virtual_address, $encoding), 8),
-      v[vd][start_bit_pos-1:0]
-    };
-    virtual_address = virtual_address + 1;
+    V[vd][end_bit_pos:start_bit_pos] = read_memory(8, virtual_address + i, $encoding)[7:0];
   }
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/V/vmadc.vi.yaml

@@ -20,6 +20,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmadc.vim.yaml

@@ -20,6 +20,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmand.mm.yaml

@@ -27,5 +27,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: vs2 == vs1
+    to: vmmv.m vd, vs2
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmerge.vim.yaml

@@ -20,6 +20,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmfle.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vmfge.vv vd, vs1, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmflt.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vmfgt.vv vd, vs1, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmnand.mm.yaml

@@ -27,5 +27,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: vs2 == vs1
+    to: vmnot.m vd, vs2
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmseq.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmsgt.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:
@@ -29,5 +30,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: imm < 5'b11111
+    to: vmsge.vi vd, vs2, imm+1, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmsgtu.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:
@@ -29,5 +30,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: imm < 5'b11111
+    to: vmsgeu.vi vd, vs2, imm+1, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmsle.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:
@@ -29,5 +30,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: imm < 5'b11111
+    to: vmslt.vi vd, vs2, imm+1, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmsle.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vmsge.vv vd, vs1, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:
@@ -29,5 +30,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: imm < 5'b11111
+    to: vmsltu.vi vd, vs2, imm+1, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmsleu.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vmsgeu.vv vd, vs1, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmslt.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vmsgt.vv vd, vs1, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmsltu.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vmsgtu.vv vd, vs1, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmsne.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmv.v.i.yaml

@@ -54,19 +54,8 @@ operation(): |
     U32 start_bit_pos = i * state.sew;
     U32 end_bit_pos = start_bit_pos + state.sew - 1;
 
-    # Write the sign-extended immediate (truncated to SEW bits) to the element,
-    # guarding against invalid bit-slice ranges at vector register boundaries
-    if (start_bit_pos == 0) {
-      if (end_bit_pos == VLEN - 1) {
-        v[vd] = sext_imm[state.sew-1:0];
-      } else {
-        v[vd] = {v[vd][VLEN-1:end_bit_pos + 1], sext_imm[state.sew-1:0]};
-      }
-    } else if (end_bit_pos == VLEN - 1) {
-      v[vd] = {sext_imm[state.sew-1:0], v[vd][start_bit_pos-1:0]};
-    } else {
-      v[vd] = {v[vd][VLEN-1:end_bit_pos + 1], sext_imm[state.sew-1:0], v[vd][start_bit_pos-1:0]};
-    }
+    # Write the sign-extended immediate (truncated to SEW bits) to the element
+    V[vd][end_bit_pos:start_bit_pos] = sext_imm[state.sew-1:0];
   }
 
   CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/V/vmv.x.s.yaml

@@ -34,6 +34,6 @@ operation(): |
   VectorState state = vector_state();
 
   # vmv.x.s copies element 0 of vs2 to xd, sign-extending to XLEN
-  X[xd] = $signed(v[vs2][state.sew-1:0]);
+  X[xd] = $signed(V[vs2][state.sew-1:0]);
 
   CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/V/vmxnor.mm.yaml

@@ -27,5 +27,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: (vs2 == vs1) && (vd == vs2)
+    to: vmset.m vd
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmxor.mm.yaml

@@ -27,5 +27,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: (vs2 == vs1) && (vd == vs2)
+    to: vmclr.m vd
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vnsrl.wx.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: xs1 == 0
+    to: vncvt.x.x.w vd, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vor.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vrsub.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vrsub.vx.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: xs1 == 0
+    to: vneg.v vd, vs2, vm
 data_independent_timing: true
 operation(): |

data/.data/spec/std/isa/inst/V/vsadd.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access: