udb 0.1.9 → 0.1.14

data/.data/spec/std/isa/inst/Zawrs/wrs.nto.yaml

@@ -73,5 +73,7 @@ operation(): |
     }
   }
 
-  # stall while the reservation set is valid and no interrupt is pending
-  wrs_nto();
+  if (!ZAWRS_NTO_IS_NOP) {
+    # stall while the reservation set is valid and no interrupt is pending
+    wrs_nto();
+  }

data/.data/spec/std/isa/inst/Zba/add.uw.yaml

@@ -16,17 +16,15 @@ definedBy:
     - extension:
         name: Zba
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: ADD.UW
-      value: 0b0000100
-    funct3:
-      display_name: ADD.UW
-      value: 0b000
-    opcode: { $inherits: inst_opcode/OP-32.yaml#/data }
+encoding:
+  match: 0000100----------000-----0111011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/Zbb/orc.b.yaml

@@ -35,7 +35,7 @@ operation(): |
   XReg input = X[xs1];
   XReg output = 0;
 
-  for (U32 i=0; i<(xlen() - 8); i = i+8) {
+  for (U32 i=0; i < xlen(); i = i+8) {
     output[(i+7):i] = (input[(i+7):i] == 0) ? 8'd0 : ~8'd0;
   }
 

data/.data/spec/std/isa/inst/Zbkb/brev8.yaml

@@ -25,14 +25,14 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   XReg input = X[xs1];
   XReg output = 0;
 
-  for(U32 i=0; i<(xlen()-8); i = i+8) {
+  for(U32 i=0; i < xlen(); i = i+8) {
     for(U32 j=0; j<8; j = j+1) {
-      output[(i*8)+(7-j)] = input[(i*8)+j];
+      output[i+(7-j)] = input[i+j];
     }
   }
 

data/.data/spec/std/isa/inst/Zbkb/packw.yaml

@@ -32,5 +32,5 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: (xs2 == 0x0)
-    to: zext.h xd,xs1
+    to: zext.h xd, xs1
 operation(): |

data/.data/spec/std/isa/inst/Zbkb/unzip.yaml

@@ -29,12 +29,12 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   XReg input = X[xs1];
   XReg output = 0;
 
-  for(U32 i=0; i<(xlen()/2-1); i = i+1) {
+  for(U32 i=0; i < (xlen()/2); i = i+1) {
     output[i] = input[2*i];
     output[i+xlen()/2] = input[2*i+1];
   }

data/.data/spec/std/isa/inst/Zbkb/zip.yaml

@@ -29,12 +29,12 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   XReg input = X[xs1];
   XReg output = 0;
 
-  for(U32 i=0; i<(xlen()/2-1); i = i+1){
+  for(U32 i=0; i < (xlen()/2); i = i+1){
     output[2*i] = input[i];
     output[2*i+1] = input[i+xlen()/2];
   }

data/.data/spec/std/isa/inst/Zbkx/xperm4.yaml

@@ -29,13 +29,13 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   XReg input1 = X[xs1];
   XReg input2 = X[xs2];
   XReg output = 0;
 
-  for(U32 i=0; i<(xlen()-4); i = i+4) {
+  for(U32 i=0; i < xlen(); i = i+4) {
     XReg index = input2[i+3:i];
     if(4*index < xlen()) {
       output[i+3:i] = input1[4*index+3:4*index];

data/.data/spec/std/isa/inst/Zbkx/xperm8.yaml

@@ -29,13 +29,13 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   XReg input1 = X[xs1];
   XReg input2 = X[xs2];
   XReg output = 0;
 
-  for(U32 i=0; i<(xlen()-8); i = i+8) {
+  for(U32 i=0; i < xlen(); i = i+8) {
     XReg index = input2[i+7:i];
     if(8*index < xlen()) {
       output[i+7:i] = input1[8*index+7:8*index];

data/.data/spec/std/isa/inst/Zcd/c.fld.yaml

@@ -38,4 +38,4 @@ operation(): |
 
   XReg virtual_address = X[creg2reg(xs1)] + imm;
 
-  f[fd] = sext(read_memory(64, virtual_address, $encoding), 64);
+  F[fd] = sext(read_memory(64, virtual_address, $encoding), 64);

data/.data/spec/std/isa/inst/Zcd/c.fldsp.yaml

@@ -39,4 +39,4 @@ operation(): |
 
   XReg virtual_address = X[2] + imm;
 
-  f[fd] = read_memory(64, virtual_address, $encoding);
+  F[fd] = read_memory(64, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zcd/c.fsdsp.yaml

@@ -39,4 +39,4 @@ operation(): |
 
   XReg virtual_address = X[2] + imm;
 
-  write_memory(64, virtual_address, f[fs2][63:0], $encoding);
+  write_memory(64, virtual_address, F[fs2][63:0], $encoding);

data/.data/spec/std/isa/inst/Zcf/c.flwsp.yaml

@@ -39,4 +39,4 @@ operation(): |
 
   XReg virtual_address = X[2] + imm;
 
-  f[fd] = read_memory(32, virtual_address, $encoding);
+  F[fd] = read_memory(32, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zcf/c.fswsp.yaml

@@ -39,4 +39,4 @@ operation(): |
 
   XReg virtual_address = X[2] + imm;
 
-  write_memory(32, virtual_address, f[fs2][31:0], $encoding);
+  write_memory(32, virtual_address, F[fs2][31:0], $encoding);

data/.data/spec/std/isa/inst/Zcmp/cm.pop.yaml

@@ -20,7 +20,7 @@ description: |
 definedBy:
   extension:
     name: Zcmp
-assembly: reg_list, stack_adj
+assembly: "{reg_list}, stack_adj"
 encoding:
   match: 10111010------10
   variables:

data/.data/spec/std/isa/inst/Zcmp/cm.popret.yaml

@@ -20,7 +20,7 @@ description: |
 definedBy:
   extension:
     name: Zcmp
-assembly: reg_list, stack_adj
+assembly: "{reg_list}, stack_adj"
 encoding:
   match: 10111110------10
   variables:

data/.data/spec/std/isa/inst/Zcmp/cm.popretz.yaml

@@ -20,7 +20,7 @@ description: |
 definedBy:
   extension:
     name: Zcmp
-assembly: reg_list, stack_adj
+assembly: "{reg_list}, stack_adj"
 encoding:
   match: 10111100------10
   variables:

data/.data/spec/std/isa/inst/Zcmp/cm.push.yaml

@@ -21,7 +21,7 @@ description: |
 definedBy:
   extension:
     name: Zcmp
-assembly: reg_list, -stack_adj
+assembly: "{reg_list}, -stack_adj"
 encoding:
   match: 10111000------10
   variables:
@@ -30,7 +30,6 @@ encoding:
       not: [0, 1, 2, 3]
     - name: spimm
       location: 3-2
-      left_shift: 4
 access:
   s: always
   u: always
@@ -45,7 +44,7 @@ operation(): |
   XReg nreg = (rlist == 15) ? 13 : (rlist - 3);
   XReg stack_aligned_adj = (nreg * 4 + 15) & ~0xF;
   XReg virtual_address_sp = X[2];
-  XReg virtual_address_new_sp = virtual_address_sp - stack_aligned_adj - spimm;
+  XReg virtual_address_new_sp = virtual_address_sp - stack_aligned_adj - spimm * 16;
   XReg virtual_address_base = virtual_address_sp - (nreg * size);
 
   write_memory_xlen_aligned(virtual_address_base +  0*size, X[ 1], $encoding);

data/.data/spec/std/isa/inst/Zfa/fround.s.yaml

@@ -37,5 +37,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = round_f32_to_integral(f[fs1], rounding_mode);
+  F[fd] = round_f32_to_integral(F[fs1], rounding_mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/Zfh/fcvt.h.s.yaml

@@ -39,7 +39,7 @@ access:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<16> hp_value = f[fs1][15:0];
+  Bits<16> hp_value = F[fs1][15:0];
 
   Bits<1> sign = hp_value[15];
   Bits<5> exp = hp_value[14:10];
@@ -50,22 +50,22 @@ operation(): |
       if ((hp_value & 0x0200) != 0) {
         set_fp_flag(FpFlag::NV);
       }
-      f[fd] = HP_CANONICAL_NAN;
+      F[fd] = HP_CANONICAL_NAN;
     } else {
-      f[fd] = packToF32UI(sign, 0xFF, 0);
+      F[fd] = packToF32UI(sign, 0xFF, 0);
     }
   } else {
     if (exp != 0) {
       if (frac != 0) {
-        f[fd] = packToF32UI(sign, 0, 0);
+        F[fd] = packToF32UI(sign, 0, 0);
       } else {
         Bits<6> norm_exp;
         (norm_exp, frac) = softfloat_normSubnormalF16Sig( frac );
         exp = norm_exp - 1;
-        f[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
+        F[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
       }
     } else {
-      f[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
+      F[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
     }
   }
 

data/.data/spec/std/isa/inst/Zfh/fcvt.s.h.yaml

@@ -36,7 +36,7 @@ access:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = f[fs1][31:0];
+  Bits<32> sp_value = F[fs1][31:0];
 
   Bits<1> sign = sp_value[31];
   Bits<8> exp = sp_value[30:23];
@@ -47,9 +47,9 @@ operation(): |
       if ((sp_value & 0x00400000) != 0) {
         set_fp_flag(FpFlag::NV);
       }
-      f[fd] = nan_box(16, FLEN, HP_CANONICAL_NAN);
+      F[fd] = nan_box(16, FLEN, HP_CANONICAL_NAN);
     } else {
-      f[fd] = nan_box(16, FLEN, packToF16UI( sign, 0x1F, 0 ));
+      F[fd] = nan_box(16, FLEN, packToF16UI( sign, 0x1F, 0 ));
     }
   } else {
 
@@ -58,10 +58,10 @@ operation(): |
     # is OR-red with the sticky
     Bits<16> frac16 = (frac >> 9) | ((frac & 0x1ff) != 0 ? 1 : 0);
     if ((exp | frac16) == 0) {
-      f[fd] = nan_box(16, FLEN, packToF16UI( sign, 0, 0 ));
+      F[fd] = nan_box(16, FLEN, packToF16UI( sign, 0, 0 ));
     } else {
       assert(false, "TODO: implement roundPackToF16");
-      # f[fd] = soffloat_roundPackToF16(sign, exp - 0x71, frac16 | 0x4000);
+      # F[fd] = soffloat_roundPackToF16(sign, exp - 0x71, frac16 | 0x4000);
     }
 
   }

data/.data/spec/std/isa/inst/Zfh/flh.yaml

@@ -39,6 +39,6 @@ operation(): |
 
   Bits<16> hp_value = read_memory(16, virtual_address, $encoding);
 
-  f[fd] = nan_box(16, FLEN, hp_value);
+  F[fd] = nan_box(16, FLEN, hp_value);
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml

@@ -33,6 +33,6 @@ operation(): |
 
   Bits<16> hp_value = X[xs1][15:0];
 
-  f[fd] = nan_box(16, FLEN, hp_value);
+  F[fd] = nan_box(16, FLEN, hp_value);
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/Zfh/fmv.x.h.yaml

@@ -35,4 +35,4 @@ access:
 operation(): |
   check_f_ok($encoding);
 
-  X[xd] = sext(f[fs1][15:0], 16);
+  X[xd] = sext(F[fs1][15:0], 16);

data/.data/spec/std/isa/inst/Zfh/fsh.yaml

@@ -40,6 +40,6 @@ operation(): |
 
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  Bits<16> hp_value = f[fs2][15:0];
+  Bits<16> hp_value = F[fs2][15:0];
 
   write_memory(16, virtual_address, hp_value, $encoding);

data/.data/spec/std/isa/inst/Zicbop/prefetch.i.yaml

@@ -21,6 +21,8 @@ encoding:
   variables:
     - name: imm
       location: 31-25
+      left_shift: 5
+      sign_extend: true
     - name: xs1
       location: 19-15
 access:

data/.data/spec/std/isa/inst/Zicbop/prefetch.r.yaml

@@ -21,6 +21,8 @@ encoding:
   variables:
     - name: imm
       location: 31-25
+      left_shift: 5
+      sign_extend: true
     - name: xs1
       location: 19-15
 access:

data/.data/spec/std/isa/inst/Zicbop/prefetch.w.yaml

@@ -21,6 +21,8 @@ encoding:
   variables:
     - name: imm
       location: 31-25
+      left_shift: 5
+      sign_extend: true
     - name: xs1
       location: 19-15
 access:

data/.data/spec/std/isa/inst/Zicsr/csrrc.yaml

@@ -41,7 +41,7 @@ access:
 data_independent_timing: false
 pseudoinstructions:
   - when: xd == 0
-    to: csrc csr,xs1
+    to: csrc csr, xs1
 operation(): |
   Csr csr_handle = direct_csr_lookup(csr);
 

data/.data/spec/std/isa/inst/Zicsr/csrrci.yaml

@@ -35,7 +35,7 @@ access:
 data_independent_timing: false
 pseudoinstructions:
   - when: xd == 0
-    to: csrci csr,imm
+    to: csrci csr, imm
 operation(): |
   Boolean will_write = imm != 0;
 

data/.data/spec/std/isa/inst/Zicsr/csrrs.yaml

@@ -54,9 +54,9 @@ pseudoinstructions:
   - when: xs1 == 0 && csr == 0xC82
     to: rdinstreth xd
   - when: xs1 == 0
-    to: csrr xd,csr
+    to: csrr xd, csr
   - when: xd == 0
-    to: csrs csr,xs1
+    to: csrs csr, xs1
 operation(): |
   Boolean will_write = xs1 != 0;
 

data/.data/spec/std/isa/inst/Zicsr/csrrsi.yaml

@@ -35,7 +35,7 @@ access:
 data_independent_timing: false
 pseudoinstructions:
   - when: xd == 0
-    to: csrsi csr,imm
+    to: csrsi csr, imm
 operation(): |
   Boolean will_write = imm != 0;
 

data/.data/spec/std/isa/inst/Zicsr/csrrw.yaml

@@ -35,7 +35,7 @@ access:
   vu: always
 pseudoinstructions:
   - when: xd == 0
-    to: csrw csr,xs1
+    to: csrw csr, xs1
 operation(): |
   Csr csr_handle = direct_csr_lookup(csr);
 

data/.data/spec/std/isa/inst/Zicsr/csrrwi.yaml

@@ -35,7 +35,7 @@ access:
   vu: always
 pseudoinstructions:
   - when: xd == 0
-    to: csrwi csr,imm
+    to: csrwi csr, imm
 operation(): |
   Csr csr_handle = direct_csr_lookup(csr);
 

data/.data/spec/std/isa/inst/Zks/sm3p0.yaml

@@ -25,5 +25,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |

data/.data/spec/std/isa/inst/Zks/sm3p1.yaml

@@ -25,5 +25,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |

data/.data/spec/std/isa/inst/Zks/sm4ed.yaml

@@ -29,5 +29,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |

data/.data/spec/std/isa/inst/Zks/sm4ks.yaml

@@ -29,5 +29,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |

data/.data/spec/std/isa/isa/builtin_functions.idl

@@ -280,6 +280,23 @@ builtin function ebreak {
   }
 }
 
+builtin function execute_instruction {
+  arguments
+    Bits<32> encoding
+  description {
+    Fetch and execute the instruction with the given 32-bit encoding in the current hart
+    context. The instruction executes as if it were a normal instruction, with the
+    following differences:
+
+    * The PC is not advanced after execution (the calling instruction is responsible
+      for PC management).
+    * If the instruction raises an exception, the exception propagates normally.
+
+    This builtin is intended for use by instructions that dynamically dispatch
+    sub-instructions fetched from memory (e.g., instruction lookup table instructions).
+  }
+}
+
 builtin function prefetch_instruction {
   arguments
     XReg virtual_address     # virtual cache block address
@@ -422,6 +439,7 @@ function read_physical_memory {
       return read_physical_memory_64(paddr);
     } else {
       assert(false, "Invalid len");
+      return 0;
     }
   }
 }

data/.data/spec/std/isa/isa/fp.idl

@@ -9,11 +9,7 @@
 # Files in berkely-softfloat-3 repository are licensed under BSD-3-clause.
 
 # floating point register file
-U32 FLEN = 64; # implemented?(ExtensionName::D) ? 7'd64 : 7'd32;
-Bits<FLEN> f[32] = [0, 0, 0, 0, 0, 0, 0, 0,
-                    0, 0, 0, 0, 0, 0, 0, 0,
-                    0, 0, 0, 0, 0, 0, 0, 0,
-                    0, 0, 0, 0, 0, 0, 0, 0];
+U32 FLEN = implemented?(ExtensionName::Q) ? 8'd128 : (implemented?(ExtensionName::D) ? 7'd64 : 7'd32);
 
 # FP constants
 Bits<32> SP_POS_INF       = 32'b0_11111111_00000000000000000000000;