udb 0.1.9 → 0.1.14

data/.data/spec/std/isa/csr/sstatus.yaml

@@ -44,6 +44,18 @@ fields:
 
     type: RO
     reset_value: 2
+  SPELP:
+    alias: mstatus.SPELP
+    location: 23
+    description: |
+      *Previous Expected Landing Pad state*
+
+      Alias of `mstatus.SPELP`.
+    type: RW-H
+    definedBy:
+      extension:
+        name: Zicfilp
+    reset_value: UNDEFINED_LEGAL
   MXR:
     alias: mstatus.MXR
     location: 19

data/.data/spec/std/isa/csr/vsstatus.yaml

@@ -60,6 +60,30 @@ fields:
       return ($array_size(VUXLEN) > 1) ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value(): |
       return ($array_size(VUXLEN) > 1) ? UNDEFINED_LEGAL : VUXLEN[0];
+  SPELP:
+    location: 23
+    long_name: VS-mode Previous Expected Landing Pad state
+    description: |
+      Holds the previous Expected Landing Pad (`ELP`) state when entering
+      VS-mode from a trap, and is restored to `ELP` on `SRET` from VS-mode.
+
+      Defined by the Zicfilp extension.
+
+      Per the privileged architecture, accesses to `sstatus.SPELP` resolve to
+      `mstatus.SPELP` when V=0, and to `vsstatus.SPELP` when V=1; the V=1
+      routing is handled by the H-extension CSR address remap (`virtual_address`
+      on this CSR), so this field is independent state — not an alias of
+      `mstatus.SPELP`.
+
+      Encoded as:
+
+      * 0 - `NO_LP_EXPECTED` - no landing pad instruction expected.
+      * 1 - `LP_EXPECTED` - a landing pad instruction is expected.
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    definedBy:
+      extension:
+        name: Zicfilp
   MXR:
     alias: mstatus.MXR
     location: 19

data/.data/spec/std/isa/ext/A.yaml

@@ -19,13 +19,11 @@ versions:
       - name: Unknown
         email: unknown@void.segfault
         company: Unknown
-    requirements:
-      extension:
-        allOf:
-          - name: Zaamo
-            version: "= 1.0.0"
-          - name: Zalrsc
-            version: "= 1.0.0"
+requirements:
+  extension:
+    allOf:
+      - name: Zaamo
+      - name: Zalrsc
 description: |
 
   The atomic-instruction extension, named `A`, contains

data/.data/spec/std/isa/ext/S.yaml

@@ -12,12 +12,24 @@ versions:
 - version: "1.11.0"
   state: ratified
   ratification_date: 2019-06
+  requirements:
+    extension:
+      name: Sm
+      version: "= 1.11"
 - version: "1.12.0"
   state: ratified
   ratification_date: 2021-12
+  requirements:
+    extension:
+      name: Sm
+      version: "= 1.12"
 - version: "1.13.0"
   state: ratified
   ratification_date: 2024-10
+  requirements:
+    extension:
+      name: Sm
+      version: "= 1.13"
 requirements:
   extension:
     name: U

data/.data/spec/std/isa/ext/Smpmpmt.yaml

@@ -0,0 +1,52 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: CC-BY-4.0
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Smpmpmt
+long_name: PMP-based Memory Types Extension
+description: |
+  The Smpmpmt extension provides a mechanism analogous to Svpbmt but associated
+  with the PMP registers rather than page-table entries.
+  A new WARL field, MT (Memory Type), is added in the unallocated bits 6--5 in
+  each PMP configuration register.
+  The MT field of the lowest-numbered PMP register that an access matches,
+  following the existing PMP address-matching rules, overrides the PMAs for
+  that access.
+  If an access matches no PMP registers, or if the MT field of the matching PMP
+  register contains the value PMA, then the access proceeds as though the
+  Smpmpmt extension were not implemented.
+
+  NOTE: The permissions checks associated with a PMP register are unrelated to
+  whether an access is considered to match a PMP register.
+  For example, even though a PMP register with its L bit clear does not enforce
+  its permissions checks on M-mode accesses, M-mode accesses within the
+  address range of that PMP register are still considered to match.
+  Hence, that PMP register's MT field takes effect for matching M-mode accesses.
+
+  The MT field is encoded as shown below.
+  The encoding is identical to that of the PBMT field, and the meaning of each
+  type is as specified by the Svpbmt extension.
+  Refer to that specification for the semantics of each type.
+
+  The MT field encoding is identical to Svpbmt's PBMT field:
+
+  * 0 (PMA): No override; use platform PMAs.
+  * 1 (NC): Non-cacheable, idempotent, weakly-ordered (RVWMO) main memory.
+  * 2 (IO): Non-cacheable, non-idempotent, strongly-ordered (I/O ordering) I/O.
+  * 3: Reserved for future standard use.
+
+  The PMP-based memory types compose with the page-based memory types as follows.
+  First, the PMP-based memory types override the PMAs, producing an intermediate
+  set of attributes.
+  Then, supervisor-level memory attributes (e.g. the page-based attributes
+  described in the Svpbmt specification) override the intermediate attributes to
+  produce a final set of attributes.
+  As with Svpbmt, it is implementation-defined whether PMP-based memory types
+  override additional PMAs not explicitly listed in the table above.
+type: privileged
+versions:
+  - version: "0.6"
+    state: frozen

data/.data/spec/std/isa/ext/Sv32.yaml

@@ -10,25 +10,13 @@ long_name: 32-bit virtual address translation (3 level)
 description: 32-bit virtual address translation (3 level)
 type: privileged
 versions:
-  - version: "1.11.0"
+  - version: "1.0"
     state: ratified
     ratification_date: 2019-05
-    requirements:
-      extension:
+requirements:
+  allOf:
+    - extension:
         name: S
-        version: ">= 1.11"
-  - version: "1.12.0"
-    state: ratified
-    ratification_date: 2021-12
-    url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf
-    requirements:
-      extension:
-        name: S
-        version: ">= 1.12"
-  - version: "1.13.0"
-    state: ratified
-    ratification_date: 2024-10
-    requirements:
-      extension:
-        name: S
-        version: ">= 1.13"
+    - param:
+        name: SXLEN
+        includes: 32

data/.data/spec/std/isa/ext/Sv39.yaml

@@ -10,25 +10,13 @@ long_name: 39-bit virtual address translation (3 level)
 description: 39-bit virtual address translation (3 level)
 type: privileged
 versions:
-  - version: "1.11.0"
+  - version: "1.0"
     state: ratified
     ratification_date: 2019-05
-    requirements:
-      extension:
+requirements:
+  allOf:
+    - extension:
         name: S
-        version: ">= 1.11"
-  - version: "1.12.0"
-    state: ratified
-    ratification_date: 2021-12
-    url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf
-    requirements:
-      extension:
-        name: S
-        version: ">= 1.12"
-  - version: "1.13.0"
-    state: ratified
-    ratification_date: 2024-10
-    requirements:
-      extension:
-        name: S
-        version: ">= 1.13"
+    - param:
+        name: SXLEN
+        includes: 64

data/.data/spec/std/isa/ext/Sv48.yaml

@@ -10,25 +10,9 @@ long_name: 48-bit virtual address translation (4 level)
 description: 48-bit virtual address translation (4 level)
 type: privileged
 versions:
-  - version: "1.11.0"
+  - version: "1.0"
     state: ratified
     ratification_date: 2019-05
-    requirements:
-      extension:
-        name: Sv39
-        version: ">= 1.11"
-  - version: "1.12.0"
-    state: ratified
-    ratification_date: 2021-12
-    url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf
-    requirements:
-      extension:
-        name: Sv39
-        version: ">= 1.12"
-  - version: "1.13.0"
-    state: ratified
-    ratification_date: 2024-10
-    requirements:
-      extension:
-        name: Sv39
-        version: ">= 1.13"
+requirements:
+  extension:
+    name: Sv39

data/.data/spec/std/isa/ext/Sv57.yaml

@@ -10,25 +10,9 @@ long_name: 57-bit virtual address translation (5 level)
 description: 57-bit virtual address translation (5 level)
 type: privileged
 versions:
-  - version: "1.11.0"
+  - version: "1.0"
     state: ratified
     ratification_date: unknown
-    requirements:
-      extension:
-        name: Sv48
-        version: ">= 1.11"
-  - version: "1.12.0"
-    state: ratified
-    ratification_date: 2021-12
-    url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf
-    requirements:
-      extension:
-        name: Sv48
-        version: ">= 1.12"
-  - version: "1.13.0"
-    state: ratified
-    ratification_date: 2024-10
-    requirements:
-      extension:
-        name: Sv48
-        version: ">= 1.13"
+requirements:
+  extension:
+    name: Sv48

data/.data/spec/std/isa/ext/Svukte.yaml

@@ -0,0 +1,71 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: CC-BY-4.0
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Svukte
+long_name: Address-Independent Latency of User-Mode Faults to Supervisor Addresses
+type: privileged
+description: |
+  == "Svukte" Extension for Address-Independent Latency of User-Mode Faults to Supervisor Addresses, Version 0.4
+
+  The Svukte extension provides a means to make user-mode accesses to supervisor
+  memory raise page faults with timing that is independent of the address-translation
+  configuration and page-table contents, thereby mitigating attacks that attempt
+  to discover the supervisor software's address-space layout.
+
+  If the Svukte extension is implemented, the `senvcfg`.UKTE field is writable.
+  If the hypervisor extension is additionally implemented, the `hstatus`.HUKTE
+  field is also writable.
+  See <<sec:senvcfg>> and <<sec:hstatus>> for the definitions of those fields.
+
+  The Svukte extension depends on the Sv39 extension.
+
+  [NOTE]
+  ====
+  Svukte is not defined for Sv32 because the small address space limits the
+  available entropy, reducing the effectiveness of address-space layout
+  randomization.
+  If an Sv32 variant were to be defined, it would need to account for the fact
+  that it is more common to reserve only the upper 1 GiB of the virtual-address
+  space for the operating system, leaving the lower 3 GiB for user
+  processes.
+  ====
+
+  When `senvcfg`.UKTE=1 and the active `satp` register's MODE field is not Bare,
+  an instruction fetch or explicit memory access whose
+  effective privilege mode is U or VU is considered to be _Svukte-qualified_.
+  For any Svukte-qualified memory access, virtual addresses >= 2^SXLEN-1^ are
+  considered to be invalid; hence, an Svukte-qualified access to such an address
+  raises a page-fault exception corresponding to the original access type.
+  The timing of an instruction that raises an exception for this reason must be
+  independent of the faulting virtual address.
+
+  [NOTE]
+  ====
+  An Svukte-qualified access to such an address raises an exception even
+  if the underlying PTE would have otherwise allowed the access.
+  Practical implementations of Svukte will raise these exceptions based upon the
+  effective address, without accessing the page tables or address-translation
+  caches.
+  ====
+
+  [NOTE]
+  ====
+  Since whether an instruction is Svukte-qualified depends on the _effective_
+  privilege mode of the access, even some instructions executed in HS-mode or M-mode
+  (e.g. HLV with `hstatus`.SPVP=0, or LW with `mstatus`.MPRV=1 and
+  `mstatus`.MPP=U) are Svukte-qualified.
+  ====
+
+  As described in <<sec:hstatus>>, the `hstatus`.HUKTE field, rather than the
+  `senvcfg`.UKTE field, determines whether HLV, HLVX, and HSV instructions
+  executed within U-mode are Svukte-qualified.
+versions:
+  - version: "0.4.0"
+    state: development
+requirements:
+  extension:
+    name: Sv39

data/.data/spec/std/isa/ext/Zawrs.yaml

@@ -20,6 +20,6 @@ description: |
     accelerator device indicating completion of a job previously submitted to the device.
 type: unprivileged
 versions:
-  - version: "1.0.1"
+  - version: "1.0.0"
     state: ratified
     ratification_date: 2022-11

data/.data/spec/std/isa/ext/Zihpm.yaml

@@ -13,15 +13,3 @@ versions:
   - version: "2.0.0"
     state: ratified
     ratification_date: 2023-03
-requirements:
-  idl(): |
-    -> (HPM_COUNTER_EN[3] || HPM_COUNTER_EN[4] || HPM_COUNTER_EN[5] ||
-        HPM_COUNTER_EN[6] || HPM_COUNTER_EN[7] || HPM_COUNTER_EN[8] ||
-        HPM_COUNTER_EN[9] || HPM_COUNTER_EN[10] || HPM_COUNTER_EN[11] ||
-        HPM_COUNTER_EN[12] || HPM_COUNTER_EN[13] || HPM_COUNTER_EN[14] ||
-        HPM_COUNTER_EN[15] || HPM_COUNTER_EN[16] || HPM_COUNTER_EN[17] ||
-        HPM_COUNTER_EN[18] || HPM_COUNTER_EN[19] || HPM_COUNTER_EN[20] ||
-        HPM_COUNTER_EN[21] || HPM_COUNTER_EN[22] || HPM_COUNTER_EN[23] ||
-        HPM_COUNTER_EN[24] || HPM_COUNTER_EN[25] || HPM_COUNTER_EN[26] ||
-        HPM_COUNTER_EN[27] || HPM_COUNTER_EN[28] || HPM_COUNTER_EN[29] ||
-        HPM_COUNTER_EN[30] || HPM_COUNTER_EN[31]);

data/.data/spec/std/isa/inst/B/andn.yaml

@@ -16,17 +16,15 @@ definedBy:
       - name: Zbb
       - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: ANDN
-      value: 0b0100000
-    funct3:
-      display_name: ANDN
-      value: 0b111
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0100000----------111-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always
@@ -38,4 +36,4 @@ operation(): |
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  X[xd] = X[xs2] & ~X[xs1];
+  X[xd] = X[xs1] & ~X[xs2];

data/.data/spec/std/isa/inst/B/clmul.yaml

@@ -15,17 +15,15 @@ definedBy:
       - name: Zbc
       - name: Zbkc
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: CLMUL
-      value: 0b0000101
-    funct3:
-      display_name: CLMUL
-      value: 0b001
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0000101----------001-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/B/clmulh.yaml

@@ -15,17 +15,15 @@ definedBy:
       - name: Zbc
       - name: Zbkc
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: CLMUL
-      value: 0b0000101
-    funct3:
-      display_name: CLMULH
-      value: 0b011
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0000101----------011-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/B/orn.yaml

@@ -15,17 +15,15 @@ definedBy:
       - name: Zbb
       - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: ORN
-      value: 0b0100000
-    funct3:
-      display_name: ORN
-      value: 0b110
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0100000----------110-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/B/rev8.yaml

@@ -54,7 +54,7 @@ operation(): |
 
   XReg j = xlen() - 1;
 
-  for (U32 i=0; i<(xlen()-8); i = i+8) {
+  for (U32 i=0; i < xlen(); i = i+8) {
     output[(i+7):i] = input[j:(j-7)];
     j = j - 8;
   }

data/.data/spec/std/isa/inst/B/rol.yaml

@@ -15,17 +15,15 @@ definedBy:
       - name: Zbb
       - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: ROL
-      value: 0b0110000
-    funct3:
-      display_name: ROL
-      value: 0b001
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0110000----------001-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/B/rolw.yaml

@@ -18,17 +18,15 @@ definedBy:
           - name: Zbb
           - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: ROLW
-      value: 0b0110000
-    funct3:
-      display_name: ROLW
-      value: 0b001
-    opcode: { $inherits: inst_opcode/OP-32.yaml#/data }
+encoding:
+  match: 0110000----------001-----0111011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/B/ror.yaml

@@ -15,17 +15,15 @@ definedBy:
       - name: Zbb
       - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: ROR
-      value: 0b0110000
-    funct3:
-      display_name: ROR
-      value: 0b101
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0110000----------101-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/B/rorw.yaml

@@ -19,17 +19,15 @@ definedBy:
           - name: Zbb
           - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: RORW
-      value: 0b0110000
-    funct3:
-      display_name: RORW
-      value: 0b101
-    opcode: { $inherits: inst_opcode/OP-32.yaml#/data }
+encoding:
+  match: 0110000----------101-----0111011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/B/xnor.yaml

@@ -15,17 +15,15 @@ definedBy:
       - name: Zbb
       - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: XNOR
-      value: 0b0100000
-    funct3:
-      display_name: XNOR
-      value: 0b100
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0100000----------100-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/C/c.addi.yaml

@@ -22,6 +22,7 @@ encoding:
     - name: imm
       location: 12|6-2
       not: 0
+      sign_extend: true
     - name: xd
       location: 11-7
       not: 0

data/.data/spec/std/isa/inst/C/c.addi16sp.yaml

@@ -23,6 +23,7 @@ encoding:
       location: 12|4-3|5|2|6
       left_shift: 4
       not: 0
+      sign_extend: true
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/C/c.addiw.yaml

@@ -23,6 +23,7 @@ encoding:
   variables:
     - name: imm
       location: 12|6-2
+      sign_extend: true
     - name: xd
       location: 11-7
       not: 0