udb 0.1.9 → 0.1.14

data/.data/spec/std/isa/isa/globals.isa

@@ -307,6 +307,7 @@ function compatible_mode? {
         (actual_mode == PrivilegeMode::VS) ||
         (actual_mode == PrivilegeMode::VU);
     }
+    return false;
   }
 }
 
@@ -327,8 +328,7 @@ function exception_handling_mode {
       } else {
         return PrivilegeMode::M;
       }
-    } else {
-      assert(implemented?(ExtensionName::H) && ((mode() == PrivilegeMode::VS) || (mode() == PrivilegeMode::VU)), "Unexpected mode");
+    } else if (implemented?(ExtensionName::H) && ((mode() == PrivilegeMode::VS) || (mode() == PrivilegeMode::VU)) ) {
       if (($bits(CSR[medeleg]) &  (MXLEN'1 << $bits(exception_code))) != 0) {
         if (($bits(CSR[hedeleg]) & (MXLEN'1 << $bits(exception_code))) != 0) {
           return PrivilegeMode::VS;
@@ -339,6 +339,8 @@ function exception_handling_mode {
         # if an exception is not delegated to HS-mode, it can't be delegated to VS-mode
         return PrivilegeMode::M;
       }
+    } else {
+      unreachable();
     }
   }
 }
@@ -717,7 +719,7 @@ function raise_precise {
       $pc = {CSR[mtvec].BASE, 2'b00};
       CSR[mcause].INT = 1'b0;
       CSR[mcause].CODE = $bits(exception_code);
-      if (CSR[misa].H == 1) {
+      if (implemented?(ExtensionName::H) && CSR[misa].H == 1) {
         # write zero into mtval2 and minst
         # (when these are non-zero values, raise_guest_page_fault should be callecd)
         CSR[mtval2].VALUE = 0;
@@ -1179,6 +1181,7 @@ function mpv {
       return (MXLEN == 32) ? CSR[mstatush].MPV : CSR[mstatus].MPV;
     } else {
       assert(false, "TODO");
+      unreachable();
     }
   }
 }
@@ -1196,13 +1199,13 @@ function effective_ldst_mode {
     if (mode() == PrivilegeMode::M) {
       if (CSR[misa].U == 1 && CSR[mstatus].MPRV == 1) {
         if (CSR[mstatus].MPP == 0b00) {
-          if (CSR[misa].H == 1 && mpv() == 0b1) {
+          if (implemented?(ExtensionName::H) && CSR[misa].H == 1 && mpv() == 0b1) {
             return PrivilegeMode::VU;
           } else {
             return PrivilegeMode::U;
           }
         } else if (CSR[misa].S == 1 && CSR[mstatus].MPP == 0b01) {
-          if (CSR[misa].H == 1 && mpv() == 0b1) {
+          if (implemented?(ExtensionName::H) && CSR[misa].H == 1 && mpv() == 0b1) {
             return PrivilegeMode::VS;
           } else {
             return PrivilegeMode::S;
@@ -1532,7 +1535,7 @@ function translate_gstage {
   body {
     TranslationResult result;
 
-    if (effective_mode == PrivilegeMode::S || effective_mode == PrivilegeMode::U) {
+    if (!implemented?(ExtensionName::H) || effective_mode == PrivilegeMode::S || effective_mode == PrivilegeMode::U) {
       # there is no gstage page walk
       result.paddr = gpaddr;
       return result;
@@ -1604,6 +1607,7 @@ function tinst_value_for_guest_page_fault {
           return tinst_transform(encoding, 0); # all guest page faults are aligned
         } else {
           unpredictable("Custom value written into htinst/mtinst");
+          return 0;
         }
       } else if (op == MemoryOperation::Write || op == MemoryOperation::ReadModifyWrite) {
         if (TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT == "always zero") {
@@ -1618,6 +1622,7 @@ function tinst_value_for_guest_page_fault {
           return tinst_transform(encoding, 0); # all guest page faults are aligned
         } else {
           unpredictable("Custom value written into htinst/mtinst");
+          return 0;
         }
       }
     } else {
@@ -1630,6 +1635,7 @@ function tinst_value_for_guest_page_fault {
         }
       }
     }
+    return 0;
   }
 }
 
@@ -1657,9 +1663,11 @@ function tinst_transform {
         return {encoding[31:20], addr_offset, encoding[14:0]};
       } else {
         assert(false, "Bad transform");
+        unreachable();
       }
     } else {
       assert(false, "TODO: compressed instruction");
+      unreachable();
     }
   }
 }
@@ -1674,7 +1682,7 @@ function transformed_standard_instruction_for_tinst {
   }
   body {
     assert(false, "TODO");
-    return 0;
+    unreachable();
   }
 }
 
@@ -1788,6 +1796,7 @@ function tinst_value {
       }
     } else {
       assert(false, "Unhandled exception type");
+      unreachable();
     }
   }
 }
@@ -1973,6 +1982,7 @@ function gstage_page_walk {
               success = atomic_check_then_write_64(pte_paddr, pte, updated_pte);
             } else {
               assert(false, "Unexpected PTESIZE");
+              unreachable();
             }
 
 
@@ -2023,6 +2033,7 @@ function gstage_page_walk {
         ppn = pte[PA_SIZE-3:10] << 12;
       }
     }
+    unreachable();
   }
 }
 
@@ -2297,6 +2308,7 @@ function stage1_page_walk {
               success = atomic_check_then_write_64(pte_phys.paddr, pte, updated_pte);
             } else {
               assert(false, "Unexpected PTESIZE");
+              unreachable();
             }
 
 
@@ -2369,6 +2381,7 @@ function stage1_page_walk {
         ppn = pte[PA_SIZE-3:10];
       }
     }
+    unreachable();
   }
 }
 
@@ -2450,6 +2463,7 @@ function translate {
       result = stage1_page_walk(57, 56, 64, 5, vaddr, op, effective_mode, encoding);
     } else {
       assert(false, "Unexpected SatpMode");
+      unreachable();
     }
 
     maybe_cache_translation(vaddr, op, result);
@@ -2495,6 +2509,7 @@ function canonical_vaddr? {
     } else if ((MXLEN == 64) && satp_mode == SatpMode::Sv57) {
       return eaddr[63:57] == {6{eaddr[56]}};
     }
+    return false;
   }
 }
 
@@ -2521,6 +2536,7 @@ function canonical_gpaddr? {
     } else if ((MXLEN > 32) && (satp_mode == SatpMode::Sv57)) {
       return gpaddr[63:57] == {6{gpaddr[56]}};
     }
+    return false;
   }
 }
 
@@ -2562,9 +2578,15 @@ function read_memory_aligned {
   arguments
     U32 LEN,
     XReg virtual_address,
-    Bits<INSTR_ENC_SIZE> encoding   # the encoding of an instruction causing this access
+    Bits<INSTR_ENC_SIZE> encoding,  # the encoding of an instruction causing this access
+    Bits<1> aq,                     # acquire semantics? 0=no, 1=yes
+    Bits<1> rl                      # release semantics? 0=no, 1=yes
   description {
     Read from virtual memory using a known aligned address.
+
+    If +rl+ is 1, then the load also acts as a memory model release (applied after all
+    checks pass but before the physical read).
+    If +aq+ is 1, then the load also acts as a memory model acquire (applied after the read).
   }
   body {
     TranslationResult result;
@@ -2578,7 +2600,17 @@ function read_memory_aligned {
     # may raise an exception
     access_check(result.paddr, LEN, virtual_address, MemoryOperation::Read, ExceptionCode::LoadAccessFault, effective_ldst_mode());
 
-    return read_physical_memory(LEN, result.paddr);
+    if (rl == 1'b1) {
+      memory_model_release();
+    }
+
+    XReg value = read_physical_memory(LEN, result.paddr);
+
+    if (aq == 1'b1) {
+      memory_model_acquire();
+    }
+
+    return value;
   }
 }
 
@@ -2597,7 +2629,7 @@ function read_memory {
     XReg physical_address;
 
     if (aligned) {
-      return read_memory_aligned(LEN, virtual_address, encoding);
+      return read_memory_aligned(LEN, virtual_address, encoding, 1'b0, 1'b0);
     }
 
     # access isn't naturally aligned, but it still might be atomic if this hart supports
@@ -2636,13 +2668,15 @@ function read_memory {
       if (MISALIGNED_SPLIT_STRATEGY == "sequential_bytes") {
         XReg result = 0;
         for (U32 I = 0; I < (LEN/8); I++) {
-          result = result | (read_memory_aligned(8, virtual_address + I, encoding) `<< (8*I));
+          result = result | (read_memory_aligned(8, virtual_address + I, encoding, 1'b0, 1'b0) `<< (8*I));
         }
         return result;
       } else if (MISALIGNED_SPLIT_STRATEGY == "custom") {
         unpredictable("An implementation is free to break a misaligned access any way, leading to unpredictable behavior when any part of the misaligned access causes an exception");
+        return 0;
       }
     }
+    return 0;
   }
 }
 
@@ -2759,6 +2793,7 @@ function register_reservation_set {
       unpredictable("Implementations may set reservation sets of any size, as long as they cover the reserved accessed");
     } else {
       assert(false, "Unexpected LRSC_RESERVATION_STRATEGY");
+      unreachable();
     }
   }
 }
@@ -2805,7 +2840,7 @@ function load_reserved {
       reservation_virtual_address = virtual_address;
     }
 
-    return read_memory_aligned(N, physical_address, encoding);
+    return read_memory_aligned(N, physical_address, encoding, 1'b0, 1'b0);
   }
 }
 
@@ -2915,12 +2950,14 @@ function amo {
     # PMA Atomicity checks
     if (pma_applies?(PmaAttribute::AmoNone, physical_address, N)) {
       raise(ExceptionCode::StoreAmoAccessFault, mode(), virtual_address);
-    } else if (((op == AmoOperation::Add || op == AmoOperation::Max || op == AmoOperation::Maxu || op == AmoOperation::Min || op == AmoOperation::Minu)) &&
-               !pma_applies?(PmaAttribute::AmoArithmetic, physical_address, N)) {
-      raise(ExceptionCode::StoreAmoAccessFault, mode(), virtual_address);
-    } else if (((op == AmoOperation::And || op == AmoOperation::Or || op == AmoOperation::Xor)) &&
-                !pma_applies?(PmaAttribute::AmoLogical, physical_address, N)) {
-      raise(ExceptionCode::StoreAmoAccessFault, mode(), virtual_address);
+    } else if (((op == AmoOperation::Add || op == AmoOperation::Max || op == AmoOperation::Maxu || op == AmoOperation::Min || op == AmoOperation::Minu))) {
+      if (!pma_applies?(PmaAttribute::AmoArithmetic, physical_address, N)) {
+        raise(ExceptionCode::StoreAmoAccessFault, mode(), virtual_address);
+      }
+    } else if (((op == AmoOperation::And || op == AmoOperation::Or || op == AmoOperation::Xor))) {
+      if (!pma_applies?(PmaAttribute::AmoLogical, physical_address, N)) {
+        raise(ExceptionCode::StoreAmoAccessFault, mode(), virtual_address);
+      }
     } else {
       assert(
         pma_applies?(PmaAttribute::AmoSwap, physical_address, N) &&
@@ -2951,9 +2988,15 @@ function write_memory_aligned {
     U32 LEN,
     XReg virtual_address,
     XReg value,
-    Bits<INSTR_ENC_SIZE> encoding # encoding of the instruction causing this access
+    Bits<INSTR_ENC_SIZE> encoding, # encoding of the instruction causing this access
+    Bits<1> aq,                    # acquire semantics? 0=no, 1=yes
+    Bits<1> rl                     # release semantics? 0=no, 1=yes
   description {
     Write to virtual memory using a known aligned address.
+
+    If +rl+ is 1, then the store also acts as a memory model release (applied after all
+    checks pass but before the physical write).
+    If +aq+ is 1, then the store also acts as a memory model acquire.
   }
   body {
     XReg physical_address;
@@ -2965,7 +3008,15 @@ function write_memory_aligned {
     # may raise an exception
     access_check(physical_address, LEN, virtual_address, MemoryOperation::Write, ExceptionCode::StoreAmoAccessFault, effective_ldst_mode());
 
+    if (rl == 1'b1) {
+      memory_model_release();
+    }
+
     write_physical_memory(LEN, physical_address, value);
+
+    if (aq == 1'b1) {
+      memory_model_acquire();
+    }
   }
 }
 
@@ -2983,7 +3034,7 @@ function write_memory {
     XReg physical_address;
 
     if (aligned) {
-      write_memory_aligned(LEN, virtual_address, value, encoding);
+      write_memory_aligned(LEN, virtual_address, value, encoding, 1'b0, 1'b0);
       return;
     }
 
@@ -3022,7 +3073,7 @@ function write_memory {
       # misaligned, must break into multiple reads
       if (MISALIGNED_SPLIT_STRATEGY == "sequential_bytes") {
         for (U32 I = 0; I < (LEN/8); I++) {
-          write_memory_aligned(8, virtual_address + I, (value >> (8*I))[7:0], encoding);
+          write_memory_aligned(8, virtual_address + I, (value >> (8*I))[7:0], encoding, 1'b0, 1'b0);
         }
       } else if (MISALIGNED_SPLIT_STRATEGY == "custom") {
         unpredictable("An implementation is free to break a misaligned access any way, leading to unpredictable behavior when any part of the misaligned access causes an exception");

data/.data/spec/std/isa/isa/interrupts.idl

@@ -259,6 +259,7 @@ function highest_priority_interrupt {
       }
     }
     assert(false, "There is no valid interrupt");
+    unreachable();
   }
 }
 

data/.data/spec/std/isa/isa/vec.idl

@@ -11,8 +11,7 @@
 #   - integer arith (vadd/vsub/vrsub(.vv,.vx,.vi), compare, min, max)
 #   - integer widening arith ()
 
-# the vector register file
-Bits<128> v[32];
+# the vector register file is populated by the symtab from V.yaml
 
 enum VectorLmulType {
   Divide

data/.data/spec/std/isa/manual_version/isa/20240411/isa_20240411.yaml

@@ -85,7 +85,7 @@ volumes:
       - { name: Zicond, version: "1.0.0" }
       - { name: M, version: "2.0.0" }
       - { name: A, version: "2.1.0" }
-      - { name: Zawrs, version: "1.0.1" }
+      - { name: Zawrs, version: "1.0" }
       - { name: Zacas, version: "1.0.0" }
       - { name: Zabha, version: "1.0.0" }
       # - { name: RVWMO, version: "2.0" }
@@ -207,10 +207,10 @@ volumes:
       - { name: Smcdeleg, version: "1.0.0" }
       - { name: S, version: "1.12.0" }
       - { name: Sm, version: "1.12.0" }
-      - { name: Sv32, version: "1.12.0" }
-      - { name: Sv39, version: "1.12.0" }
-      - { name: Sv48, version: "1.12.0" }
-      - { name: Sv57, version: "1.12.0" }
+      - { name: Sv32, version: "1.0" }
+      - { name: Sv39, version: "1.0" }
+      - { name: Sv48, version: "1.0" }
+      - { name: Sv57, version: "1.0" }
       - { name: Svnapot, version: "1.0.0" }
       - { name: Svpbmt, version: "1.0.0" }
       - { name: Svinval, version: "1.0.0" }

data/.data/spec/std/isa/param/COUNTINHIBIT_EN.yaml

@@ -26,5 +26,11 @@ schema:
   maxItems: 32
   minItems: 32
 definedBy:
-  extension:
-    name: Sm
+  allOf:
+    - extension:
+        name: Sm
+    - param:
+        name: MCOUNTINHIBIT_IMPLEMENTED
+        equal: true
+        reason: |
+          `COUNTINHIBIT_EN` only has effect when the `mcountinhibit` CSR is implemented.

data/.data/spec/std/isa/param/HSTATEEN_CONTEXT_TYPE.yaml

@@ -19,6 +19,7 @@ schema:
     - rw
     - read-only-0
     - read-only-1
+  default: rw
 requirements:
   idl(): |
     MSTATEEN_CONTEXT_TYPE == "read-only-0" -> HSTATEEN_CONTEXT_TYPE == "read-only-0";

data/.data/spec/std/isa/param/JVT_BASE_MASK.yaml

@@ -23,6 +23,6 @@ schema:
   maximum: 0x7ffffffffffffff # 58 bits
 requirements:
   idl(): |
-    MXLEN == 32 -> JVT_BASE_MASK < 0xffff_ffc0;
+    MXLEN == 32 -> JVT_BASE_MASK <= 0xffff_ffc0;
   reason: |
     Includes the implicitly-zero bits of jvt.BASE, so JVT_BASE_MASK[5:0] must always be 0.

data/.data/spec/std/isa/param/MCOUNTINHIBIT_IMPLEMENTED.yaml

@@ -0,0 +1,25 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: MCOUNTINHIBIT_IMPLEMENTED
+long_name: |
+  Whether or not the `mcountinhibit` CSR is implemented
+description: |
+  Options:
+
+    true::
+      The `mcountinhibit` CSR is implemented and can be accessed in M-mode.
+
+    false::
+      The `mcountinhibit` CSR is not implemented.
+      Accessing the CSR will cause an IllegalInstruction trap or enter an unpredictable state,
+      depending on TRAP_ON_UNIMPLEMENTED_CSR.
+schema:
+  type: boolean
+definedBy:
+  extension:
+    name: Sm

data/.data/spec/std/isa/param/MSTATEEN_CONTEXT_TYPE.yaml

@@ -19,6 +19,7 @@ schema:
     - rw
     - read-only-0
     - read-only-1
+  default: rw
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml

@@ -25,6 +25,7 @@ description: |
   the base, the minimum alignment cannot be less than 4.
 schema:
   description: An unsigned power of 2 greater than or equal to 4 that fits in 64 bits
+  default: 4
   enum:
     [
       4,

data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_VECTORED.yaml

@@ -25,6 +25,7 @@ description: |
   the base, the minimum alignment cannot be less than 4.
 schema:
   description: An unsigned power of 2 greater than or equal to 4 that fits in 64 bits
+  default: 4
   enum:
     [
       4,

data/.data/spec/std/isa/param/MTVEC_MODES.yaml

@@ -30,6 +30,13 @@ schema:
   maxItems: 2
   uniqueItems: true
 requirements:
-  idl(): |
-    (MTVEC_ACCESS == "ro") -> ($array_size(MTVEC_MODES) == 1);
-  reason: If `mtvec` is read-only, the mode cannot be changed.
+  # If `mtvec` is read-only, the mode cannot be changed.
+  if:
+    param:
+      name: MTVEC_ACCESS
+      equal: ro
+  then:
+    param:
+      name: MTVEC_MODES
+      size: true
+      equal: 1

data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml

@@ -7,36 +7,25 @@ $schema: param_schema.json#
 kind: parameter
 name: NUM_PMP_ENTRIES
 description: |
-  Number of implemented PMP entries. Can be any value between 0-64, inclusive.
+  Number of implemented PMP entries.
 
   The architecture mandates that the number of implemented PMP registers
-  must appear to be 0, 16, or 64.
-
-  Therefore, pmp registers will behave as follows according to NUN_PMP_ENTRIES:
-
-  [separator="!"]
-  !===
-  ! NUM_PMP_ENTRIES ! pmpaddr<0-15> / pmpcfg<0-3> ! pmpaddr<16-63> / pmpcfg<4-15>
-  ! 0               ! N                           ! N
-  ! 1-16            ! Y                           ! N
-  ! 17-64           ! Y                           ! Y
-  !===
-
-  ** N = Not implemented; access will cause `IllegalInstruction`
-     if TRAP_ON_UNIMPLEMENTED_CSR is true
-  ** Y = Implemented; access will not cause an exception (from M-mode), but register
-     may be read-only-zero if NUM_PMP_ENTRIES is less than the corresponding register
+  must appear to be 0, 16, or 64, so NUM_PMP_ENTRIES must be one of those values.
+  It directly determines which PMP registers exist: `pmpaddr0`-`pmpaddr<N-1>`
+  and their corresponding `pmpNcfg` fields are implemented, and the rest are
+  not. Accessing an unimplemented PMP register causes an `IllegalInstruction`
+  when TRAP_ON_UNIMPLEMENTED_CSR is true.
 
   [NOTE]
-  `pmpcfgN` for an odd N never exists when XLEN == 64
+  `pmpcfgN` for an odd N never exists when XLEN == 64.
 
-  When NUM_PMP_ENTRIES is not exactly 0, 16, or 64, some extant pmp registers,
-  and associated pmpNcfg, will be read-only zero (but will never cause an exception).
+  An implemented entry may still be read-only zero (but will never cause an exception).
+  The number of entries that are actually usable is given by
+  NUM_USABLE_PMP_ENTRIES.
 long_name: TODO
 schema:
   type: integer
-  minimum: 0
-  maximum: 64
+  enum: [0, 16, 64]
 definedBy:
   extension:
     name: Sm

data/.data/spec/std/isa/param/NUM_USABLE_PMP_ENTRIES.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: NUM_USABLE_PMP_ENTRIES
+description: |
+  Number of implemented PMP entries that are actually usable.
+
+  An implementation may implement PMP entries (NUM_PMP_ENTRIES) but hardwire
+  some of them to zero (read-only zero). Such entries exist -- their
+  `pmpaddrN`/`pmpNcfg` registers are accessible and will not cause an exception
+  from M-mode -- but they cannot be configured to guard a region.
+
+  NUM_USABLE_PMP_ENTRIES gives the number of low-numbered entries that are
+  writable/usable. Entries `0` through `NUM_USABLE_PMP_ENTRIES-1` are usable;
+  entries `NUM_USABLE_PMP_ENTRIES` through `NUM_PMP_ENTRIES-1` are read-only
+  zero.
+
+  Must be between 0 and NUM_PMP_ENTRIES, inclusive.
+long_name: TODO
+schema:
+  type: integer
+  minimum: 0
+  maximum: 64
+definedBy:
+  param:
+    name: NUM_PMP_ENTRIES
+    greaterThan: 0
+requirements:
+  idl(): |
+    NUM_PMP_ENTRIES == 16 -> NUM_USABLE_PMP_ENTRIES <= 16;
+  reason: Usable PMP entries cannot exceed the number of implemented PMP entries

data/.data/spec/std/isa/param/PMP_NA4_SUPPORTED.yaml

@@ -0,0 +1,23 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: PMP_NA4_SUPPORTED
+description: |
+  Whether or not the Naturally Aligned four-byte (NA4) PMP address matching
+  mode is supported.
+
+long_name: PMP NA4 mode supported
+schema:
+  type: boolean
+definedBy:
+  param:
+    name: NUM_PMP_ENTRIES
+    greaterThan: 0
+requirements:
+  idl(): |
+    PMP_NA4_SUPPORTED -> (PMP_GRANULARITY == 2);
+  reason: NA4 is not valid when the PMP granularity is larger than 4 bytes

data/.data/spec/std/isa/param/PMP_NAPOT_SUPPORTED.yaml

@@ -0,0 +1,19 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: PMP_NAPOT_SUPPORTED
+description: |
+  Whether or not the Naturally Aligned Power-Of-Two (NAPOT) PMP address
+  matching mode is supported.
+
+long_name: PMP NAPOT mode supported
+schema:
+  type: boolean
+definedBy:
+  param:
+    name: NUM_PMP_ENTRIES
+    greaterThan: 0

data/.data/spec/std/isa/param/{MSTATUS_TVM_IMPLEMENTED.yaml → PMP_TOR_SUPPORTED.yaml}

@@ -5,14 +5,14 @@
 
 $schema: param_schema.json#
 kind: parameter
-name: MSTATUS_TVM_IMPLEMENTED
+name: PMP_TOR_SUPPORTED
 description: |
-  Whether or not mstatus.TVM is implemented.
+  Whether or not the Top-of-Range (TOR) PMP address matching mode is supported.
 
-  When not implemented mstatus.TVM will be read-only-zero.
-long_name: TODO
+long_name: PMP TOR mode supported
 schema:
   type: boolean
 definedBy:
-  extension:
-    name: S
+  param:
+    name: NUM_PMP_ENTRIES
+    greaterThan: 0

data/.data/spec/std/isa/param/PRECISE_SYNCHRONOUS_EXCEPTIONS.yaml

@@ -15,3 +15,4 @@ description: |
   will cause execution to enter an unpredictable state.
 schema:
   type: boolean
+  default: true

data/.data/spec/std/isa/param/TRAP_ON_EBREAK.yaml

@@ -15,3 +15,4 @@ description: |
   without raising a trap, in which case the EEI must provide a builtin.
 schema:
   type: boolean
+  default: true

data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_M.yaml

@@ -15,3 +15,4 @@ description: |
   without raising a trap, in which case the EEI must provide a builtin.
 schema:
   type: boolean
+  default: true

data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml

@@ -20,6 +20,7 @@ description: |
 long_name: TODO
 schema:
   type: boolean
+  default: false
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/param/VLEN.yaml

@@ -11,6 +11,8 @@ description: |
 long_name: TODO
 schema:
   type: integer
+  minimum: 32
+  maximum: 65536
 #    requirements:
 #      idl(): |
 #        -> (VLEN >= ELEN) && (VLEN <='h10000) && (popcount(VLEN) == 1);