udb 0.1.9 → 0.1.14

data/.data/spec/std/isa/csr/I/pmpcfg9.yaml

@@ -36,23 +36,15 @@ fields:
       ! Name ! Location ! Description
 
       h! L ! 7   ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
-      h! - ! 6:5 ! _Reserved_ Writes shall be ignored.
+      h! MT ! 6:5 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry.  See the `Smpmpmt` extension definition for encodings.  When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
       h! A ! 4:3
-      a! Address matching mode. One of:
+      a! Address matching mode. Encodings:
 
-          [when="PMP_GRANULARITY < 2"]
           * *OFF* (0) - Null region (disabled)
           * *TOR* (1) - Top of range
           * *NA4* (2) - Naturally aligned four-byte region
           * *NAPOT* (3) - Naturally aligned power of two
 
-          [when="PMP_GRANULARITY >= 2"]
-          * *OFF* (0) - Null region (disabled)
-          * *TOR* (1) - Top of range
-          * *NAPOT* (3) - Naturally aligned power of two
-
-      [when="PMP_GRANULARITY >= 2"]
-      Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
 
       h! X ! 2 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
       h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -61,23 +53,28 @@ fields:
 
       The combination of R = 0, W = 1 is reserved.
     type(): |
-      if (NUM_PMP_ENTRIES > 36) {
+      if (NUM_USABLE_PMP_ENTRIES > 36) {
         return CsrFieldType::RWR;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if ((CSR[pmpcfg9].pmp36cfg & 0x80) == 0) {
-        # entry is not locked
-        if (!(((csr_value.pmp36cfg & 0x1) == 0) && ((csr_value.pmp36cfg & 0x2) == 0x2))) {
-          # not R = 0, W =1, which is reserved
-          if ((PMP_GRANULARITY < 2) ||
-              ((csr_value.pmp36cfg & 0x18) != 0x10)) {
-            # NA4 is not allowed when PMP granularity is larger than 4 bytes
-            return csr_value.pmp36cfg;
+      if (NUM_USABLE_PMP_ENTRIES > 36 && (CSR[pmpcfg9].pmp36cfg & 0x80) == 0) {
+        # entry is usable and not locked
+        Bits<8> new_cfg = csr_value.pmp36cfg;
+        Bits<2> a_mode = (new_cfg & 0x18) >> 3;
+        if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
+          # not R = 0, W = 1, which is reserved
+          if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
+              ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
+              ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
+            # unsupported address matching mode; keep old value
+            return CSR[pmpcfg9].pmp36cfg;
           }
+          return new_cfg;
         }
       }
       # fall through: keep old value
@@ -94,23 +91,15 @@ fields:
       ! Name ! Location ! Description
 
       h! L ! 15   ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
-      h! - ! 14:13 ! _Reserved_ Writes shall be ignored.
+      h! MT ! 14:13 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry.  See the `Smpmpmt` extension definition for encodings.  When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
       h! A ! 12:11
-      a! Address matching mode. One of:
+      a! Address matching mode. Encodings:
 
-          [when="PMP_GRANULARITY < 2"]
           * *OFF* (0) - Null region (disabled)
           * *TOR* (1) - Top of range
           * *NA4* (2) - Naturally aligned four-byte region
           * *NAPOT* (3) - Naturally aligned power of two
 
-          [when="PMP_GRANULARITY >= 2"]
-          * *OFF* (0) - Null region (disabled)
-          * *TOR* (1) - Top of range
-          * *NAPOT* (3) - Naturally aligned power of two
-
-      [when="PMP_GRANULARITY >= 2"]
-      Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
 
       h! X ! 10 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
       h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -119,23 +108,28 @@ fields:
 
       The combination of R = 0, W = 1 is reserved.
     type(): |
-      if (NUM_PMP_ENTRIES > 37) {
+      if (NUM_USABLE_PMP_ENTRIES > 37) {
         return CsrFieldType::RWR;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if ((CSR[pmpcfg9].pmp37cfg & 0x80) == 0) {
-        # entry is not locked
-        if (!(((csr_value.pmp37cfg & 0x1) == 0) && ((csr_value.pmp37cfg & 0x2) == 0x2))) {
-          # not R = 0, W =1, which is reserved
-          if ((PMP_GRANULARITY < 2) ||
-              ((csr_value.pmp37cfg & 0x18) != 0x10)) {
-            # NA4 is not allowed when PMP granularity is larger than 4 bytes
-            return csr_value.pmp37cfg;
+      if (NUM_USABLE_PMP_ENTRIES > 37 && (CSR[pmpcfg9].pmp37cfg & 0x80) == 0) {
+        # entry is usable and not locked
+        Bits<8> new_cfg = csr_value.pmp37cfg;
+        Bits<2> a_mode = (new_cfg & 0x18) >> 3;
+        if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
+          # not R = 0, W = 1, which is reserved
+          if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
+              ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
+              ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
+            # unsupported address matching mode; keep old value
+            return CSR[pmpcfg9].pmp37cfg;
           }
+          return new_cfg;
         }
       }
       # fall through: keep old value
@@ -152,23 +146,15 @@ fields:
       ! Name ! Location ! Description
 
       h! L ! 23   ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
-      h! - ! 22:21 ! _Reserved_ Writes shall be ignored.
+      h! MT ! 22:21 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry.  See the `Smpmpmt` extension definition for encodings.  When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
       h! A ! 20:19
-      a! Address matching mode. One of:
+      a! Address matching mode. Encodings:
 
-          [when="PMP_GRANULARITY < 2"]
           * *OFF* (0) - Null region (disabled)
           * *TOR* (1) - Top of range
           * *NA4* (2) - Naturally aligned four-byte region
           * *NAPOT* (3) - Naturally aligned power of two
 
-          [when="PMP_GRANULARITY >= 2"]
-          * *OFF* (0) - Null region (disabled)
-          * *TOR* (1) - Top of range
-          * *NAPOT* (3) - Naturally aligned power of two
-
-      [when="PMP_GRANULARITY >= 2"]
-      Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
 
       h! X ! 18 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
       h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -177,23 +163,28 @@ fields:
 
       The combination of R = 0, W = 1 is reserved.
     type(): |
-      if (NUM_PMP_ENTRIES > 38) {
+      if (NUM_USABLE_PMP_ENTRIES > 38) {
         return CsrFieldType::RWR;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if ((CSR[pmpcfg9].pmp38cfg & 0x80) == 0) {
-        # entry is not locked
-        if (!(((csr_value.pmp38cfg & 0x1) == 0) && ((csr_value.pmp38cfg & 0x2) == 0x2))) {
-          # not R = 0, W =1, which is reserved
-          if ((PMP_GRANULARITY < 2) ||
-              ((csr_value.pmp38cfg & 0x18) != 0x10)) {
-            # NA4 is not allowed when PMP granularity is larger than 4 bytes
-            return csr_value.pmp38cfg;
+      if (NUM_USABLE_PMP_ENTRIES > 38 && (CSR[pmpcfg9].pmp38cfg & 0x80) == 0) {
+        # entry is usable and not locked
+        Bits<8> new_cfg = csr_value.pmp38cfg;
+        Bits<2> a_mode = (new_cfg & 0x18) >> 3;
+        if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
+          # not R = 0, W = 1, which is reserved
+          if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
+              ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
+              ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
+            # unsupported address matching mode; keep old value
+            return CSR[pmpcfg9].pmp38cfg;
           }
+          return new_cfg;
         }
       }
       # fall through: keep old value
@@ -210,23 +201,15 @@ fields:
       ! Name ! Location ! Description
 
       h! L ! 31   ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
-      h! - ! 30:29 ! _Reserved_ Writes shall be ignored.
+      h! MT ! 30:29 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry.  See the `Smpmpmt` extension definition for encodings.  When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
       h! A ! 28:27
-      a! Address matching mode. One of:
+      a! Address matching mode. Encodings:
 
-          [when="PMP_GRANULARITY < 2"]
           * *OFF* (0) - Null region (disabled)
           * *TOR* (1) - Top of range
           * *NA4* (2) - Naturally aligned four-byte region
           * *NAPOT* (3) - Naturally aligned power of two
 
-          [when="PMP_GRANULARITY >= 2"]
-          * *OFF* (0) - Null region (disabled)
-          * *TOR* (1) - Top of range
-          * *NAPOT* (3) - Naturally aligned power of two
-
-      [when="PMP_GRANULARITY >= 2"]
-      Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
 
       h! X ! 26 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
       h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -235,23 +218,28 @@ fields:
 
       The combination of R = 0, W = 1 is reserved.
     type(): |
-      if (NUM_PMP_ENTRIES > 39) {
+      if (NUM_USABLE_PMP_ENTRIES > 39) {
         return CsrFieldType::RWR;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if ((CSR[pmpcfg9].pmp39cfg & 0x80) == 0) {
-        # entry is not locked
-        if (!(((csr_value.pmp39cfg & 0x1) == 0) && ((csr_value.pmp39cfg & 0x2) == 0x2))) {
-          # not R = 0, W =1, which is reserved
-          if ((PMP_GRANULARITY < 2) ||
-              ((csr_value.pmp39cfg & 0x18) != 0x10)) {
-            # NA4 is not allowed when PMP granularity is larger than 4 bytes
-            return csr_value.pmp39cfg;
+      if (NUM_USABLE_PMP_ENTRIES > 39 && (CSR[pmpcfg9].pmp39cfg & 0x80) == 0) {
+        # entry is usable and not locked
+        Bits<8> new_cfg = csr_value.pmp39cfg;
+        Bits<2> a_mode = (new_cfg & 0x18) >> 3;
+        if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
+          # not R = 0, W = 1, which is reserved
+          if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
+              ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
+              ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
+            # unsupported address matching mode; keep old value
+            return CSR[pmpcfg9].pmp39cfg;
           }
+          return new_cfg;
         }
       }
       # fall through: keep old value

data/.data/spec/std/isa/csr/I/pmpcfgN.layout

@@ -48,23 +48,15 @@ fields:
       ! Name ! Location ! Description
 
       h! L ! <%= ((i+1)*8)-1 %>   ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
-      h! - ! <%= ((i+1)*8)-2 %>:<%= ((i+1)*8)-3 %> ! _Reserved_ Writes shall be ignored.
+      h! MT ! <%= ((i+1)*8)-2 %>:<%= ((i+1)*8)-3 %> ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry.  See the `Smpmpmt` extension definition for encodings.  When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
       h! A ! <%= ((i+1)*8)-4 %>:<%= ((i+1)*8)-5 %>
-      a! Address matching mode. One of:
+      a! Address matching mode. Encodings:
 
-          [when="PMP_GRANULARITY < 2"]
           * *OFF* (0) - Null region (disabled)
           * *TOR* (1) - Top of range
           * *NA4* (2) - Naturally aligned four-byte region
           * *NAPOT* (3) - Naturally aligned power of two
 
-          [when="PMP_GRANULARITY >= 2"]
-          * *OFF* (0) - Null region (disabled)
-          * *TOR* (1) - Top of range
-          * *NAPOT* (3) - Naturally aligned power of two
-
-      [when="PMP_GRANULARITY >= 2"]
-      Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
 
       h! X ! <%= ((i)*8)+2 %> ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
       h! W ! <%= ((i)*8)+1 %> ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -73,23 +65,28 @@ fields:
 
       The combination of R = 0, W = 1 is reserved.
     type(): |
-      if (NUM_PMP_ENTRIES > <%= pmpcfg_num*4 + i %>) {
+      if (NUM_USABLE_PMP_ENTRIES > <%= pmpcfg_num*4 + i %>) {
         return CsrFieldType::RWR;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if (<%- if i > 4 -%>(xlen() == 64) && <%- end -%>(CSR[<%= "pmpcfg#{pmpcfg_num}" %>].pmp<%= pmpcfg_num*4 + i %>cfg & 0x80) == 0) {
-        # entry is not locked
-        if (!(((csr_value.pmp<%= pmpcfg_num*4 + i %>cfg & 0x1) == 0) && ((csr_value.pmp<%= pmpcfg_num*4 + i %>cfg & 0x2) == 0x2))) {
-          # not R = 0, W =1, which is reserved
-          if ((PMP_GRANULARITY < 2) ||
-              ((csr_value.pmp<%= pmpcfg_num*4 + i %>cfg & 0x18) != 0x10)) {
-            # NA4 is not allowed when PMP granularity is larger than 4 bytes
-            return csr_value.pmp<%= pmpcfg_num*4 + i %>cfg;
+      if (<%- if i > 4 -%>(xlen() == 64) && <%- end -%>NUM_USABLE_PMP_ENTRIES > <%= pmpcfg_num*4 + i %> && (CSR[<%= "pmpcfg#{pmpcfg_num}" %>].pmp<%= pmpcfg_num*4 + i %>cfg & 0x80) == 0) {
+        # entry is usable and not locked
+        Bits<8> new_cfg = csr_value.pmp<%= pmpcfg_num*4 + i %>cfg;
+        Bits<2> a_mode = (new_cfg & 0x18) >> 3;
+        if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
+          # not R = 0, W = 1, which is reserved
+          if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
+              ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
+              ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
+            # unsupported address matching mode; keep old value
+            return CSR[<%= "pmpcfg#{pmpcfg_num}" %>].pmp<%= pmpcfg_num*4 + i %>cfg;
           }
+          return new_cfg;
         }
       }
       # fall through: keep old value

data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.layout

@@ -44,8 +44,12 @@ description: |
   ====
 
 definedBy:
-  extension:
-    name: Sm
+  allOf:
+    - extension:
+        name: Sm
+    - param:
+        name: MCOUNTINHIBIT_IMPLEMENTED
+        equal: true
 fields:
   CY:
     location: 0

data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.yaml

@@ -47,8 +47,12 @@ description: |
   ====
 
 definedBy:
-  extension:
-    name: Sm
+  allOf:
+    - extension:
+        name: Sm
+    - param:
+        name: MCOUNTINHIBIT_IMPLEMENTED
+        equal: true
 fields:
   CY:
     location: 0

data/.data/spec/std/isa/csr/hstatus.yaml

@@ -73,6 +73,22 @@ fields:
       } else {
         return csr_value.VSXL;
       }
+  HUKTE:
+    location: 24
+    long_name: Hypervisor UKTE
+    description: |
+      If the Svukte extension is implemented, the HUKTE field determines
+      whether the HLV, HLVX, and HSV instructions, when executed in U-mode,
+      are Svukte-qualified.
+      When one of these instructions is executed in U-mode, it behaves as though
+      `senvcfg`.UKTE were set to the value of HUKTE.
+      If Svukte is not implemented, HUKTE is read-only zero.
+
+    definedBy:
+      extension:
+        name: Svukte
+    type: RW
+    reset_value: UNDEFINED_LEGAL
   VTSR:
     location: 22
     long_name: Virtual Trap SRET

data/.data/spec/std/isa/csr/jvt.yaml

@@ -56,6 +56,7 @@ fields:
             && (CSR[sstateen0].JVT == 1'b0 || CSR[hstateen0].JVT == 1'b0) )) {
 
         unimplemented_csr($encoding);
+        return 0;
       }
       else {
         if (JVT_BASE_TYPE == "custom") {

data/.data/spec/std/isa/csr/mcycleh.yaml

@@ -11,7 +11,7 @@ definedBy:
   allOf:
     - xlen: 32
     - extension:
-        name: Zicntr
+        name: Sm
 address: 0xB80
 writable: true
 description: |

data/.data/spec/std/isa/csr/menvcfg.yaml

@@ -296,6 +296,26 @@ fields:
         name: Zicfiss
     type: RW
     reset_value: UNDEFINED_LEGAL
+  LPE:
+    location: 2
+    description: |
+      *Landing Pad Enable*
+
+      When the LPE field is set to 1 and S-mode is implemented, the Zicfilp
+      extension is enabled in S-mode. If the LPE field is set to 1 and S-mode
+      is not implemented, the Zicfilp extension is enabled in U-mode. When the
+      LPE field is 0, the Zicfilp extension is not enabled in S-mode (or U-mode
+      if S-mode is not implemented), and the following rules apply:
+
+        * The hart does not update the `ELP` state; it remains as `NO_LP_EXPECTED`.
+        * The `LPAD` instruction operates as a no-op.
+
+      When `menvcfg.LPE` is 0, `henvcfg.LPE` and `senvcfg.LPE` are read-only zero.
+    definedBy:
+      extension:
+        name: Zicfilp
+    type: RW
+    reset_value: UNDEFINED_LEGAL
   FIOM:
     location: 0
     description: |

data/.data/spec/std/isa/csr/misa.yaml

@@ -165,12 +165,6 @@ fields:
     definedBy:
       extension:
         name: M
-    cert_normative_rules:
-      - id: csr_field.misa.M.disabled
-        name: Disabling `misa.M` bit
-        description: What happens when you turn off `misa.M`
-        doc_links:
-          - manual:csr:misa:disabling-extension
   Q:
     location: 16
     description: |
@@ -251,9 +245,3 @@ sw_read(): |
     (CSR[misa].C `<< 2) |
     (CSR[misa].B `<< 1) |
     CSR[misa].A);
-cert_normative_rules:
-  - id: csr.misa.disabling_bits
-    name: Disabling `misa` bits
-    description: What happens when you turn off bits
-    doc_links:
-      - manual:csr:misa:disabling-extension

data/.data/spec/std/isa/csr/mstatus.yaml

@@ -72,6 +72,26 @@ fields:
             name: Smdbltrp
     type: RW-H
     reset_value: UNDEFINED_LEGAL
+  MPELP:
+    location: 41
+    long_name: M-mode Previous Expected Landing Pad state
+    description: |
+      Holds the previous Expected Landing Pad (`ELP`) state when entering
+      M-mode from a trap, and is restored to `ELP` on `MRET`.
+
+      Defined by the Zicfilp extension.
+
+      Encoded as:
+
+      * 0 - `NO_LP_EXPECTED` - no landing pad instruction expected.
+      * 1 - `LP_EXPECTED` - a landing pad instruction is expected.
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    definedBy:
+      allOf:
+        - xlen: 64
+        - extension:
+            name: Zicfilp
   MPV:
     location: 39
     long_name: Machine Previous Virtualization mode
@@ -245,6 +265,24 @@ fields:
         return 2;
       }
 
+  SPELP:
+    location: 23
+    long_name: S-mode Previous Expected Landing Pad state
+    description: |
+      Holds the previous Expected Landing Pad (`ELP`) state when entering
+      (H)S-mode from a trap, and is restored to `ELP` on `SRET`.
+
+      Defined by the Zicfilp extension.
+
+      Encoded as:
+
+      * 0 - `NO_LP_EXPECTED` - no landing pad instruction expected.
+      * 1 - `LP_EXPECTED` - a landing pad instruction is expected.
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    definedBy:
+      extension:
+        name: Zicfilp
   TSR:
     location: 22
     long_name: Trap SRET
@@ -290,6 +328,8 @@ fields:
     type(): |
       if (CSR[misa].S == 1'b0) {
         return CsrFieldType::RO;
+      } else if (!(implemented?(ExtensionName::Sv32) || implemented?(ExtensionName::Sv39) || implemented?(ExtensionName::Sv48) || implemented?(ExtensionName::Sv57))) {
+        return CsrFieldType::RO;
       } else {
         return CsrFieldType::RW;
       }
@@ -299,18 +339,18 @@ fields:
     reset_value(): |
       if (CSR[misa].S == 1'b0) {
         return 0;
-      } else if (MSTATUS_TVM_IMPLEMENTED) {
-        return UNDEFINED_LEGAL;
-      } else {
+      } else if (!(implemented?(ExtensionName::Sv32) || implemented?(ExtensionName::Sv39) || implemented?(ExtensionName::Sv48) || implemented?(ExtensionName::Sv57))) {
         return 0;
+      } else {
+        return UNDEFINED_LEGAL;
       }
     sw_write(csr_value): |
       if (CSR[misa].S == 1'b0) {
         return 0;
-      } else if (MSTATUS_TVM_IMPLEMENTED) {
-        return csr_value.TVM;
-      } else {
+      } else if (!(implemented?(ExtensionName::Sv32) || implemented?(ExtensionName::Sv39) || implemented?(ExtensionName::Sv48) || implemented?(ExtensionName::Sv57))) {
         return 0;
+      } else {
+        return csr_value.TVM;
       }
   MXR:
     location: 19

data/.data/spec/std/isa/csr/mstatush.yaml

@@ -24,39 +24,40 @@ fields:
   MDT:
     location: 10
     description: |
-      *Machine Disable Trap*
-
-      Written to 1 when entering M-mode from an exception/interrupt.
-      When returning via an MRET instruction, the bit is written to 0.
-      On reset in set to 1, and software should write it to 0 when boot sequence is done.
-      When mstatush.MDT=1, direct write by CSR instruction cannot set mstatus.MIE to 1.
+      see `mstatus.MDT`
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    alias: mstatus.MDT
     definedBy:
       extension:
         name: Smdbltrp
+  MPELP:
+    location: 9
+    description: |
+      see `mstatus.MPELP`
     type: RW-H
     reset_value: UNDEFINED_LEGAL
+    alias: mstatus.MPELP
+    definedBy:
+      extension:
+        name: Zicfilp
   MPV:
     location: 7
     description: |
-      *Machine Previous Virtualization mode*
-
-      Written with the prior virtualization mode when entering M-mode from an exception/interrupt.
-      When returning via an MRET instruction, the virtualization mode becomes the value of MPV unless MPP=3, in which case the virtualization mode is always 0.
-      Can also be written by software.
+      see `mstatus.MPV`
     type: RW-H
     reset_value: UNDEFINED_LEGAL
+    alias: mstatus.MPV
     definedBy:
       extension:
         name: H
   GVA:
     location: 6
     description: |
-      *Guest Virtual Address*
-
-      When a trap is taken and a guest virtual address is written into mtval, GVA is set.
-      When a trap is taken and a guest virtual address is written into mtval, GVA is cleared.
+      see `mstatus.GVA`
     type: RW-H
     reset_value: 0
+    alias: mstatus.GVA
     definedBy:
       extension:
         name: H
@@ -86,3 +87,4 @@ fields:
       } else {
         return UNDEFINED_LEGAL;
       }
+    alias: mstatus.SBE

data/.data/spec/std/isa/csr/senvcfg.yaml

@@ -124,6 +124,22 @@ fields:
         return UNDEFINED_LEGAL_DETERMINISTIC;
       }
     reset_value: UNDEFINED_LEGAL
+  UKTE:
+    location: 8
+    description: |
+      If the Svukte extension is implemented, the UKTE field affects the behavior of
+      instruction fetches and explicit memory accesses.
+      When UKTE=0, instruction fetches and explicit memory accesses proceed as
+      though the Svukte extension were not implemented.
+      When UKTE=1, instruction fetches and explicit memory accesses with effective
+      privilege mode U or VU are Svukte-qualified, as described in <<sec:svukte>>.
+      If Svukte is not implemented, UKTE is read-only zero.
+
+    definedBy:
+      extension:
+        name: Svukte
+    type: RW
+    reset_value: UNDEFINED_LEGAL
   SSE:
     location: 3
     description: |
@@ -149,6 +165,28 @@ fields:
         return 0;
       }
       return csr_value.SSE;
+  LPE:
+    location: 2
+    description: |
+      *Landing Pad Enable*
+
+      When the LPE field is set to 1 and `menvcfg.LPE` is 1, the Zicfilp extension
+      is enabled in U/VU-mode. Read-only zero when `menvcfg.LPE` is 0. When the LPE
+      field is 0, the Zicfilp extension is not enabled in U/VU-mode and the following
+      rules apply:
+
+        * The hart does not update the `ELP` state; it remains as `NO_LP_EXPECTED`.
+        * The `LPAD` instruction operates as a no-op.
+    definedBy:
+      extension:
+        name: Zicfilp
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (CSR[menvcfg].LPE == 0) {
+        return 0;
+      }
+      return csr_value.LPE;
   FIOM:
     location: 0
     description: |
@@ -186,4 +224,8 @@ sw_read(): |
     # senvcfg.SSE must read-as-zero
     value = value & ~(1 `<< 3);
   }
+  if (implemented?(ExtensionName::Zicfilp) && CSR[menvcfg].LPE == 0) {
+    # senvcfg.LPE must read-as-zero when menvcfg.LPE is 0
+    value = value & ~(1 `<< 2);
+  }
   return value;