udb 0.1.9 → 0.1.14

data/.data/spec/std/isa/inst/C/c.andi.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 12|6-2
+      sign_extend: true
     - name: xd
       location: 9-7
 access:

data/.data/spec/std/isa/inst/C/c.ldsp.yaml

@@ -34,7 +34,7 @@ encoding:
         left_shift: 3
       - name: xd
         location: 11-7
-        not: [0, 1, 3, 5, 7]
+        not: [0, 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
   RV64:
     match: 011-----------10
     variables:
@@ -57,8 +57,8 @@ operation(): |
   Bits<64> value = read_memory(64, virtual_address, $encoding);
 
   if (xlen()== 64) {
-    X[creg2reg(xd)] = value;
+    X[xd] = value;
   } else if (xlen() == 32) {
-    X[creg2reg(xd)]     = value[31:0];
-    X[creg2reg(xd) + 1] = value[63:32];
+    X[xd]     = value[31:0];
+    X[xd + 1] = value[63:32];
   }

data/.data/spec/std/isa/inst/C/c.li.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 12|6-2
+      sign_extend: true
     - name: xd
       location: 11-7
       not: 0

data/.data/spec/std/isa/inst/C/c.lui.yaml

@@ -22,6 +22,7 @@ encoding:
     - name: imm
       location: 12|6-2
       left_shift: 12
+      sign_extend: true
     - name: xd
       location: 11-7
       not: [0, 2]

data/.data/spec/std/isa/inst/C/c.mv.yaml

@@ -9,7 +9,7 @@ name: c.mv
 long_name: Move Register
 description: |
   C.MV (move register) performs copy of the data in register xs2 to register xd
-  C.MV expands to addi xd, x0, xs2.
+  C.MV expands to add xd, x0, xs2.
 definedBy:
   extension:
     name: Zca

data/.data/spec/std/isa/inst/C/c.sdsp.yaml

@@ -27,7 +27,7 @@ encoding:
     variables:
       - name: xs2
         location: 6-2
-        not: [1, 3, 5, 7]
+        not: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
       - name: imm
         location: 9-7|12-10
         left_shift: 3

data/.data/spec/std/isa/inst/D/fsgnj.d.yaml

@@ -27,6 +27,9 @@ encoding:
       location: 19-15
     - name: fd
       location: 11-7
+pseudoinstructions:
+  - when: fs1 == fs2
+    to: fmv.d fd, fs1
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/D/fsgnjn.d.yaml

@@ -32,5 +32,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: fs1 == fs2
+    to: fneg.d fd, fs1
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/D/fsgnjx.d.yaml

@@ -32,5 +32,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: fs1 == fs2
+    to: fabs.d fd, fs1
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/F/fadd.s.yaml

@@ -34,19 +34,19 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  Bits<32> a = f[fs1];
-  Bits<32> b = f[fs2];
+  Bits<32> a = F[fs1];
+  Bits<32> b = F[fs2];
 
   if (implemented?(ExtensionName::D)) {
     # check for incorrectly NaN-boxed inputs
-    if (f[fs1][63:32] != 32'hffffffff) {
+    if (F[fs1][63:32] != 32'hffffffff) {
       a = SP_CANONICAL_NAN;
     }
-    if (f[fs2][63:32] != 32'hffffffff) {
+    if (F[fs2][63:32] != 32'hffffffff) {
       b = SP_CANONICAL_NAN;
     }
   }
 
-  f[fd] = f32_add(a, b, mode);
+  F[fd] = f32_add(a, b, mode);
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fclass.s.yaml

@@ -51,11 +51,11 @@ data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = f[fs1][31:0];
+  Bits<32> sp_value = F[fs1][31:0];
 
   if (implemented?(ExtensionName::D)) {
     # check for an incorrectly NaN-boxed value
-    if (f[fs1][63:32] != 32'hffffffff) {
+    if (F[fs1][63:32] != 32'hffffffff) {
       sp_value = SP_CANONICAL_NAN;
     }
   }

data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml

@@ -34,4 +34,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  X[xd] = f32_to_i64(f[fs1], rounding_mode);
+  X[xd] = f32_to_i64(F[fs1], rounding_mode);

data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml

@@ -34,4 +34,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  X[xd] = f32_to_ui64(f[fs1], rounding_mode);
+  X[xd] = f32_to_ui64(F[fs1], rounding_mode);

data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml

@@ -34,5 +34,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = i64_to_f32(X[xs1], rounding_mode);
+  F[fd] = i64_to_f32(X[xs1], rounding_mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml

@@ -33,5 +33,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = ui64_to_f32(X[xs1], rounding_mode);
+  F[fd] = ui64_to_f32(X[xs1], rounding_mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fcvt.s.w.yaml

@@ -41,5 +41,5 @@ data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = i32_to_f32(X[xs1], rounding_mode);
+  F[fd] = i32_to_f32(X[xs1], rounding_mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fcvt.s.wu.yaml

@@ -41,5 +41,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = ui32_to_f32(X[xs1], rounding_mode);
+  F[fd] = ui32_to_f32(X[xs1], rounding_mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml

@@ -60,4 +60,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  X[xd] = $signed(f32_to_i32(f[fs1], rounding_mode));
+  X[xd] = $signed(f32_to_i32(F[fs1], rounding_mode));

data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml

@@ -59,4 +59,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  X[xd] = $signed(f32_to_ui32(f[fs1], rounding_mode));
+  X[xd] = $signed(f32_to_ui32(F[fs1], rounding_mode));

data/.data/spec/std/isa/inst/F/fdiv.s.yaml

@@ -34,5 +34,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_div(f[fs1], f[fs2], mode);
+  F[fd] = f32_div(F[fs1], F[fs2], mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/feq.s.yaml

@@ -34,8 +34,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {

data/.data/spec/std/isa/inst/F/fle.s.yaml

@@ -34,8 +34,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
   Bits<1> sign_a = sp_value_a[31];
   Bits<1> sign_b = sp_value_b[31];
 

data/.data/spec/std/isa/inst/F/fleq.s.yaml

@@ -32,8 +32,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     # Quiet comparison: only set NV for signaling NaN

data/.data/spec/std/isa/inst/F/flt.s.yaml

@@ -34,8 +34,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
   Bits<1> sign_a = sp_value_a[31];
   Bits<1> sign_b = sp_value_b[31];
 

data/.data/spec/std/isa/inst/F/fltq.s.yaml

@@ -32,8 +32,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     # Quiet comparison: only set NV for signaling NaN

data/.data/spec/std/isa/inst/F/flw.yaml

@@ -38,9 +38,9 @@ operation(): |
   Bits<32> sp_value = read_memory(32, virtual_address, $encoding);
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmadd.s.yaml

@@ -35,5 +35,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], F32MulAddOp::Softfloat_mulAdd_addC, mode);
+  F[fd] = f32_muladd(F[fs1], F[fs2], F[fs3], F32MulAddOp::Softfloat_mulAdd_addC, mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmax.s.yaml

@@ -41,8 +41,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
@@ -50,11 +50,11 @@ operation(): |
     }
     # If both are NaN, return canonical NaN; otherwise return the non-NaN operand
     if (is_sp_nan?(sp_value_a) && is_sp_nan?(sp_value_b)) {
-      f[fd] = SP_CANONICAL_NAN;
+      F[fd] = SP_CANONICAL_NAN;
     } else if (is_sp_nan?(sp_value_a)) {
-      f[fd] = sp_value_b;
+      F[fd] = sp_value_b;
     } else {
-      f[fd] = sp_value_a;
+      F[fd] = sp_value_a;
     }
   } else {
     Boolean sign_a = sp_value_a[31] == 1;
@@ -66,6 +66,6 @@ operation(): |
     } else {
       a_lt_b = (sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b));
     }
-    f[fd] = a_lt_b ? sp_value_b : sp_value_a;
+    F[fd] = a_lt_b ? sp_value_b : sp_value_a;
   }
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmin.s.yaml

@@ -41,8 +41,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
@@ -50,11 +50,11 @@ operation(): |
     }
     # If both are NaN, return canonical NaN; otherwise return the non-NaN operand
     if (is_sp_nan?(sp_value_a) && is_sp_nan?(sp_value_b)) {
-      f[fd] = SP_CANONICAL_NAN;
+      F[fd] = SP_CANONICAL_NAN;
     } else if (is_sp_nan?(sp_value_a)) {
-      f[fd] = sp_value_b;
+      F[fd] = sp_value_b;
     } else {
-      f[fd] = sp_value_a;
+      F[fd] = sp_value_a;
     }
   } else {
     Boolean sign_a = sp_value_a[31] == 1;
@@ -66,6 +66,6 @@ operation(): |
     } else {
       a_lt_b = (sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b));
     }
-    f[fd] = a_lt_b ? sp_value_a : sp_value_b;
+    F[fd] = a_lt_b ? sp_value_a : sp_value_b;
   }
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmsub.s.yaml

@@ -35,5 +35,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], F32MulAddOp::Softfloat_mulAdd_subC, mode);
+  F[fd] = f32_muladd(F[fs1], F[fs2], F[fs3], F32MulAddOp::Softfloat_mulAdd_subC, mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmul.s.yaml

@@ -34,5 +34,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_mul(f[fs1], f[fs2], mode);
+  F[fd] = f32_mul(F[fs1], F[fs2], mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmv.w.x.yaml

@@ -34,9 +34,9 @@ operation(): |
   Bits<32> sp_value = X[xs1][31:0];
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmv.x.w.yaml

@@ -32,4 +32,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  X[xd] = sext(f[fs1][31:0], 32);
+  X[xd] = sext(F[fs1][31:0], 32);

data/.data/spec/std/isa/inst/F/fnmadd.s.yaml

@@ -38,6 +38,6 @@ operation(): |
   RoundingMode mode = rm_to_mode(rm, $encoding);
   # fnmadd: -(fs1 * fs2) - fs3 = -(fs1 * fs2) + (-fs3)
   # Negate fs3 by flipping its sign bit, then use subProd op
-  Bits<32> fs3_negated = f[fs3][31:0] ^ 32'h80000000;
-  f[fd] = f32_muladd(f[fs1], f[fs2], fs3_negated, F32MulAddOp::Softfloat_mulAdd_subProd, mode);
+  Bits<32> fs3_negated = F[fs3][31:0] ^ 32'h80000000;
+  F[fd] = f32_muladd(F[fs1], F[fs2], fs3_negated, F32MulAddOp::Softfloat_mulAdd_subProd, mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fnmsub.s.yaml

@@ -36,5 +36,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], F32MulAddOp::Softfloat_mulAdd_subProd, mode);
+  F[fd] = f32_muladd(F[fs1], F[fs2], F[fs3], F32MulAddOp::Softfloat_mulAdd_subProd, mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fsgnj.s.yaml

@@ -34,17 +34,17 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: (fs2 == fs1)
-    to: fmv.s fd,fs1
+    to: fmv.s fd, fs1
 
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = {f[fs2][31], f[fs1][30:0]};
+  Bits<32> sp_value = {F[fs2][31], F[fs1][30:0]};
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml

@@ -38,12 +38,12 @@ pseudoinstructions:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = {~f[fs2][31], f[fs1][30:0]};
+  Bits<32> sp_value = {~F[fs2][31], F[fs1][30:0]};
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml

@@ -33,16 +33,16 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: (fs2 == fs1)
-    to: fabs.s fd,fs1
+    to: fabs.s fd, fs1
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = {f[fs1][31] ^ f[fs2][31], f[fs1][30:0]};
+  Bits<32> sp_value = {F[fs1][31] ^ F[fs2][31], F[fs1][30:0]};
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fsqrt.s.yaml

@@ -31,5 +31,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_sqrt(f[fs1], mode);
+  F[fd] = f32_sqrt(F[fs1], mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fsub.s.yaml

@@ -33,4 +33,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_sub(f[fs1], f[fs2], mode);
+  F[fd] = f32_sub(F[fs1], F[fs2], mode);

data/.data/spec/std/isa/inst/F/fsw.yaml

@@ -35,4 +35,4 @@ operation(): |
 
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  write_memory(32, virtual_address, f[fs2][31:0], $encoding);
+  write_memory(32, virtual_address, F[fs2][31:0], $encoding);

data/.data/spec/std/isa/inst/I/addi.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd
@@ -33,5 +34,5 @@ pseudoinstructions:
   - when: (xd == 0 && xs1 == 0 && imm == 0)
     to: nop
   - when: imm == 0
-    to: mv xd,xs1
+    to: mv xd, xs1
 operation(): X[xd] = X[xs1] + $signed(imm);

data/.data/spec/std/isa/inst/I/addiw.yaml

@@ -21,6 +21,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd
@@ -33,6 +34,6 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: imm == 0
-    to: sext.w xd,xs1
+    to: sext.w xd, xs1
 operation(): |
   X[xd] = $signed((X[xs1] + $signed(imm))[31:0]);

data/.data/spec/std/isa/inst/I/andi.yaml

@@ -17,6 +17,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd
@@ -29,5 +30,5 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: imm == 255
-    to: zext.b xd,xs1
+    to: zext.b xd, xs1
 operation(): X[xd] = X[xs1] & $signed(imm);

data/.data/spec/std/isa/inst/I/auipc.yaml

@@ -18,6 +18,7 @@ encoding:
     - name: imm
       location: 31-12
       left_shift: 12
+      sign_extend: true
     - name: xd
       location: 11-7
 hints:

data/.data/spec/std/isa/inst/I/beq.yaml

@@ -34,7 +34,7 @@ access:
   vu: always
 pseudoinstructions:
   - when: xs2 == 0
-    to: beqz xs1,imm
+    to: beqz xs1, imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];

data/.data/spec/std/isa/inst/I/bge.yaml

@@ -34,9 +34,11 @@ access:
   vu: always
 pseudoinstructions:
   - when: xs1 == 0
-    to: blez xs2,imm
+    to: blez xs2, imm
   - when: xs2 == 0
-    to: bgez xs1,imm
+    to: bgez xs1, imm
+  - when: "true"
+    to: ble xs2, xs1, imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];

data/.data/spec/std/isa/inst/I/bgeu.yaml

@@ -32,6 +32,9 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: bleu xs2, xs1, imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];

data/.data/spec/std/isa/inst/I/blt.yaml

@@ -34,9 +34,11 @@ access:
   vu: always
 pseudoinstructions:
   - when: xs2 == 0
-    to: bltz xs1,imm
+    to: bltz xs1, imm
   - when: xs1 == 0
-    to: bgtz xs2,imm
+    to: bgtz xs2, imm
+  - when: "true"
+    to: bgt xs2, xs1, imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];

data/.data/spec/std/isa/inst/I/bltu.yaml

@@ -32,6 +32,9 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: bgtu xs2, xs1, imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];

data/.data/spec/std/isa/inst/I/bne.yaml

@@ -34,7 +34,7 @@ access:
   vu: always
 pseudoinstructions:
   - when: xs2 == 0
-    to: bnez xs1,imm
+    to: bnez xs1, imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];

data/.data/spec/std/isa/inst/I/lb.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/lbu.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd