udb 0.1.9 → 0.1.14
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.data/cfgs/example_rv64_with_overlay.yaml +20 -20
- data/.data/cfgs/mc100-32-full-example.yaml +1 -0
- data/.data/cfgs/profile/README.adoc +10 -0
- data/.data/cfgs/profile/RVA20S64.yaml +26 -6
- data/.data/cfgs/profile/RVA20U64.yaml +18 -4
- data/.data/cfgs/profile/RVA22S64.yaml +27 -7
- data/.data/cfgs/profile/RVA22U64.yaml +18 -4
- data/.data/cfgs/profile/RVA23S64.yaml +61 -7
- data/.data/cfgs/profile/RVA23U64.yaml +36 -4
- data/.data/cfgs/profile/RVB23S64.yaml +27 -7
- data/.data/cfgs/profile/RVB23U64.yaml +18 -4
- data/.data/cfgs/profile/RVI20U32.yaml +10 -4
- data/.data/cfgs/profile/RVI20U64.yaml +10 -4
- data/.data/cfgs/qc_iu.yaml +8 -1
- data/.data/cfgs/rv32-riscv-tests.yaml +6 -2
- data/.data/cfgs/rv32-vector.yaml +6 -2
- data/.data/cfgs/rv64-riscv-tests.yaml +6 -2
- data/.data/cfgs/rv64-vector.yaml +6 -2
- data/.data/spec/custom/isa/qc_iu/csr/Smrnmi/mnepc.yaml +17 -0
- data/.data/spec/custom/isa/qc_iu/csr/Xqccmi/qc.itba.yaml +45 -0
- data/.data/spec/custom/isa/qc_iu/csr/Xqccmi/qc.itdec.yaml +39 -0
- data/.data/spec/custom/isa/qc_iu/csr/jvt.yaml +11 -0
- data/.data/spec/custom/isa/qc_iu/csr/mepc.yaml +16 -0
- data/.data/spec/custom/isa/qc_iu/ext/Xqccmi.yaml +290 -0
- data/.data/spec/custom/isa/qc_iu/ext/Xqccmt.yaml +127 -0
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmi/qc.cm.ilut.yaml +136 -0
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmt/qc.cm.jalt.yaml +84 -0
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmt/qc.cm.jt.yaml +60 -0
- data/.data/spec/custom/isa/qc_iu/isa/globals.isa +134 -0
- data/.data/spec/schemas/config_schema.json +220 -27
- data/.data/spec/schemas/csr_schema.json +0 -6
- data/.data/spec/schemas/ext_schema.json +80 -24
- data/.data/spec/schemas/inst_schema.json +0 -3
- data/.data/spec/schemas/mmr_schema.json +3 -3
- data/.data/spec/schemas/profile_release_schema.json +1 -1
- data/.data/spec/schemas/profile_schema.json +0 -3
- data/.data/spec/schemas/register_file_schema.json +8 -3
- data/.data/spec/schemas/schema_defs.json +13 -27
- data/.data/spec/std/isa/csr/H/henvcfg.yaml +25 -0
- data/.data/spec/std/isa/csr/I/pmpaddr0.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr1.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr10.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr11.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr12.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr13.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr14.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr15.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr16.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr17.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr18.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr19.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr2.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr20.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr21.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr22.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr23.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr24.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr25.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr26.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr27.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr28.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr29.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr3.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr30.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr31.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr32.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr33.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr34.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr35.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr36.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr37.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr38.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr39.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr4.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr40.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr41.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr42.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr43.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr44.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr45.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr46.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr47.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr48.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr49.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr5.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr50.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr51.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr52.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr53.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr54.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr55.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr56.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr57.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr58.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr59.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr6.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr60.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr61.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr62.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr63.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr7.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr8.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddr9.yaml +6 -4
- data/.data/spec/std/isa/csr/I/pmpaddrN.layout +6 -4
- data/.data/spec/std/isa/csr/I/pmpcfg0.yaml +128 -152
- data/.data/spec/std/isa/csr/I/pmpcfg1.yaml +64 -76
- data/.data/spec/std/isa/csr/I/pmpcfg10.yaml +128 -152
- data/.data/spec/std/isa/csr/I/pmpcfg11.yaml +64 -76
- data/.data/spec/std/isa/csr/I/pmpcfg12.yaml +128 -152
- data/.data/spec/std/isa/csr/I/pmpcfg13.yaml +64 -76
- data/.data/spec/std/isa/csr/I/pmpcfg14.yaml +128 -152
- data/.data/spec/std/isa/csr/I/pmpcfg15.yaml +64 -76
- data/.data/spec/std/isa/csr/I/pmpcfg2.yaml +128 -152
- data/.data/spec/std/isa/csr/I/pmpcfg3.yaml +64 -76
- data/.data/spec/std/isa/csr/I/pmpcfg4.yaml +128 -152
- data/.data/spec/std/isa/csr/I/pmpcfg5.yaml +64 -76
- data/.data/spec/std/isa/csr/I/pmpcfg6.yaml +128 -152
- data/.data/spec/std/isa/csr/I/pmpcfg7.yaml +64 -76
- data/.data/spec/std/isa/csr/I/pmpcfg8.yaml +128 -152
- data/.data/spec/std/isa/csr/I/pmpcfg9.yaml +64 -76
- data/.data/spec/std/isa/csr/I/pmpcfgN.layout +16 -19
- data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.layout +6 -2
- data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.yaml +6 -2
- data/.data/spec/std/isa/csr/hstatus.yaml +16 -0
- data/.data/spec/std/isa/csr/jvt.yaml +1 -0
- data/.data/spec/std/isa/csr/mcycleh.yaml +1 -1
- data/.data/spec/std/isa/csr/menvcfg.yaml +20 -0
- data/.data/spec/std/isa/csr/misa.yaml +0 -12
- data/.data/spec/std/isa/csr/mstatus.yaml +46 -6
- data/.data/spec/std/isa/csr/mstatush.yaml +17 -15
- data/.data/spec/std/isa/csr/senvcfg.yaml +42 -0
- data/.data/spec/std/isa/csr/sstatus.yaml +12 -0
- data/.data/spec/std/isa/csr/vsstatus.yaml +24 -0
- data/.data/spec/std/isa/ext/A.yaml +5 -7
- data/.data/spec/std/isa/ext/S.yaml +12 -0
- data/.data/spec/std/isa/ext/Smpmpmt.yaml +52 -0
- data/.data/spec/std/isa/ext/Sv32.yaml +7 -19
- data/.data/spec/std/isa/ext/Sv39.yaml +7 -19
- data/.data/spec/std/isa/ext/Sv48.yaml +4 -20
- data/.data/spec/std/isa/ext/Sv57.yaml +4 -20
- data/.data/spec/std/isa/ext/Svukte.yaml +71 -0
- data/.data/spec/std/isa/ext/Zawrs.yaml +1 -1
- data/.data/spec/std/isa/ext/Zihpm.yaml +0 -12
- data/.data/spec/std/isa/inst/B/andn.yaml +10 -12
- data/.data/spec/std/isa/inst/B/clmul.yaml +9 -11
- data/.data/spec/std/isa/inst/B/clmulh.yaml +9 -11
- data/.data/spec/std/isa/inst/B/orn.yaml +9 -11
- data/.data/spec/std/isa/inst/B/rev8.yaml +1 -1
- data/.data/spec/std/isa/inst/B/rol.yaml +9 -11
- data/.data/spec/std/isa/inst/B/rolw.yaml +9 -11
- data/.data/spec/std/isa/inst/B/ror.yaml +9 -11
- data/.data/spec/std/isa/inst/B/rorw.yaml +9 -11
- data/.data/spec/std/isa/inst/B/xnor.yaml +9 -11
- data/.data/spec/std/isa/inst/C/c.addi.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.addi16sp.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.addiw.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.andi.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.ldsp.yaml +4 -4
- data/.data/spec/std/isa/inst/C/c.li.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.lui.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.mv.yaml +1 -1
- data/.data/spec/std/isa/inst/C/c.sdsp.yaml +1 -1
- data/.data/spec/std/isa/inst/D/fsgnj.d.yaml +3 -0
- data/.data/spec/std/isa/inst/D/fsgnjn.d.yaml +3 -0
- data/.data/spec/std/isa/inst/D/fsgnjx.d.yaml +3 -0
- data/.data/spec/std/isa/inst/F/fadd.s.yaml +5 -5
- data/.data/spec/std/isa/inst/F/fclass.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.w.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.wu.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fdiv.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/feq.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fle.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fleq.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/flt.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fltq.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/flw.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fmadd.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmax.s.yaml +6 -6
- data/.data/spec/std/isa/inst/F/fmin.s.yaml +6 -6
- data/.data/spec/std/isa/inst/F/fmsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmul.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmv.w.x.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fmv.x.w.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fnmadd.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fnmsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsgnj.s.yaml +4 -4
- data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml +3 -3
- data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml +4 -4
- data/.data/spec/std/isa/inst/F/fsqrt.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsw.yaml +1 -1
- data/.data/spec/std/isa/inst/I/addi.yaml +2 -1
- data/.data/spec/std/isa/inst/I/addiw.yaml +2 -1
- data/.data/spec/std/isa/inst/I/andi.yaml +2 -1
- data/.data/spec/std/isa/inst/I/auipc.yaml +1 -0
- data/.data/spec/std/isa/inst/I/beq.yaml +1 -1
- data/.data/spec/std/isa/inst/I/bge.yaml +4 -2
- data/.data/spec/std/isa/inst/I/bgeu.yaml +3 -0
- data/.data/spec/std/isa/inst/I/blt.yaml +4 -2
- data/.data/spec/std/isa/inst/I/bltu.yaml +3 -0
- data/.data/spec/std/isa/inst/I/bne.yaml +1 -1
- data/.data/spec/std/isa/inst/I/lb.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lbu.yaml +1 -0
- data/.data/spec/std/isa/inst/I/ld.yaml +2 -0
- data/.data/spec/std/isa/inst/I/lh.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lhu.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lui.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lw.yaml +1 -0
- data/.data/spec/std/isa/inst/I/lwu.yaml +1 -0
- data/.data/spec/std/isa/inst/I/ori.yaml +1 -0
- data/.data/spec/std/isa/inst/I/sb.yaml +1 -0
- data/.data/spec/std/isa/inst/I/sd.yaml +1 -0
- data/.data/spec/std/isa/inst/I/sh.yaml +1 -0
- data/.data/spec/std/isa/inst/I/slt.yaml +2 -2
- data/.data/spec/std/isa/inst/I/slti.yaml +1 -0
- data/.data/spec/std/isa/inst/I/sltiu.yaml +2 -1
- data/.data/spec/std/isa/inst/I/sltu.yaml +1 -1
- data/.data/spec/std/isa/inst/I/sub.yaml +1 -1
- data/.data/spec/std/isa/inst/I/subw.yaml +1 -1
- data/.data/spec/std/isa/inst/I/sw.yaml +1 -0
- data/.data/spec/std/isa/inst/I/xori.yaml +2 -1
- data/.data/spec/std/isa/inst/M/mul.yaml +0 -19
- data/.data/spec/std/isa/inst/Q/fsgnj.q.yaml +1 -1
- data/.data/spec/std/isa/inst/S/sret.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vadc.vim.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vadd.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vadd.vv.yaml +1 -5
- data/.data/spec/std/isa/inst/V/vand.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vfsgnjn.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vfsgnjx.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vl1re8.v.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vl2re8.v.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vl4re8.v.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vl8re8.v.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vle8.v.yaml +4 -8
- data/.data/spec/std/isa/inst/V/vmadc.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmadc.vim.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmand.mm.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmerge.vim.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmfle.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmflt.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmnand.mm.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmseq.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmsgt.vi.yaml +4 -0
- data/.data/spec/std/isa/inst/V/vmsgtu.vi.yaml +4 -0
- data/.data/spec/std/isa/inst/V/vmsle.vi.yaml +4 -0
- data/.data/spec/std/isa/inst/V/vmsle.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml +4 -0
- data/.data/spec/std/isa/inst/V/vmsleu.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmslt.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsltu.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsne.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vmv.v.i.yaml +2 -13
- data/.data/spec/std/isa/inst/V/vmv.x.s.yaml +1 -1
- data/.data/spec/std/isa/inst/V/vmxnor.mm.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmxor.mm.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vnsrl.wx.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vor.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vrsub.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vrsub.vx.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vsadd.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vsaddu.vi.yaml +1 -0
- data/.data/spec/std/isa/inst/V/vse8.v.yaml +4 -4
- data/.data/spec/std/isa/inst/V/vwadd.vx.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vwaddu.vx.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vxor.vi.yaml +4 -0
- data/.data/spec/std/isa/inst/Zalasr/lSIZE.AQRL.layout +40 -5
- data/.data/spec/std/isa/inst/Zalasr/lb.aq.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lb.aqrl.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/ld.aq.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/ld.aqrl.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lh.aq.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lh.aqrl.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lw.aq.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lw.aqrl.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/sSIZE.AQRL.layout +46 -5
- data/.data/spec/std/isa/inst/Zalasr/sb.aqrl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sb.rl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sd.aqrl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sd.rl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sh.aqrl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sh.rl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sw.aqrl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sw.rl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zawrs/wrs.nto.yaml +4 -2
- data/.data/spec/std/isa/inst/Zba/add.uw.yaml +9 -11
- data/.data/spec/std/isa/inst/Zbb/orc.b.yaml +1 -1
- data/.data/spec/std/isa/inst/Zbkb/brev8.yaml +3 -3
- data/.data/spec/std/isa/inst/Zbkb/packw.yaml +1 -1
- data/.data/spec/std/isa/inst/Zbkb/unzip.yaml +2 -2
- data/.data/spec/std/isa/inst/Zbkb/zip.yaml +2 -2
- data/.data/spec/std/isa/inst/Zbkx/xperm4.yaml +2 -2
- data/.data/spec/std/isa/inst/Zbkx/xperm8.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcd/c.fld.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcd/c.fldsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcd/c.fsdsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcf/c.flwsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcf/c.fswsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmp/cm.pop.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmp/cm.popret.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmp/cm.popretz.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmp/cm.push.yaml +2 -3
- data/.data/spec/std/isa/inst/Zfa/fround.s.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/fcvt.h.s.yaml +6 -6
- data/.data/spec/std/isa/inst/Zfh/fcvt.s.h.yaml +5 -5
- data/.data/spec/std/isa/inst/Zfh/flh.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/fmv.x.h.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/fsh.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicbop/prefetch.i.yaml +2 -0
- data/.data/spec/std/isa/inst/Zicbop/prefetch.r.yaml +2 -0
- data/.data/spec/std/isa/inst/Zicbop/prefetch.w.yaml +2 -0
- data/.data/spec/std/isa/inst/Zicsr/csrrc.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrci.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrs.yaml +2 -2
- data/.data/spec/std/isa/inst/Zicsr/csrrsi.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrw.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrwi.yaml +1 -1
- data/.data/spec/std/isa/inst/Zks/sm3p0.yaml +1 -1
- data/.data/spec/std/isa/inst/Zks/sm3p1.yaml +1 -1
- data/.data/spec/std/isa/inst/Zks/sm4ed.yaml +1 -1
- data/.data/spec/std/isa/inst/Zks/sm4ks.yaml +1 -1
- data/.data/spec/std/isa/isa/builtin_functions.idl +18 -0
- data/.data/spec/std/isa/isa/fp.idl +1 -5
- data/.data/spec/std/isa/isa/globals.isa +72 -21
- data/.data/spec/std/isa/isa/interrupts.idl +1 -0
- data/.data/spec/std/isa/isa/vec.idl +1 -2
- data/.data/spec/std/isa/manual_version/isa/20240411/isa_20240411.yaml +5 -5
- data/.data/spec/std/isa/param/COUNTINHIBIT_EN.yaml +8 -2
- data/.data/spec/std/isa/param/HSTATEEN_CONTEXT_TYPE.yaml +1 -0
- data/.data/spec/std/isa/param/JVT_BASE_MASK.yaml +1 -1
- data/.data/spec/std/isa/param/MCOUNTINHIBIT_IMPLEMENTED.yaml +25 -0
- data/.data/spec/std/isa/param/MSTATEEN_CONTEXT_TYPE.yaml +1 -0
- data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml +1 -0
- data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_VECTORED.yaml +1 -0
- data/.data/spec/std/isa/param/MTVEC_MODES.yaml +10 -3
- data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml +11 -22
- data/.data/spec/std/isa/param/NUM_USABLE_PMP_ENTRIES.yaml +35 -0
- data/.data/spec/std/isa/param/PMP_NA4_SUPPORTED.yaml +23 -0
- data/.data/spec/std/isa/param/PMP_NAPOT_SUPPORTED.yaml +19 -0
- data/.data/spec/std/isa/param/{MSTATUS_TVM_IMPLEMENTED.yaml → PMP_TOR_SUPPORTED.yaml} +6 -6
- data/.data/spec/std/isa/param/PRECISE_SYNCHRONOUS_EXCEPTIONS.yaml +1 -0
- data/.data/spec/std/isa/param/TRAP_ON_EBREAK.yaml +1 -0
- data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_M.yaml +1 -0
- data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml +1 -0
- data/.data/spec/std/isa/param/VLEN.yaml +2 -0
- data/.data/spec/std/isa/param/ZAWRS_NTO_IS_NOP.yaml +19 -0
- data/.data/spec/std/isa/profile/RVA20S64.yaml +11 -4
- data/.data/spec/std/isa/profile/RVA20U64.yaml +14 -5
- data/.data/spec/std/isa/profile/RVA22S64.yaml +14 -3
- data/.data/spec/std/isa/profile/RVA22U64.yaml +8 -1
- data/.data/spec/std/isa/profile/RVA23S64.yaml +13 -0
- data/.data/spec/std/isa/profile/RVA23U64.yaml +15 -1
- data/.data/spec/std/isa/profile/RVB23S64.yaml +15 -3
- data/.data/spec/std/isa/profile/RVB23U64.yaml +8 -1
- data/.data/spec/std/isa/profile/RVI20U32.yaml +8 -1
- data/.data/spec/std/isa/profile/RVI20U64.yaml +7 -0
- data/.data/spec/std/isa/register_file/F.yaml +3 -2
- data/.data/spec/std/isa/register_file/V.yaml +2 -2
- data/.data/spec/std/isa/register_file/X.yaml +2 -1
- data/lib/udb/ESPRESSO_VERSION +1 -1
- data/lib/udb/architecture.rb +4 -25
- data/lib/udb/cfg_arch.rb +171 -59
- data/lib/udb/cli.rb +10 -1
- data/lib/udb/condition.rb +38 -37
- data/lib/udb/config.rb +86 -8
- data/lib/udb/doc_link.rb +3 -4
- data/lib/udb/logic.rb +29 -56
- data/lib/udb/obj/csr.rb +23 -5
- data/lib/udb/obj/csr_field.rb +36 -21
- data/lib/udb/obj/database_obj.rb +2 -5
- data/lib/udb/obj/extension.rb +0 -3
- data/lib/udb/obj/instruction.rb +2 -5
- data/lib/udb/obj/non_isa_specification.rb +22 -100
- data/lib/udb/obj/portfolio.rb +75 -20
- data/lib/udb/obj/profile.rb +0 -4
- data/lib/udb/obj/register_file.rb +63 -2
- data/lib/udb/portfolio_design.rb +3 -6
- data/lib/udb/resolver.rb +84 -23
- data/lib/udb/version.rb +1 -1
- data/lib/udb/version_spec.rb +8 -0
- data/lib/udb/z3.rb +25 -2
- data/lib/udb.rb +0 -3
- metadata +30 -38
- data/.data/cfgs/profile/RVA23M64.yaml +0 -159
- data/.data/cfgs/profile/RVB23M64.yaml +0 -149
- data/.data/spec/schemas/proc_cert_class_schema.json +0 -35
- data/.data/spec/schemas/proc_cert_model_schema.json +0 -336
- data/.data/spec/std/isa/proc_cert_class/AC.yaml +0 -13
- data/.data/spec/std/isa/proc_cert_class/MC.yaml +0 -13
- data/.data/spec/std/isa/proc_cert_class/RVI.yaml +0 -16
- data/.data/spec/std/isa/proc_cert_model/AC100.yaml +0 -72
- data/.data/spec/std/isa/proc_cert_model/AC200.yaml +0 -58
- data/.data/spec/std/isa/proc_cert_model/MC100-32.yaml +0 -155
- data/.data/spec/std/isa/proc_cert_model/MC100-64.yaml +0 -21
- data/.data/spec/std/isa/proc_cert_model/MC200-32.yaml +0 -60
- data/.data/spec/std/isa/proc_cert_model/MC200-64.yaml +0 -21
- data/.data/spec/std/isa/proc_cert_model/MC300-32.yaml +0 -40
- data/.data/spec/std/isa/proc_cert_model/MC300-64.yaml +0 -21
- data/.data/spec/std/isa/proc_cert_model/RVI20-32.yaml +0 -39
- data/.data/spec/std/isa/proc_cert_model/RVI20-64.yaml +0 -19
- data/.data/spec/std/isa/profile/RVA23M64.yaml +0 -24
- data/.data/spec/std/isa/profile/RVB23M64.yaml +0 -86
- data/lib/udb/cert_normative_rule.rb +0 -41
- data/lib/udb/obj/certifiable_obj.rb +0 -21
- data/lib/udb/obj/certificate.rb +0 -230
- data/lib/udb/proc_cert_design.rb +0 -77
|
@@ -35,23 +35,15 @@ fields:
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35
35
|
! Name ! Location ! Description
|
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36
36
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37
37
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h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
|
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38
|
-
h!
|
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38
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+
h! MT ! 6:5 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
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39
39
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h! A ! 4:3
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40
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a! Address matching mode.
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40
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+
a! Address matching mode. Encodings:
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41
41
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42
|
-
[when="PMP_GRANULARITY < 2"]
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43
42
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* *OFF* (0) - Null region (disabled)
|
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44
43
|
* *TOR* (1) - Top of range
|
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45
44
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* *NA4* (2) - Naturally aligned four-byte region
|
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46
45
|
* *NAPOT* (3) - Naturally aligned power of two
|
|
47
46
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|
|
48
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
49
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-
* *OFF* (0) - Null region (disabled)
|
|
50
|
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* *TOR* (1) - Top of range
|
|
51
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-
* *NAPOT* (3) - Naturally aligned power of two
|
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52
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-
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53
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
54
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-
Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
|
|
55
47
|
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56
48
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h! X ! 2 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
|
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57
49
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h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
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|
@@ -60,23 +52,28 @@ fields:
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60
52
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61
53
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The combination of R = 0, W = 1 is reserved.
|
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62
54
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type(): |
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63
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if (
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55
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+
if (NUM_USABLE_PMP_ENTRIES > 40) {
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64
56
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return CsrFieldType::RWR;
|
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65
57
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} else {
|
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58
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# entry is either not implemented or implemented as read-only zero
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66
59
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return CsrFieldType::RO;
|
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67
60
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}
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61
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reset_value(): |
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62
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return 0;
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70
63
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sw_write(csr_value): |
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71
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-
if ((CSR[pmpcfg10].pmp40cfg & 0x80) == 0) {
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72
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# entry is not locked
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73
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74
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64
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if (NUM_USABLE_PMP_ENTRIES > 40 && (CSR[pmpcfg10].pmp40cfg & 0x80) == 0) {
|
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65
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+
# entry is usable and not locked
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66
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+
Bits<8> new_cfg = csr_value.pmp40cfg;
|
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67
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+
Bits<2> a_mode = (new_cfg & 0x18) >> 3;
|
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68
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+
if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
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69
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+
# not R = 0, W = 1, which is reserved
|
|
70
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+
if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
|
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71
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+
((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
|
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72
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+
((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
|
|
73
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+
# unsupported address matching mode; keep old value
|
|
74
|
+
return CSR[pmpcfg10].pmp40cfg;
|
|
79
75
|
}
|
|
76
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+
return new_cfg;
|
|
80
77
|
}
|
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81
78
|
}
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79
|
# fall through: keep old value
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@@ -93,23 +90,15 @@ fields:
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93
90
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! Name ! Location ! Description
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94
91
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95
92
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h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
|
|
96
|
-
h!
|
|
93
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+
h! MT ! 14:13 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
|
|
97
94
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h! A ! 12:11
|
|
98
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-
a! Address matching mode.
|
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95
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+
a! Address matching mode. Encodings:
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99
96
|
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|
100
|
-
[when="PMP_GRANULARITY < 2"]
|
|
101
97
|
* *OFF* (0) - Null region (disabled)
|
|
102
98
|
* *TOR* (1) - Top of range
|
|
103
99
|
* *NA4* (2) - Naturally aligned four-byte region
|
|
104
100
|
* *NAPOT* (3) - Naturally aligned power of two
|
|
105
101
|
|
|
106
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
107
|
-
* *OFF* (0) - Null region (disabled)
|
|
108
|
-
* *TOR* (1) - Top of range
|
|
109
|
-
* *NAPOT* (3) - Naturally aligned power of two
|
|
110
|
-
|
|
111
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
112
|
-
Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
|
|
113
102
|
|
|
114
103
|
h! X ! 10 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
|
|
115
104
|
h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
|
|
@@ -118,23 +107,28 @@ fields:
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|
118
107
|
|
|
119
108
|
The combination of R = 0, W = 1 is reserved.
|
|
120
109
|
type(): |
|
|
121
|
-
if (
|
|
110
|
+
if (NUM_USABLE_PMP_ENTRIES > 41) {
|
|
122
111
|
return CsrFieldType::RWR;
|
|
123
112
|
} else {
|
|
113
|
+
# entry is either not implemented or implemented as read-only zero
|
|
124
114
|
return CsrFieldType::RO;
|
|
125
115
|
}
|
|
126
116
|
reset_value(): |
|
|
127
117
|
return 0;
|
|
128
118
|
sw_write(csr_value): |
|
|
129
|
-
if ((CSR[pmpcfg10].pmp41cfg & 0x80) == 0) {
|
|
130
|
-
# entry is not locked
|
|
131
|
-
|
|
132
|
-
|
|
133
|
-
|
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134
|
-
|
|
135
|
-
|
|
136
|
-
|
|
119
|
+
if (NUM_USABLE_PMP_ENTRIES > 41 && (CSR[pmpcfg10].pmp41cfg & 0x80) == 0) {
|
|
120
|
+
# entry is usable and not locked
|
|
121
|
+
Bits<8> new_cfg = csr_value.pmp41cfg;
|
|
122
|
+
Bits<2> a_mode = (new_cfg & 0x18) >> 3;
|
|
123
|
+
if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
|
|
124
|
+
# not R = 0, W = 1, which is reserved
|
|
125
|
+
if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
|
|
126
|
+
((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
|
|
127
|
+
((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
|
|
128
|
+
# unsupported address matching mode; keep old value
|
|
129
|
+
return CSR[pmpcfg10].pmp41cfg;
|
|
137
130
|
}
|
|
131
|
+
return new_cfg;
|
|
138
132
|
}
|
|
139
133
|
}
|
|
140
134
|
# fall through: keep old value
|
|
@@ -151,23 +145,15 @@ fields:
|
|
|
151
145
|
! Name ! Location ! Description
|
|
152
146
|
|
|
153
147
|
h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
|
|
154
|
-
h!
|
|
148
|
+
h! MT ! 22:21 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
|
|
155
149
|
h! A ! 20:19
|
|
156
|
-
a! Address matching mode.
|
|
150
|
+
a! Address matching mode. Encodings:
|
|
157
151
|
|
|
158
|
-
[when="PMP_GRANULARITY < 2"]
|
|
159
152
|
* *OFF* (0) - Null region (disabled)
|
|
160
153
|
* *TOR* (1) - Top of range
|
|
161
154
|
* *NA4* (2) - Naturally aligned four-byte region
|
|
162
155
|
* *NAPOT* (3) - Naturally aligned power of two
|
|
163
156
|
|
|
164
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
165
|
-
* *OFF* (0) - Null region (disabled)
|
|
166
|
-
* *TOR* (1) - Top of range
|
|
167
|
-
* *NAPOT* (3) - Naturally aligned power of two
|
|
168
|
-
|
|
169
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
170
|
-
Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
|
|
171
157
|
|
|
172
158
|
h! X ! 18 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
|
|
173
159
|
h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
|
|
@@ -176,23 +162,28 @@ fields:
|
|
|
176
162
|
|
|
177
163
|
The combination of R = 0, W = 1 is reserved.
|
|
178
164
|
type(): |
|
|
179
|
-
if (
|
|
165
|
+
if (NUM_USABLE_PMP_ENTRIES > 42) {
|
|
180
166
|
return CsrFieldType::RWR;
|
|
181
167
|
} else {
|
|
168
|
+
# entry is either not implemented or implemented as read-only zero
|
|
182
169
|
return CsrFieldType::RO;
|
|
183
170
|
}
|
|
184
171
|
reset_value(): |
|
|
185
172
|
return 0;
|
|
186
173
|
sw_write(csr_value): |
|
|
187
|
-
if ((CSR[pmpcfg10].pmp42cfg & 0x80) == 0) {
|
|
188
|
-
# entry is not locked
|
|
189
|
-
|
|
190
|
-
|
|
191
|
-
|
|
192
|
-
|
|
193
|
-
|
|
194
|
-
|
|
174
|
+
if (NUM_USABLE_PMP_ENTRIES > 42 && (CSR[pmpcfg10].pmp42cfg & 0x80) == 0) {
|
|
175
|
+
# entry is usable and not locked
|
|
176
|
+
Bits<8> new_cfg = csr_value.pmp42cfg;
|
|
177
|
+
Bits<2> a_mode = (new_cfg & 0x18) >> 3;
|
|
178
|
+
if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
|
|
179
|
+
# not R = 0, W = 1, which is reserved
|
|
180
|
+
if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
|
|
181
|
+
((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
|
|
182
|
+
((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
|
|
183
|
+
# unsupported address matching mode; keep old value
|
|
184
|
+
return CSR[pmpcfg10].pmp42cfg;
|
|
195
185
|
}
|
|
186
|
+
return new_cfg;
|
|
196
187
|
}
|
|
197
188
|
}
|
|
198
189
|
# fall through: keep old value
|
|
@@ -209,23 +200,15 @@ fields:
|
|
|
209
200
|
! Name ! Location ! Description
|
|
210
201
|
|
|
211
202
|
h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
|
|
212
|
-
h!
|
|
203
|
+
h! MT ! 30:29 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
|
|
213
204
|
h! A ! 28:27
|
|
214
|
-
a! Address matching mode.
|
|
205
|
+
a! Address matching mode. Encodings:
|
|
215
206
|
|
|
216
|
-
[when="PMP_GRANULARITY < 2"]
|
|
217
207
|
* *OFF* (0) - Null region (disabled)
|
|
218
208
|
* *TOR* (1) - Top of range
|
|
219
209
|
* *NA4* (2) - Naturally aligned four-byte region
|
|
220
210
|
* *NAPOT* (3) - Naturally aligned power of two
|
|
221
211
|
|
|
222
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
223
|
-
* *OFF* (0) - Null region (disabled)
|
|
224
|
-
* *TOR* (1) - Top of range
|
|
225
|
-
* *NAPOT* (3) - Naturally aligned power of two
|
|
226
|
-
|
|
227
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
228
|
-
Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
|
|
229
212
|
|
|
230
213
|
h! X ! 26 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
|
|
231
214
|
h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
|
|
@@ -234,23 +217,28 @@ fields:
|
|
|
234
217
|
|
|
235
218
|
The combination of R = 0, W = 1 is reserved.
|
|
236
219
|
type(): |
|
|
237
|
-
if (
|
|
220
|
+
if (NUM_USABLE_PMP_ENTRIES > 43) {
|
|
238
221
|
return CsrFieldType::RWR;
|
|
239
222
|
} else {
|
|
223
|
+
# entry is either not implemented or implemented as read-only zero
|
|
240
224
|
return CsrFieldType::RO;
|
|
241
225
|
}
|
|
242
226
|
reset_value(): |
|
|
243
227
|
return 0;
|
|
244
228
|
sw_write(csr_value): |
|
|
245
|
-
if ((CSR[pmpcfg10].pmp43cfg & 0x80) == 0) {
|
|
246
|
-
# entry is not locked
|
|
247
|
-
|
|
248
|
-
|
|
249
|
-
|
|
250
|
-
|
|
251
|
-
|
|
252
|
-
|
|
229
|
+
if (NUM_USABLE_PMP_ENTRIES > 43 && (CSR[pmpcfg10].pmp43cfg & 0x80) == 0) {
|
|
230
|
+
# entry is usable and not locked
|
|
231
|
+
Bits<8> new_cfg = csr_value.pmp43cfg;
|
|
232
|
+
Bits<2> a_mode = (new_cfg & 0x18) >> 3;
|
|
233
|
+
if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
|
|
234
|
+
# not R = 0, W = 1, which is reserved
|
|
235
|
+
if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
|
|
236
|
+
((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
|
|
237
|
+
((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
|
|
238
|
+
# unsupported address matching mode; keep old value
|
|
239
|
+
return CSR[pmpcfg10].pmp43cfg;
|
|
253
240
|
}
|
|
241
|
+
return new_cfg;
|
|
254
242
|
}
|
|
255
243
|
}
|
|
256
244
|
# fall through: keep old value
|
|
@@ -269,23 +257,15 @@ fields:
|
|
|
269
257
|
! Name ! Location ! Description
|
|
270
258
|
|
|
271
259
|
h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
|
|
272
|
-
h!
|
|
260
|
+
h! MT ! 38:37 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
|
|
273
261
|
h! A ! 36:35
|
|
274
|
-
a! Address matching mode.
|
|
262
|
+
a! Address matching mode. Encodings:
|
|
275
263
|
|
|
276
|
-
[when="PMP_GRANULARITY < 2"]
|
|
277
264
|
* *OFF* (0) - Null region (disabled)
|
|
278
265
|
* *TOR* (1) - Top of range
|
|
279
266
|
* *NA4* (2) - Naturally aligned four-byte region
|
|
280
267
|
* *NAPOT* (3) - Naturally aligned power of two
|
|
281
268
|
|
|
282
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
283
|
-
* *OFF* (0) - Null region (disabled)
|
|
284
|
-
* *TOR* (1) - Top of range
|
|
285
|
-
* *NAPOT* (3) - Naturally aligned power of two
|
|
286
|
-
|
|
287
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
288
|
-
Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
|
|
289
269
|
|
|
290
270
|
h! X ! 34 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
|
|
291
271
|
h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
|
|
@@ -294,23 +274,28 @@ fields:
|
|
|
294
274
|
|
|
295
275
|
The combination of R = 0, W = 1 is reserved.
|
|
296
276
|
type(): |
|
|
297
|
-
if (
|
|
277
|
+
if (NUM_USABLE_PMP_ENTRIES > 44) {
|
|
298
278
|
return CsrFieldType::RWR;
|
|
299
279
|
} else {
|
|
280
|
+
# entry is either not implemented or implemented as read-only zero
|
|
300
281
|
return CsrFieldType::RO;
|
|
301
282
|
}
|
|
302
283
|
reset_value(): |
|
|
303
284
|
return 0;
|
|
304
285
|
sw_write(csr_value): |
|
|
305
|
-
if ((CSR[pmpcfg10].pmp44cfg & 0x80) == 0) {
|
|
306
|
-
# entry is not locked
|
|
307
|
-
|
|
308
|
-
|
|
309
|
-
|
|
310
|
-
|
|
311
|
-
|
|
312
|
-
|
|
286
|
+
if (NUM_USABLE_PMP_ENTRIES > 44 && (CSR[pmpcfg10].pmp44cfg & 0x80) == 0) {
|
|
287
|
+
# entry is usable and not locked
|
|
288
|
+
Bits<8> new_cfg = csr_value.pmp44cfg;
|
|
289
|
+
Bits<2> a_mode = (new_cfg & 0x18) >> 3;
|
|
290
|
+
if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
|
|
291
|
+
# not R = 0, W = 1, which is reserved
|
|
292
|
+
if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
|
|
293
|
+
((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
|
|
294
|
+
((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
|
|
295
|
+
# unsupported address matching mode; keep old value
|
|
296
|
+
return CSR[pmpcfg10].pmp44cfg;
|
|
313
297
|
}
|
|
298
|
+
return new_cfg;
|
|
314
299
|
}
|
|
315
300
|
}
|
|
316
301
|
# fall through: keep old value
|
|
@@ -329,23 +314,15 @@ fields:
|
|
|
329
314
|
! Name ! Location ! Description
|
|
330
315
|
|
|
331
316
|
h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
|
|
332
|
-
h!
|
|
317
|
+
h! MT ! 46:45 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
|
|
333
318
|
h! A ! 44:43
|
|
334
|
-
a! Address matching mode.
|
|
319
|
+
a! Address matching mode. Encodings:
|
|
335
320
|
|
|
336
|
-
[when="PMP_GRANULARITY < 2"]
|
|
337
321
|
* *OFF* (0) - Null region (disabled)
|
|
338
322
|
* *TOR* (1) - Top of range
|
|
339
323
|
* *NA4* (2) - Naturally aligned four-byte region
|
|
340
324
|
* *NAPOT* (3) - Naturally aligned power of two
|
|
341
325
|
|
|
342
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
343
|
-
* *OFF* (0) - Null region (disabled)
|
|
344
|
-
* *TOR* (1) - Top of range
|
|
345
|
-
* *NAPOT* (3) - Naturally aligned power of two
|
|
346
|
-
|
|
347
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
348
|
-
Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
|
|
349
326
|
|
|
350
327
|
h! X ! 42 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
|
|
351
328
|
h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
|
|
@@ -354,23 +331,28 @@ fields:
|
|
|
354
331
|
|
|
355
332
|
The combination of R = 0, W = 1 is reserved.
|
|
356
333
|
type(): |
|
|
357
|
-
if (
|
|
334
|
+
if (NUM_USABLE_PMP_ENTRIES > 45) {
|
|
358
335
|
return CsrFieldType::RWR;
|
|
359
336
|
} else {
|
|
337
|
+
# entry is either not implemented or implemented as read-only zero
|
|
360
338
|
return CsrFieldType::RO;
|
|
361
339
|
}
|
|
362
340
|
reset_value(): |
|
|
363
341
|
return 0;
|
|
364
342
|
sw_write(csr_value): |
|
|
365
|
-
if ((xlen() == 64) && (CSR[pmpcfg10].pmp45cfg & 0x80) == 0) {
|
|
366
|
-
# entry is not locked
|
|
367
|
-
|
|
368
|
-
|
|
369
|
-
|
|
370
|
-
|
|
371
|
-
|
|
372
|
-
|
|
343
|
+
if ((xlen() == 64) && NUM_USABLE_PMP_ENTRIES > 45 && (CSR[pmpcfg10].pmp45cfg & 0x80) == 0) {
|
|
344
|
+
# entry is usable and not locked
|
|
345
|
+
Bits<8> new_cfg = csr_value.pmp45cfg;
|
|
346
|
+
Bits<2> a_mode = (new_cfg & 0x18) >> 3;
|
|
347
|
+
if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
|
|
348
|
+
# not R = 0, W = 1, which is reserved
|
|
349
|
+
if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
|
|
350
|
+
((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
|
|
351
|
+
((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
|
|
352
|
+
# unsupported address matching mode; keep old value
|
|
353
|
+
return CSR[pmpcfg10].pmp45cfg;
|
|
373
354
|
}
|
|
355
|
+
return new_cfg;
|
|
374
356
|
}
|
|
375
357
|
}
|
|
376
358
|
# fall through: keep old value
|
|
@@ -389,23 +371,15 @@ fields:
|
|
|
389
371
|
! Name ! Location ! Description
|
|
390
372
|
|
|
391
373
|
h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
|
|
392
|
-
h!
|
|
374
|
+
h! MT ! 54:53 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
|
|
393
375
|
h! A ! 52:51
|
|
394
|
-
a! Address matching mode.
|
|
376
|
+
a! Address matching mode. Encodings:
|
|
395
377
|
|
|
396
|
-
[when="PMP_GRANULARITY < 2"]
|
|
397
378
|
* *OFF* (0) - Null region (disabled)
|
|
398
379
|
* *TOR* (1) - Top of range
|
|
399
380
|
* *NA4* (2) - Naturally aligned four-byte region
|
|
400
381
|
* *NAPOT* (3) - Naturally aligned power of two
|
|
401
382
|
|
|
402
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
403
|
-
* *OFF* (0) - Null region (disabled)
|
|
404
|
-
* *TOR* (1) - Top of range
|
|
405
|
-
* *NAPOT* (3) - Naturally aligned power of two
|
|
406
|
-
|
|
407
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
408
|
-
Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
|
|
409
383
|
|
|
410
384
|
h! X ! 50 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
|
|
411
385
|
h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
|
|
@@ -414,23 +388,28 @@ fields:
|
|
|
414
388
|
|
|
415
389
|
The combination of R = 0, W = 1 is reserved.
|
|
416
390
|
type(): |
|
|
417
|
-
if (
|
|
391
|
+
if (NUM_USABLE_PMP_ENTRIES > 46) {
|
|
418
392
|
return CsrFieldType::RWR;
|
|
419
393
|
} else {
|
|
394
|
+
# entry is either not implemented or implemented as read-only zero
|
|
420
395
|
return CsrFieldType::RO;
|
|
421
396
|
}
|
|
422
397
|
reset_value(): |
|
|
423
398
|
return 0;
|
|
424
399
|
sw_write(csr_value): |
|
|
425
|
-
if ((xlen() == 64) && (CSR[pmpcfg10].pmp46cfg & 0x80) == 0) {
|
|
426
|
-
# entry is not locked
|
|
427
|
-
|
|
428
|
-
|
|
429
|
-
|
|
430
|
-
|
|
431
|
-
|
|
432
|
-
|
|
400
|
+
if ((xlen() == 64) && NUM_USABLE_PMP_ENTRIES > 46 && (CSR[pmpcfg10].pmp46cfg & 0x80) == 0) {
|
|
401
|
+
# entry is usable and not locked
|
|
402
|
+
Bits<8> new_cfg = csr_value.pmp46cfg;
|
|
403
|
+
Bits<2> a_mode = (new_cfg & 0x18) >> 3;
|
|
404
|
+
if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
|
|
405
|
+
# not R = 0, W = 1, which is reserved
|
|
406
|
+
if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
|
|
407
|
+
((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
|
|
408
|
+
((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
|
|
409
|
+
# unsupported address matching mode; keep old value
|
|
410
|
+
return CSR[pmpcfg10].pmp46cfg;
|
|
433
411
|
}
|
|
412
|
+
return new_cfg;
|
|
434
413
|
}
|
|
435
414
|
}
|
|
436
415
|
# fall through: keep old value
|
|
@@ -449,23 +428,15 @@ fields:
|
|
|
449
428
|
! Name ! Location ! Description
|
|
450
429
|
|
|
451
430
|
h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
|
|
452
|
-
h!
|
|
431
|
+
h! MT ! 62:61 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
|
|
453
432
|
h! A ! 60:59
|
|
454
|
-
a! Address matching mode.
|
|
433
|
+
a! Address matching mode. Encodings:
|
|
455
434
|
|
|
456
|
-
[when="PMP_GRANULARITY < 2"]
|
|
457
435
|
* *OFF* (0) - Null region (disabled)
|
|
458
436
|
* *TOR* (1) - Top of range
|
|
459
437
|
* *NA4* (2) - Naturally aligned four-byte region
|
|
460
438
|
* *NAPOT* (3) - Naturally aligned power of two
|
|
461
439
|
|
|
462
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
463
|
-
* *OFF* (0) - Null region (disabled)
|
|
464
|
-
* *TOR* (1) - Top of range
|
|
465
|
-
* *NAPOT* (3) - Naturally aligned power of two
|
|
466
|
-
|
|
467
|
-
[when="PMP_GRANULARITY >= 2"]
|
|
468
|
-
Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
|
|
469
440
|
|
|
470
441
|
h! X ! 58 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
|
|
471
442
|
h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
|
|
@@ -474,23 +445,28 @@ fields:
|
|
|
474
445
|
|
|
475
446
|
The combination of R = 0, W = 1 is reserved.
|
|
476
447
|
type(): |
|
|
477
|
-
if (
|
|
448
|
+
if (NUM_USABLE_PMP_ENTRIES > 47) {
|
|
478
449
|
return CsrFieldType::RWR;
|
|
479
450
|
} else {
|
|
451
|
+
# entry is either not implemented or implemented as read-only zero
|
|
480
452
|
return CsrFieldType::RO;
|
|
481
453
|
}
|
|
482
454
|
reset_value(): |
|
|
483
455
|
return 0;
|
|
484
456
|
sw_write(csr_value): |
|
|
485
|
-
if ((xlen() == 64) && (CSR[pmpcfg10].pmp47cfg & 0x80) == 0) {
|
|
486
|
-
# entry is not locked
|
|
487
|
-
|
|
488
|
-
|
|
489
|
-
|
|
490
|
-
|
|
491
|
-
|
|
492
|
-
|
|
457
|
+
if ((xlen() == 64) && NUM_USABLE_PMP_ENTRIES > 47 && (CSR[pmpcfg10].pmp47cfg & 0x80) == 0) {
|
|
458
|
+
# entry is usable and not locked
|
|
459
|
+
Bits<8> new_cfg = csr_value.pmp47cfg;
|
|
460
|
+
Bits<2> a_mode = (new_cfg & 0x18) >> 3;
|
|
461
|
+
if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
|
|
462
|
+
# not R = 0, W = 1, which is reserved
|
|
463
|
+
if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
|
|
464
|
+
((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
|
|
465
|
+
((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
|
|
466
|
+
# unsupported address matching mode; keep old value
|
|
467
|
+
return CSR[pmpcfg10].pmp47cfg;
|
|
493
468
|
}
|
|
469
|
+
return new_cfg;
|
|
494
470
|
}
|
|
495
471
|
}
|
|
496
472
|
# fall through: keep old value
|