crabstone 3.0.3 → 4.0.4

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (347) hide show
  1. checksums.yaml +5 -5
  2. data/CHANGES.md +59 -42
  3. data/README.md +37 -39
  4. data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
  5. data/lib/crabstone/arch/3/arm64.rb +124 -0
  6. data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
  7. data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
  8. data/lib/crabstone/arch/3/mips.rb +57 -0
  9. data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
  10. data/lib/crabstone/arch/3/ppc.rb +73 -0
  11. data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
  12. data/lib/crabstone/arch/3/sparc.rb +60 -0
  13. data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
  14. data/lib/crabstone/arch/3/sysz.rb +67 -0
  15. data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
  16. data/lib/crabstone/arch/3/x86.rb +82 -0
  17. data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
  18. data/lib/crabstone/arch/3/xcore.rb +59 -0
  19. data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
  20. data/lib/crabstone/arch/4/arm.rb +110 -0
  21. data/lib/crabstone/arch/4/arm64.rb +125 -0
  22. data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
  23. data/lib/crabstone/arch/4/arm_const.rb +785 -0
  24. data/lib/crabstone/arch/4/evm.rb +20 -0
  25. data/lib/crabstone/arch/4/evm_const.rb +161 -0
  26. data/lib/crabstone/arch/4/m680x.rb +106 -0
  27. data/lib/crabstone/arch/4/m680x_const.rb +426 -0
  28. data/lib/crabstone/arch/4/m68k.rb +129 -0
  29. data/lib/crabstone/arch/4/m68k_const.rb +496 -0
  30. data/lib/crabstone/arch/4/mips.rb +57 -0
  31. data/lib/crabstone/arch/4/mips_const.rb +869 -0
  32. data/lib/crabstone/arch/4/ppc.rb +73 -0
  33. data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
  34. data/lib/crabstone/arch/4/sparc.rb +60 -0
  35. data/lib/crabstone/arch/4/sparc_const.rb +439 -0
  36. data/lib/crabstone/arch/4/sysz.rb +67 -0
  37. data/lib/crabstone/arch/4/sysz_const.rb +763 -0
  38. data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
  39. data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
  40. data/lib/crabstone/arch/4/x86.rb +91 -0
  41. data/lib/crabstone/arch/4/x86_const.rb +1972 -0
  42. data/lib/crabstone/arch/4/xcore.rb +59 -0
  43. data/lib/crabstone/arch/4/xcore_const.rb +171 -0
  44. data/lib/crabstone/arch/extension.rb +27 -0
  45. data/lib/crabstone/arch/register.rb +34 -0
  46. data/lib/crabstone/arch.rb +37 -0
  47. data/lib/crabstone/binding/3/detail.rb +36 -0
  48. data/lib/crabstone/binding/3/instruction.rb +23 -0
  49. data/lib/crabstone/binding/4/detail.rb +40 -0
  50. data/lib/crabstone/binding/4/instruction.rb +23 -0
  51. data/lib/crabstone/binding/structs.rb +32 -0
  52. data/lib/crabstone/binding.rb +59 -0
  53. data/lib/crabstone/constants.rb +110 -0
  54. data/lib/crabstone/cs_version.rb +57 -0
  55. data/lib/crabstone/disassembler.rb +147 -0
  56. data/lib/crabstone/error.rb +74 -0
  57. data/lib/crabstone/instruction.rb +178 -0
  58. data/lib/crabstone/version.rb +5 -0
  59. data/lib/crabstone.rb +5 -557
  60. metadata +142 -331
  61. data/MANIFEST +0 -312
  62. data/Rakefile +0 -27
  63. data/bin/genconst +0 -66
  64. data/bin/genreg +0 -99
  65. data/crabstone.gemspec +0 -27
  66. data/examples/hello_world.rb +0 -43
  67. data/lib/arch/arm64.rb +0 -167
  68. data/lib/arch/arm64_registers.rb +0 -295
  69. data/lib/arch/arm_registers.rb +0 -149
  70. data/lib/arch/mips.rb +0 -78
  71. data/lib/arch/mips_registers.rb +0 -208
  72. data/lib/arch/ppc.rb +0 -90
  73. data/lib/arch/ppc_registers.rb +0 -209
  74. data/lib/arch/sparc.rb +0 -79
  75. data/lib/arch/sparc_registers.rb +0 -121
  76. data/lib/arch/systemz.rb +0 -79
  77. data/lib/arch/sysz_registers.rb +0 -66
  78. data/lib/arch/x86.rb +0 -107
  79. data/lib/arch/x86_registers.rb +0 -265
  80. data/lib/arch/xcore.rb +0 -78
  81. data/lib/arch/xcore_registers.rb +0 -57
  82. data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
  83. data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
  84. data/test/MC/AArch64/neon-2velem.s.cs +0 -113
  85. data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
  86. data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
  87. data/test/MC/AArch64/neon-across.s.cs +0 -40
  88. data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
  89. data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
  90. data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
  91. data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
  92. data/test/MC/AArch64/neon-crypto.s.cs +0 -15
  93. data/test/MC/AArch64/neon-extract.s.cs +0 -3
  94. data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
  95. data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
  96. data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
  97. data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
  98. data/test/MC/AArch64/neon-max-min.s.cs +0 -37
  99. data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
  100. data/test/MC/AArch64/neon-mov.s.cs +0 -74
  101. data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
  102. data/test/MC/AArch64/neon-perm.s.cs +0 -43
  103. data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
  104. data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
  105. data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
  106. data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
  107. data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
  108. data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
  109. data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
  110. data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
  111. data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
  112. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
  113. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
  114. data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
  115. data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
  116. data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
  117. data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
  118. data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
  119. data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
  120. data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
  121. data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
  122. data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
  123. data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
  124. data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
  125. data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
  126. data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
  127. data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
  128. data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
  129. data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
  130. data/test/MC/AArch64/neon-shift.s.cs +0 -22
  131. data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
  132. data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
  133. data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
  134. data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
  135. data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
  136. data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
  137. data/test/MC/AArch64/neon-tbl.s.cs +0 -21
  138. data/test/MC/AArch64/trace-regs.s.cs +0 -383
  139. data/test/MC/ARM/arm-aliases.s.cs +0 -7
  140. data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
  141. data/test/MC/ARM/arm-it-block.s.cs +0 -2
  142. data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
  143. data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
  144. data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
  145. data/test/MC/ARM/arm-trustzone.s.cs +0 -3
  146. data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
  147. data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
  148. data/test/MC/ARM/arm_instructions.s.cs +0 -25
  149. data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
  150. data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
  151. data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
  152. data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
  153. data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
  154. data/test/MC/ARM/crc32-thumb.s.cs +0 -7
  155. data/test/MC/ARM/crc32.s.cs +0 -7
  156. data/test/MC/ARM/dot-req.s.cs +0 -3
  157. data/test/MC/ARM/fp-armv8.s.cs +0 -52
  158. data/test/MC/ARM/idiv-thumb.s.cs +0 -3
  159. data/test/MC/ARM/idiv.s.cs +0 -3
  160. data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
  161. data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
  162. data/test/MC/ARM/mode-switch.s.cs +0 -7
  163. data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
  164. data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
  165. data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
  166. data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
  167. data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
  168. data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
  169. data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
  170. data/test/MC/ARM/neon-crypto.s.cs +0 -16
  171. data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
  172. data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
  173. data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
  174. data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
  175. data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
  176. data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
  177. data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
  178. data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
  179. data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
  180. data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
  181. data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
  182. data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
  183. data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
  184. data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
  185. data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
  186. data/test/MC/ARM/neon-v8.s.cs +0 -38
  187. data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
  188. data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
  189. data/test/MC/ARM/neon-vswp.s.cs +0 -3
  190. data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
  191. data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
  192. data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
  193. data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
  194. data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
  195. data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
  196. data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
  197. data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
  198. data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
  199. data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
  200. data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
  201. data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
  202. data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
  203. data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
  204. data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
  205. data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
  206. data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
  207. data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
  208. data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
  209. data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
  210. data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
  211. data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
  212. data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
  213. data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
  214. data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
  215. data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
  216. data/test/MC/ARM/thumb-hints.s.cs +0 -12
  217. data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
  218. data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
  219. data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
  220. data/test/MC/ARM/thumb.s.cs +0 -19
  221. data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
  222. data/test/MC/ARM/thumb2-branches.s.cs +0 -85
  223. data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
  224. data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
  225. data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
  226. data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
  227. data/test/MC/ARM/vfp4.s.cs +0 -13
  228. data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
  229. data/test/MC/ARM/vpush-vpop.s.cs +0 -9
  230. data/test/MC/Mips/hilo-addressing.s.cs +0 -4
  231. data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
  232. data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
  233. data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
  234. data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
  235. data/test/MC/Mips/micromips-expansions.s.cs +0 -20
  236. data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
  237. data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
  238. data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
  239. data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
  240. data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
  241. data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
  242. data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
  243. data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
  244. data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
  245. data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
  246. data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
  247. data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
  248. data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
  249. data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
  250. data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
  251. data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
  252. data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
  253. data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
  254. data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
  255. data/test/MC/Mips/mips-expansions.s.cs +0 -20
  256. data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
  257. data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
  258. data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
  259. data/test/MC/Mips/mips-register-names.s.cs +0 -33
  260. data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
  261. data/test/MC/Mips/mips64-instructions.s.cs +0 -3
  262. data/test/MC/Mips/mips64-register-names.s.cs +0 -33
  263. data/test/MC/Mips/mips_directives.s.cs +0 -12
  264. data/test/MC/Mips/nabi-regs.s.cs +0 -12
  265. data/test/MC/Mips/set-at-directive.s.cs +0 -6
  266. data/test/MC/Mips/test_2r.s.cs +0 -16
  267. data/test/MC/Mips/test_2rf.s.cs +0 -33
  268. data/test/MC/Mips/test_3r.s.cs +0 -243
  269. data/test/MC/Mips/test_3rf.s.cs +0 -83
  270. data/test/MC/Mips/test_bit.s.cs +0 -49
  271. data/test/MC/Mips/test_cbranch.s.cs +0 -11
  272. data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
  273. data/test/MC/Mips/test_elm.s.cs +0 -16
  274. data/test/MC/Mips/test_elm_insert.s.cs +0 -4
  275. data/test/MC/Mips/test_elm_insve.s.cs +0 -5
  276. data/test/MC/Mips/test_i10.s.cs +0 -5
  277. data/test/MC/Mips/test_i5.s.cs +0 -45
  278. data/test/MC/Mips/test_i8.s.cs +0 -11
  279. data/test/MC/Mips/test_lsa.s.cs +0 -5
  280. data/test/MC/Mips/test_mi10.s.cs +0 -24
  281. data/test/MC/Mips/test_vec.s.cs +0 -8
  282. data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
  283. data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
  284. data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
  285. data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
  286. data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
  287. data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
  288. data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
  289. data/test/MC/README +0 -6
  290. data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
  291. data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
  292. data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
  293. data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
  294. data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
  295. data/test/MC/Sparc/sparc-vis.s.cs +0 -2
  296. data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
  297. data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
  298. data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
  299. data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
  300. data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
  301. data/test/MC/SystemZ/insn-good.s.cs +0 -2265
  302. data/test/MC/SystemZ/regs-good.s.cs +0 -45
  303. data/test/MC/X86/3DNow.s.cs +0 -29
  304. data/test/MC/X86/address-size.s.cs +0 -5
  305. data/test/MC/X86/avx512-encodings.s.cs +0 -12
  306. data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
  307. data/test/MC/X86/x86-32-avx.s.cs +0 -833
  308. data/test/MC/X86/x86-32-fma3.s.cs +0 -169
  309. data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
  310. data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
  311. data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
  312. data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
  313. data/test/MC/X86/x86_64-encoding.s.cs +0 -59
  314. data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
  315. data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
  316. data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
  317. data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
  318. data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
  319. data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
  320. data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
  321. data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
  322. data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
  323. data/test/README +0 -6
  324. data/test/test.rb +0 -205
  325. data/test/test.rb.SPEC +0 -235
  326. data/test/test_arm.rb +0 -202
  327. data/test/test_arm.rb.SPEC +0 -275
  328. data/test/test_arm64.rb +0 -150
  329. data/test/test_arm64.rb.SPEC +0 -116
  330. data/test/test_detail.rb +0 -228
  331. data/test/test_detail.rb.SPEC +0 -322
  332. data/test/test_exhaustive.rb +0 -80
  333. data/test/test_mips.rb +0 -118
  334. data/test/test_mips.rb.SPEC +0 -91
  335. data/test/test_ppc.rb +0 -137
  336. data/test/test_ppc.rb.SPEC +0 -84
  337. data/test/test_sanity.rb +0 -83
  338. data/test/test_skipdata.rb +0 -111
  339. data/test/test_skipdata.rb.SPEC +0 -58
  340. data/test/test_sparc.rb +0 -113
  341. data/test/test_sparc.rb.SPEC +0 -116
  342. data/test/test_sysz.rb +0 -111
  343. data/test/test_sysz.rb.SPEC +0 -61
  344. data/test/test_x86.rb +0 -189
  345. data/test/test_x86.rb.SPEC +0 -579
  346. data/test/test_xcore.rb +0 -100
  347. data/test/test_xcore.rb.SPEC +0 -75
data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs DELETED
@@ -1,170 +0,0 @@
1
- # CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME
2
- 0x7c,0x43,0x20,0x0e = lvebx 2, 3, 4
3
- 0x7c,0x43,0x20,0x4e = lvehx 2, 3, 4
4
- 0x7c,0x43,0x20,0x8e = lvewx 2, 3, 4
5
- 0x7c,0x43,0x20,0xce = lvx 2, 3, 4
6
- 0x7c,0x43,0x22,0xce = lvxl 2, 3, 4
7
- 0x7c,0x43,0x21,0x0e = stvebx 2, 3, 4
8
- 0x7c,0x43,0x21,0x4e = stvehx 2, 3, 4
9
- 0x7c,0x43,0x21,0x8e = stvewx 2, 3, 4
10
- 0x7c,0x43,0x21,0xce = stvx 2, 3, 4
11
- 0x7c,0x43,0x23,0xce = stvxl 2, 3, 4
12
- 0x7c,0x43,0x20,0x0c = lvsl 2, 3, 4
13
- 0x7c,0x43,0x20,0x4c = lvsr 2, 3, 4
14
- 0x10,0x43,0x23,0x0e = vpkpx 2, 3, 4
15
- 0x10,0x43,0x21,0x8e = vpkshss 2, 3, 4
16
- 0x10,0x43,0x21,0x0e = vpkshus 2, 3, 4
17
- 0x10,0x43,0x21,0xce = vpkswss 2, 3, 4
18
- 0x10,0x43,0x21,0x4e = vpkswus 2, 3, 4
19
- 0x10,0x43,0x20,0x0e = vpkuhum 2, 3, 4
20
- 0x10,0x43,0x20,0x8e = vpkuhus 2, 3, 4
21
- 0x10,0x43,0x20,0x4e = vpkuwum 2, 3, 4
22
- 0x10,0x43,0x20,0xce = vpkuwus 2, 3, 4
23
- 0x10,0x40,0x1b,0x4e = vupkhpx 2, 3
24
- 0x10,0x40,0x1a,0x0e = vupkhsb 2, 3
25
- 0x10,0x40,0x1a,0x4e = vupkhsh 2, 3
26
- 0x10,0x40,0x1b,0xce = vupklpx 2, 3
27
- 0x10,0x40,0x1a,0x8e = vupklsb 2, 3
28
- 0x10,0x40,0x1a,0xce = vupklsh 2, 3
29
- 0x10,0x43,0x20,0x0c = vmrghb 2, 3, 4
30
- 0x10,0x43,0x20,0x4c = vmrghh 2, 3, 4
31
- 0x10,0x43,0x20,0x8c = vmrghw 2, 3, 4
32
- 0x10,0x43,0x21,0x0c = vmrglb 2, 3, 4
33
- 0x10,0x43,0x21,0x4c = vmrglh 2, 3, 4
34
- 0x10,0x43,0x21,0x8c = vmrglw 2, 3, 4
35
- 0x10,0x41,0x1a,0x0c = vspltb 2, 3, 1
36
- 0x10,0x41,0x1a,0x4c = vsplth 2, 3, 1
37
- 0x10,0x41,0x1a,0x8c = vspltw 2, 3, 1
38
- 0x10,0x43,0x03,0x0c = vspltisb 2, 3
39
- 0x10,0x43,0x03,0x4c = vspltish 2, 3
40
- 0x10,0x43,0x03,0x8c = vspltisw 2, 3
41
- 0x10,0x43,0x21,0x6b = vperm 2, 3, 4, 5
42
- 0x10,0x43,0x21,0x6a = vsel 2, 3, 4, 5
43
- 0x10,0x43,0x21,0xc4 = vsl 2, 3, 4
44
- 0x10,0x43,0x21,0x6c = vsldoi 2, 3, 4, 5
45
- 0x10,0x43,0x24,0x0c = vslo 2, 3, 4
46
- 0x10,0x43,0x22,0xc4 = vsr 2, 3, 4
47
- 0x10,0x43,0x24,0x4c = vsro 2, 3, 4
48
- 0x10,0x43,0x21,0x80 = vaddcuw 2, 3, 4
49
- 0x10,0x43,0x23,0x00 = vaddsbs 2, 3, 4
50
- 0x10,0x43,0x23,0x40 = vaddshs 2, 3, 4
51
- 0x10,0x43,0x23,0x80 = vaddsws 2, 3, 4
52
- 0x10,0x43,0x20,0x00 = vaddubm 2, 3, 4
53
- 0x10,0x43,0x20,0x40 = vadduhm 2, 3, 4
54
- 0x10,0x43,0x20,0x80 = vadduwm 2, 3, 4
55
- 0x10,0x43,0x22,0x00 = vaddubs 2, 3, 4
56
- 0x10,0x43,0x22,0x40 = vadduhs 2, 3, 4
57
- 0x10,0x43,0x22,0x80 = vadduws 2, 3, 4
58
- 0x10,0x43,0x25,0x80 = vsubcuw 2, 3, 4
59
- 0x10,0x43,0x27,0x00 = vsubsbs 2, 3, 4
60
- 0x10,0x43,0x27,0x40 = vsubshs 2, 3, 4
61
- 0x10,0x43,0x27,0x80 = vsubsws 2, 3, 4
62
- 0x10,0x43,0x24,0x00 = vsububm 2, 3, 4
63
- 0x10,0x43,0x24,0x40 = vsubuhm 2, 3, 4
64
- 0x10,0x43,0x24,0x80 = vsubuwm 2, 3, 4
65
- 0x10,0x43,0x26,0x00 = vsububs 2, 3, 4
66
- 0x10,0x43,0x26,0x40 = vsubuhs 2, 3, 4
67
- 0x10,0x43,0x26,0x80 = vsubuws 2, 3, 4
68
- 0x10,0x43,0x23,0x08 = vmulesb 2, 3, 4
69
- 0x10,0x43,0x23,0x48 = vmulesh 2, 3, 4
70
- 0x10,0x43,0x22,0x08 = vmuleub 2, 3, 4
71
- 0x10,0x43,0x22,0x48 = vmuleuh 2, 3, 4
72
- 0x10,0x43,0x21,0x08 = vmulosb 2, 3, 4
73
- 0x10,0x43,0x21,0x48 = vmulosh 2, 3, 4
74
- 0x10,0x43,0x20,0x08 = vmuloub 2, 3, 4
75
- 0x10,0x43,0x20,0x48 = vmulouh 2, 3, 4
76
- 0x10,0x43,0x21,0x60 = vmhaddshs 2, 3, 4, 5
77
- 0x10,0x43,0x21,0x61 = vmhraddshs 2, 3, 4, 5
78
- 0x10,0x43,0x21,0x62 = vmladduhm 2, 3, 4, 5
79
- 0x10,0x43,0x21,0x64 = vmsumubm 2, 3, 4, 5
80
- 0x10,0x43,0x21,0x65 = vmsummbm 2, 3, 4, 5
81
- 0x10,0x43,0x21,0x68 = vmsumshm 2, 3, 4, 5
82
- 0x10,0x43,0x21,0x69 = vmsumshs 2, 3, 4, 5
83
- 0x10,0x43,0x21,0x66 = vmsumuhm 2, 3, 4, 5
84
- 0x10,0x43,0x21,0x67 = vmsumuhs 2, 3, 4, 5
85
- 0x10,0x43,0x27,0x88 = vsumsws 2, 3, 4
86
- 0x10,0x43,0x26,0x88 = vsum2sws 2, 3, 4
87
- 0x10,0x43,0x27,0x08 = vsum4sbs 2, 3, 4
88
- 0x10,0x43,0x26,0x48 = vsum4shs 2, 3, 4
89
- 0x10,0x43,0x26,0x08 = vsum4ubs 2, 3, 4
90
- 0x10,0x43,0x25,0x02 = vavgsb 2, 3, 4
91
- 0x10,0x43,0x25,0x42 = vavgsh 2, 3, 4
92
- 0x10,0x43,0x25,0x82 = vavgsw 2, 3, 4
93
- 0x10,0x43,0x24,0x02 = vavgub 2, 3, 4
94
- 0x10,0x43,0x24,0x42 = vavguh 2, 3, 4
95
- 0x10,0x43,0x24,0x82 = vavguw 2, 3, 4
96
- 0x10,0x43,0x21,0x02 = vmaxsb 2, 3, 4
97
- 0x10,0x43,0x21,0x42 = vmaxsh 2, 3, 4
98
- 0x10,0x43,0x21,0x82 = vmaxsw 2, 3, 4
99
- 0x10,0x43,0x20,0x02 = vmaxub 2, 3, 4
100
- 0x10,0x43,0x20,0x42 = vmaxuh 2, 3, 4
101
- 0x10,0x43,0x20,0x82 = vmaxuw 2, 3, 4
102
- 0x10,0x43,0x23,0x02 = vminsb 2, 3, 4
103
- 0x10,0x43,0x23,0x42 = vminsh 2, 3, 4
104
- 0x10,0x43,0x23,0x82 = vminsw 2, 3, 4
105
- 0x10,0x43,0x22,0x02 = vminub 2, 3, 4
106
- 0x10,0x43,0x22,0x42 = vminuh 2, 3, 4
107
- 0x10,0x43,0x22,0x82 = vminuw 2, 3, 4
108
- 0x10,0x43,0x20,0x06 = vcmpequb 2, 3, 4
109
- 0x10,0x43,0x24,0x06 = vcmpequb. 2, 3, 4
110
- 0x10,0x43,0x20,0x46 = vcmpequh 2, 3, 4
111
- 0x10,0x43,0x24,0x46 = vcmpequh. 2, 3, 4
112
- 0x10,0x43,0x20,0x86 = vcmpequw 2, 3, 4
113
- 0x10,0x43,0x24,0x86 = vcmpequw. 2, 3, 4
114
- 0x10,0x43,0x23,0x06 = vcmpgtsb 2, 3, 4
115
- 0x10,0x43,0x27,0x06 = vcmpgtsb. 2, 3, 4
116
- 0x10,0x43,0x23,0x46 = vcmpgtsh 2, 3, 4
117
- 0x10,0x43,0x27,0x46 = vcmpgtsh. 2, 3, 4
118
- 0x10,0x43,0x23,0x86 = vcmpgtsw 2, 3, 4
119
- 0x10,0x43,0x27,0x86 = vcmpgtsw. 2, 3, 4
120
- 0x10,0x43,0x22,0x06 = vcmpgtub 2, 3, 4
121
- 0x10,0x43,0x26,0x06 = vcmpgtub. 2, 3, 4
122
- 0x10,0x43,0x22,0x46 = vcmpgtuh 2, 3, 4
123
- 0x10,0x43,0x26,0x46 = vcmpgtuh. 2, 3, 4
124
- 0x10,0x43,0x22,0x86 = vcmpgtuw 2, 3, 4
125
- 0x10,0x43,0x26,0x86 = vcmpgtuw. 2, 3, 4
126
- 0x10,0x43,0x24,0x04 = vand 2, 3, 4
127
- 0x10,0x43,0x24,0x44 = vandc 2, 3, 4
128
- 0x10,0x43,0x25,0x04 = vnor 2, 3, 4
129
- 0x10,0x43,0x24,0x84 = vor 2, 3, 4
130
- 0x10,0x43,0x24,0xc4 = vxor 2, 3, 4
131
- 0x10,0x43,0x20,0x04 = vrlb 2, 3, 4
132
- 0x10,0x43,0x20,0x44 = vrlh 2, 3, 4
133
- 0x10,0x43,0x20,0x84 = vrlw 2, 3, 4
134
- 0x10,0x43,0x21,0x04 = vslb 2, 3, 4
135
- 0x10,0x43,0x21,0x44 = vslh 2, 3, 4
136
- 0x10,0x43,0x21,0x84 = vslw 2, 3, 4
137
- 0x10,0x43,0x22,0x04 = vsrb 2, 3, 4
138
- 0x10,0x43,0x22,0x44 = vsrh 2, 3, 4
139
- 0x10,0x43,0x22,0x84 = vsrw 2, 3, 4
140
- 0x10,0x43,0x23,0x04 = vsrab 2, 3, 4
141
- 0x10,0x43,0x23,0x44 = vsrah 2, 3, 4
142
- 0x10,0x43,0x23,0x84 = vsraw 2, 3, 4
143
- 0x10,0x43,0x20,0x0a = vaddfp 2, 3, 4
144
- 0x10,0x43,0x20,0x4a = vsubfp 2, 3, 4
145
- 0x10,0x43,0x29,0x2e = vmaddfp 2, 3, 4, 5
146
- 0x10,0x43,0x29,0x2f = vnmsubfp 2, 3, 4, 5
147
- 0x10,0x43,0x24,0x0a = vmaxfp 2, 3, 4
148
- 0x10,0x43,0x24,0x4a = vminfp 2, 3, 4
149
- 0x10,0x44,0x1b,0xca = vctsxs 2, 3, 4
150
- 0x10,0x44,0x1b,0x8a = vctuxs 2, 3, 4
151
- 0x10,0x44,0x1b,0x4a = vcfsx 2, 3, 4
152
- 0x10,0x44,0x1b,0x0a = vcfux 2, 3, 4
153
- 0x10,0x40,0x1a,0xca = vrfim 2, 3
154
- 0x10,0x40,0x1a,0x0a = vrfin 2, 3
155
- 0x10,0x40,0x1a,0x8a = vrfip 2, 3
156
- 0x10,0x40,0x1a,0x4a = vrfiz 2, 3
157
- 0x10,0x43,0x23,0xc6 = vcmpbfp 2, 3, 4
158
- 0x10,0x43,0x27,0xc6 = vcmpbfp. 2, 3, 4
159
- 0x10,0x43,0x20,0xc6 = vcmpeqfp 2, 3, 4
160
- 0x10,0x43,0x24,0xc6 = vcmpeqfp. 2, 3, 4
161
- 0x10,0x43,0x21,0xc6 = vcmpgefp 2, 3, 4
162
- 0x10,0x43,0x25,0xc6 = vcmpgefp. 2, 3, 4
163
- 0x10,0x43,0x22,0xc6 = vcmpgtfp 2, 3, 4
164
- 0x10,0x43,0x26,0xc6 = vcmpgtfp. 2, 3, 4
165
- 0x10,0x40,0x19,0x8a = vexptefp 2, 3
166
- 0x10,0x40,0x19,0xca = vlogefp 2, 3
167
- 0x10,0x40,0x19,0x0a = vrefp 2, 3
168
- 0x10,0x40,0x19,0x4a = vrsqrtefp 2, 3
169
- 0x10,0x00,0x16,0x44 = mtvscr 2
170
- 0x10,0x40,0x06,0x04 = mfvscr 2
data/test/MC/PowerPC/ppc64-encoding.s.cs DELETED
@@ -1,202 +0,0 @@
1
- # CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME
2
- 0x4c,0x8a,0x18,0x20 = bclr 4, 10, 3
3
- 0x4c,0x8a,0x00,0x20 = bclr 4, 10, 0
4
- 0x4c,0x8a,0x18,0x21 = bclrl 4, 10, 3
5
- 0x4c,0x8a,0x00,0x21 = bclrl 4, 10, 0
6
- 0x4c,0x8a,0x1c,0x20 = bcctr 4, 10, 3
7
- 0x4c,0x8a,0x04,0x20 = bcctr 4, 10, 0
8
- 0x4c,0x8a,0x1c,0x21 = bcctrl 4, 10, 3
9
- 0x4c,0x8a,0x04,0x21 = bcctrl 4, 10, 0
10
- 0x4c,0x43,0x22,0x02 = crand 2, 3, 4
11
- 0x4c,0x43,0x21,0xc2 = crnand 2, 3, 4
12
- 0x4c,0x43,0x23,0x82 = cror 2, 3, 4
13
- 0x4c,0x43,0x21,0x82 = crxor 2, 3, 4
14
- 0x4c,0x43,0x20,0x42 = crnor 2, 3, 4
15
- 0x4c,0x43,0x22,0x42 = creqv 2, 3, 4
16
- 0x4c,0x43,0x21,0x02 = crandc 2, 3, 4
17
- 0x4c,0x43,0x23,0x42 = crorc 2, 3, 4
18
- 0x4d,0x0c,0x00,0x00 = mcrf 2, 3
19
- 0x44,0x00,0x00,0x22 = sc 1
20
- 0x44,0x00,0x00,0x02 = sc 0
21
- 0x88,0x44,0x00,0x80 = lbz 2, 128(4)
22
- 0x7c,0x43,0x20,0xae = lbzx 2, 3, 4
23
- 0x8c,0x44,0x00,0x80 = lbzu 2, 128(4)
24
- 0x7c,0x43,0x20,0xee = lbzux 2, 3, 4
25
- 0xa0,0x44,0x00,0x80 = lhz 2, 128(4)
26
- 0x7c,0x43,0x22,0x2e = lhzx 2, 3, 4
27
- 0xa4,0x44,0x00,0x80 = lhzu 2, 128(4)
28
- 0x7c,0x43,0x22,0x6e = lhzux 2, 3, 4
29
- 0xa8,0x44,0x00,0x80 = lha 2, 128(4)
30
- 0x7c,0x43,0x22,0xae = lhax 2, 3, 4
31
- 0xac,0x44,0x00,0x80 = lhau 2, 128(4)
32
- 0x7c,0x43,0x22,0xee = lhaux 2, 3, 4
33
- 0x80,0x44,0x00,0x80 = lwz 2, 128(4)
34
- 0x7c,0x43,0x20,0x2e = lwzx 2, 3, 4
35
- 0x84,0x44,0x00,0x80 = lwzu 2, 128(4)
36
- 0x7c,0x43,0x20,0x6e = lwzux 2, 3, 4
37
- 0xe8,0x44,0x00,0x82 = lwa 2, 128(4)
38
- 0x7c,0x43,0x22,0xaa = lwax 2, 3, 4
39
- 0x7c,0x43,0x22,0xea = lwaux 2, 3, 4
40
- 0xe8,0x44,0x00,0x80 = ld 2, 128(4)
41
- 0x7c,0x43,0x20,0x2a = ldx 2, 3, 4
42
- 0xe8,0x44,0x00,0x81 = ldu 2, 128(4)
43
- 0x7c,0x43,0x20,0x6a = ldux 2, 3, 4
44
- 0x98,0x44,0x00,0x80 = stb 2, 128(4)
45
- 0x7c,0x43,0x21,0xae = stbx 2, 3, 4
46
- 0x9c,0x44,0x00,0x80 = stbu 2, 128(4)
47
- 0x7c,0x43,0x21,0xee = stbux 2, 3, 4
48
- 0xb0,0x44,0x00,0x80 = sth 2, 128(4)
49
- 0x7c,0x43,0x23,0x2e = sthx 2, 3, 4
50
- 0xb4,0x44,0x00,0x80 = sthu 2, 128(4)
51
- 0x7c,0x43,0x23,0x6e = sthux 2, 3, 4
52
- 0x90,0x44,0x00,0x80 = stw 2, 128(4)
53
- 0x7c,0x43,0x21,0x2e = stwx 2, 3, 4
54
- 0x94,0x44,0x00,0x80 = stwu 2, 128(4)
55
- 0x7c,0x43,0x21,0x6e = stwux 2, 3, 4
56
- 0xf8,0x44,0x00,0x80 = std 2, 128(4)
57
- 0x7c,0x43,0x21,0x2a = stdx 2, 3, 4
58
- 0xf8,0x44,0x00,0x81 = stdu 2, 128(4)
59
- 0x7c,0x43,0x21,0x6a = stdux 2, 3, 4
60
- 0x7c,0x43,0x26,0x2c = lhbrx 2, 3, 4
61
- 0x7c,0x43,0x27,0x2c = sthbrx 2, 3, 4
62
- 0x7c,0x43,0x24,0x2c = lwbrx 2, 3, 4
63
- 0x7c,0x43,0x25,0x2c = stwbrx 2, 3, 4
64
- 0x7c,0x43,0x24,0x28 = ldbrx 2, 3, 4
65
- 0x7c,0x43,0x25,0x28 = stdbrx 2, 3, 4
66
- 0xb8,0x41,0x00,0x80 = lmw 2, 128(1)
67
- 0xbc,0x41,0x00,0x80 = stmw 2, 128(1)
68
- 0x38,0x43,0x00,0x80 = addi 2, 3, 128
69
- 0x3c,0x43,0x00,0x80 = addis 2, 3, 128
70
- 0x7c,0x43,0x22,0x14 = add 2, 3, 4
71
- 0x7c,0x43,0x22,0x15 = add. 2, 3, 4
72
- 0x7c,0x43,0x20,0x50 = subf 2, 3, 4
73
- 0x7c,0x43,0x20,0x51 = subf. 2, 3, 4
74
- 0x30,0x43,0x00,0x80 = addic 2, 3, 128
75
- 0x34,0x43,0x00,0x80 = addic. 2, 3, 128
76
- 0x20,0x43,0x00,0x04 = subfic 2, 3, 4
77
- 0x7c,0x43,0x20,0x14 = addc 2, 3, 4
78
- 0x7c,0x43,0x20,0x15 = addc. 2, 3, 4
79
- 0x7c,0x43,0x20,0x10 = subfc 2, 3, 4
80
- 0x7c,0x43,0x20,0x10 = subfc 2, 3, 4
81
- 0x7c,0x43,0x21,0x14 = adde 2, 3, 4
82
- 0x7c,0x43,0x21,0x15 = adde. 2, 3, 4
83
- 0x7c,0x43,0x21,0x10 = subfe 2, 3, 4
84
- 0x7c,0x43,0x21,0x11 = subfe. 2, 3, 4
85
- 0x7c,0x43,0x01,0xd4 = addme 2, 3
86
- 0x7c,0x43,0x01,0xd5 = addme. 2, 3
87
- 0x7c,0x43,0x01,0xd0 = subfme 2, 3
88
- 0x7c,0x43,0x01,0xd1 = subfme. 2, 3
89
- 0x7c,0x43,0x01,0x94 = addze 2, 3
90
- 0x7c,0x43,0x01,0x95 = addze. 2, 3
91
- 0x7c,0x43,0x01,0x90 = subfze 2, 3
92
- 0x7c,0x43,0x01,0x91 = subfze. 2, 3
93
- 0x7c,0x43,0x00,0xd0 = neg 2, 3
94
- 0x7c,0x43,0x00,0xd1 = neg. 2, 3
95
- 0x1c,0x43,0x00,0x80 = mulli 2, 3, 128
96
- 0x7c,0x43,0x20,0x96 = mulhw 2, 3, 4
97
- 0x7c,0x43,0x20,0x97 = mulhw. 2, 3, 4
98
- 0x7c,0x43,0x21,0xd6 = mullw 2, 3, 4
99
- 0x7c,0x43,0x21,0xd7 = mullw. 2, 3, 4
100
- 0x7c,0x43,0x20,0x16 = mulhwu 2, 3, 4
101
- 0x7c,0x43,0x20,0x17 = mulhwu. 2, 3, 4
102
- 0x7c,0x43,0x23,0xd6 = divw 2, 3, 4
103
- 0x7c,0x43,0x23,0xd7 = divw. 2, 3, 4
104
- 0x7c,0x43,0x23,0x96 = divwu 2, 3, 4
105
- 0x7c,0x43,0x23,0x97 = divwu. 2, 3, 4
106
- 0x7c,0x43,0x21,0xd2 = mulld 2, 3, 4
107
- 0x7c,0x43,0x21,0xd3 = mulld. 2, 3, 4
108
- 0x7c,0x43,0x20,0x92 = mulhd 2, 3, 4
109
- 0x7c,0x43,0x20,0x93 = mulhd. 2, 3, 4
110
- 0x7c,0x43,0x20,0x12 = mulhdu 2, 3, 4
111
- 0x7c,0x43,0x20,0x13 = mulhdu. 2, 3, 4
112
- 0x7c,0x43,0x23,0xd2 = divd 2, 3, 4
113
- 0x7c,0x43,0x23,0xd3 = divd. 2, 3, 4
114
- 0x7c,0x43,0x23,0x92 = divdu 2, 3, 4
115
- 0x7c,0x43,0x23,0x93 = divdu. 2, 3, 4
116
- 0x2d,0x23,0x00,0x80 = cmpdi 2, 3, 128
117
- 0x7d,0x23,0x20,0x00 = cmpd 2, 3, 4
118
- 0x29,0x23,0x00,0x80 = cmpldi 2, 3, 128
119
- 0x7d,0x23,0x20,0x40 = cmpld 2, 3, 4
120
- 0x2d,0x03,0x00,0x80 = cmpwi 2, 3, 128
121
- 0x7d,0x03,0x20,0x00 = cmpw 2, 3, 4
122
- 0x29,0x03,0x00,0x80 = cmplwi 2, 3, 128
123
- 0x7d,0x03,0x20,0x40 = cmplw 2, 3, 4
124
- 0x0c,0x43,0x00,0x04 = twi 2, 3, 4
125
- 0x7c,0x43,0x20,0x08 = tw 2, 3, 4
126
- 0x08,0x43,0x00,0x04 = tdi 2, 3, 4
127
- 0x7c,0x43,0x20,0x88 = td 2, 3, 4
128
- 0x7c,0x43,0x21,0x5e = isel 2, 3, 4, 5
129
- 0x70,0x62,0x00,0x80 = andi. 2, 3, 128
130
- 0x74,0x62,0x00,0x80 = andis. 2, 3, 128
131
- 0x60,0x62,0x00,0x80 = ori 2, 3, 128
132
- 0x64,0x62,0x00,0x80 = oris 2, 3, 128
133
- 0x68,0x62,0x00,0x80 = xori 2, 3, 128
134
- 0x6c,0x62,0x00,0x80 = xoris 2, 3, 128
135
- 0x7c,0x62,0x20,0x38 = and 2, 3, 4
136
- 0x7c,0x62,0x20,0x39 = and. 2, 3, 4
137
- 0x7c,0x62,0x22,0x78 = xor 2, 3, 4
138
- 0x7c,0x62,0x22,0x79 = xor. 2, 3, 4
139
- 0x7c,0x62,0x23,0xb8 = nand 2, 3, 4
140
- 0x7c,0x62,0x23,0xb9 = nand. 2, 3, 4
141
- 0x7c,0x62,0x23,0x78 = or 2, 3, 4
142
- 0x7c,0x62,0x23,0x79 = or. 2, 3, 4
143
- 0x7c,0x62,0x20,0xf8 = nor 2, 3, 4
144
- 0x7c,0x62,0x20,0xf9 = nor. 2, 3, 4
145
- 0x7c,0x62,0x22,0x38 = eqv 2, 3, 4
146
- 0x7c,0x62,0x22,0x39 = eqv. 2, 3, 4
147
- 0x7c,0x62,0x20,0x78 = andc 2, 3, 4
148
- 0x7c,0x62,0x20,0x79 = andc. 2, 3, 4
149
- 0x7c,0x62,0x23,0x38 = orc 2, 3, 4
150
- 0x7c,0x62,0x23,0x39 = orc. 2, 3, 4
151
- 0x7c,0x62,0x07,0x74 = extsb 2, 3
152
- 0x7c,0x62,0x07,0x75 = extsb. 2, 3
153
- 0x7c,0x62,0x07,0x34 = extsh 2, 3
154
- 0x7c,0x62,0x07,0x35 = extsh. 2, 3
155
- 0x7c,0x62,0x00,0x34 = cntlzw 2, 3
156
- 0x7c,0x62,0x00,0x35 = cntlzw. 2, 3
157
- 0x7c,0x62,0x02,0xf4 = popcntw 2, 3
158
- 0x7c,0x62,0x07,0xb4 = extsw 2, 3
159
- 0x7c,0x62,0x07,0xb5 = extsw. 2, 3
160
- 0x7c,0x62,0x00,0x74 = cntlzd 2, 3
161
- 0x7c,0x62,0x00,0x75 = cntlzd. 2, 3
162
- 0x7c,0x62,0x03,0xf4 = popcntd 2, 3
163
- 0x54,0x62,0x21,0x4c = rlwinm 2, 3, 4, 5, 6
164
- 0x54,0x62,0x21,0x4d = rlwinm. 2, 3, 4, 5, 6
165
- 0x5c,0x62,0x21,0x4c = rlwnm 2, 3, 4, 5, 6
166
- 0x5c,0x62,0x21,0x4d = rlwnm. 2, 3, 4, 5, 6
167
- 0x50,0x62,0x21,0x4c = rlwimi 2, 3, 4, 5, 6
168
- 0x50,0x62,0x21,0x4d = rlwimi. 2, 3, 4, 5, 6
169
- 0x78,0x62,0x21,0x40 = rldicl 2, 3, 4, 5
170
- 0x78,0x62,0x21,0x41 = rldicl. 2, 3, 4, 5
171
- 0x78,0x62,0x21,0x44 = rldicr 2, 3, 4, 5
172
- 0x78,0x62,0x21,0x45 = rldicr. 2, 3, 4, 5
173
- 0x78,0x62,0x21,0x48 = rldic 2, 3, 4, 5
174
- 0x78,0x62,0x21,0x49 = rldic. 2, 3, 4, 5
175
- 0x78,0x62,0x21,0x50 = rldcl 2, 3, 4, 5
176
- 0x78,0x62,0x21,0x51 = rldcl. 2, 3, 4, 5
177
- 0x78,0x62,0x21,0x52 = rldcr 2, 3, 4, 5
178
- 0x78,0x62,0x21,0x53 = rldcr. 2, 3, 4, 5
179
- 0x78,0x62,0x21,0x4c = rldimi 2, 3, 4, 5
180
- 0x78,0x62,0x21,0x4d = rldimi. 2, 3, 4, 5
181
- 0x7c,0x62,0x20,0x30 = slw 2, 3, 4
182
- 0x7c,0x62,0x20,0x31 = slw. 2, 3, 4
183
- 0x7c,0x62,0x24,0x30 = srw 2, 3, 4
184
- 0x7c,0x62,0x24,0x31 = srw. 2, 3, 4
185
- 0x7c,0x62,0x26,0x70 = srawi 2, 3, 4
186
- 0x7c,0x62,0x26,0x71 = srawi. 2, 3, 4
187
- 0x7c,0x62,0x26,0x30 = sraw 2, 3, 4
188
- 0x7c,0x62,0x26,0x31 = sraw. 2, 3, 4
189
- 0x7c,0x62,0x20,0x36 = sld 2, 3, 4
190
- 0x7c,0x62,0x20,0x37 = sld. 2, 3, 4
191
- 0x7c,0x62,0x24,0x36 = srd 2, 3, 4
192
- 0x7c,0x62,0x24,0x37 = srd. 2, 3, 4
193
- 0x7c,0x62,0x26,0x74 = sradi 2, 3, 4
194
- 0x7c,0x62,0x26,0x75 = sradi. 2, 3, 4
195
- 0x7c,0x62,0x26,0x34 = srad 2, 3, 4
196
- 0x7c,0x62,0x26,0x35 = srad. 2, 3, 4
197
- 0x7c,0x58,0x93,0xa6 = mtspr 600, 2
198
- 0x7c,0x58,0x92,0xa6 = mfspr 2, 600
199
- 0x7c,0x47,0xb1,0x20 = mtcrf 123, 2
200
- 0x7c,0x40,0x00,0x26 = mfcr 2
201
- 0x7c,0x51,0x01,0x20 = mtocrf 16, 2
202
- 0x7e,0x10,0x80,0x26 = mfocrf 16, 8
data/test/MC/PowerPC/ppc64-operands.s.cs DELETED
@@ -1,32 +0,0 @@
1
- # CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME
2
- 0x7c,0x22,0x1a,0x14 = add 1, 2, 3
3
- 0x7c,0x22,0x1a,0x14 = add 1, 2, 3
4
- 0x7c,0x00,0x02,0x14 = add 0, 0, 0
5
- 0x7f,0xff,0xfa,0x14 = add 31, 31, 31
6
- 0x38,0x20,0x00,0x00 = addi 1, 0, 0
7
- 0x38,0x20,0x00,0x00 = addi 1, 0, 0
8
- 0x38,0x22,0x00,0x00 = addi 1, 2, 0
9
- 0x38,0x20,0x80,0x00 = addi 1, 0, -32768
10
- 0x38,0x20,0x7f,0xff = addi 1, 0, 32767
11
- 0x60,0x41,0x00,0x00 = ori 1, 2, 0
12
- 0x60,0x41,0xff,0xff = ori 1, 2, 65535
13
- 0x3c,0x20,0x00,0x00 = addis 1, 0, 0
14
- 0x3c,0x20,0xff,0xff = addis 1, 0, -1
15
- 0x80,0x20,0x00,0x00 = lwz 1, 0(0)
16
- 0x80,0x20,0x00,0x00 = lwz 1, 0(0)
17
- 0x80,0x3f,0x00,0x00 = lwz 1, 0(31)
18
- 0x80,0x3f,0x00,0x00 = lwz 1, 0(31)
19
- 0x80,0x22,0x80,0x00 = lwz 1, -32768(2)
20
- 0x80,0x22,0x7f,0xff = lwz 1, 32767(2)
21
- 0xe8,0x20,0x00,0x00 = ld 1, 0(0)
22
- 0xe8,0x20,0x00,0x00 = ld 1, 0(0)
23
- 0xe8,0x3f,0x00,0x00 = ld 1, 0(31)
24
- 0xe8,0x3f,0x00,0x00 = ld 1, 0(31)
25
- 0xe8,0x22,0x80,0x00 = ld 1, -32768(2)
26
- 0xe8,0x22,0x7f,0xfc = ld 1, 32764(2)
27
- 0xe8,0x22,0x00,0x04 = ld 1, 4(2)
28
- 0xe8,0x22,0xff,0xfc = ld 1, -4(2)
29
- 0x48,0x00,0x04,0x00 = b .+1024
30
- 0x48,0x00,0x04,0x02 = ba 1024
31
- 0x41,0x82,0x04,0x00 = beq 0, .+1024
32
- 0x41,0x82,0x04,0x02 = beqa 0, 1024
data/test/MC/README DELETED
@@ -1,6 +0,0 @@
1
- Input files for testing Capstone engine.
2
-
3
- Format of input files:
4
-
5
- # ARCH, MODE, OPTION
6
- hexcode = assembly
data/test/MC/Sparc/sparc-alu-instructions.s.cs DELETED
@@ -1,47 +0,0 @@
1
- # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None
2
- 0x80,0x00,0x00,0x00 = add %g0, %g0, %g0
3
- 0x86,0x00,0x40,0x02 = add %g1, %g2, %g3
4
- 0xa0,0x02,0x00,0x09 = add %o0, %o1, %l0
5
- 0xa0,0x02,0x20,0x0a = add %o0, 10, %l0
6
- 0x86,0x80,0x40,0x02 = addcc %g1, %g2, %g3
7
- 0x86,0xc0,0x40,0x02 = addxcc %g1, %g2, %g3
8
- 0x86,0x70,0x40,0x02 = udiv %g1, %g2, %g3
9
- 0x86,0x78,0x40,0x02 = sdiv %g1, %g2, %g3
10
- 0x86,0x08,0x40,0x02 = and %g1, %g2, %g3
11
- 0x86,0x28,0x40,0x02 = andn %g1, %g2, %g3
12
- 0x86,0x10,0x40,0x02 = or %g1, %g2, %g3
13
- 0x86,0x30,0x40,0x02 = orn %g1, %g2, %g3
14
- 0x86,0x18,0x40,0x02 = xor %g1, %g2, %g3
15
- 0x86,0x38,0x40,0x02 = xnor %g1, %g2, %g3
16
- 0x86,0x50,0x40,0x02 = umul %g1, %g2, %g3
17
- 0x86,0x58,0x40,0x02 = smul %g1, %g2, %g3
18
- 0x01,0x00,0x00,0x00 = nop
19
- 0x21,0x00,0x00,0x0a = sethi 10, %l0
20
- 0x87,0x28,0x40,0x02 = sll %g1, %g2, %g3
21
- 0x87,0x28,0x60,0x1f = sll %g1, 31, %g3
22
- 0x87,0x30,0x40,0x02 = srl %g1, %g2, %g3
23
- 0x87,0x30,0x60,0x1f = srl %g1, 31, %g3
24
- 0x87,0x38,0x40,0x02 = sra %g1, %g2, %g3
25
- 0x87,0x38,0x60,0x1f = sra %g1, 31, %g3
26
- 0x86,0x20,0x40,0x02 = sub %g1, %g2, %g3
27
- 0x86,0xa0,0x40,0x02 = subcc %g1, %g2, %g3
28
- 0x86,0xe0,0x40,0x02 = subxcc %g1, %g2, %g3
29
- 0x86,0x10,0x00,0x01 = or %g0, %g1, %g3
30
- 0x86,0x10,0x20,0xff = or %g0, 255, %g3
31
- 0x81,0xe8,0x00,0x00 = restore
32
- 0x86,0x40,0x80,0x01 = addx %g2, %g1, %g3
33
- 0x86,0x60,0x80,0x01 = subx %g2, %g1, %g3
34
- 0x86,0xd0,0x80,0x01 = umulcc %g2, %g1, %g3
35
- 0x86,0xd8,0x80,0x01 = smulcc %g2, %g1, %g3
36
- 0x86,0xf0,0x80,0x01 = udivcc %g2, %g1, %g3
37
- 0x86,0xf8,0x80,0x01 = sdivcc %g2, %g1, %g3
38
- 0x86,0x88,0x80,0x01 = andcc %g2, %g1, %g3
39
- 0x86,0xa8,0x80,0x01 = andncc %g2, %g1, %g3
40
- 0x86,0x90,0x80,0x01 = orcc %g2, %g1, %g3
41
- 0x86,0xb0,0x80,0x01 = orncc %g2, %g1, %g3
42
- 0x86,0x98,0x80,0x01 = xorcc %g2, %g1, %g3
43
- 0x86,0xb8,0x80,0x01 = xnorcc %g2, %g1, %g3
44
- 0x87,0x00,0x80,0x01 = taddcc %g2, %g1, %g3
45
- 0x87,0x08,0x80,0x01 = tsubcc %g2, %g1, %g3
46
- 0x87,0x10,0x80,0x01 = taddcctv %g2, %g1, %g3
47
- 0x87,0x18,0x80,0x01 = tsubcctv %g2, %g1, %g3
data/test/MC/Sparc/sparc-atomic-instructions.s.cs DELETED
@@ -1,7 +0,0 @@
1
- # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None
2
- 0x81,0x43,0xe0,0x0f = membar 15
3
- 0x81,0x43,0xc0,0x00 = stbar
4
- 0xd4,0x7e,0x00,0x16 = swap [%i0+%l6], %o2
5
- 0xd4,0x7e,0x20,0x20 = swap [%i0+32], %o2
6
- 0xd5,0xe6,0x10,0x16 = cas [%i0], %l6, %o2
7
- 0xd5,0xf6,0x10,0x16 = casx [%i0], %l6, %o2
data/test/MC/Sparc/sparc-ctrl-instructions.s.cs DELETED
@@ -1,11 +0,0 @@
1
- # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None
2
- 0x9f,0xc0,0x40,0x1a = call %g1+%i2
3
- 0x9f,0xc2,0x60,0x08 = call %o1+8
4
- 0x9f,0xc0,0x60,0x00 = call %g1
5
- 0x81,0xc0,0x40,0x1a = jmp %g1+%i2
6
- 0x81,0xc2,0x60,0x08 = jmp %o1+8
7
- 0x81,0xc0,0x60,0x00 = jmp %g1
8
- 0x85,0xc0,0x40,0x1a = jmpl %g1+%i2, %g2
9
- 0x85,0xc2,0x60,0x08 = jmpl %o1+8, %g2
10
- 0x85,0xc0,0x60,0x00 = jmpl %g1, %g2
11
- 0x81,0xcf,0xe0,0x08 = rett %i7+8
data/test/MC/Sparc/sparc-fp-instructions.s.cs DELETED
@@ -1,59 +0,0 @@
1
- # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, None
2
- 0x89,0xa0,0x18,0x80 = fitos %f0, %f4
3
- 0x89,0xa0,0x19,0x00 = fitod %f0, %f4
4
- 0x89,0xa0,0x19,0x80 = fitoq %f0, %f4
5
- 0x89,0xa0,0x1a,0x20 = fstoi %f0, %f4
6
- 0x89,0xa0,0x1a,0x40 = fdtoi %f0, %f4
7
- 0x89,0xa0,0x1a,0x60 = fqtoi %f0, %f4
8
- 0x89,0xa0,0x19,0x20 = fstod %f0, %f4
9
- 0x89,0xa0,0x19,0xa0 = fstoq %f0, %f4
10
- 0x89,0xa0,0x18,0xc0 = fdtos %f0, %f4
11
- 0x89,0xa0,0x19,0xc0 = fdtoq %f0, %f4
12
- 0x89,0xa0,0x18,0xe0 = fqtos %f0, %f4
13
- 0x89,0xa0,0x19,0x60 = fqtod %f0, %f4
14
- 0x89,0xa0,0x00,0x20 = fmovs %f0, %f4
15
- 0x89,0xa0,0x00,0x40 = fmovd %f0, %f4
16
- 0x89,0xa0,0x00,0x60 = fmovq %f0, %f4
17
- 0x89,0xa0,0x00,0xa0 = fnegs %f0, %f4
18
- 0x89,0xa0,0x00,0xc0 = fnegd %f0, %f4
19
- 0x89,0xa0,0x00,0xe0 = fnegq %f0, %f4
20
- 0x89,0xa0,0x01,0x20 = fabss %f0, %f4
21
- 0x89,0xa0,0x01,0x40 = fabsd %f0, %f4
22
- 0x89,0xa0,0x01,0x60 = fabsq %f0, %f4
23
- 0x89,0xa0,0x05,0x20 = fsqrts %f0, %f4
24
- 0x89,0xa0,0x05,0x40 = fsqrtd %f0, %f4
25
- 0x89,0xa0,0x05,0x60 = fsqrtq %f0, %f4
26
- 0x91,0xa0,0x08,0x24 = fadds %f0, %f4, %f8
27
- 0x91,0xa0,0x08,0x44 = faddd %f0, %f4, %f8
28
- 0x91,0xa0,0x08,0x64 = faddq %f0, %f4, %f8
29
- 0xbf,0xa0,0x48,0x43 = faddd %f32, %f34, %f62
30
- 0xbb,0xa0,0x48,0x65 = faddq %f32, %f36, %f60
31
- 0x91,0xa0,0x08,0xa4 = fsubs %f0, %f4, %f8
32
- 0x91,0xa0,0x08,0xc4 = fsubd %f0, %f4, %f8
33
- 0x91,0xa0,0x08,0xe4 = fsubq %f0, %f4, %f8
34
- 0x91,0xa0,0x09,0x24 = fmuls %f0, %f4, %f8
35
- 0x91,0xa0,0x09,0x44 = fmuld %f0, %f4, %f8
36
- 0x91,0xa0,0x09,0x64 = fmulq %f0, %f4, %f8
37
- 0x91,0xa0,0x0d,0x24 = fsmuld %f0, %f4, %f8
38
- 0x91,0xa0,0x0d,0xc4 = fdmulq %f0, %f4, %f8
39
- 0x91,0xa0,0x09,0xa4 = fdivs %f0, %f4, %f8
40
- 0x91,0xa0,0x09,0xc4 = fdivd %f0, %f4, %f8
41
- 0x91,0xa0,0x09,0xe4 = fdivq %f0, %f4, %f8
42
- 0x81,0xa8,0x0a,0x24 = fcmps %fcc0, %f0, %f4
43
- 0x81,0xa8,0x0a,0x44 = fcmpd %fcc0, %f0, %f4
44
- 0x81,0xa8,0x0a,0x64 = fcmpq %fcc0, %f0, %f4
45
- 0x81,0xa8,0x0a,0xa4 = fcmpes %fcc0, %f0, %f4
46
- 0x81,0xa8,0x0a,0xc4 = fcmped %fcc0, %f0, %f4
47
- 0x81,0xa8,0x0a,0xe4 = fcmpeq %fcc0, %f0, %f4
48
- 0x85,0xa8,0x0a,0x24 = fcmps %fcc2, %f0, %f4
49
- 0x85,0xa8,0x0a,0x44 = fcmpd %fcc2, %f0, %f4
50
- 0x85,0xa8,0x0a,0x64 = fcmpq %fcc2, %f0, %f4
51
- 0x85,0xa8,0x0a,0xa4 = fcmpes %fcc2, %f0, %f4
52
- 0x85,0xa8,0x0a,0xc4 = fcmped %fcc2, %f0, %f4
53
- 0x85,0xa8,0x0a,0xe4 = fcmpeq %fcc2, %f0, %f4
54
- 0x89,0xa0,0x10,0x80 = fxtos %f0, %f4
55
- 0x89,0xa0,0x11,0x00 = fxtod %f0, %f4
56
- 0x89,0xa0,0x11,0x80 = fxtoq %f0, %f4
57
- 0x89,0xa0,0x10,0x20 = fstox %f0, %f4
58
- 0x89,0xa0,0x10,0x40 = fdtox %f0, %f4
59
- 0x89,0xa0,0x10,0x60 = fqtox %f0, %f4
data/test/MC/Sparc/sparc-mem-instructions.s.cs DELETED
@@ -1,25 +0,0 @@
1
- # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None
2
- 0xd4,0x4e,0x00,0x16 = ldsb [%i0+%l6], %o2
3
- 0xd4,0x4e,0x20,0x20 = ldsb [%i0+32], %o2
4
- 0xd8,0x48,0x60,0x00 = ldsb [%g1], %o4
5
- 0xd4,0x56,0x00,0x16 = ldsh [%i0+%l6], %o2
6
- 0xd4,0x56,0x20,0x20 = ldsh [%i0+32], %o2
7
- 0xd8,0x50,0x60,0x00 = ldsh [%g1], %o4
8
- 0xd4,0x0e,0x00,0x16 = ldub [%i0+%l6], %o2
9
- 0xd4,0x0e,0x20,0x20 = ldub [%i0+32], %o2
10
- 0xd4,0x08,0x60,0x00 = ldub [%g1], %o2
11
- 0xd4,0x16,0x00,0x16 = lduh [%i0+%l6], %o2
12
- 0xd4,0x16,0x20,0x20 = lduh [%i0+32], %o2
13
- 0xd4,0x10,0x60,0x00 = lduh [%g1], %o2
14
- 0xd4,0x06,0x00,0x16 = ld [%i0+%l6], %o2
15
- 0xd4,0x06,0x20,0x20 = ld [%i0+32], %o2
16
- 0xd4,0x00,0x60,0x00 = ld [%g1], %o2
17
- 0xd4,0x2e,0x00,0x16 = stb %o2, [%i0+%l6]
18
- 0xd4,0x2e,0x20,0x20 = stb %o2, [%i0+32]
19
- 0xd4,0x28,0x60,0x00 = stb %o2, [%g1]
20
- 0xd4,0x36,0x00,0x16 = sth %o2, [%i0+%l6]
21
- 0xd4,0x36,0x20,0x20 = sth %o2, [%i0+32]
22
- 0xd4,0x30,0x60,0x00 = sth %o2, [%g1]
23
- 0xd4,0x26,0x00,0x16 = st %o2, [%i0+%l6]
24
- 0xd4,0x26,0x20,0x20 = st %o2, [%i0+32]
25
- 0xd4,0x20,0x60,0x00 = st %o2, [%g1]
data/test/MC/Sparc/sparc-vis.s.cs DELETED
@@ -1,2 +0,0 @@
1
- # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None
2
- 0xbf,0xb0,0x0c,0x20 = fzeros %f31
data/test/MC/Sparc/sparc64-alu-instructions.s.cs DELETED
@@ -1,13 +0,0 @@
1
- # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None
2
- 0xb1,0x28,0x50,0x1a = sllx %g1, %i2, %i0
3
- 0xb1,0x28,0x70,0x3f = sllx %g1, 63, %i0
4
- 0xb1,0x30,0x50,0x1a = srlx %g1, %i2, %i0
5
- 0xb1,0x30,0x70,0x3f = srlx %g1, 63, %i0
6
- 0xb1,0x38,0x50,0x1a = srax %g1, %i2, %i0
7
- 0xb1,0x38,0x70,0x3f = srax %g1, 63, %i0
8
- 0xb0,0x48,0x40,0x1a = mulx %g1, %i2, %i0
9
- 0xb0,0x48,0x60,0x3f = mulx %g1, 63, %i0
10
- 0xb1,0x68,0x40,0x1a = sdivx %g1, %i2, %i0
11
- 0xb1,0x68,0x60,0x3f = sdivx %g1, 63, %i0
12
- 0xb0,0x68,0x40,0x1a = udivx %g1, %i2, %i0
13
- 0xb0,0x68,0x60,0x3f = udivx %g1, 63, %i0
data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs DELETED
@@ -1,102 +0,0 @@
1
- # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None
2
- 0x85,0x66,0x40,0x01 = movne %icc, %g1, %g2
3
- 0x85,0x64,0x40,0x01 = move %icc, %g1, %g2
4
- 0x85,0x66,0x80,0x01 = movg %icc, %g1, %g2
5
- 0x85,0x64,0x80,0x01 = movle %icc, %g1, %g2
6
- 0x85,0x66,0xc0,0x01 = movge %icc, %g1, %g2
7
- 0x85,0x64,0xc0,0x01 = movl %icc, %g1, %g2
8
- 0x85,0x67,0x00,0x01 = movgu %icc, %g1, %g2
9
- 0x85,0x65,0x00,0x01 = movleu %icc, %g1, %g2
10
- 0x85,0x67,0x40,0x01 = movcc %icc, %g1, %g2
11
- 0x85,0x65,0x40,0x01 = movcs %icc, %g1, %g2
12
- 0x85,0x67,0x80,0x01 = movpos %icc, %g1, %g2
13
- 0x85,0x65,0x80,0x01 = movneg %icc, %g1, %g2
14
- 0x85,0x67,0xc0,0x01 = movvc %icc, %g1, %g2
15
- 0x85,0x65,0xc0,0x01 = movvs %icc, %g1, %g2
16
- 0x85,0x66,0x50,0x01 = movne %xcc, %g1, %g2
17
- 0x85,0x64,0x50,0x01 = move %xcc, %g1, %g2
18
- 0x85,0x66,0x90,0x01 = movg %xcc, %g1, %g2
19
- 0x85,0x64,0x90,0x01 = movle %xcc, %g1, %g2
20
- 0x85,0x66,0xd0,0x01 = movge %xcc, %g1, %g2
21
- 0x85,0x64,0xd0,0x01 = movl %xcc, %g1, %g2
22
- 0x85,0x67,0x10,0x01 = movgu %xcc, %g1, %g2
23
- 0x85,0x65,0x10,0x01 = movleu %xcc, %g1, %g2
24
- 0x85,0x67,0x50,0x01 = movcc %xcc, %g1, %g2
25
- 0x85,0x65,0x50,0x01 = movcs %xcc, %g1, %g2
26
- 0x85,0x67,0x90,0x01 = movpos %xcc, %g1, %g2
27
- 0x85,0x65,0x90,0x01 = movneg %xcc, %g1, %g2
28
- 0x85,0x67,0xd0,0x01 = movvc %xcc, %g1, %g2
29
- 0x85,0x65,0xd0,0x01 = movvs %xcc, %g1, %g2
30
- 0x85,0x61,0xc0,0x01 = movu %fcc0, %g1, %g2
31
- 0x85,0x61,0x80,0x01 = movg %fcc0, %g1, %g2
32
- 0x85,0x61,0x40,0x01 = movug %fcc0, %g1, %g2
33
- 0x85,0x61,0x00,0x01 = movl %fcc0, %g1, %g2
34
- 0x85,0x60,0xc0,0x01 = movul %fcc0, %g1, %g2
35
- 0x85,0x60,0x80,0x01 = movlg %fcc0, %g1, %g2
36
- 0x85,0x60,0x40,0x01 = movne %fcc0, %g1, %g2
37
- 0x85,0x62,0x40,0x01 = move %fcc0, %g1, %g2
38
- 0x85,0x62,0x80,0x01 = movue %fcc0, %g1, %g2
39
- 0x85,0x62,0xc0,0x01 = movge %fcc0, %g1, %g2
40
- 0x85,0x63,0x00,0x01 = movuge %fcc0, %g1, %g2
41
- 0x85,0x63,0x40,0x01 = movle %fcc0, %g1, %g2
42
- 0x85,0x63,0x80,0x01 = movule %fcc0, %g1, %g2
43
- 0x85,0x63,0xc0,0x01 = movo %fcc0, %g1, %g2
44
- 0x85,0xaa,0x60,0x21 = fmovsne %icc, %f1, %f2
45
- 0x85,0xa8,0x60,0x21 = fmovse %icc, %f1, %f2
46
- 0x85,0xaa,0xa0,0x21 = fmovsg %icc, %f1, %f2
47
- 0x85,0xa8,0xa0,0x21 = fmovsle %icc, %f1, %f2
48
- 0x85,0xaa,0xe0,0x21 = fmovsge %icc, %f1, %f2
49
- 0x85,0xa8,0xe0,0x21 = fmovsl %icc, %f1, %f2
50
- 0x85,0xab,0x20,0x21 = fmovsgu %icc, %f1, %f2
51
- 0x85,0xa9,0x20,0x21 = fmovsleu %icc, %f1, %f2
52
- 0x85,0xab,0x60,0x21 = fmovscc %icc, %f1, %f2
53
- 0x85,0xa9,0x60,0x21 = fmovscs %icc, %f1, %f2
54
- 0x85,0xab,0xa0,0x21 = fmovspos %icc, %f1, %f2
55
- 0x85,0xa9,0xa0,0x21 = fmovsneg %icc, %f1, %f2
56
- 0x85,0xab,0xe0,0x21 = fmovsvc %icc, %f1, %f2
57
- 0x85,0xa9,0xe0,0x21 = fmovsvs %icc, %f1, %f2
58
- 0x85,0xaa,0x70,0x21 = fmovsne %xcc, %f1, %f2
59
- 0x85,0xa8,0x70,0x21 = fmovse %xcc, %f1, %f2
60
- 0x85,0xaa,0xb0,0x21 = fmovsg %xcc, %f1, %f2
61
- 0x85,0xa8,0xb0,0x21 = fmovsle %xcc, %f1, %f2
62
- 0x85,0xaa,0xf0,0x21 = fmovsge %xcc, %f1, %f2
63
- 0x85,0xa8,0xf0,0x21 = fmovsl %xcc, %f1, %f2
64
- 0x85,0xab,0x30,0x21 = fmovsgu %xcc, %f1, %f2
65
- 0x85,0xa9,0x30,0x21 = fmovsleu %xcc, %f1, %f2
66
- 0x85,0xab,0x70,0x21 = fmovscc %xcc, %f1, %f2
67
- 0x85,0xa9,0x70,0x21 = fmovscs %xcc, %f1, %f2
68
- 0x85,0xab,0xb0,0x21 = fmovspos %xcc, %f1, %f2
69
- 0x85,0xa9,0xb0,0x21 = fmovsneg %xcc, %f1, %f2
70
- 0x85,0xab,0xf0,0x21 = fmovsvc %xcc, %f1, %f2
71
- 0x85,0xa9,0xf0,0x21 = fmovsvs %xcc, %f1, %f2
72
- 0x85,0xa9,0xc0,0x21 = fmovsu %fcc0, %f1, %f2
73
- 0x85,0xa9,0x80,0x21 = fmovsg %fcc0, %f1, %f2
74
- 0x85,0xa9,0x40,0x21 = fmovsug %fcc0, %f1, %f2
75
- 0x85,0xa9,0x00,0x21 = fmovsl %fcc0, %f1, %f2
76
- 0x85,0xa8,0xc0,0x21 = fmovsul %fcc0, %f1, %f2
77
- 0x85,0xa8,0x80,0x21 = fmovslg %fcc0, %f1, %f2
78
- 0x85,0xa8,0x40,0x21 = fmovsne %fcc0, %f1, %f2
79
- 0x85,0xaa,0x40,0x21 = fmovse %fcc0, %f1, %f2
80
- 0x85,0xaa,0x80,0x21 = fmovsue %fcc0, %f1, %f2
81
- 0x85,0xaa,0xc0,0x21 = fmovsge %fcc0, %f1, %f2
82
- 0x85,0xab,0x00,0x21 = fmovsuge %fcc0, %f1, %f2
83
- 0x85,0xab,0x40,0x21 = fmovsle %fcc0, %f1, %f2
84
- 0x85,0xab,0x80,0x21 = fmovsule %fcc0, %f1, %f2
85
- 0x85,0xab,0xc0,0x21 = fmovso %fcc0, %f1, %f2
86
- 0x85,0x61,0xc8,0x01 = movu %fcc1, %g1, %g2
87
- 0x85,0xa9,0x90,0x21 = fmovsg %fcc2, %f1, %f2
88
- 0x87,0x78,0x44,0x02 = movrz %g1, %g2, %g3
89
- 0x87,0x78,0x48,0x02 = movrlez %g1, %g2, %g3
90
- 0x87,0x78,0x4c,0x02 = movrlz %g1, %g2, %g3
91
- 0x87,0x78,0x54,0x02 = movrnz %g1, %g2, %g3
92
- 0x87,0x78,0x58,0x02 = movrgz %g1, %g2, %g3
93
- 0x87,0x78,0x5c,0x02 = movrgez %g1, %g2, %g3
94
- 0x87,0xa8,0x44,0xa2 = fmovrsz %g1, %f2, %f3
95
- 0x87,0xa8,0x48,0xa2 = fmovrslez %g1, %f2, %f3
96
- 0x87,0xa8,0x4c,0xa2 = fmovrslz %g1, %f2, %f3
97
- 0x87,0xa8,0x54,0xa2 = fmovrsnz %g1, %f2, %f3
98
- 0x87,0xa8,0x58,0xa2 = fmovrsgz %g1, %f2, %f3
99
- 0x87,0xa8,0x5c,0xa2 = fmovrsgez %g1, %f2, %f3
100
- 0x81,0xcf,0xe0,0x08 = rett %i7+8
101
- 0x91,0xd0,0x20,0x05 = ta %icc, %g0 + 5
102
- 0x83,0xd0,0x30,0x03 = te %xcc, %g0 + 3