crabstone 3.0.3 → 4.0.4

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (347) hide show
  1. checksums.yaml +5 -5
  2. data/CHANGES.md +59 -42
  3. data/README.md +37 -39
  4. data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
  5. data/lib/crabstone/arch/3/arm64.rb +124 -0
  6. data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
  7. data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
  8. data/lib/crabstone/arch/3/mips.rb +57 -0
  9. data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
  10. data/lib/crabstone/arch/3/ppc.rb +73 -0
  11. data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
  12. data/lib/crabstone/arch/3/sparc.rb +60 -0
  13. data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
  14. data/lib/crabstone/arch/3/sysz.rb +67 -0
  15. data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
  16. data/lib/crabstone/arch/3/x86.rb +82 -0
  17. data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
  18. data/lib/crabstone/arch/3/xcore.rb +59 -0
  19. data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
  20. data/lib/crabstone/arch/4/arm.rb +110 -0
  21. data/lib/crabstone/arch/4/arm64.rb +125 -0
  22. data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
  23. data/lib/crabstone/arch/4/arm_const.rb +785 -0
  24. data/lib/crabstone/arch/4/evm.rb +20 -0
  25. data/lib/crabstone/arch/4/evm_const.rb +161 -0
  26. data/lib/crabstone/arch/4/m680x.rb +106 -0
  27. data/lib/crabstone/arch/4/m680x_const.rb +426 -0
  28. data/lib/crabstone/arch/4/m68k.rb +129 -0
  29. data/lib/crabstone/arch/4/m68k_const.rb +496 -0
  30. data/lib/crabstone/arch/4/mips.rb +57 -0
  31. data/lib/crabstone/arch/4/mips_const.rb +869 -0
  32. data/lib/crabstone/arch/4/ppc.rb +73 -0
  33. data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
  34. data/lib/crabstone/arch/4/sparc.rb +60 -0
  35. data/lib/crabstone/arch/4/sparc_const.rb +439 -0
  36. data/lib/crabstone/arch/4/sysz.rb +67 -0
  37. data/lib/crabstone/arch/4/sysz_const.rb +763 -0
  38. data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
  39. data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
  40. data/lib/crabstone/arch/4/x86.rb +91 -0
  41. data/lib/crabstone/arch/4/x86_const.rb +1972 -0
  42. data/lib/crabstone/arch/4/xcore.rb +59 -0
  43. data/lib/crabstone/arch/4/xcore_const.rb +171 -0
  44. data/lib/crabstone/arch/extension.rb +27 -0
  45. data/lib/crabstone/arch/register.rb +34 -0
  46. data/lib/crabstone/arch.rb +37 -0
  47. data/lib/crabstone/binding/3/detail.rb +36 -0
  48. data/lib/crabstone/binding/3/instruction.rb +23 -0
  49. data/lib/crabstone/binding/4/detail.rb +40 -0
  50. data/lib/crabstone/binding/4/instruction.rb +23 -0
  51. data/lib/crabstone/binding/structs.rb +32 -0
  52. data/lib/crabstone/binding.rb +59 -0
  53. data/lib/crabstone/constants.rb +110 -0
  54. data/lib/crabstone/cs_version.rb +57 -0
  55. data/lib/crabstone/disassembler.rb +147 -0
  56. data/lib/crabstone/error.rb +74 -0
  57. data/lib/crabstone/instruction.rb +178 -0
  58. data/lib/crabstone/version.rb +5 -0
  59. data/lib/crabstone.rb +5 -557
  60. metadata +142 -331
  61. data/MANIFEST +0 -312
  62. data/Rakefile +0 -27
  63. data/bin/genconst +0 -66
  64. data/bin/genreg +0 -99
  65. data/crabstone.gemspec +0 -27
  66. data/examples/hello_world.rb +0 -43
  67. data/lib/arch/arm64.rb +0 -167
  68. data/lib/arch/arm64_registers.rb +0 -295
  69. data/lib/arch/arm_registers.rb +0 -149
  70. data/lib/arch/mips.rb +0 -78
  71. data/lib/arch/mips_registers.rb +0 -208
  72. data/lib/arch/ppc.rb +0 -90
  73. data/lib/arch/ppc_registers.rb +0 -209
  74. data/lib/arch/sparc.rb +0 -79
  75. data/lib/arch/sparc_registers.rb +0 -121
  76. data/lib/arch/systemz.rb +0 -79
  77. data/lib/arch/sysz_registers.rb +0 -66
  78. data/lib/arch/x86.rb +0 -107
  79. data/lib/arch/x86_registers.rb +0 -265
  80. data/lib/arch/xcore.rb +0 -78
  81. data/lib/arch/xcore_registers.rb +0 -57
  82. data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
  83. data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
  84. data/test/MC/AArch64/neon-2velem.s.cs +0 -113
  85. data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
  86. data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
  87. data/test/MC/AArch64/neon-across.s.cs +0 -40
  88. data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
  89. data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
  90. data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
  91. data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
  92. data/test/MC/AArch64/neon-crypto.s.cs +0 -15
  93. data/test/MC/AArch64/neon-extract.s.cs +0 -3
  94. data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
  95. data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
  96. data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
  97. data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
  98. data/test/MC/AArch64/neon-max-min.s.cs +0 -37
  99. data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
  100. data/test/MC/AArch64/neon-mov.s.cs +0 -74
  101. data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
  102. data/test/MC/AArch64/neon-perm.s.cs +0 -43
  103. data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
  104. data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
  105. data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
  106. data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
  107. data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
  108. data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
  109. data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
  110. data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
  111. data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
  112. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
  113. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
  114. data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
  115. data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
  116. data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
  117. data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
  118. data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
  119. data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
  120. data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
  121. data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
  122. data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
  123. data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
  124. data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
  125. data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
  126. data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
  127. data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
  128. data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
  129. data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
  130. data/test/MC/AArch64/neon-shift.s.cs +0 -22
  131. data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
  132. data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
  133. data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
  134. data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
  135. data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
  136. data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
  137. data/test/MC/AArch64/neon-tbl.s.cs +0 -21
  138. data/test/MC/AArch64/trace-regs.s.cs +0 -383
  139. data/test/MC/ARM/arm-aliases.s.cs +0 -7
  140. data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
  141. data/test/MC/ARM/arm-it-block.s.cs +0 -2
  142. data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
  143. data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
  144. data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
  145. data/test/MC/ARM/arm-trustzone.s.cs +0 -3
  146. data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
  147. data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
  148. data/test/MC/ARM/arm_instructions.s.cs +0 -25
  149. data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
  150. data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
  151. data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
  152. data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
  153. data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
  154. data/test/MC/ARM/crc32-thumb.s.cs +0 -7
  155. data/test/MC/ARM/crc32.s.cs +0 -7
  156. data/test/MC/ARM/dot-req.s.cs +0 -3
  157. data/test/MC/ARM/fp-armv8.s.cs +0 -52
  158. data/test/MC/ARM/idiv-thumb.s.cs +0 -3
  159. data/test/MC/ARM/idiv.s.cs +0 -3
  160. data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
  161. data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
  162. data/test/MC/ARM/mode-switch.s.cs +0 -7
  163. data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
  164. data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
  165. data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
  166. data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
  167. data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
  168. data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
  169. data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
  170. data/test/MC/ARM/neon-crypto.s.cs +0 -16
  171. data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
  172. data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
  173. data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
  174. data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
  175. data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
  176. data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
  177. data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
  178. data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
  179. data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
  180. data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
  181. data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
  182. data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
  183. data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
  184. data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
  185. data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
  186. data/test/MC/ARM/neon-v8.s.cs +0 -38
  187. data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
  188. data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
  189. data/test/MC/ARM/neon-vswp.s.cs +0 -3
  190. data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
  191. data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
  192. data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
  193. data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
  194. data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
  195. data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
  196. data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
  197. data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
  198. data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
  199. data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
  200. data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
  201. data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
  202. data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
  203. data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
  204. data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
  205. data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
  206. data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
  207. data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
  208. data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
  209. data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
  210. data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
  211. data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
  212. data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
  213. data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
  214. data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
  215. data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
  216. data/test/MC/ARM/thumb-hints.s.cs +0 -12
  217. data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
  218. data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
  219. data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
  220. data/test/MC/ARM/thumb.s.cs +0 -19
  221. data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
  222. data/test/MC/ARM/thumb2-branches.s.cs +0 -85
  223. data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
  224. data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
  225. data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
  226. data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
  227. data/test/MC/ARM/vfp4.s.cs +0 -13
  228. data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
  229. data/test/MC/ARM/vpush-vpop.s.cs +0 -9
  230. data/test/MC/Mips/hilo-addressing.s.cs +0 -4
  231. data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
  232. data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
  233. data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
  234. data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
  235. data/test/MC/Mips/micromips-expansions.s.cs +0 -20
  236. data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
  237. data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
  238. data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
  239. data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
  240. data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
  241. data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
  242. data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
  243. data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
  244. data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
  245. data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
  246. data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
  247. data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
  248. data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
  249. data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
  250. data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
  251. data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
  252. data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
  253. data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
  254. data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
  255. data/test/MC/Mips/mips-expansions.s.cs +0 -20
  256. data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
  257. data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
  258. data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
  259. data/test/MC/Mips/mips-register-names.s.cs +0 -33
  260. data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
  261. data/test/MC/Mips/mips64-instructions.s.cs +0 -3
  262. data/test/MC/Mips/mips64-register-names.s.cs +0 -33
  263. data/test/MC/Mips/mips_directives.s.cs +0 -12
  264. data/test/MC/Mips/nabi-regs.s.cs +0 -12
  265. data/test/MC/Mips/set-at-directive.s.cs +0 -6
  266. data/test/MC/Mips/test_2r.s.cs +0 -16
  267. data/test/MC/Mips/test_2rf.s.cs +0 -33
  268. data/test/MC/Mips/test_3r.s.cs +0 -243
  269. data/test/MC/Mips/test_3rf.s.cs +0 -83
  270. data/test/MC/Mips/test_bit.s.cs +0 -49
  271. data/test/MC/Mips/test_cbranch.s.cs +0 -11
  272. data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
  273. data/test/MC/Mips/test_elm.s.cs +0 -16
  274. data/test/MC/Mips/test_elm_insert.s.cs +0 -4
  275. data/test/MC/Mips/test_elm_insve.s.cs +0 -5
  276. data/test/MC/Mips/test_i10.s.cs +0 -5
  277. data/test/MC/Mips/test_i5.s.cs +0 -45
  278. data/test/MC/Mips/test_i8.s.cs +0 -11
  279. data/test/MC/Mips/test_lsa.s.cs +0 -5
  280. data/test/MC/Mips/test_mi10.s.cs +0 -24
  281. data/test/MC/Mips/test_vec.s.cs +0 -8
  282. data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
  283. data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
  284. data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
  285. data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
  286. data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
  287. data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
  288. data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
  289. data/test/MC/README +0 -6
  290. data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
  291. data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
  292. data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
  293. data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
  294. data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
  295. data/test/MC/Sparc/sparc-vis.s.cs +0 -2
  296. data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
  297. data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
  298. data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
  299. data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
  300. data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
  301. data/test/MC/SystemZ/insn-good.s.cs +0 -2265
  302. data/test/MC/SystemZ/regs-good.s.cs +0 -45
  303. data/test/MC/X86/3DNow.s.cs +0 -29
  304. data/test/MC/X86/address-size.s.cs +0 -5
  305. data/test/MC/X86/avx512-encodings.s.cs +0 -12
  306. data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
  307. data/test/MC/X86/x86-32-avx.s.cs +0 -833
  308. data/test/MC/X86/x86-32-fma3.s.cs +0 -169
  309. data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
  310. data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
  311. data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
  312. data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
  313. data/test/MC/X86/x86_64-encoding.s.cs +0 -59
  314. data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
  315. data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
  316. data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
  317. data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
  318. data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
  319. data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
  320. data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
  321. data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
  322. data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
  323. data/test/README +0 -6
  324. data/test/test.rb +0 -205
  325. data/test/test.rb.SPEC +0 -235
  326. data/test/test_arm.rb +0 -202
  327. data/test/test_arm.rb.SPEC +0 -275
  328. data/test/test_arm64.rb +0 -150
  329. data/test/test_arm64.rb.SPEC +0 -116
  330. data/test/test_detail.rb +0 -228
  331. data/test/test_detail.rb.SPEC +0 -322
  332. data/test/test_exhaustive.rb +0 -80
  333. data/test/test_mips.rb +0 -118
  334. data/test/test_mips.rb.SPEC +0 -91
  335. data/test/test_ppc.rb +0 -137
  336. data/test/test_ppc.rb.SPEC +0 -84
  337. data/test/test_sanity.rb +0 -83
  338. data/test/test_skipdata.rb +0 -111
  339. data/test/test_skipdata.rb.SPEC +0 -58
  340. data/test/test_sparc.rb +0 -113
  341. data/test/test_sparc.rb.SPEC +0 -116
  342. data/test/test_sysz.rb +0 -111
  343. data/test/test_sysz.rb.SPEC +0 -61
  344. data/test/test_x86.rb +0 -189
  345. data/test/test_x86.rb.SPEC +0 -579
  346. data/test/test_xcore.rb +0 -100
  347. data/test/test_xcore.rb.SPEC +0 -75
@@ -0,0 +1,59 @@
1
+ # frozen_string_literal: true
2
+
3
+ # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
4
+
5
+ require 'ffi'
6
+
7
+ require 'crabstone/arch/extension'
8
+ require_relative 'xcore_const'
9
+
10
+ module Crabstone
11
+ module XCore
12
+ class OperandMemory < FFI::Struct
13
+ layout(
14
+ :base, :uint8,
15
+ :index, :uint8,
16
+ :disp, :int,
17
+ :direct, :int
18
+ )
19
+ end
20
+
21
+ class OperandValue < FFI::Union
22
+ layout(
23
+ :reg, :uint,
24
+ :imm, :int,
25
+ :mem, OperandMemory
26
+ )
27
+ end
28
+
29
+ class Operand < FFI::Struct
30
+ layout(
31
+ :type, :uint,
32
+ :value, OperandValue
33
+ )
34
+
35
+ include Crabstone::Extension::Operand
36
+
37
+ def reg?
38
+ self[:type] == OP_REG
39
+ end
40
+
41
+ def imm?
42
+ self[:type] == OP_IMM
43
+ end
44
+
45
+ def mem?
46
+ self[:type] == OP_MEM
47
+ end
48
+ end
49
+
50
+ class Instruction < FFI::Struct
51
+ layout(
52
+ :op_count, :uint8,
53
+ :operands, [Operand, 8]
54
+ )
55
+
56
+ include Crabstone::Extension::Instruction
57
+ end
58
+ end
59
+ end
@@ -0,0 +1,171 @@
1
+ # frozen_string_literal: true
2
+
3
+ # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
4
+
5
+ require 'crabstone/arch/register'
6
+
7
+ module Crabstone
8
+ module XCore
9
+ OP_INVALID = 0
10
+ OP_REG = 1
11
+ OP_IMM = 2
12
+ OP_MEM = 3
13
+
14
+ REG_INVALID = 0
15
+ REG_CP = 1
16
+ REG_DP = 2
17
+ REG_LR = 3
18
+ REG_SP = 4
19
+ REG_R0 = 5
20
+ REG_R1 = 6
21
+ REG_R2 = 7
22
+ REG_R3 = 8
23
+ REG_R4 = 9
24
+ REG_R5 = 10
25
+ REG_R6 = 11
26
+ REG_R7 = 12
27
+ REG_R8 = 13
28
+ REG_R9 = 14
29
+ REG_R10 = 15
30
+ REG_R11 = 16
31
+ REG_PC = 17
32
+ REG_SCP = 18
33
+ REG_SSR = 19
34
+ REG_ET = 20
35
+ REG_ED = 21
36
+ REG_SED = 22
37
+ REG_KEP = 23
38
+ REG_KSP = 24
39
+ REG_ID = 25
40
+ REG_ENDING = 26
41
+
42
+ INS_INVALID = 0
43
+ INS_ADD = 1
44
+ INS_ANDNOT = 2
45
+ INS_AND = 3
46
+ INS_ASHR = 4
47
+ INS_BAU = 5
48
+ INS_BITREV = 6
49
+ INS_BLA = 7
50
+ INS_BLAT = 8
51
+ INS_BL = 9
52
+ INS_BF = 10
53
+ INS_BT = 11
54
+ INS_BU = 12
55
+ INS_BRU = 13
56
+ INS_BYTEREV = 14
57
+ INS_CHKCT = 15
58
+ INS_CLRE = 16
59
+ INS_CLRPT = 17
60
+ INS_CLRSR = 18
61
+ INS_CLZ = 19
62
+ INS_CRC8 = 20
63
+ INS_CRC32 = 21
64
+ INS_DCALL = 22
65
+ INS_DENTSP = 23
66
+ INS_DGETREG = 24
67
+ INS_DIVS = 25
68
+ INS_DIVU = 26
69
+ INS_DRESTSP = 27
70
+ INS_DRET = 28
71
+ INS_ECALLF = 29
72
+ INS_ECALLT = 30
73
+ INS_EDU = 31
74
+ INS_EEF = 32
75
+ INS_EET = 33
76
+ INS_EEU = 34
77
+ INS_ENDIN = 35
78
+ INS_ENTSP = 36
79
+ INS_EQ = 37
80
+ INS_EXTDP = 38
81
+ INS_EXTSP = 39
82
+ INS_FREER = 40
83
+ INS_FREET = 41
84
+ INS_GETD = 42
85
+ INS_GET = 43
86
+ INS_GETN = 44
87
+ INS_GETR = 45
88
+ INS_GETSR = 46
89
+ INS_GETST = 47
90
+ INS_GETTS = 48
91
+ INS_INCT = 49
92
+ INS_INIT = 50
93
+ INS_INPW = 51
94
+ INS_INSHR = 52
95
+ INS_INT = 53
96
+ INS_IN = 54
97
+ INS_KCALL = 55
98
+ INS_KENTSP = 56
99
+ INS_KRESTSP = 57
100
+ INS_KRET = 58
101
+ INS_LADD = 59
102
+ INS_LD16S = 60
103
+ INS_LD8U = 61
104
+ INS_LDA16 = 62
105
+ INS_LDAP = 63
106
+ INS_LDAW = 64
107
+ INS_LDC = 65
108
+ INS_LDW = 66
109
+ INS_LDIVU = 67
110
+ INS_LMUL = 68
111
+ INS_LSS = 69
112
+ INS_LSUB = 70
113
+ INS_LSU = 71
114
+ INS_MACCS = 72
115
+ INS_MACCU = 73
116
+ INS_MJOIN = 74
117
+ INS_MKMSK = 75
118
+ INS_MSYNC = 76
119
+ INS_MUL = 77
120
+ INS_NEG = 78
121
+ INS_NOT = 79
122
+ INS_OR = 80
123
+ INS_OUTCT = 81
124
+ INS_OUTPW = 82
125
+ INS_OUTSHR = 83
126
+ INS_OUTT = 84
127
+ INS_OUT = 85
128
+ INS_PEEK = 86
129
+ INS_REMS = 87
130
+ INS_REMU = 88
131
+ INS_RETSP = 89
132
+ INS_SETCLK = 90
133
+ INS_SET = 91
134
+ INS_SETC = 92
135
+ INS_SETD = 93
136
+ INS_SETEV = 94
137
+ INS_SETN = 95
138
+ INS_SETPSC = 96
139
+ INS_SETPT = 97
140
+ INS_SETRDY = 98
141
+ INS_SETSR = 99
142
+ INS_SETTW = 100
143
+ INS_SETV = 101
144
+ INS_SEXT = 102
145
+ INS_SHL = 103
146
+ INS_SHR = 104
147
+ INS_SSYNC = 105
148
+ INS_ST16 = 106
149
+ INS_ST8 = 107
150
+ INS_STW = 108
151
+ INS_SUB = 109
152
+ INS_SYNCR = 110
153
+ INS_TESTCT = 111
154
+ INS_TESTLCL = 112
155
+ INS_TESTWCT = 113
156
+ INS_TSETMR = 114
157
+ INS_START = 115
158
+ INS_WAITEF = 116
159
+ INS_WAITET = 117
160
+ INS_WAITEU = 118
161
+ INS_XOR = 119
162
+ INS_ZEXT = 120
163
+ INS_ENDING = 121
164
+
165
+ GRP_INVALID = 0
166
+ GRP_JUMP = 1
167
+ GRP_ENDING = 2
168
+
169
+ extend Register
170
+ end
171
+ end
@@ -0,0 +1,27 @@
1
+ # frozen_string_literal: true
2
+
3
+ module Crabstone
4
+ # These modules is for +class Operand+ and +class Instruction+ to extend.
5
+ # @private
6
+ module Extension
7
+ # For +class Operand+.
8
+ module Operand
9
+ def value
10
+ self[:value].class.members.find do |s|
11
+ return self[:value][s] if __send__("#{s}?".to_sym)
12
+ end
13
+ end
14
+
15
+ def valid?
16
+ !value.nil?
17
+ end
18
+ end
19
+
20
+ # For +class Instruction+.
21
+ module Instruction
22
+ def operands
23
+ self[:operands].take_while { |op| op[:type] != OP_INVALID }
24
+ end
25
+ end
26
+ end
27
+ end
@@ -0,0 +1,34 @@
1
+ # frozen_string_literal: true
2
+
3
+ require 'set'
4
+
5
+ module Crabstone
6
+ # Module for arch/<version>/<arch>_const.rb to extend.
7
+ module Register
8
+ # @param [Integer, String, Symbol] reg
9
+ # @return [Integer]
10
+ def register(reg)
11
+ return reg if value?(reg)
12
+
13
+ dict[reg.to_s.upcase] || invalid
14
+ end
15
+
16
+ private
17
+
18
+ def dict
19
+ return @dict if defined?(@dict)
20
+
21
+ keys = constants.select { |k| k.to_s.start_with?('REG_') }
22
+ @dict = keys.map { |k| [k.to_s[4..], const_get(k)] }.to_h.freeze
23
+ end
24
+
25
+ def value?(val)
26
+ @val_set ||= Set.new(dict.values)
27
+ @val_set.member?(val)
28
+ end
29
+
30
+ def invalid
31
+ dict['INVALID']
32
+ end
33
+ end
34
+ end
@@ -0,0 +1,37 @@
1
+ # frozen_string_literal: true
2
+
3
+ require 'crabstone/constants'
4
+ require 'crabstone/cs_version'
5
+
6
+ # require all files under 'crabstone/arch/<cs_major_version>'
7
+ Dir.glob(File.join(__dir__, 'arch', Crabstone.cs_major_version.to_s, '*.rb')).sort.each do |f|
8
+ require f
9
+ end
10
+
11
+ module Crabstone
12
+ module Arch
13
+ module_function
14
+
15
+ # @param [Integer] arch
16
+ # @return [Module]
17
+ # @example
18
+ # Arch.module_of(Crabstone::ARCH_X86)
19
+ # #=> Crabstone::X86
20
+ def module_of(arch)
21
+ case arch
22
+ when ARCH_ARM then ARM
23
+ when ARCH_ARM64 then ARM64
24
+ when ARCH_X86 then X86
25
+ when ARCH_MIPS then MIPS
26
+ when ARCH_PPC then PPC
27
+ when ARCH_SPARC then Sparc
28
+ when ARCH_SYSZ then SysZ
29
+ when ARCH_XCORE then XCore
30
+ when ARCH_M68K then M68K
31
+ when ARCH_TMS320C64X then TMS320C64X
32
+ when ARCH_M680X then M680X
33
+ when ARCH_EVM then EVM
34
+ end
35
+ end
36
+ end
37
+ end
@@ -0,0 +1,36 @@
1
+ # frozen_string_literal: true
2
+
3
+ # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
4
+
5
+ require 'ffi'
6
+
7
+ require 'crabstone/arch'
8
+
9
+ module Crabstone
10
+ module Binding
11
+ class Architecture < FFI::Union
12
+ layout(
13
+ :arm, ARM::Instruction,
14
+ :arm64, ARM64::Instruction,
15
+ :mips, MIPS::Instruction,
16
+ :ppc, PPC::Instruction,
17
+ :sparc, Sparc::Instruction,
18
+ :sysz, SysZ::Instruction,
19
+ :x86, X86::Instruction,
20
+ :xcore, XCore::Instruction
21
+ )
22
+ end
23
+
24
+ class Detail < FFI::Struct
25
+ layout(
26
+ :regs_read, [:uint8, 12],
27
+ :regs_read_count, :uint8,
28
+ :regs_write, [:uint8, 20],
29
+ :regs_write_count, :uint8,
30
+ :groups, [:uint8, 8],
31
+ :groups_count, :uint8,
32
+ :arch, Architecture
33
+ )
34
+ end
35
+ end
36
+ end
@@ -0,0 +1,23 @@
1
+ # frozen_string_literal: true
2
+
3
+ # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
4
+
5
+ require 'ffi'
6
+
7
+ require_relative 'detail'
8
+
9
+ module Crabstone
10
+ module Binding
11
+ class Instruction < FFI::ManagedStruct
12
+ layout(
13
+ :id, :uint32,
14
+ :address, :uint64,
15
+ :size, :uint16,
16
+ :bytes, [:uint8, 16],
17
+ :mnemonic, [:char, 32],
18
+ :op_str, [:char, 160],
19
+ :detail, Detail.by_ref
20
+ )
21
+ end
22
+ end
23
+ end
@@ -0,0 +1,40 @@
1
+ # frozen_string_literal: true
2
+
3
+ # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
4
+
5
+ require 'ffi'
6
+
7
+ require 'crabstone/arch'
8
+
9
+ module Crabstone
10
+ module Binding
11
+ class Architecture < FFI::Union
12
+ layout(
13
+ :arm, ARM::Instruction,
14
+ :arm64, ARM64::Instruction,
15
+ :evm, EVM::Instruction,
16
+ :m680x, M680X::Instruction,
17
+ :m68k, M68K::Instruction,
18
+ :mips, MIPS::Instruction,
19
+ :ppc, PPC::Instruction,
20
+ :sparc, Sparc::Instruction,
21
+ :sysz, SysZ::Instruction,
22
+ :tms320c64x, TMS320C64X::Instruction,
23
+ :x86, X86::Instruction,
24
+ :xcore, XCore::Instruction
25
+ )
26
+ end
27
+
28
+ class Detail < FFI::Struct
29
+ layout(
30
+ :regs_read, [:uint16, 12],
31
+ :regs_read_count, :uint8,
32
+ :regs_write, [:uint16, 20],
33
+ :regs_write_count, :uint8,
34
+ :groups, [:uint8, 8],
35
+ :groups_count, :uint8,
36
+ :arch, Architecture
37
+ )
38
+ end
39
+ end
40
+ end
@@ -0,0 +1,23 @@
1
+ # frozen_string_literal: true
2
+
3
+ # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
4
+
5
+ require 'ffi'
6
+
7
+ require_relative 'detail'
8
+
9
+ module Crabstone
10
+ module Binding
11
+ class Instruction < FFI::ManagedStruct
12
+ layout(
13
+ :id, :uint32,
14
+ :address, :uint64,
15
+ :size, :uint16,
16
+ :bytes, [:uint8, 16],
17
+ :mnemonic, [:char, 32],
18
+ :op_str, [:char, 160],
19
+ :detail, Detail.by_ref
20
+ )
21
+ end
22
+ end
23
+ end
@@ -0,0 +1,32 @@
1
+ # frozen_string_literal: true
2
+
3
+ require 'ffi'
4
+
5
+ require 'crabstone/cs_version'
6
+ Crabstone.version_require 'crabstone/binding/%v/instruction'
7
+
8
+ module Crabstone
9
+ module Binding
10
+ # This is because JRuby FFI on x64 Windows thinks size_t is 32 bit
11
+ typedef(FFI::Platform::ADDRESS_SIZE == 32 ? :ulong : :ulong_long, :size_t)
12
+
13
+ # If one day these definitions change, move them to <version>/ dir.
14
+
15
+ typedef :size_t, :csh
16
+ typedef :size_t, :cs_opt_value
17
+ typedef :uint, :cs_opt_type
18
+ typedef :uint, :cs_err
19
+ typedef :uint, :cs_arch
20
+ typedef :uint, :cs_mode
21
+
22
+ callback :skipdata_cb, %i[pointer size_t size_t pointer], :size_t
23
+
24
+ class SkipdataConfig < FFI::Struct
25
+ layout(
26
+ :mnemonic, :pointer,
27
+ :callback, :skipdata_cb,
28
+ :unused, :pointer
29
+ )
30
+ end
31
+ end
32
+ end
@@ -0,0 +1,59 @@
1
+ # frozen_string_literal: true
2
+
3
+ require 'crabstone/constants'
4
+ require 'crabstone/binding/structs'
5
+
6
+ module Crabstone
7
+ module Binding
8
+ class Instruction < FFI::ManagedStruct
9
+ def self.release(obj)
10
+ detail_ptr = obj.+(Instruction.offset_of(:detail)).read_pointer
11
+ Binding.free(detail_ptr)
12
+ Binding.free(obj)
13
+ end
14
+ end
15
+
16
+ # These APIs still might be changed in a new Capstone version.
17
+ attach_function(
18
+ :cs_disasm,
19
+ %i[csh pointer size_t ulong_long size_t pointer],
20
+ :size_t
21
+ )
22
+ attach_function :cs_close, [:pointer], :cs_err
23
+ attach_function :cs_errno, [:csh], :cs_err
24
+ attach_function :cs_group_name, %i[csh uint], :string
25
+ attach_function :cs_insn_group, [:csh, Instruction, :uint], :bool
26
+ attach_function :cs_insn_name, %i[csh uint], :string
27
+ attach_function :cs_op_count, [:csh, Instruction, :uint], :cs_err
28
+ attach_function :cs_open, %i[cs_arch cs_mode pointer], :cs_err
29
+ attach_function :cs_option, %i[csh cs_opt_type cs_opt_value], :cs_err
30
+ attach_function :cs_reg_name, %i[csh uint], :string
31
+ attach_function :cs_reg_read, [:csh, Instruction, :uint], :bool
32
+ attach_function :cs_reg_write, [:csh, Instruction, :uint], :bool
33
+ attach_function :cs_strerror, [:cs_err], :string
34
+ attach_function :cs_support, [:cs_arch], :bool
35
+ # Already defined in cs_version.rb
36
+ # attach_function :cs_version, %i[pointer pointer], :uint
37
+ attach_function :memcpy, %i[pointer pointer size_t], :pointer
38
+ attach_function :malloc, [:size_t], :pointer
39
+ attach_function :free, [:pointer], :void
40
+
41
+ # Wrap to prevent function not found in elder Capstone.
42
+ def self.safe_attach(*args)
43
+ attach_function(*args)
44
+ rescue FFI::NotFoundError
45
+ end
46
+
47
+ # New APIs since Capstone 4.
48
+ safe_attach :cs_regs_access, [:csh, Instruction, :pointer, :pointer, :pointer, :pointer], :cs_err
49
+ end
50
+
51
+ # This is a C engine build option, so we can set it here, not when we
52
+ # instantiate a new Disassembler.
53
+ # Diet mode means:
54
+ # - No op_str or mnemonic in Instruction
55
+ # - No regs_read, regs_write or groups ( even with detail on )
56
+ # - No reg_name or insn_name id2str convenience functions
57
+ # - detail mode CAN still be on - so the arch insn operands MAY be available
58
+ DIET_MODE = Binding.cs_support(SUPPORT_DIET)
59
+ end
@@ -0,0 +1,110 @@
1
+ # frozen_string_literal: true
2
+
3
+ # XXX: Auto-gerneate this file?
4
+ # Constants in this file might be added in a newer Capstone version,
5
+ # but I expect they are always backward compatible.
6
+
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+ require 'crabstone/version'
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+
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+ module Crabstone
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+ # API version
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+ BINDING_MAJ = VERSION.split('.').first.to_i
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+
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+ # architectures
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+ ARCH_ARM = 0
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+ ARCH_ARM64 = 1
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+ ARCH_MIPS = 2
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+ ARCH_X86 = 3
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+ ARCH_PPC = 4
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+ ARCH_SPARC = 5
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+ ARCH_SYSZ = 6
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+ ARCH_XCORE = 7
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+ ARCH_M68K = 8
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+ ARCH_TMS320C64X = 9
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+ ARCH_M680X = 10
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+ ARCH_EVM = 11
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+ ARCH_MAX = 12
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+ ARCH_ALL = 0xFFFF
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+
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+ # disasm mode
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+ MODE_LITTLE_ENDIAN = 0 # little-endian mode (default mode)
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+ MODE_ARM = 0 # 32-bit ARM
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+ MODE_16 = 1 << 1 # 16-bit mode (X86)
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+ MODE_32 = 1 << 2 # 32-bit mode (X86)
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+ MODE_64 = 1 << 3 # 64-bit mode (X86, PPC)
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+ MODE_THUMB = 1 << 4 # ARM's Thumb mode, including Thumb-2
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+ MODE_MCLASS = 1 << 5 # ARM's Cortex-M series
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+ MODE_V8 = 1 << 6 # ARMv8 A32 encodings for ARM
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+ MODE_MICRO = 1 << 4 # MicroMips mode (MIPS)
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+ MODE_MIPS3 = 1 << 5 # Mips III ISA
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+ MODE_MIPS32R6 = 1 << 6 # Mips32r6 ISA
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+ MODE_MIPSGP64 = 1 << 7 # General Purpose Registers are 64-bit wide (MIPS)
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+ MODE_MODE_MIPS2 = 1 << 7 # Mips II ISA
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+ MODE_V9 = 1 << 4 # SparcV9 mode (Sparc)
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+ MODE_QPX = 1 << 4 # Quad Processing eXtensions mode (PPC)
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+ MODE_M68K_000 = 1 << 1 # M68K 68000 mode
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+ MODE_M68K_010 = 1 << 2 # M68K 68010 mode
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+ MODE_M68K_020 = 1 << 3 # M68K 68020 mode
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+ MODE_M68K_030 = 1 << 4 # M68K 68030 mode
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+ MODE_M68K_040 = 1 << 5 # M68K 68040 mode
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+ MODE_M68K_060 = 1 << 6 # M68K 68060 mode
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+ MODE_BIG_ENDIAN = 1 << 31 # big-endian mode
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+ MODE_MIPS32 = MODE_32 # Mips32 ISA (Mips)
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+ MODE_MIPS64 = MODE_64 # Mips64 ISA (Mips)
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+ MODE_M680X_6301 = 1 << 1 # M680X HD6301/3 mode
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+ MODE_M680X_6309 = 1 << 2 # M680X HD6309 mode
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+ MODE_M680X_6800 = 1 << 3 # M680X M6800/2 mode
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+ MODE_M680X_6801 = 1 << 4 # M680X M6801/3 mode
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+ MODE_M680X_6805 = 1 << 5 # M680X M6805 mode
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+ MODE_M680X_6808 = 1 << 6 # M680X M68HC08 mode
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+ MODE_M680X_6809 = 1 << 7 # M680X M6809 mode
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+ MODE_M680X_6811 = 1 << 8 # M680X M68HC11 mode
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+ MODE_M680X_CPU12 = 1 << 9 # M680X CPU12 mode
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+ MODE_M680X_HCS08 = 1 << 10 # M680X HCS08 mode
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+
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+ # Capstone option type
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+ OPT_SYNTAX = 1 # Intel X86 asm syntax (ARCH_X86 arch)
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+ OPT_DETAIL = 2 # Break down instruction structure into details
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+ OPT_MODE = 3 # Change engine's mode at run-time
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+ OPT_MEM = 4 # Change engine's mode at run-time
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+ OPT_SKIPDATA = 5 # Skip data when disassembling
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+ OPT_SKIPDATA_SETUP = 6 # Setup user-defined function for SKIPDATA option
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+ OPT_MNEMONIC = 7 # Customize instruction mnemonic
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+ OPT_UNSIGNED = 8 # Print immediate in unsigned form
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+
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+ # Capstone option value
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+ OPT_OFF = 0 # Turn OFF an option - default option of OPT_DETAIL
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+ OPT_ON = 3 # Turn ON an option (OPT_DETAIL)
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+
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+ # Common instruction operand types - to be consistent across all architectures.
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+ OP_INVALID = 0
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+ OP_REG = 1
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+ OP_IMM = 2
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+ OP_MEM = 3
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+ OP_FP = 4
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+
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+ # Common instruction groups - to be consistent across all architectures.
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+ GRP_INVALID = 0 # uninitialized/invalid group.
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+ GRP_JUMP = 1 # all jump instructions (conditional+direct+indirect jumps)
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+ GRP_CALL = 2 # all call instructions
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+ GRP_RET = 3 # all return instructions
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+ GRP_INT = 4 # all interrupt instructions (int+syscall)
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+ GRP_IRET = 5 # all interrupt return instructions
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+ GRP_PRIVILEGE = 6 # all privileged instructions
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+
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+ # Access types for instruction operands.
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+ AC_INVALID = 0 # Invalid/unitialized access type.
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+ AC_READ = 1 << 0 # Operand that is read from.
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+ AC_WRITE = 1 << 1 # Operand that is written to.
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+
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+ # Capstone syntax value
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+ OPT_SYNTAX_DEFAULT = 0 # Default assembly syntax of all platforms (OPT_SYNTAX)
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+ OPT_SYNTAX_INTEL = 1 # Intel X86 asm syntax - default syntax on X86 (OPT_SYNTAX, ARCH_X86)
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+ OPT_SYNTAX_ATT = 2 # ATT asm syntax (OPT_SYNTAX, ARCH_X86)
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+ OPT_SYNTAX_NOREGNAME = 3 # Asm syntax prints register name with only number - (OPT_SYNTAX, ARCH_PPC, ARCH_ARM)
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+ OPT_SYNTAX_MASM = 4 # MASM syntax (CS_OPT_SYNTAX, CS_ARCH_X86)
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+
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+ # query id for cs_support()
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+ SUPPORT_DIET = ARCH_ALL + 1
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+ SUPPORT_X86_REDUCE = ARCH_ALL + 2
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+ end