crabstone 3.0.3 → 4.0.4

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (347) hide show
  1. checksums.yaml +5 -5
  2. data/CHANGES.md +59 -42
  3. data/README.md +37 -39
  4. data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
  5. data/lib/crabstone/arch/3/arm64.rb +124 -0
  6. data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
  7. data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
  8. data/lib/crabstone/arch/3/mips.rb +57 -0
  9. data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
  10. data/lib/crabstone/arch/3/ppc.rb +73 -0
  11. data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
  12. data/lib/crabstone/arch/3/sparc.rb +60 -0
  13. data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
  14. data/lib/crabstone/arch/3/sysz.rb +67 -0
  15. data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
  16. data/lib/crabstone/arch/3/x86.rb +82 -0
  17. data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
  18. data/lib/crabstone/arch/3/xcore.rb +59 -0
  19. data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
  20. data/lib/crabstone/arch/4/arm.rb +110 -0
  21. data/lib/crabstone/arch/4/arm64.rb +125 -0
  22. data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
  23. data/lib/crabstone/arch/4/arm_const.rb +785 -0
  24. data/lib/crabstone/arch/4/evm.rb +20 -0
  25. data/lib/crabstone/arch/4/evm_const.rb +161 -0
  26. data/lib/crabstone/arch/4/m680x.rb +106 -0
  27. data/lib/crabstone/arch/4/m680x_const.rb +426 -0
  28. data/lib/crabstone/arch/4/m68k.rb +129 -0
  29. data/lib/crabstone/arch/4/m68k_const.rb +496 -0
  30. data/lib/crabstone/arch/4/mips.rb +57 -0
  31. data/lib/crabstone/arch/4/mips_const.rb +869 -0
  32. data/lib/crabstone/arch/4/ppc.rb +73 -0
  33. data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
  34. data/lib/crabstone/arch/4/sparc.rb +60 -0
  35. data/lib/crabstone/arch/4/sparc_const.rb +439 -0
  36. data/lib/crabstone/arch/4/sysz.rb +67 -0
  37. data/lib/crabstone/arch/4/sysz_const.rb +763 -0
  38. data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
  39. data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
  40. data/lib/crabstone/arch/4/x86.rb +91 -0
  41. data/lib/crabstone/arch/4/x86_const.rb +1972 -0
  42. data/lib/crabstone/arch/4/xcore.rb +59 -0
  43. data/lib/crabstone/arch/4/xcore_const.rb +171 -0
  44. data/lib/crabstone/arch/extension.rb +27 -0
  45. data/lib/crabstone/arch/register.rb +34 -0
  46. data/lib/crabstone/arch.rb +37 -0
  47. data/lib/crabstone/binding/3/detail.rb +36 -0
  48. data/lib/crabstone/binding/3/instruction.rb +23 -0
  49. data/lib/crabstone/binding/4/detail.rb +40 -0
  50. data/lib/crabstone/binding/4/instruction.rb +23 -0
  51. data/lib/crabstone/binding/structs.rb +32 -0
  52. data/lib/crabstone/binding.rb +59 -0
  53. data/lib/crabstone/constants.rb +110 -0
  54. data/lib/crabstone/cs_version.rb +57 -0
  55. data/lib/crabstone/disassembler.rb +147 -0
  56. data/lib/crabstone/error.rb +74 -0
  57. data/lib/crabstone/instruction.rb +178 -0
  58. data/lib/crabstone/version.rb +5 -0
  59. data/lib/crabstone.rb +5 -557
  60. metadata +142 -331
  61. data/MANIFEST +0 -312
  62. data/Rakefile +0 -27
  63. data/bin/genconst +0 -66
  64. data/bin/genreg +0 -99
  65. data/crabstone.gemspec +0 -27
  66. data/examples/hello_world.rb +0 -43
  67. data/lib/arch/arm64.rb +0 -167
  68. data/lib/arch/arm64_registers.rb +0 -295
  69. data/lib/arch/arm_registers.rb +0 -149
  70. data/lib/arch/mips.rb +0 -78
  71. data/lib/arch/mips_registers.rb +0 -208
  72. data/lib/arch/ppc.rb +0 -90
  73. data/lib/arch/ppc_registers.rb +0 -209
  74. data/lib/arch/sparc.rb +0 -79
  75. data/lib/arch/sparc_registers.rb +0 -121
  76. data/lib/arch/systemz.rb +0 -79
  77. data/lib/arch/sysz_registers.rb +0 -66
  78. data/lib/arch/x86.rb +0 -107
  79. data/lib/arch/x86_registers.rb +0 -265
  80. data/lib/arch/xcore.rb +0 -78
  81. data/lib/arch/xcore_registers.rb +0 -57
  82. data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
  83. data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
  84. data/test/MC/AArch64/neon-2velem.s.cs +0 -113
  85. data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
  86. data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
  87. data/test/MC/AArch64/neon-across.s.cs +0 -40
  88. data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
  89. data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
  90. data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
  91. data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
  92. data/test/MC/AArch64/neon-crypto.s.cs +0 -15
  93. data/test/MC/AArch64/neon-extract.s.cs +0 -3
  94. data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
  95. data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
  96. data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
  97. data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
  98. data/test/MC/AArch64/neon-max-min.s.cs +0 -37
  99. data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
  100. data/test/MC/AArch64/neon-mov.s.cs +0 -74
  101. data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
  102. data/test/MC/AArch64/neon-perm.s.cs +0 -43
  103. data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
  104. data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
  105. data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
  106. data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
  107. data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
  108. data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
  109. data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
  110. data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
  111. data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
  112. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
  113. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
  114. data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
  115. data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
  116. data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
  117. data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
  118. data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
  119. data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
  120. data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
  121. data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
  122. data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
  123. data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
  124. data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
  125. data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
  126. data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
  127. data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
  128. data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
  129. data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
  130. data/test/MC/AArch64/neon-shift.s.cs +0 -22
  131. data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
  132. data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
  133. data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
  134. data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
  135. data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
  136. data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
  137. data/test/MC/AArch64/neon-tbl.s.cs +0 -21
  138. data/test/MC/AArch64/trace-regs.s.cs +0 -383
  139. data/test/MC/ARM/arm-aliases.s.cs +0 -7
  140. data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
  141. data/test/MC/ARM/arm-it-block.s.cs +0 -2
  142. data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
  143. data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
  144. data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
  145. data/test/MC/ARM/arm-trustzone.s.cs +0 -3
  146. data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
  147. data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
  148. data/test/MC/ARM/arm_instructions.s.cs +0 -25
  149. data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
  150. data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
  151. data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
  152. data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
  153. data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
  154. data/test/MC/ARM/crc32-thumb.s.cs +0 -7
  155. data/test/MC/ARM/crc32.s.cs +0 -7
  156. data/test/MC/ARM/dot-req.s.cs +0 -3
  157. data/test/MC/ARM/fp-armv8.s.cs +0 -52
  158. data/test/MC/ARM/idiv-thumb.s.cs +0 -3
  159. data/test/MC/ARM/idiv.s.cs +0 -3
  160. data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
  161. data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
  162. data/test/MC/ARM/mode-switch.s.cs +0 -7
  163. data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
  164. data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
  165. data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
  166. data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
  167. data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
  168. data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
  169. data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
  170. data/test/MC/ARM/neon-crypto.s.cs +0 -16
  171. data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
  172. data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
  173. data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
  174. data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
  175. data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
  176. data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
  177. data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
  178. data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
  179. data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
  180. data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
  181. data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
  182. data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
  183. data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
  184. data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
  185. data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
  186. data/test/MC/ARM/neon-v8.s.cs +0 -38
  187. data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
  188. data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
  189. data/test/MC/ARM/neon-vswp.s.cs +0 -3
  190. data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
  191. data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
  192. data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
  193. data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
  194. data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
  195. data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
  196. data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
  197. data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
  198. data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
  199. data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
  200. data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
  201. data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
  202. data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
  203. data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
  204. data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
  205. data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
  206. data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
  207. data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
  208. data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
  209. data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
  210. data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
  211. data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
  212. data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
  213. data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
  214. data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
  215. data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
  216. data/test/MC/ARM/thumb-hints.s.cs +0 -12
  217. data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
  218. data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
  219. data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
  220. data/test/MC/ARM/thumb.s.cs +0 -19
  221. data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
  222. data/test/MC/ARM/thumb2-branches.s.cs +0 -85
  223. data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
  224. data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
  225. data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
  226. data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
  227. data/test/MC/ARM/vfp4.s.cs +0 -13
  228. data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
  229. data/test/MC/ARM/vpush-vpop.s.cs +0 -9
  230. data/test/MC/Mips/hilo-addressing.s.cs +0 -4
  231. data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
  232. data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
  233. data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
  234. data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
  235. data/test/MC/Mips/micromips-expansions.s.cs +0 -20
  236. data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
  237. data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
  238. data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
  239. data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
  240. data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
  241. data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
  242. data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
  243. data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
  244. data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
  245. data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
  246. data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
  247. data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
  248. data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
  249. data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
  250. data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
  251. data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
  252. data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
  253. data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
  254. data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
  255. data/test/MC/Mips/mips-expansions.s.cs +0 -20
  256. data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
  257. data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
  258. data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
  259. data/test/MC/Mips/mips-register-names.s.cs +0 -33
  260. data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
  261. data/test/MC/Mips/mips64-instructions.s.cs +0 -3
  262. data/test/MC/Mips/mips64-register-names.s.cs +0 -33
  263. data/test/MC/Mips/mips_directives.s.cs +0 -12
  264. data/test/MC/Mips/nabi-regs.s.cs +0 -12
  265. data/test/MC/Mips/set-at-directive.s.cs +0 -6
  266. data/test/MC/Mips/test_2r.s.cs +0 -16
  267. data/test/MC/Mips/test_2rf.s.cs +0 -33
  268. data/test/MC/Mips/test_3r.s.cs +0 -243
  269. data/test/MC/Mips/test_3rf.s.cs +0 -83
  270. data/test/MC/Mips/test_bit.s.cs +0 -49
  271. data/test/MC/Mips/test_cbranch.s.cs +0 -11
  272. data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
  273. data/test/MC/Mips/test_elm.s.cs +0 -16
  274. data/test/MC/Mips/test_elm_insert.s.cs +0 -4
  275. data/test/MC/Mips/test_elm_insve.s.cs +0 -5
  276. data/test/MC/Mips/test_i10.s.cs +0 -5
  277. data/test/MC/Mips/test_i5.s.cs +0 -45
  278. data/test/MC/Mips/test_i8.s.cs +0 -11
  279. data/test/MC/Mips/test_lsa.s.cs +0 -5
  280. data/test/MC/Mips/test_mi10.s.cs +0 -24
  281. data/test/MC/Mips/test_vec.s.cs +0 -8
  282. data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
  283. data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
  284. data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
  285. data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
  286. data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
  287. data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
  288. data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
  289. data/test/MC/README +0 -6
  290. data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
  291. data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
  292. data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
  293. data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
  294. data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
  295. data/test/MC/Sparc/sparc-vis.s.cs +0 -2
  296. data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
  297. data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
  298. data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
  299. data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
  300. data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
  301. data/test/MC/SystemZ/insn-good.s.cs +0 -2265
  302. data/test/MC/SystemZ/regs-good.s.cs +0 -45
  303. data/test/MC/X86/3DNow.s.cs +0 -29
  304. data/test/MC/X86/address-size.s.cs +0 -5
  305. data/test/MC/X86/avx512-encodings.s.cs +0 -12
  306. data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
  307. data/test/MC/X86/x86-32-avx.s.cs +0 -833
  308. data/test/MC/X86/x86-32-fma3.s.cs +0 -169
  309. data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
  310. data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
  311. data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
  312. data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
  313. data/test/MC/X86/x86_64-encoding.s.cs +0 -59
  314. data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
  315. data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
  316. data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
  317. data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
  318. data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
  319. data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
  320. data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
  321. data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
  322. data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
  323. data/test/README +0 -6
  324. data/test/test.rb +0 -205
  325. data/test/test.rb.SPEC +0 -235
  326. data/test/test_arm.rb +0 -202
  327. data/test/test_arm.rb.SPEC +0 -275
  328. data/test/test_arm64.rb +0 -150
  329. data/test/test_arm64.rb.SPEC +0 -116
  330. data/test/test_detail.rb +0 -228
  331. data/test/test_detail.rb.SPEC +0 -322
  332. data/test/test_exhaustive.rb +0 -80
  333. data/test/test_mips.rb +0 -118
  334. data/test/test_mips.rb.SPEC +0 -91
  335. data/test/test_ppc.rb +0 -137
  336. data/test/test_ppc.rb.SPEC +0 -84
  337. data/test/test_sanity.rb +0 -83
  338. data/test/test_skipdata.rb +0 -111
  339. data/test/test_skipdata.rb.SPEC +0 -58
  340. data/test/test_sparc.rb +0 -113
  341. data/test/test_sparc.rb.SPEC +0 -116
  342. data/test/test_sysz.rb +0 -111
  343. data/test/test_sysz.rb.SPEC +0 -61
  344. data/test/test_x86.rb +0 -189
  345. data/test/test_x86.rb.SPEC +0 -579
  346. data/test/test_xcore.rb +0 -100
  347. data/test/test_xcore.rb.SPEC +0 -75
@@ -1,26 +1,18 @@
1
- # Library by Nguyen Anh Quynh
2
- # Original binding by Nguyen Anh Quynh and Tan Sheng Di
3
- # Additional binding work by Ben Nagy
4
- # (c) 2013 COSEINC. All Rights Reserved.
1
+ # frozen_string_literal: true
5
2
 
6
3
  # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
7
- # Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/
8
- # 2015-05-02T13:24:01+12:00
4
+
5
+ require 'crabstone/arch/register'
9
6
 
10
7
  module Crabstone
11
8
  module ARM64
12
-
13
- # ARM64 shift type
14
-
15
9
  SFT_INVALID = 0
16
10
  SFT_LSL = 1
17
11
  SFT_MSL = 2
18
12
  SFT_LSR = 3
19
13
  SFT_ASR = 4
20
14
  SFT_ROR = 5
21
-
22
- # ARM64 extender type
23
-
15
+
24
16
  EXT_INVALID = 0
25
17
  EXT_UXTB = 1
26
18
  EXT_UXTH = 2
@@ -30,9 +22,7 @@ module Crabstone
30
22
  EXT_SXTH = 6
31
23
  EXT_SXTW = 7
32
24
  EXT_SXTX = 8
33
-
34
- # ARM64 condition code
35
-
25
+
36
26
  CC_INVALID = 0
37
27
  CC_EQ = 1
38
28
  CC_NE = 2
@@ -50,11 +40,7 @@ module Crabstone
50
40
  CC_LE = 14
51
41
  CC_AL = 15
52
42
  CC_NV = 16
53
-
54
- # System registers
55
-
56
- # System registers for MRS
57
-
43
+
58
44
  SYSREG_INVALID = 0
59
45
  SYSREG_MDCCSR_EL0 = 0x9808
60
46
  SYSREG_DBGDTRRX_EL0 = 0x9828
@@ -148,8 +134,7 @@ module Crabstone
148
134
  SYSREG_ICH_VTR_EL2 = 0xe659
149
135
  SYSREG_ICH_EISR_EL2 = 0xe65b
150
136
  SYSREG_ICH_ELSR_EL2 = 0xe65d
151
-
152
- # System registers for MSR
137
+
153
138
  SYSREG_DBGDTRTX_EL0 = 0x9828
154
139
  SYSREG_OSLAR_EL1 = 0x8084
155
140
  SYSREG_PMSWINC_EL0 = 0xdce4
@@ -161,16 +146,12 @@ module Crabstone
161
146
  SYSREG_ICC_SGI1R_EL1 = 0xc65d
162
147
  SYSREG_ICC_ASGI1R_EL1 = 0xc65e
163
148
  SYSREG_ICC_SGI0R_EL1 = 0xc65f
164
-
165
- # System PState Field (MSR instruction)
166
-
149
+
167
150
  PSTATE_INVALID = 0
168
151
  PSTATE_SPSEL = 0x05
169
152
  PSTATE_DAIFSET = 0x1e
170
153
  PSTATE_DAIFCLR = 0x1f
171
-
172
- # Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)
173
-
154
+
174
155
  VAS_INVALID = 0
175
156
  VAS_8B = 1
176
157
  VAS_16B = 2
@@ -181,17 +162,13 @@ module Crabstone
181
162
  VAS_1D = 7
182
163
  VAS_2D = 8
183
164
  VAS_1Q = 9
184
-
185
- # Vector element size specifier
186
-
165
+
187
166
  VESS_INVALID = 0
188
167
  VESS_B = 1
189
168
  VESS_H = 2
190
169
  VESS_S = 3
191
170
  VESS_D = 4
192
-
193
- # Memory barrier operands
194
-
171
+
195
172
  BARRIER_INVALID = 0
196
173
  BARRIER_OSHLD = 0x1
197
174
  BARRIER_OSHST = 0x2
@@ -205,9 +182,7 @@ module Crabstone
205
182
  BARRIER_LD = 0xd
206
183
  BARRIER_ST = 0xe
207
184
  BARRIER_SY = 0xf
208
-
209
- # Operand type for instruction's operands
210
-
185
+
211
186
  OP_INVALID = 0
212
187
  OP_REG = 1
213
188
  OP_IMM = 2
@@ -220,9 +195,7 @@ module Crabstone
220
195
  OP_SYS = 68
221
196
  OP_PREFETCH = 69
222
197
  OP_BARRIER = 70
223
-
224
- # TLBI operations
225
-
198
+
226
199
  TLBI_INVALID = 0
227
200
  TLBI_VMALLE1IS = 1
228
201
  TLBI_VAE1IS = 2
@@ -256,8 +229,7 @@ module Crabstone
256
229
  TLBI_ALLE3 = 30
257
230
  TLBI_VAE3 = 31
258
231
  TLBI_VALE3 = 32
259
-
260
- # AT operations
232
+
261
233
  AT_S1E1R = 33
262
234
  AT_S1E1W = 34
263
235
  AT_S1E0R = 35
@@ -270,9 +242,7 @@ module Crabstone
270
242
  AT_S12E0W = 42
271
243
  AT_S1E3R = 43
272
244
  AT_S1E3W = 44
273
-
274
- # DC operations
275
-
245
+
276
246
  DC_INVALID = 0
277
247
  DC_ZVA = 1
278
248
  DC_IVAC = 2
@@ -282,38 +252,32 @@ module Crabstone
282
252
  DC_CVAU = 6
283
253
  DC_CIVAC = 7
284
254
  DC_CISW = 8
285
-
286
- # IC operations
287
-
255
+
288
256
  IC_INVALID = 0
289
257
  IC_IALLUIS = 1
290
258
  IC_IALLU = 2
291
259
  IC_IVAU = 3
292
-
293
- # Prefetch operations (PRFM)
294
-
260
+
295
261
  PRFM_INVALID = 0
296
- PRFM_PLDL1KEEP = 0x00+1
297
- PRFM_PLDL1STRM = 0x01+1
298
- PRFM_PLDL2KEEP = 0x02+1
299
- PRFM_PLDL2STRM = 0x03+1
300
- PRFM_PLDL3KEEP = 0x04+1
301
- PRFM_PLDL3STRM = 0x05+1
302
- PRFM_PLIL1KEEP = 0x08+1
303
- PRFM_PLIL1STRM = 0x09+1
304
- PRFM_PLIL2KEEP = 0x0a+1
305
- PRFM_PLIL2STRM = 0x0b+1
306
- PRFM_PLIL3KEEP = 0x0c+1
307
- PRFM_PLIL3STRM = 0x0d+1
308
- PRFM_PSTL1KEEP = 0x10+1
309
- PRFM_PSTL1STRM = 0x11+1
310
- PRFM_PSTL2KEEP = 0x12+1
311
- PRFM_PSTL2STRM = 0x13+1
312
- PRFM_PSTL3KEEP = 0x14+1
313
- PRFM_PSTL3STRM = 0x15+1
314
-
315
- # ARM64 registers
316
-
262
+ PRFM_PLDL1KEEP = 0x00 + 1
263
+ PRFM_PLDL1STRM = 0x01 + 1
264
+ PRFM_PLDL2KEEP = 0x02 + 1
265
+ PRFM_PLDL2STRM = 0x03 + 1
266
+ PRFM_PLDL3KEEP = 0x04 + 1
267
+ PRFM_PLDL3STRM = 0x05 + 1
268
+ PRFM_PLIL1KEEP = 0x08 + 1
269
+ PRFM_PLIL1STRM = 0x09 + 1
270
+ PRFM_PLIL2KEEP = 0x0a + 1
271
+ PRFM_PLIL2STRM = 0x0b + 1
272
+ PRFM_PLIL3KEEP = 0x0c + 1
273
+ PRFM_PLIL3STRM = 0x0d + 1
274
+ PRFM_PSTL1KEEP = 0x10 + 1
275
+ PRFM_PSTL1STRM = 0x11 + 1
276
+ PRFM_PSTL2KEEP = 0x12 + 1
277
+ PRFM_PSTL2STRM = 0x13 + 1
278
+ PRFM_PSTL3KEEP = 0x14 + 1
279
+ PRFM_PSTL3STRM = 0x15 + 1
280
+
317
281
  REG_INVALID = 0
318
282
  REG_X29 = 1
319
283
  REG_X30 = 2
@@ -575,15 +539,12 @@ module Crabstone
575
539
  REG_V30 = 258
576
540
  REG_V31 = 259
577
541
  REG_ENDING = 260
578
-
579
- # alias registers
580
- REG_IP1 = REG_X16
581
- REG_IP0 = REG_X17
542
+
543
+ REG_IP0 = REG_X16
544
+ REG_IP1 = REG_X17
582
545
  REG_FP = REG_X29
583
546
  REG_LR = REG_X30
584
-
585
- # ARM64 instruction
586
-
547
+
587
548
  INS_INVALID = 0
588
549
  INS_ABS = 1
589
550
  INS_ADC = 2
@@ -1037,19 +998,17 @@ module Crabstone
1037
998
  INS_AT = 450
1038
999
  INS_TLBI = 451
1039
1000
  INS_ENDING = 452
1040
-
1041
- # Group of ARM64 instructions
1042
-
1001
+
1043
1002
  GRP_INVALID = 0
1044
-
1045
- # Generic groups
1003
+
1046
1004
  GRP_JUMP = 1
1047
-
1048
- # Architecture-specific groups
1005
+
1049
1006
  GRP_CRYPTO = 128
1050
1007
  GRP_FPARMV8 = 129
1051
1008
  GRP_NEON = 130
1052
1009
  GRP_CRC = 131
1053
1010
  GRP_ENDING = 132
1011
+
1012
+ extend Register
1054
1013
  end
1055
1014
  end
@@ -1,17 +1,11 @@
1
- # Library by Nguyen Anh Quynh
2
- # Original binding by Nguyen Anh Quynh and Tan Sheng Di
3
- # Additional binding work by Ben Nagy
4
- # (c) 2013 COSEINC. All Rights Reserved.
1
+ # frozen_string_literal: true
5
2
 
6
3
  # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
7
- # Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/
8
- # 2015-05-02T13:24:01+12:00
4
+
5
+ require 'crabstone/arch/register'
9
6
 
10
7
  module Crabstone
11
8
  module ARM
12
-
13
- # ARM shift type
14
-
15
9
  SFT_INVALID = 0
16
10
  SFT_ASR = 1
17
11
  SFT_LSL = 2
@@ -23,9 +17,7 @@ module Crabstone
23
17
  SFT_LSR_REG = 8
24
18
  SFT_ROR_REG = 9
25
19
  SFT_RRX_REG = 10
26
-
27
- # ARM condition code
28
-
20
+
29
21
  CC_INVALID = 0
30
22
  CC_EQ = 1
31
23
  CC_NE = 2
@@ -42,9 +34,7 @@ module Crabstone
42
34
  CC_GT = 13
43
35
  CC_LE = 14
44
36
  CC_AL = 15
45
-
46
- # Special registers for MSR
47
-
37
+
48
38
  SYSREG_INVALID = 0
49
39
  SYSREG_SPSR_C = 1
50
40
  SYSREG_SPSR_X = 2
@@ -77,10 +67,7 @@ module Crabstone
77
67
  SYSREG_BASEPRI_MAX = 276
78
68
  SYSREG_FAULTMASK = 277
79
69
  SYSREG_CONTROL = 278
80
-
81
- # The memory barrier constants map directly to the 4-bit encoding of
82
- # the option field for Memory Barrier operations.
83
-
70
+
84
71
  MB_INVALID = 0
85
72
  MB_RESERVED_0 = 1
86
73
  MB_OSHLD = 2
@@ -98,9 +85,7 @@ module Crabstone
98
85
  MB_LD = 14
99
86
  MB_ST = 15
100
87
  MB_SY = 16
101
-
102
- # Operand type for instruction's operands
103
-
88
+
104
89
  OP_INVALID = 0
105
90
  OP_REG = 1
106
91
  OP_IMM = 2
@@ -110,27 +95,21 @@ module Crabstone
110
95
  OP_PIMM = 65
111
96
  OP_SETEND = 66
112
97
  OP_SYSREG = 67
113
-
114
- # Operand type for SETEND instruction
115
-
98
+
116
99
  SETEND_INVALID = 0
117
100
  SETEND_BE = 1
118
101
  SETEND_LE = 2
119
-
102
+
120
103
  CPSMODE_INVALID = 0
121
104
  CPSMODE_IE = 2
122
105
  CPSMODE_ID = 3
123
-
124
- # Operand type for SETEND instruction
125
-
106
+
126
107
  CPSFLAG_INVALID = 0
127
108
  CPSFLAG_F = 1
128
109
  CPSFLAG_I = 2
129
110
  CPSFLAG_A = 4
130
111
  CPSFLAG_NONE = 16
131
-
132
- # Data type for elements of vector instructions.
133
-
112
+
134
113
  VECTORDATA_INVALID = 0
135
114
  VECTORDATA_I8 = 1
136
115
  VECTORDATA_I16 = 2
@@ -169,9 +148,7 @@ module Crabstone
169
148
  VECTORDATA_F64U16 = 35
170
149
  VECTORDATA_F32U16 = 36
171
150
  VECTORDATA_F64U32 = 37
172
-
173
- # ARM registers
174
-
151
+
175
152
  REG_INVALID = 0
176
153
  REG_APSR = 1
177
154
  REG_APSR_NZCV = 2
@@ -284,8 +261,7 @@ module Crabstone
284
261
  REG_S30 = 109
285
262
  REG_S31 = 110
286
263
  REG_ENDING = 111
287
-
288
- # alias registers
264
+
289
265
  REG_R13 = REG_SP
290
266
  REG_R14 = REG_LR
291
267
  REG_R15 = REG_PC
@@ -293,9 +269,7 @@ module Crabstone
293
269
  REG_SL = REG_R10
294
270
  REG_FP = REG_R11
295
271
  REG_IP = REG_R12
296
-
297
- # ARM instruction
298
-
272
+
299
273
  INS_INVALID = 0
300
274
  INS_ADC = 1
301
275
  INS_ADD = 2
@@ -732,15 +706,11 @@ module Crabstone
732
706
  INS_VPUSH = 433
733
707
  INS_VPOP = 434
734
708
  INS_ENDING = 435
735
-
736
- # Group of ARM instructions
737
-
709
+
738
710
  GRP_INVALID = 0
739
-
740
- # Generic groups
711
+
741
712
  GRP_JUMP = 1
742
-
743
- # Architecture-specific groups
713
+
744
714
  GRP_CRYPTO = 128
745
715
  GRP_DATABARRIER = 129
746
716
  GRP_DIVIDE = 130
@@ -773,5 +743,7 @@ module Crabstone
773
743
  GRP_DPVFP = 157
774
744
  GRP_V6M = 158
775
745
  GRP_ENDING = 159
746
+
747
+ extend Register
776
748
  end
777
749
  end
@@ -0,0 +1,57 @@
1
+ # frozen_string_literal: true
2
+
3
+ # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
4
+
5
+ require 'ffi'
6
+
7
+ require 'crabstone/arch/extension'
8
+ require_relative 'mips_const'
9
+
10
+ module Crabstone
11
+ module MIPS
12
+ class OperandMemory < FFI::Struct
13
+ layout(
14
+ :base, :uint,
15
+ :disp, :long
16
+ )
17
+ end
18
+
19
+ class OperandValue < FFI::Union
20
+ layout(
21
+ :reg, :uint,
22
+ :imm, :long,
23
+ :mem, OperandMemory
24
+ )
25
+ end
26
+
27
+ class Operand < FFI::Struct
28
+ layout(
29
+ :type, :uint,
30
+ :value, OperandValue
31
+ )
32
+
33
+ include Crabstone::Extension::Operand
34
+
35
+ def reg?
36
+ self[:type] == OP_REG
37
+ end
38
+
39
+ def imm?
40
+ self[:type] == OP_IMM
41
+ end
42
+
43
+ def mem?
44
+ self[:type] == OP_MEM
45
+ end
46
+ end
47
+
48
+ class Instruction < FFI::Struct
49
+ layout(
50
+ :op_count, :uint8,
51
+ :operands, [Operand, 8]
52
+ )
53
+
54
+ include Crabstone::Extension::Instruction
55
+ end
56
+ end
57
+ end
@@ -1,27 +1,18 @@
1
- # Library by Nguyen Anh Quynh
2
- # Original binding by Nguyen Anh Quynh and Tan Sheng Di
3
- # Additional binding work by Ben Nagy
4
- # (c) 2013 COSEINC. All Rights Reserved.
1
+ # frozen_string_literal: true
5
2
 
6
3
  # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
7
- # Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/
8
- # 2015-05-02T13:24:01+12:00
4
+
5
+ require 'crabstone/arch/register'
9
6
 
10
7
  module Crabstone
11
8
  module MIPS
12
-
13
- # Operand type for instruction's operands
14
-
15
9
  OP_INVALID = 0
16
10
  OP_REG = 1
17
11
  OP_IMM = 2
18
12
  OP_MEM = 3
19
-
20
- # MIPS registers
21
-
13
+
22
14
  REG_INVALID = 0
23
-
24
- # General purpose registers
15
+
25
16
  REG_0 = 1
26
17
  REG_1 = 2
27
18
  REG_2 = 3
@@ -54,8 +45,7 @@ module Crabstone
54
45
  REG_29 = 30
55
46
  REG_30 = 31
56
47
  REG_31 = 32
57
-
58
- # DSP registers
48
+
59
49
  REG_DSPCCOND = 33
60
50
  REG_DSPCARRY = 34
61
51
  REG_DSPEFI = 35
@@ -67,14 +57,12 @@ module Crabstone
67
57
  REG_DSPOUTFLAG23 = 41
68
58
  REG_DSPPOS = 42
69
59
  REG_DSPSCOUNT = 43
70
-
71
- # ACC registers
60
+
72
61
  REG_AC0 = 44
73
62
  REG_AC1 = 45
74
63
  REG_AC2 = 46
75
64
  REG_AC3 = 47
76
-
77
- # COP registers
65
+
78
66
  REG_CC0 = 48
79
67
  REG_CC1 = 49
80
68
  REG_CC2 = 50
@@ -83,8 +71,7 @@ module Crabstone
83
71
  REG_CC5 = 53
84
72
  REG_CC6 = 54
85
73
  REG_CC7 = 55
86
-
87
- # FPU registers
74
+
88
75
  REG_F0 = 56
89
76
  REG_F1 = 57
90
77
  REG_F2 = 58
@@ -125,8 +112,7 @@ module Crabstone
125
112
  REG_FCC5 = 93
126
113
  REG_FCC6 = 94
127
114
  REG_FCC7 = 95
128
-
129
- # AFPR128
115
+
130
116
  REG_W0 = 96
131
117
  REG_W1 = 97
132
118
  REG_W2 = 98
@@ -209,9 +195,7 @@ module Crabstone
209
195
  REG_LO1 = REG_HI1
210
196
  REG_LO2 = REG_HI2
211
197
  REG_LO3 = REG_HI3
212
-
213
- # MIPS instruction
214
-
198
+
215
199
  INS_INVALID = 0
216
200
  INS_ABSQ_S = 1
217
201
  INS_ADD = 2
@@ -794,24 +778,18 @@ module Crabstone
794
778
  INS_WSBH = 579
795
779
  INS_XOR = 580
796
780
  INS_XORI = 581
797
-
798
- # some alias instructions
781
+
799
782
  INS_NOP = 582
800
783
  INS_NEGU = 583
801
-
802
- # special instructions
784
+
803
785
  INS_JALR_HB = 584
804
786
  INS_JR_HB = 585
805
787
  INS_ENDING = 586
806
-
807
- # Group of MIPS instructions
808
-
788
+
809
789
  GRP_INVALID = 0
810
-
811
- # Generic groups
790
+
812
791
  GRP_JUMP = 1
813
-
814
- # Architecture-specific groups
792
+
815
793
  GRP_BITCOUNT = 128
816
794
  GRP_DSP = 129
817
795
  GRP_DSPR2 = 130
@@ -846,5 +824,7 @@ module Crabstone
846
824
  GRP_GP32BIT = 159
847
825
  GRP_GP64BIT = 160
848
826
  GRP_ENDING = 161
827
+
828
+ extend Register
849
829
  end
850
830
  end
@@ -0,0 +1,73 @@
1
+ # frozen_string_literal: true
2
+
3
+ # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
4
+
5
+ require 'ffi'
6
+
7
+ require 'crabstone/arch/extension'
8
+ require_relative 'ppc_const'
9
+
10
+ module Crabstone
11
+ module PPC
12
+ class OperandMemory < FFI::Struct
13
+ layout(
14
+ :base, :uint,
15
+ :disp, :int
16
+ )
17
+ end
18
+
19
+ class OperandCrx < FFI::Struct
20
+ layout(
21
+ :scale, :uint,
22
+ :reg, :uint,
23
+ :cond, :uint
24
+ )
25
+ end
26
+
27
+ class OperandValue < FFI::Union
28
+ layout(
29
+ :reg, :uint,
30
+ :imm, :int,
31
+ :mem, OperandMemory,
32
+ :crx, OperandCrx
33
+ )
34
+ end
35
+
36
+ class Operand < FFI::Struct
37
+ layout(
38
+ :type, :uint,
39
+ :value, OperandValue
40
+ )
41
+
42
+ include Crabstone::Extension::Operand
43
+
44
+ def reg?
45
+ self[:type] == OP_REG
46
+ end
47
+
48
+ def imm?
49
+ self[:type] == OP_IMM
50
+ end
51
+
52
+ def mem?
53
+ self[:type] == OP_MEM
54
+ end
55
+
56
+ def crx?
57
+ self[:type] == OP_CRX
58
+ end
59
+ end
60
+
61
+ class Instruction < FFI::Struct
62
+ layout(
63
+ :bc, :uint,
64
+ :bh, :uint,
65
+ :update_cr0, :bool,
66
+ :op_count, :uint8,
67
+ :operands, [Operand, 8]
68
+ )
69
+
70
+ include Crabstone::Extension::Instruction
71
+ end
72
+ end
73
+ end