crabstone 3.0.3 → 4.0.4

data/lib/{arch → crabstone/arch/3}/arm64_const.rb

@@ -1,26 +1,18 @@
-# Library by Nguyen Anh Quynh
-# Original binding by Nguyen Anh Quynh and Tan Sheng Di
-# Additional binding work by Ben Nagy
-# (c) 2013 COSEINC. All Rights Reserved.
+# frozen_string_literal: true
 
 # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
-# Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/
-# 2015-05-02T13:24:01+12:00
+
+require 'crabstone/arch/register'
 
 module Crabstone
   module ARM64
-
-    # ARM64 shift type
-    
     SFT_INVALID = 0
     SFT_LSL = 1
     SFT_MSL = 2
     SFT_LSR = 3
     SFT_ASR = 4
     SFT_ROR = 5
-    
-    # ARM64 extender type
-    
+
     EXT_INVALID = 0
     EXT_UXTB = 1
     EXT_UXTH = 2
@@ -30,9 +22,7 @@ module Crabstone
     EXT_SXTH = 6
     EXT_SXTW = 7
     EXT_SXTX = 8
-    
-    # ARM64 condition code
-    
+
     CC_INVALID = 0
     CC_EQ = 1
     CC_NE = 2
@@ -50,11 +40,7 @@ module Crabstone
     CC_LE = 14
     CC_AL = 15
     CC_NV = 16
-    
-    # System registers
-    
-    # System registers for MRS
-    
+
     SYSREG_INVALID = 0
     SYSREG_MDCCSR_EL0 = 0x9808
     SYSREG_DBGDTRRX_EL0 = 0x9828
@@ -148,8 +134,7 @@ module Crabstone
     SYSREG_ICH_VTR_EL2 = 0xe659
     SYSREG_ICH_EISR_EL2 = 0xe65b
     SYSREG_ICH_ELSR_EL2 = 0xe65d
-    
-    # System registers for MSR
+
     SYSREG_DBGDTRTX_EL0 = 0x9828
     SYSREG_OSLAR_EL1 = 0x8084
     SYSREG_PMSWINC_EL0 = 0xdce4
@@ -161,16 +146,12 @@ module Crabstone
     SYSREG_ICC_SGI1R_EL1 = 0xc65d
     SYSREG_ICC_ASGI1R_EL1 = 0xc65e
     SYSREG_ICC_SGI0R_EL1 = 0xc65f
-    
-    # System PState Field (MSR instruction)
-    
+
     PSTATE_INVALID = 0
     PSTATE_SPSEL = 0x05
     PSTATE_DAIFSET = 0x1e
     PSTATE_DAIFCLR = 0x1f
-    
-    # Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)
-    
+
     VAS_INVALID = 0
     VAS_8B = 1
     VAS_16B = 2
@@ -181,17 +162,13 @@ module Crabstone
     VAS_1D = 7
     VAS_2D = 8
     VAS_1Q = 9
-    
-    # Vector element size specifier
-    
+
     VESS_INVALID = 0
     VESS_B = 1
     VESS_H = 2
     VESS_S = 3
     VESS_D = 4
-    
-    # Memory barrier operands
-    
+
     BARRIER_INVALID = 0
     BARRIER_OSHLD = 0x1
     BARRIER_OSHST = 0x2
@@ -205,9 +182,7 @@ module Crabstone
     BARRIER_LD = 0xd
     BARRIER_ST = 0xe
     BARRIER_SY = 0xf
-    
-    # Operand type for instruction's operands
-    
+
     OP_INVALID = 0
     OP_REG = 1
     OP_IMM = 2
@@ -220,9 +195,7 @@ module Crabstone
     OP_SYS = 68
     OP_PREFETCH = 69
     OP_BARRIER = 70
-    
-    # TLBI operations
-    
+
     TLBI_INVALID = 0
     TLBI_VMALLE1IS = 1
     TLBI_VAE1IS = 2
@@ -256,8 +229,7 @@ module Crabstone
     TLBI_ALLE3 = 30
     TLBI_VAE3 = 31
     TLBI_VALE3 = 32
-    
-    # AT operations
+
     AT_S1E1R = 33
     AT_S1E1W = 34
     AT_S1E0R = 35
@@ -270,9 +242,7 @@ module Crabstone
     AT_S12E0W = 42
     AT_S1E3R = 43
     AT_S1E3W = 44
-    
-    # DC operations
-    
+
     DC_INVALID = 0
     DC_ZVA = 1
     DC_IVAC = 2
@@ -282,38 +252,32 @@ module Crabstone
     DC_CVAU = 6
     DC_CIVAC = 7
     DC_CISW = 8
-    
-    # IC operations
-    
+
     IC_INVALID = 0
     IC_IALLUIS = 1
     IC_IALLU = 2
     IC_IVAU = 3
-    
-    # Prefetch operations (PRFM)
-    
+
     PRFM_INVALID = 0
-    PRFM_PLDL1KEEP = 0x00+1
-    PRFM_PLDL1STRM = 0x01+1
-    PRFM_PLDL2KEEP = 0x02+1
-    PRFM_PLDL2STRM = 0x03+1
-    PRFM_PLDL3KEEP = 0x04+1
-    PRFM_PLDL3STRM = 0x05+1
-    PRFM_PLIL1KEEP = 0x08+1
-    PRFM_PLIL1STRM = 0x09+1
-    PRFM_PLIL2KEEP = 0x0a+1
-    PRFM_PLIL2STRM = 0x0b+1
-    PRFM_PLIL3KEEP = 0x0c+1
-    PRFM_PLIL3STRM = 0x0d+1
-    PRFM_PSTL1KEEP = 0x10+1
-    PRFM_PSTL1STRM = 0x11+1
-    PRFM_PSTL2KEEP = 0x12+1
-    PRFM_PSTL2STRM = 0x13+1
-    PRFM_PSTL3KEEP = 0x14+1
-    PRFM_PSTL3STRM = 0x15+1
-    
-    # ARM64 registers
-    
+    PRFM_PLDL1KEEP = 0x00 + 1
+    PRFM_PLDL1STRM = 0x01 + 1
+    PRFM_PLDL2KEEP = 0x02 + 1
+    PRFM_PLDL2STRM = 0x03 + 1
+    PRFM_PLDL3KEEP = 0x04 + 1
+    PRFM_PLDL3STRM = 0x05 + 1
+    PRFM_PLIL1KEEP = 0x08 + 1
+    PRFM_PLIL1STRM = 0x09 + 1
+    PRFM_PLIL2KEEP = 0x0a + 1
+    PRFM_PLIL2STRM = 0x0b + 1
+    PRFM_PLIL3KEEP = 0x0c + 1
+    PRFM_PLIL3STRM = 0x0d + 1
+    PRFM_PSTL1KEEP = 0x10 + 1
+    PRFM_PSTL1STRM = 0x11 + 1
+    PRFM_PSTL2KEEP = 0x12 + 1
+    PRFM_PSTL2STRM = 0x13 + 1
+    PRFM_PSTL3KEEP = 0x14 + 1
+    PRFM_PSTL3STRM = 0x15 + 1
+
     REG_INVALID = 0
     REG_X29 = 1
     REG_X30 = 2
@@ -575,15 +539,12 @@ module Crabstone
     REG_V30 = 258
     REG_V31 = 259
     REG_ENDING = 260
-    
-    # alias registers
-    REG_IP1 = REG_X16
-    REG_IP0 = REG_X17
+
+    REG_IP0 = REG_X16
+    REG_IP1 = REG_X17
     REG_FP = REG_X29
     REG_LR = REG_X30
-    
-    # ARM64 instruction
-    
+
     INS_INVALID = 0
     INS_ABS = 1
     INS_ADC = 2
@@ -1037,19 +998,17 @@ module Crabstone
     INS_AT = 450
     INS_TLBI = 451
     INS_ENDING = 452
-    
-    # Group of ARM64 instructions
-    
+
     GRP_INVALID = 0
-    
-    # Generic groups
+
     GRP_JUMP = 1
-    
-    # Architecture-specific groups
+
     GRP_CRYPTO = 128
     GRP_FPARMV8 = 129
     GRP_NEON = 130
     GRP_CRC = 131
     GRP_ENDING = 132
+
+    extend Register
   end
 end

data/lib/{arch → crabstone/arch/3}/arm_const.rb

@@ -1,17 +1,11 @@
-# Library by Nguyen Anh Quynh
-# Original binding by Nguyen Anh Quynh and Tan Sheng Di
-# Additional binding work by Ben Nagy
-# (c) 2013 COSEINC. All Rights Reserved.
+# frozen_string_literal: true
 
 # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
-# Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/
-# 2015-05-02T13:24:01+12:00
+
+require 'crabstone/arch/register'
 
 module Crabstone
   module ARM
-
-    # ARM shift type
-    
     SFT_INVALID = 0
     SFT_ASR = 1
     SFT_LSL = 2
@@ -23,9 +17,7 @@ module Crabstone
     SFT_LSR_REG = 8
     SFT_ROR_REG = 9
     SFT_RRX_REG = 10
-    
-    # ARM condition code
-    
+
     CC_INVALID = 0
     CC_EQ = 1
     CC_NE = 2
@@ -42,9 +34,7 @@ module Crabstone
     CC_GT = 13
     CC_LE = 14
     CC_AL = 15
-    
-    # Special registers for MSR
-    
+
     SYSREG_INVALID = 0
     SYSREG_SPSR_C = 1
     SYSREG_SPSR_X = 2
@@ -77,10 +67,7 @@ module Crabstone
     SYSREG_BASEPRI_MAX = 276
     SYSREG_FAULTMASK = 277
     SYSREG_CONTROL = 278
-    
-    # The memory barrier constants map directly to the 4-bit encoding of
-    # the option field for Memory Barrier operations.
-    
+
     MB_INVALID = 0
     MB_RESERVED_0 = 1
     MB_OSHLD = 2
@@ -98,9 +85,7 @@ module Crabstone
     MB_LD = 14
     MB_ST = 15
     MB_SY = 16
-    
-    # Operand type for instruction's operands
-    
+
     OP_INVALID = 0
     OP_REG = 1
     OP_IMM = 2
@@ -110,27 +95,21 @@ module Crabstone
     OP_PIMM = 65
     OP_SETEND = 66
     OP_SYSREG = 67
-    
-    # Operand type for SETEND instruction
-    
+
     SETEND_INVALID = 0
     SETEND_BE = 1
     SETEND_LE = 2
-    
+
     CPSMODE_INVALID = 0
     CPSMODE_IE = 2
     CPSMODE_ID = 3
-    
-    # Operand type for SETEND instruction
-    
+
     CPSFLAG_INVALID = 0
     CPSFLAG_F = 1
     CPSFLAG_I = 2
     CPSFLAG_A = 4
     CPSFLAG_NONE = 16
-    
-    # Data type for elements of vector instructions.
-    
+
     VECTORDATA_INVALID = 0
     VECTORDATA_I8 = 1
     VECTORDATA_I16 = 2
@@ -169,9 +148,7 @@ module Crabstone
     VECTORDATA_F64U16 = 35
     VECTORDATA_F32U16 = 36
     VECTORDATA_F64U32 = 37
-    
-    # ARM registers
-    
+
     REG_INVALID = 0
     REG_APSR = 1
     REG_APSR_NZCV = 2
@@ -284,8 +261,7 @@ module Crabstone
     REG_S30 = 109
     REG_S31 = 110
     REG_ENDING = 111
-    
-    # alias registers
+
     REG_R13 = REG_SP
     REG_R14 = REG_LR
     REG_R15 = REG_PC
@@ -293,9 +269,7 @@ module Crabstone
     REG_SL = REG_R10
     REG_FP = REG_R11
     REG_IP = REG_R12
-    
-    # ARM instruction
-    
+
     INS_INVALID = 0
     INS_ADC = 1
     INS_ADD = 2
@@ -732,15 +706,11 @@ module Crabstone
     INS_VPUSH = 433
     INS_VPOP = 434
     INS_ENDING = 435
-    
-    # Group of ARM instructions
-    
+
     GRP_INVALID = 0
-    
-    # Generic groups
+
     GRP_JUMP = 1
-    
-    # Architecture-specific groups
+
     GRP_CRYPTO = 128
     GRP_DATABARRIER = 129
     GRP_DIVIDE = 130
@@ -773,5 +743,7 @@ module Crabstone
     GRP_DPVFP = 157
     GRP_V6M = 158
     GRP_ENDING = 159
+
+    extend Register
   end
 end

data/lib/crabstone/arch/3/mips.rb

@@ -0,0 +1,57 @@
+# frozen_string_literal: true
+
+# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
+
+require 'ffi'
+
+require 'crabstone/arch/extension'
+require_relative 'mips_const'
+
+module Crabstone
+  module MIPS
+    class OperandMemory < FFI::Struct
+      layout(
+        :base, :uint,
+        :disp, :long
+      )
+    end
+
+    class OperandValue < FFI::Union
+      layout(
+        :reg, :uint,
+        :imm, :long,
+        :mem, OperandMemory
+      )
+    end
+
+    class Operand < FFI::Struct
+      layout(
+        :type, :uint,
+        :value, OperandValue
+      )
+
+      include Crabstone::Extension::Operand
+
+      def reg?
+        self[:type] == OP_REG
+      end
+
+      def imm?
+        self[:type] == OP_IMM
+      end
+
+      def mem?
+        self[:type] == OP_MEM
+      end
+    end
+
+    class Instruction < FFI::Struct
+      layout(
+        :op_count, :uint8,
+        :operands, [Operand, 8]
+      )
+
+      include Crabstone::Extension::Instruction
+    end
+  end
+end

data/lib/{arch → crabstone/arch/3}/mips_const.rb

@@ -1,27 +1,18 @@
-# Library by Nguyen Anh Quynh
-# Original binding by Nguyen Anh Quynh and Tan Sheng Di
-# Additional binding work by Ben Nagy
-# (c) 2013 COSEINC. All Rights Reserved.
+# frozen_string_literal: true
 
 # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
-# Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/
-# 2015-05-02T13:24:01+12:00
+
+require 'crabstone/arch/register'
 
 module Crabstone
   module MIPS
-
-    # Operand type for instruction's operands
-    
     OP_INVALID = 0
     OP_REG = 1
     OP_IMM = 2
     OP_MEM = 3
-    
-    # MIPS registers
-    
+
     REG_INVALID = 0
-    
-    # General purpose registers
+
     REG_0 = 1
     REG_1 = 2
     REG_2 = 3
@@ -54,8 +45,7 @@ module Crabstone
     REG_29 = 30
     REG_30 = 31
     REG_31 = 32
-    
-    # DSP registers
+
     REG_DSPCCOND = 33
     REG_DSPCARRY = 34
     REG_DSPEFI = 35
@@ -67,14 +57,12 @@ module Crabstone
     REG_DSPOUTFLAG23 = 41
     REG_DSPPOS = 42
     REG_DSPSCOUNT = 43
-    
-    # ACC registers
+
     REG_AC0 = 44
     REG_AC1 = 45
     REG_AC2 = 46
     REG_AC3 = 47
-    
-    # COP registers
+
     REG_CC0 = 48
     REG_CC1 = 49
     REG_CC2 = 50
@@ -83,8 +71,7 @@ module Crabstone
     REG_CC5 = 53
     REG_CC6 = 54
     REG_CC7 = 55
-    
-    # FPU registers
+
     REG_F0 = 56
     REG_F1 = 57
     REG_F2 = 58
@@ -125,8 +112,7 @@ module Crabstone
     REG_FCC5 = 93
     REG_FCC6 = 94
     REG_FCC7 = 95
-    
-    # AFPR128
+
     REG_W0 = 96
     REG_W1 = 97
     REG_W2 = 98
@@ -209,9 +195,7 @@ module Crabstone
     REG_LO1 = REG_HI1
     REG_LO2 = REG_HI2
     REG_LO3 = REG_HI3
-    
-    # MIPS instruction
-    
+
     INS_INVALID = 0
     INS_ABSQ_S = 1
     INS_ADD = 2
@@ -794,24 +778,18 @@ module Crabstone
     INS_WSBH = 579
     INS_XOR = 580
     INS_XORI = 581
-    
-    # some alias instructions
+
     INS_NOP = 582
     INS_NEGU = 583
-    
-    # special instructions
+
     INS_JALR_HB = 584
     INS_JR_HB = 585
     INS_ENDING = 586
-    
-    # Group of MIPS instructions
-    
+
     GRP_INVALID = 0
-    
-    # Generic groups
+
     GRP_JUMP = 1
-    
-    # Architecture-specific groups
+
     GRP_BITCOUNT = 128
     GRP_DSP = 129
     GRP_DSPR2 = 130
@@ -846,5 +824,7 @@ module Crabstone
     GRP_GP32BIT = 159
     GRP_GP64BIT = 160
     GRP_ENDING = 161
+
+    extend Register
   end
 end

data/lib/crabstone/arch/3/ppc.rb

@@ -0,0 +1,73 @@
+# frozen_string_literal: true
+
+# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
+
+require 'ffi'
+
+require 'crabstone/arch/extension'
+require_relative 'ppc_const'
+
+module Crabstone
+  module PPC
+    class OperandMemory < FFI::Struct
+      layout(
+        :base, :uint,
+        :disp, :int
+      )
+    end
+
+    class OperandCrx < FFI::Struct
+      layout(
+        :scale, :uint,
+        :reg, :uint,
+        :cond, :uint
+      )
+    end
+
+    class OperandValue < FFI::Union
+      layout(
+        :reg, :uint,
+        :imm, :int,
+        :mem, OperandMemory,
+        :crx, OperandCrx
+      )
+    end
+
+    class Operand < FFI::Struct
+      layout(
+        :type, :uint,
+        :value, OperandValue
+      )
+
+      include Crabstone::Extension::Operand
+
+      def reg?
+        self[:type] == OP_REG
+      end
+
+      def imm?
+        self[:type] == OP_IMM
+      end
+
+      def mem?
+        self[:type] == OP_MEM
+      end
+
+      def crx?
+        self[:type] == OP_CRX
+      end
+    end
+
+    class Instruction < FFI::Struct
+      layout(
+        :bc, :uint,
+        :bh, :uint,
+        :update_cr0, :bool,
+        :op_count, :uint8,
+        :operands, [Operand, 8]
+      )
+
+      include Crabstone::Extension::Instruction
+    end
+  end
+end