crabstone 3.0.3 → 4.0.4

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (347) hide show
  1. checksums.yaml +5 -5
  2. data/CHANGES.md +59 -42
  3. data/README.md +37 -39
  4. data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
  5. data/lib/crabstone/arch/3/arm64.rb +124 -0
  6. data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
  7. data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
  8. data/lib/crabstone/arch/3/mips.rb +57 -0
  9. data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
  10. data/lib/crabstone/arch/3/ppc.rb +73 -0
  11. data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
  12. data/lib/crabstone/arch/3/sparc.rb +60 -0
  13. data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
  14. data/lib/crabstone/arch/3/sysz.rb +67 -0
  15. data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
  16. data/lib/crabstone/arch/3/x86.rb +82 -0
  17. data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
  18. data/lib/crabstone/arch/3/xcore.rb +59 -0
  19. data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
  20. data/lib/crabstone/arch/4/arm.rb +110 -0
  21. data/lib/crabstone/arch/4/arm64.rb +125 -0
  22. data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
  23. data/lib/crabstone/arch/4/arm_const.rb +785 -0
  24. data/lib/crabstone/arch/4/evm.rb +20 -0
  25. data/lib/crabstone/arch/4/evm_const.rb +161 -0
  26. data/lib/crabstone/arch/4/m680x.rb +106 -0
  27. data/lib/crabstone/arch/4/m680x_const.rb +426 -0
  28. data/lib/crabstone/arch/4/m68k.rb +129 -0
  29. data/lib/crabstone/arch/4/m68k_const.rb +496 -0
  30. data/lib/crabstone/arch/4/mips.rb +57 -0
  31. data/lib/crabstone/arch/4/mips_const.rb +869 -0
  32. data/lib/crabstone/arch/4/ppc.rb +73 -0
  33. data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
  34. data/lib/crabstone/arch/4/sparc.rb +60 -0
  35. data/lib/crabstone/arch/4/sparc_const.rb +439 -0
  36. data/lib/crabstone/arch/4/sysz.rb +67 -0
  37. data/lib/crabstone/arch/4/sysz_const.rb +763 -0
  38. data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
  39. data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
  40. data/lib/crabstone/arch/4/x86.rb +91 -0
  41. data/lib/crabstone/arch/4/x86_const.rb +1972 -0
  42. data/lib/crabstone/arch/4/xcore.rb +59 -0
  43. data/lib/crabstone/arch/4/xcore_const.rb +171 -0
  44. data/lib/crabstone/arch/extension.rb +27 -0
  45. data/lib/crabstone/arch/register.rb +34 -0
  46. data/lib/crabstone/arch.rb +37 -0
  47. data/lib/crabstone/binding/3/detail.rb +36 -0
  48. data/lib/crabstone/binding/3/instruction.rb +23 -0
  49. data/lib/crabstone/binding/4/detail.rb +40 -0
  50. data/lib/crabstone/binding/4/instruction.rb +23 -0
  51. data/lib/crabstone/binding/structs.rb +32 -0
  52. data/lib/crabstone/binding.rb +59 -0
  53. data/lib/crabstone/constants.rb +110 -0
  54. data/lib/crabstone/cs_version.rb +57 -0
  55. data/lib/crabstone/disassembler.rb +147 -0
  56. data/lib/crabstone/error.rb +74 -0
  57. data/lib/crabstone/instruction.rb +178 -0
  58. data/lib/crabstone/version.rb +5 -0
  59. data/lib/crabstone.rb +5 -557
  60. metadata +142 -331
  61. data/MANIFEST +0 -312
  62. data/Rakefile +0 -27
  63. data/bin/genconst +0 -66
  64. data/bin/genreg +0 -99
  65. data/crabstone.gemspec +0 -27
  66. data/examples/hello_world.rb +0 -43
  67. data/lib/arch/arm64.rb +0 -167
  68. data/lib/arch/arm64_registers.rb +0 -295
  69. data/lib/arch/arm_registers.rb +0 -149
  70. data/lib/arch/mips.rb +0 -78
  71. data/lib/arch/mips_registers.rb +0 -208
  72. data/lib/arch/ppc.rb +0 -90
  73. data/lib/arch/ppc_registers.rb +0 -209
  74. data/lib/arch/sparc.rb +0 -79
  75. data/lib/arch/sparc_registers.rb +0 -121
  76. data/lib/arch/systemz.rb +0 -79
  77. data/lib/arch/sysz_registers.rb +0 -66
  78. data/lib/arch/x86.rb +0 -107
  79. data/lib/arch/x86_registers.rb +0 -265
  80. data/lib/arch/xcore.rb +0 -78
  81. data/lib/arch/xcore_registers.rb +0 -57
  82. data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
  83. data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
  84. data/test/MC/AArch64/neon-2velem.s.cs +0 -113
  85. data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
  86. data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
  87. data/test/MC/AArch64/neon-across.s.cs +0 -40
  88. data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
  89. data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
  90. data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
  91. data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
  92. data/test/MC/AArch64/neon-crypto.s.cs +0 -15
  93. data/test/MC/AArch64/neon-extract.s.cs +0 -3
  94. data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
  95. data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
  96. data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
  97. data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
  98. data/test/MC/AArch64/neon-max-min.s.cs +0 -37
  99. data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
  100. data/test/MC/AArch64/neon-mov.s.cs +0 -74
  101. data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
  102. data/test/MC/AArch64/neon-perm.s.cs +0 -43
  103. data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
  104. data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
  105. data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
  106. data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
  107. data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
  108. data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
  109. data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
  110. data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
  111. data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
  112. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
  113. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
  114. data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
  115. data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
  116. data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
  117. data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
  118. data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
  119. data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
  120. data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
  121. data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
  122. data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
  123. data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
  124. data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
  125. data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
  126. data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
  127. data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
  128. data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
  129. data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
  130. data/test/MC/AArch64/neon-shift.s.cs +0 -22
  131. data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
  132. data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
  133. data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
  134. data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
  135. data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
  136. data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
  137. data/test/MC/AArch64/neon-tbl.s.cs +0 -21
  138. data/test/MC/AArch64/trace-regs.s.cs +0 -383
  139. data/test/MC/ARM/arm-aliases.s.cs +0 -7
  140. data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
  141. data/test/MC/ARM/arm-it-block.s.cs +0 -2
  142. data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
  143. data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
  144. data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
  145. data/test/MC/ARM/arm-trustzone.s.cs +0 -3
  146. data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
  147. data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
  148. data/test/MC/ARM/arm_instructions.s.cs +0 -25
  149. data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
  150. data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
  151. data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
  152. data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
  153. data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
  154. data/test/MC/ARM/crc32-thumb.s.cs +0 -7
  155. data/test/MC/ARM/crc32.s.cs +0 -7
  156. data/test/MC/ARM/dot-req.s.cs +0 -3
  157. data/test/MC/ARM/fp-armv8.s.cs +0 -52
  158. data/test/MC/ARM/idiv-thumb.s.cs +0 -3
  159. data/test/MC/ARM/idiv.s.cs +0 -3
  160. data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
  161. data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
  162. data/test/MC/ARM/mode-switch.s.cs +0 -7
  163. data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
  164. data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
  165. data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
  166. data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
  167. data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
  168. data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
  169. data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
  170. data/test/MC/ARM/neon-crypto.s.cs +0 -16
  171. data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
  172. data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
  173. data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
  174. data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
  175. data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
  176. data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
  177. data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
  178. data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
  179. data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
  180. data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
  181. data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
  182. data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
  183. data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
  184. data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
  185. data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
  186. data/test/MC/ARM/neon-v8.s.cs +0 -38
  187. data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
  188. data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
  189. data/test/MC/ARM/neon-vswp.s.cs +0 -3
  190. data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
  191. data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
  192. data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
  193. data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
  194. data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
  195. data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
  196. data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
  197. data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
  198. data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
  199. data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
  200. data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
  201. data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
  202. data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
  203. data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
  204. data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
  205. data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
  206. data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
  207. data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
  208. data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
  209. data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
  210. data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
  211. data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
  212. data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
  213. data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
  214. data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
  215. data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
  216. data/test/MC/ARM/thumb-hints.s.cs +0 -12
  217. data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
  218. data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
  219. data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
  220. data/test/MC/ARM/thumb.s.cs +0 -19
  221. data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
  222. data/test/MC/ARM/thumb2-branches.s.cs +0 -85
  223. data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
  224. data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
  225. data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
  226. data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
  227. data/test/MC/ARM/vfp4.s.cs +0 -13
  228. data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
  229. data/test/MC/ARM/vpush-vpop.s.cs +0 -9
  230. data/test/MC/Mips/hilo-addressing.s.cs +0 -4
  231. data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
  232. data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
  233. data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
  234. data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
  235. data/test/MC/Mips/micromips-expansions.s.cs +0 -20
  236. data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
  237. data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
  238. data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
  239. data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
  240. data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
  241. data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
  242. data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
  243. data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
  244. data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
  245. data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
  246. data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
  247. data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
  248. data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
  249. data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
  250. data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
  251. data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
  252. data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
  253. data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
  254. data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
  255. data/test/MC/Mips/mips-expansions.s.cs +0 -20
  256. data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
  257. data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
  258. data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
  259. data/test/MC/Mips/mips-register-names.s.cs +0 -33
  260. data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
  261. data/test/MC/Mips/mips64-instructions.s.cs +0 -3
  262. data/test/MC/Mips/mips64-register-names.s.cs +0 -33
  263. data/test/MC/Mips/mips_directives.s.cs +0 -12
  264. data/test/MC/Mips/nabi-regs.s.cs +0 -12
  265. data/test/MC/Mips/set-at-directive.s.cs +0 -6
  266. data/test/MC/Mips/test_2r.s.cs +0 -16
  267. data/test/MC/Mips/test_2rf.s.cs +0 -33
  268. data/test/MC/Mips/test_3r.s.cs +0 -243
  269. data/test/MC/Mips/test_3rf.s.cs +0 -83
  270. data/test/MC/Mips/test_bit.s.cs +0 -49
  271. data/test/MC/Mips/test_cbranch.s.cs +0 -11
  272. data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
  273. data/test/MC/Mips/test_elm.s.cs +0 -16
  274. data/test/MC/Mips/test_elm_insert.s.cs +0 -4
  275. data/test/MC/Mips/test_elm_insve.s.cs +0 -5
  276. data/test/MC/Mips/test_i10.s.cs +0 -5
  277. data/test/MC/Mips/test_i5.s.cs +0 -45
  278. data/test/MC/Mips/test_i8.s.cs +0 -11
  279. data/test/MC/Mips/test_lsa.s.cs +0 -5
  280. data/test/MC/Mips/test_mi10.s.cs +0 -24
  281. data/test/MC/Mips/test_vec.s.cs +0 -8
  282. data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
  283. data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
  284. data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
  285. data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
  286. data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
  287. data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
  288. data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
  289. data/test/MC/README +0 -6
  290. data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
  291. data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
  292. data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
  293. data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
  294. data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
  295. data/test/MC/Sparc/sparc-vis.s.cs +0 -2
  296. data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
  297. data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
  298. data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
  299. data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
  300. data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
  301. data/test/MC/SystemZ/insn-good.s.cs +0 -2265
  302. data/test/MC/SystemZ/regs-good.s.cs +0 -45
  303. data/test/MC/X86/3DNow.s.cs +0 -29
  304. data/test/MC/X86/address-size.s.cs +0 -5
  305. data/test/MC/X86/avx512-encodings.s.cs +0 -12
  306. data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
  307. data/test/MC/X86/x86-32-avx.s.cs +0 -833
  308. data/test/MC/X86/x86-32-fma3.s.cs +0 -169
  309. data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
  310. data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
  311. data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
  312. data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
  313. data/test/MC/X86/x86_64-encoding.s.cs +0 -59
  314. data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
  315. data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
  316. data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
  317. data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
  318. data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
  319. data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
  320. data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
  321. data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
  322. data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
  323. data/test/README +0 -6
  324. data/test/test.rb +0 -205
  325. data/test/test.rb.SPEC +0 -235
  326. data/test/test_arm.rb +0 -202
  327. data/test/test_arm.rb.SPEC +0 -275
  328. data/test/test_arm64.rb +0 -150
  329. data/test/test_arm64.rb.SPEC +0 -116
  330. data/test/test_detail.rb +0 -228
  331. data/test/test_detail.rb.SPEC +0 -322
  332. data/test/test_exhaustive.rb +0 -80
  333. data/test/test_mips.rb +0 -118
  334. data/test/test_mips.rb.SPEC +0 -91
  335. data/test/test_ppc.rb +0 -137
  336. data/test/test_ppc.rb.SPEC +0 -84
  337. data/test/test_sanity.rb +0 -83
  338. data/test/test_skipdata.rb +0 -111
  339. data/test/test_skipdata.rb.SPEC +0 -58
  340. data/test/test_sparc.rb +0 -113
  341. data/test/test_sparc.rb.SPEC +0 -116
  342. data/test/test_sysz.rb +0 -111
  343. data/test/test_sysz.rb.SPEC +0 -61
  344. data/test/test_x86.rb +0 -189
  345. data/test/test_x86.rb.SPEC +0 -579
  346. data/test/test_xcore.rb +0 -100
  347. data/test/test_xcore.rb.SPEC +0 -75
data/test/MC/Mips/micromips-shift-instructions.s.cs DELETED
@@ -1,9 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
2
- 0x83,0x00,0x00,0x38 = sll $4, $3, 7
3
- 0x65,0x00,0x10,0x10 = sllv $2, $3, $5
4
- 0x83,0x00,0x80,0x38 = sra $4, $3, 7
5
- 0x65,0x00,0x90,0x10 = srav $2, $3, $5
6
- 0x83,0x00,0x40,0x38 = srl $4, $3, 7
7
- 0x65,0x00,0x50,0x10 = srlv $2, $3, $5
8
- 0x26,0x01,0xc0,0x38 = rotr $9, $6, 7
9
- 0xc7,0x00,0xd0,0x48 = rotrv $9, $6, $7
data/test/MC/Mips/micromips-trap-instructions-EB.s.cs DELETED
@@ -1,13 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
2
- 0x01,0x28,0x00,0x3c = teq $8, $9
3
- 0x01,0x28,0x02,0x3c = tge $8, $9
4
- 0x01,0x28,0x04,0x3c = tgeu $8, $9
5
- 0x01,0x28,0x08,0x3c = tlt $8, $9
6
- 0x01,0x28,0x0a,0x3c = tltu $8, $9
7
- 0x01,0x28,0x0c,0x3c = tne $8, $9
8
- 0x41,0xc9,0x45,0x67 = teqi $9, 17767
9
- 0x41,0x29,0x45,0x67 = tgei $9, 17767
10
- 0x41,0x69,0x45,0x67 = tgeiu $9, 17767
11
- 0x41,0x09,0x45,0x67 = tlti $9, 17767
12
- 0x41,0x49,0x45,0x67 = tltiu $9, 17767
13
- 0x41,0x89,0x45,0x67 = tnei $9, 17767
data/test/MC/Mips/micromips-trap-instructions.s.cs DELETED
@@ -1,13 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
2
- 0x28,0x01,0x3c,0x00 = teq $8, $9
3
- 0x28,0x01,0x3c,0x02 = tge $8, $9
4
- 0x28,0x01,0x3c,0x04 = tgeu $8, $9
5
- 0x28,0x01,0x3c,0x08 = tlt $8, $9
6
- 0x28,0x01,0x3c,0x0a = tltu $8, $9
7
- 0x28,0x01,0x3c,0x0c = tne $8, $9
8
- 0xc9,0x41,0x67,0x45 = teqi $9, 17767
9
- 0x29,0x41,0x67,0x45 = tgei $9, 17767
10
- 0x69,0x41,0x67,0x45 = tgeiu $9, 17767
11
- 0x09,0x41,0x67,0x45 = tlti $9, 17767
12
- 0x49,0x41,0x67,0x45 = tltiu $9, 17767
13
- 0x89,0x41,0x67,0x45 = tnei $9, 17767
data/test/MC/Mips/mips-alu-instructions.s.cs DELETED
@@ -1,53 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32, None
2
- 0x24,0x48,0xc7,0x00 = and $9, $6, $7
3
- 0x67,0x45,0xc9,0x30 = andi $9, $6, 17767
4
- 0x67,0x45,0xc9,0x30 = andi $9, $6, 17767
5
- 0x67,0x45,0x29,0x31 = andi $9, $9, 17767
6
- 0x21,0x30,0xe6,0x70 = clo $6, $7
7
- 0x20,0x30,0xe6,0x70 = clz $6, $7
8
- 0x84,0x61,0x33,0x7d = ins $19, $9, 6, 7
9
- 0x27,0x48,0xc7,0x00 = nor $9, $6, $7
10
- 0x25,0x18,0x65,0x00 = or $3, $3, $5
11
- 0x67,0x45,0xa4,0x34 = ori $4, $5, 17767
12
- 0x67,0x45,0xc9,0x34 = ori $9, $6, 17767
13
- 0x80,0x00,0x6b,0x35 = ori $11, $11, 128
14
- 0xc2,0x49,0x26,0x00 = rotr $9, $6, 7
15
- 0x46,0x48,0xe6,0x00 = rotrv $9, $6, $7
16
- 0xc0,0x21,0x03,0x00 = sll $4, $3, 7
17
- 0x04,0x10,0xa3,0x00 = sllv $2, $3, $5
18
- 0x2a,0x18,0x65,0x00 = slt $3, $3, $5
19
- 0x67,0x00,0x63,0x28 = slti $3, $3, 103
20
- 0x67,0x00,0x63,0x28 = slti $3, $3, 103
21
- 0x67,0x00,0x63,0x2c = sltiu $3, $3, 103
22
- 0x2b,0x18,0x65,0x00 = sltu $3, $3, $5
23
- 0xc3,0x21,0x03,0x00 = sra $4, $3, 7
24
- 0x07,0x10,0xa3,0x00 = srav $2, $3, $5
25
- 0xc2,0x21,0x03,0x00 = srl $4, $3, 7
26
- 0x06,0x10,0xa3,0x00 = srlv $2, $3, $5
27
- 0x26,0x18,0x65,0x00 = xor $3, $3, $5
28
- 0x67,0x45,0xc9,0x38 = xori $9, $6, 17767
29
- 0x67,0x45,0xc9,0x38 = xori $9, $6, 17767
30
- 0x0c,0x00,0x6b,0x39 = xori $11, $11, 12
31
- 0xa0,0x30,0x07,0x7c = wsbh $6, $7
32
- 0x27,0x38,0x00,0x01 = not $7, $8
33
- 0x20,0x48,0xc7,0x00 = add $9, $6, $7
34
- 0x67,0x45,0xc9,0x20 = addi $9, $6, 17767
35
- 0x67,0xc5,0xc9,0x24 = addiu $9, $6, -15001
36
- 0x67,0x45,0xc9,0x20 = addi $9, $6, 17767
37
- 0x67,0x45,0x29,0x21 = addi $9, $9, 17767
38
- 0x67,0xc5,0xc9,0x24 = addiu $9, $6, -15001
39
- 0x28,0x00,0x6b,0x25 = addiu $11, $11, 40
40
- 0x21,0x48,0xc7,0x00 = addu $9, $6, $7
41
- 0x00,0x00,0xc7,0x70 = madd $6, $7
42
- 0x01,0x00,0xc7,0x70 = maddu $6, $7
43
- 0x04,0x00,0xc7,0x70 = msub $6, $7
44
- 0x05,0x00,0xc7,0x70 = msubu $6, $7
45
- 0x18,0x00,0x65,0x00 = mult $3, $5
46
- 0x19,0x00,0x65,0x00 = multu $3, $5
47
- 0x22,0x48,0xc7,0x00 = sub $9, $6, $7
48
- 0xc8,0xff,0xbd,0x23 = addi $sp, $sp, -56
49
- 0x23,0x20,0x65,0x00 = subu $4, $3, $5
50
- 0xd8,0xff,0xbd,0x27 = addiu $sp, $sp, -40
51
- 0x22,0x30,0x07,0x00 = neg $6, $7
52
- 0x23,0x30,0x07,0x00 = negu $6, $7
53
- 0x21,0x38,0x00,0x01 = move $7, $8
data/test/MC/Mips/mips-control-instructions-64.s.cs DELETED
@@ -1,33 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
2
- 0x00,0x00,0x00,0x0d = break
3
- 0x00,0x07,0x00,0x0d = break 7, 0
4
- 0x00,0x07,0x01,0x4d = break 7, 5
5
- 0x00,0x00,0x00,0x0c = syscall
6
- 0x00,0x0d,0x15,0x0c = syscall 13396
7
- 0x42,0x00,0x00,0x18 = eret
8
- 0x42,0x00,0x00,0x1f = deret
9
- 0x41,0x60,0x60,0x00 = di
10
- 0x41,0x60,0x60,0x00 = di
11
- 0x41,0x6a,0x60,0x00 = di $10
12
- 0x41,0x60,0x60,0x20 = ei
13
- 0x41,0x60,0x60,0x20 = ei
14
- 0x41,0x6a,0x60,0x20 = ei $10
15
- 0x42,0x00,0x00,0x20 = wait
16
- 0x00,0x03,0x00,0x34 = teq $zero, $3
17
- 0x00,0x03,0x00,0x74 = teq $zero, $3, 1
18
- 0x04,0x6c,0x00,0x01 = teqi $3, 1
19
- 0x00,0x03,0x00,0x30 = tge $zero, $3
20
- 0x00,0x03,0x00,0xf0 = tge $zero, $3, 3
21
- 0x04,0x68,0x00,0x03 = tgei $3, 3
22
- 0x00,0x03,0x00,0x31 = tgeu $zero, $3
23
- 0x00,0x03,0x01,0xf1 = tgeu $zero, $3, 7
24
- 0x04,0x69,0x00,0x07 = tgeiu $3, 7
25
- 0x00,0x03,0x00,0x32 = tlt $zero, $3
26
- 0x00,0x03,0x07,0xf2 = tlt $zero, $3, 31
27
- 0x04,0x6a,0x00,0x1f = tlti $3, 31
28
- 0x00,0x03,0x00,0x33 = tltu $zero, $3
29
- 0x00,0x03,0x3f,0xf3 = tltu $zero, $3, 255
30
- 0x04,0x6b,0x00,0xff = tltiu $3, 255
31
- 0x00,0x03,0x00,0x36 = tne $zero, $3
32
- 0x00,0x03,0xff,0xf6 = tne $zero, $3, 1023
33
- 0x04,0x6e,0x03,0xff = tnei $3, 1023
data/test/MC/Mips/mips-control-instructions.s.cs DELETED
@@ -1,33 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
2
- 0x00,0x00,0x00,0x0d = break
3
- 0x00,0x07,0x00,0x0d = break 7, 0
4
- 0x00,0x07,0x01,0x4d = break 7, 5
5
- 0x00,0x00,0x00,0x0c = syscall
6
- 0x00,0x0d,0x15,0x0c = syscall 13396
7
- 0x42,0x00,0x00,0x18 = eret
8
- 0x42,0x00,0x00,0x1f = deret
9
- 0x41,0x60,0x60,0x00 = di
10
- 0x41,0x60,0x60,0x00 = di
11
- 0x41,0x6a,0x60,0x00 = di $10
12
- 0x41,0x60,0x60,0x20 = ei
13
- 0x41,0x60,0x60,0x20 = ei
14
- 0x41,0x6a,0x60,0x20 = ei $10
15
- 0x42,0x00,0x00,0x20 = wait
16
- 0x00,0x03,0x00,0x34 = teq $zero, $3
17
- 0x00,0x03,0x00,0x74 = teq $zero, $3, 1
18
- 0x04,0x6c,0x00,0x01 = teqi $3, 1
19
- 0x00,0x03,0x00,0x30 = tge $zero, $3
20
- 0x00,0x03,0x00,0xf0 = tge $zero, $3, 3
21
- 0x04,0x68,0x00,0x03 = tgei $3, 3
22
- 0x00,0x03,0x00,0x31 = tgeu $zero, $3
23
- 0x00,0x03,0x01,0xf1 = tgeu $zero, $3, 7
24
- 0x04,0x69,0x00,0x07 = tgeiu $3, 7
25
- 0x00,0x03,0x00,0x32 = tlt $zero, $3
26
- 0x00,0x03,0x07,0xf2 = tlt $zero, $3, 31
27
- 0x04,0x6a,0x00,0x1f = tlti $3, 31
28
- 0x00,0x03,0x00,0x33 = tltu $zero, $3
29
- 0x00,0x03,0x3f,0xf3 = tltu $zero, $3, 255
30
- 0x04,0x6b,0x00,0xff = tltiu $3, 255
31
- 0x00,0x03,0x00,0x36 = tne $zero, $3
32
- 0x00,0x03,0xff,0xf6 = tne $zero, $3, 1023
33
- 0x04,0x6e,0x03,0xff = tnei $3, 1023
data/test/MC/Mips/mips-coprocessor-encodings.s.cs DELETED
@@ -1,17 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
2
- 0x40,0xac,0x80,0x02 = dmtc0 $12, $16, 2
3
- 0x40,0xac,0x80,0x00 = dmtc0 $12, $16, 0
4
- 0x40,0x8c,0x80,0x02 = mtc0 $12, $16, 2
5
- 0x40,0x8c,0x80,0x00 = mtc0 $12, $16, 0
6
- 0x40,0x2c,0x80,0x02 = dmfc0 $12, $16, 2
7
- 0x40,0x2c,0x80,0x00 = dmfc0 $12, $16, 0
8
- 0x40,0x0c,0x80,0x02 = mfc0 $12, $16, 2
9
- 0x40,0x0c,0x80,0x00 = mfc0 $12, $16, 0
10
- 0x48,0xac,0x80,0x02 = dmtc2 $12, $16, 2
11
- 0x48,0xac,0x80,0x00 = dmtc2 $12, $16, 0
12
- 0x48,0x8c,0x80,0x02 = mtc2 $12, $16, 2
13
- 0x48,0x8c,0x80,0x00 = mtc2 $12, $16, 0
14
- 0x48,0x2c,0x80,0x02 = dmfc2 $12, $16, 2
15
- 0x48,0x2c,0x80,0x00 = dmfc2 $12, $16, 0
16
- 0x48,0x0c,0x80,0x02 = mfc2 $12, $16, 2
17
- 0x48,0x0c,0x80,0x00 = mfc2 $12, $16, 0
data/test/MC/Mips/mips-dsp-instructions.s.cs DELETED
@@ -1,43 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
2
- 0x7e,0x32,0x83,0x11 = precrq.qb.ph $16, $17, $18
3
- 0x7e,0x53,0x8d,0x11 = precrq.ph.w $17, $18, $19
4
- 0x7e,0x74,0x95,0x51 = precrq_rs.ph.w $18, $19, $20
5
- 0x7e,0x95,0x9b,0xd1 = precrqu_s.qb.ph $19, $20, $21
6
- 0x7c,0x15,0xa3,0x12 = preceq.w.phl $20, $21
7
- 0x7c,0x16,0xab,0x52 = preceq.w.phr $21, $22
8
- 0x7c,0x17,0xb1,0x12 = precequ.ph.qbl $22, $23
9
- 0x7c,0x18,0xb9,0x52 = precequ.ph.qbr $23, $24
10
- 0x7c,0x19,0xc1,0x92 = precequ.ph.qbla $24, $25
11
- 0x7c,0x1a,0xc9,0xd2 = precequ.ph.qbra $25, $26
12
- 0x7c,0x1b,0xd7,0x12 = preceu.ph.qbl $26, $27
13
- 0x7c,0x1c,0xdf,0x52 = preceu.ph.qbr $27, $gp
14
- 0x7c,0x1d,0xe7,0x92 = preceu.ph.qbla $gp, $sp
15
- 0x7c,0x1e,0xef,0xd2 = preceu.ph.qbra $sp, $fp
16
- 0x7f,0x19,0xbb,0x51 = precr.qb.ph $23, $24, $25
17
- 0x7f,0x38,0x07,0x91 = precr_sra.ph.w $24, $25, 0
18
- 0x7f,0x38,0xff,0x91 = precr_sra.ph.w $24, $25, 31
19
- 0x7f,0x59,0x07,0xd1 = precr_sra_r.ph.w $25, $26, 0
20
- 0x7f,0x59,0xff,0xd1 = precr_sra_r.ph.w $25, $26, 31
21
- 0x7f,0x54,0x51,0x8a = lbux $10, $20($26)
22
- 0x7f,0x75,0x59,0x0a = lhx $11, $21($27)
23
- 0x7f,0x96,0x60,0x0a = lwx $12, $22($gp)
24
- 0x00,0x43,0x18,0x18 = mult $ac3, $2, $3
25
- 0x00,0x85,0x10,0x19 = multu $ac2, $4, $5
26
- 0x70,0xc7,0x08,0x00 = madd $ac1, $6, $7
27
- 0x71,0x09,0x00,0x01 = maddu $ac0, $8, $9
28
- 0x71,0x4b,0x18,0x04 = msub $ac3, $10, $11
29
- 0x71,0x8d,0x10,0x05 = msubu $ac2, $12, $13
30
- 0x00,0x20,0x70,0x10 = mfhi $14, $ac1
31
- 0x00,0x00,0x78,0x12 = mflo $15, $ac0
32
- 0x02,0x00,0x18,0x11 = mthi $16, $ac3
33
- 0x02,0x20,0x10,0x13 = mtlo $17, $ac2
34
- 0x00,0x43,0x00,0x18 = mult $2, $3
35
- 0x00,0x85,0x00,0x19 = multu $4, $5
36
- 0x70,0xc7,0x00,0x00 = madd $6, $7
37
- 0x71,0x09,0x00,0x01 = maddu $8, $9
38
- 0x71,0x4b,0x00,0x04 = msub $10, $11
39
- 0x71,0x8d,0x00,0x05 = msubu $12, $13
40
- 0x00,0x00,0x70,0x10 = mfhi $14
41
- 0x00,0x00,0x78,0x12 = mflo $15
42
- 0x02,0x00,0x00,0x11 = mthi $16
43
- 0x02,0x20,0x00,0x13 = mtlo $17
data/test/MC/Mips/mips-expansions.s.cs DELETED
@@ -1,20 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32, None
2
- 0x7b,0x00,0x05,0x34 = ori $5, $zero, 123
3
- 0xd7,0xf6,0x06,0x24 = addiu $6, $zero, -2345
4
- 0x01,0x00,0x07,0x3c = lui $7, 1
5
- 0x02,0x00,0xe7,0x34 = ori $7, $7, 2
6
- 0x14,0x00,0x04,0x24 = addiu $4, $zero, 20
7
- 0x01,0x00,0x07,0x3c = lui $7, 1
8
- 0x02,0x00,0xe7,0x34 = ori $7, $7, 2
9
- 0x14,0x00,0xa4,0x24 = addiu $4, $5, 20
10
- 0x01,0x00,0x07,0x3c = lui $7, 1
11
- 0x02,0x00,0xe7,0x34 = ori $7, $7, 2
12
- 0x21,0x38,0xe8,0x00 = addu $7, $7, $8
13
- 0x21,0x50,0x44,0x01 = addu $10, $10, $4
14
- 0x21,0x08,0x29,0x00 = addu $1, $1, $9
15
- 0x0a,0x00,0x0a,0x3c = lui $10, 10
16
- 0x21,0x50,0x44,0x01 = addu $10, $10, $4
17
- 0x7b,0x00,0x4a,0x8d = lw $10, 123($10)
18
- 0x02,0x00,0x01,0x3c = lui $1, 2
19
- 0x21,0x08,0x29,0x00 = addu $1, $1, $9
20
- 0x40,0xe2,0x2a,0xac = sw $10, 57920($1)
data/test/MC/Mips/mips-fpu-instructions.s.cs DELETED
@@ -1,93 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32, None
2
- 0x05,0x73,0x20,0x46 = abs.d $f12, $f14
3
- 0x85,0x39,0x00,0x46 = abs.s $f6, $f7
4
- 0x00,0x62,0x2e,0x46 = add.d $f8, $f12, $f14
5
- 0x40,0x32,0x07,0x46 = add.s $f9, $f6, $f7
6
- 0x0f,0x73,0x20,0x46 = floor.w.d $f12, $f14
7
- 0x8f,0x39,0x00,0x46 = floor.w.s $f6, $f7
8
- 0x0e,0x73,0x20,0x46 = ceil.w.d $f12, $f14
9
- 0x8e,0x39,0x00,0x46 = ceil.w.s $f6, $f7
10
- 0x02,0x62,0x2e,0x46 = mul.d $f8, $f12, $f14
11
- 0x42,0x32,0x07,0x46 = mul.s $f9, $f6, $f7
12
- 0x07,0x73,0x20,0x46 = neg.d $f12, $f14
13
- 0x87,0x39,0x00,0x46 = neg.s $f6, $f7
14
- 0x0c,0x73,0x20,0x46 = round.w.d $f12, $f14
15
- 0x8c,0x39,0x00,0x46 = round.w.s $f6, $f7
16
- 0x04,0x73,0x20,0x46 = sqrt.d $f12, $f14
17
- 0x84,0x39,0x00,0x46 = sqrt.s $f6, $f7
18
- 0x01,0x62,0x2e,0x46 = sub.d $f8, $f12, $f14
19
- 0x41,0x32,0x07,0x46 = sub.s $f9, $f6, $f7
20
- 0x0d,0x73,0x20,0x46 = trunc.w.d $f12, $f14
21
- 0x8d,0x39,0x00,0x46 = trunc.w.s $f6, $f7
22
- 0x32,0x60,0x2e,0x46 = c.eq.d $f12, $f14
23
- 0x32,0x30,0x07,0x46 = c.eq.s $f6, $f7
24
- 0x30,0x60,0x2e,0x46 = c.f.d $f12, $f14
25
- 0x30,0x30,0x07,0x46 = c.f.s $f6, $f7
26
- 0x3e,0x60,0x2e,0x46 = c.le.d $f12, $f14
27
- 0x3e,0x30,0x07,0x46 = c.le.s $f6, $f7
28
- 0x3c,0x60,0x2e,0x46 = c.lt.d $f12, $f14
29
- 0x3c,0x30,0x07,0x46 = c.lt.s $f6, $f7
30
- 0x3d,0x60,0x2e,0x46 = c.nge.d $f12, $f14
31
- 0x3d,0x30,0x07,0x46 = c.nge.s $f6, $f7
32
- 0x3b,0x60,0x2e,0x46 = c.ngl.d $f12, $f14
33
- 0x3b,0x30,0x07,0x46 = c.ngl.s $f6, $f7
34
- 0x39,0x60,0x2e,0x46 = c.ngle.d $f12, $f14
35
- 0x39,0x30,0x07,0x46 = c.ngle.s $f6, $f7
36
- 0x3f,0x60,0x2e,0x46 = c.ngt.d $f12, $f14
37
- 0x3f,0x30,0x07,0x46 = c.ngt.s $f6, $f7
38
- 0x36,0x60,0x2e,0x46 = c.ole.d $f12, $f14
39
- 0x36,0x30,0x07,0x46 = c.ole.s $f6, $f7
40
- 0x34,0x60,0x2e,0x46 = c.olt.d $f12, $f14
41
- 0x34,0x30,0x07,0x46 = c.olt.s $f6, $f7
42
- 0x3a,0x60,0x2e,0x46 = c.seq.d $f12, $f14
43
- 0x3a,0x30,0x07,0x46 = c.seq.s $f6, $f7
44
- 0x38,0x60,0x2e,0x46 = c.sf.d $f12, $f14
45
- 0x38,0x30,0x07,0x46 = c.sf.s $f6, $f7
46
- 0x33,0x60,0x2e,0x46 = c.ueq.d $f12, $f14
47
- 0x33,0xe0,0x12,0x46 = c.ueq.s $f28, $f18
48
- 0x37,0x60,0x2e,0x46 = c.ule.d $f12, $f14
49
- 0x37,0x30,0x07,0x46 = c.ule.s $f6, $f7
50
- 0x35,0x60,0x2e,0x46 = c.ult.d $f12, $f14
51
- 0x35,0x30,0x07,0x46 = c.ult.s $f6, $f7
52
- 0x31,0x60,0x2e,0x46 = c.un.d $f12, $f14
53
- 0x31,0x30,0x07,0x46 = c.un.s $f6, $f7
54
- 0xa1,0x39,0x00,0x46 = cvt.d.s $f6, $f7
55
- 0x21,0x73,0x80,0x46 = cvt.d.w $f12, $f14
56
- 0x20,0x73,0x20,0x46 = cvt.s.d $f12, $f14
57
- 0xa0,0x39,0x80,0x46 = cvt.s.w $f6, $f7
58
- 0x24,0x73,0x20,0x46 = cvt.w.d $f12, $f14
59
- 0xa4,0x39,0x00,0x46 = cvt.w.s $f6, $f7
60
- 0x00,0x00,0x46,0x44 = cfc1 $6, $0
61
- 0x00,0xf8,0xca,0x44 = ctc1 $10, $31
62
- 0x00,0x38,0x06,0x44 = mfc1 $6, $f7
63
- 0x10,0x28,0x00,0x00 = mfhi $5
64
- 0x12,0x28,0x00,0x00 = mflo $5
65
- 0x86,0x41,0x20,0x46 = mov.d $f6, $f8
66
- 0x86,0x39,0x00,0x46 = mov.s $f6, $f7
67
- 0x00,0x38,0x86,0x44 = mtc1 $6, $f7
68
- 0x11,0x00,0xe0,0x00 = mthi $7
69
- 0x13,0x00,0xe0,0x00 = mtlo $7
70
- 0xc6,0x23,0xe9,0xe4 = swc1 $f9, 9158($7)
71
- 0x00,0x38,0x06,0x40 = mfc0 $6, $7, 0
72
- 0x00,0x40,0x89,0x40 = mtc0 $9, $8, 0
73
- 0x00,0x38,0x05,0x48 = mfc2 $5, $7, 0
74
- 0x00,0x20,0x89,0x48 = mtc2 $9, $4, 0
75
- 0x02,0x38,0x06,0x40 = mfc0 $6, $7, 2
76
- 0x03,0x40,0x89,0x40 = mtc0 $9, $8, 3
77
- 0x04,0x38,0x05,0x48 = mfc2 $5, $7, 4
78
- 0x05,0x20,0x89,0x48 = mtc2 $9, $4, 5
79
- 0x01,0x10,0x20,0x00 = movf $2, $1, $fcc0
80
- 0x01,0x10,0x21,0x00 = movt $2, $1, $fcc0
81
- 0x01,0x20,0xb1,0x00 = movt $4, $5, $fcc4
82
- 0x11,0x31,0x28,0x46 = movf.d $f4, $f6, $fcc2
83
- 0x11,0x31,0x14,0x46 = movf.s $f4, $f6, $fcc5
84
- 0x05,0x00,0xa6,0x4c = luxc1 $f0, $6($5)
85
- 0x0d,0x20,0xb8,0x4c = suxc1 $f4, $24($5)
86
- 0x00,0x05,0xcc,0x4d = lwxc1 $f20, $12($14)
87
- 0x08,0xd0,0xd2,0x4e = swxc1 $f26, $18($22)
88
- 0x00,0x20,0x71,0x44 = mfhc1 $17, $f4
89
- 0x00,0x30,0xf1,0x44 = mthc1 $17, $f6
90
- 0x10,0x00,0xa4,0xeb = swc2 $4, 16($sp)
91
- 0x10,0x00,0xa4,0xfb = sdc2 $4, 16($sp)
92
- 0x0c,0x00,0xeb,0xcb = lwc2 $11, 12($ra)
93
- 0x0c,0x00,0xeb,0xdb = ldc2 $11, 12($ra)
data/test/MC/Mips/mips-jump-instructions.s.cs DELETED
@@ -1 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32, None
data/test/MC/Mips/mips-memory-instructions.s.cs DELETED
@@ -1,17 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32, None
2
- 0x10,0x00,0xa4,0xa0 = sb $4, 16($5)
3
- 0x10,0x00,0xa4,0xe0 = sc $4, 16($5)
4
- 0x10,0x00,0xa4,0xa4 = sh $4, 16($5)
5
- 0x10,0x00,0xa4,0xac = sw $4, 16($5)
6
- 0x00,0x00,0xa7,0xac = sw $7, 0($5)
7
- 0x10,0x00,0xa2,0xe4 = swc1 $f2, 16($5)
8
- 0x10,0x00,0xa4,0xa8 = swl $4, 16($5)
9
- 0x04,0x00,0xa4,0x80 = lb $4, 4($5)
10
- 0x04,0x00,0xa4,0x8c = lw $4, 4($5)
11
- 0x04,0x00,0xa4,0x90 = lbu $4, 4($5)
12
- 0x04,0x00,0xa4,0x84 = lh $4, 4($5)
13
- 0x04,0x00,0xa4,0x94 = lhu $4, 4($5)
14
- 0x04,0x00,0xa4,0xc0 = ll $4, 4($5)
15
- 0x04,0x00,0xa4,0x8c = lw $4, 4($5)
16
- 0x00,0x00,0xe7,0x8c = lw $7, 0($7)
17
- 0x10,0x00,0xa2,0x8f = lw $2, 16($sp)
data/test/MC/Mips/mips-register-names.s.cs DELETED
@@ -1,33 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
2
- 0x24,0x00,0x00,0x00 = addiu $zero, $zero, 0
3
- 0x24,0x01,0x00,0x00 = addiu $at, $zero, 0
4
- 0x24,0x02,0x00,0x00 = addiu $v0, $zero, 0
5
- 0x24,0x03,0x00,0x00 = addiu $v1, $zero, 0
6
- 0x24,0x04,0x00,0x00 = addiu $a0, $zero, 0
7
- 0x24,0x05,0x00,0x00 = addiu $a1, $zero, 0
8
- 0x24,0x06,0x00,0x00 = addiu $a2, $zero, 0
9
- 0x24,0x07,0x00,0x00 = addiu $a3, $zero, 0
10
- 0x24,0x08,0x00,0x00 = addiu $t0, $zero, 0
11
- 0x24,0x09,0x00,0x00 = addiu $t1, $zero, 0
12
- 0x24,0x0a,0x00,0x00 = addiu $t2, $zero, 0
13
- 0x24,0x0b,0x00,0x00 = addiu $t3, $zero, 0
14
- 0x24,0x0c,0x00,0x00 = addiu $t4, $zero, 0
15
- 0x24,0x0d,0x00,0x00 = addiu $t5, $zero, 0
16
- 0x24,0x0e,0x00,0x00 = addiu $t6, $zero, 0
17
- 0x24,0x0f,0x00,0x00 = addiu $t7, $zero, 0
18
- 0x24,0x10,0x00,0x00 = addiu $s0, $zero, 0
19
- 0x24,0x11,0x00,0x00 = addiu $s1, $zero, 0
20
- 0x24,0x12,0x00,0x00 = addiu $s2, $zero, 0
21
- 0x24,0x13,0x00,0x00 = addiu $s3, $zero, 0
22
- 0x24,0x14,0x00,0x00 = addiu $s4, $zero, 0
23
- 0x24,0x15,0x00,0x00 = addiu $s5, $zero, 0
24
- 0x24,0x16,0x00,0x00 = addiu $s6, $zero, 0
25
- 0x24,0x17,0x00,0x00 = addiu $s7, $zero, 0
26
- 0x24,0x18,0x00,0x00 = addiu $t8, $zero, 0
27
- 0x24,0x19,0x00,0x00 = addiu $t9, $zero, 0
28
- 0x24,0x1a,0x00,0x00 = addiu $k0, $zero, 0
29
- 0x24,0x1b,0x00,0x00 = addiu $k1, $zero, 0
30
- 0x24,0x1c,0x00,0x00 = addiu $gp, $zero, 0
31
- 0x24,0x1d,0x00,0x00 = addiu $sp, $zero, 0
32
- 0x24,0x1e,0x00,0x00 = addiu $fp, $zero, 0
33
- 0x24,0x1f,0x00,0x00 = addiu $sp, $zero, 0
data/test/MC/Mips/mips64-alu-instructions.s.cs DELETED
@@ -1,47 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS64, None
2
- 0x24,0x48,0xc7,0x00 = and $9, $6, $7
3
- 0x67,0x45,0xc9,0x30 = andi $9, $6, 17767
4
- 0x67,0x45,0xc9,0x30 = andi $9, $6, 17767
5
- 0x21,0x30,0xe6,0x70 = clo $6, $7
6
- 0x20,0x30,0xe6,0x70 = clz $6, $7
7
- 0x84,0x61,0x33,0x7d = ins $19, $9, 6, 7
8
- 0x27,0x48,0xc7,0x00 = nor $9, $6, $7
9
- 0x25,0x18,0x65,0x00 = or $3, $3, $5
10
- 0x67,0x45,0xa4,0x34 = ori $4, $5, 17767
11
- 0x67,0x45,0xc9,0x34 = ori $9, $6, 17767
12
- 0xc2,0x49,0x26,0x00 = rotr $9, $6, 7
13
- 0x46,0x48,0xe6,0x00 = rotrv $9, $6, $7
14
- 0xc0,0x21,0x03,0x00 = sll $4, $3, 7
15
- 0x04,0x10,0xa3,0x00 = sllv $2, $3, $5
16
- 0x2a,0x18,0x65,0x00 = slt $3, $3, $5
17
- 0x67,0x00,0x63,0x28 = slti $3, $3, 103
18
- 0x67,0x00,0x63,0x28 = slti $3, $3, 103
19
- 0x67,0x00,0x63,0x2c = sltiu $3, $3, 103
20
- 0x2b,0x18,0x65,0x00 = sltu $3, $3, $5
21
- 0xc3,0x21,0x03,0x00 = sra $4, $3, 7
22
- 0x07,0x10,0xa3,0x00 = srav $2, $3, $5
23
- 0xc2,0x21,0x03,0x00 = srl $4, $3, 7
24
- 0x06,0x10,0xa3,0x00 = srlv $2, $3, $5
25
- 0x26,0x18,0x65,0x00 = xor $3, $3, $5
26
- 0x67,0x45,0xc9,0x38 = xori $9, $6, 17767
27
- 0x67,0x45,0xc9,0x38 = xori $9, $6, 17767
28
- 0xa0,0x30,0x07,0x7c = wsbh $6, $7
29
- 0x27,0x38,0x00,0x01 = not $7, $8
30
- 0x2c,0x48,0xc7,0x00 = dadd $9, $6, $7
31
- 0x67,0x45,0xc9,0x60 = daddi $9, $6, 17767
32
- 0x67,0xc5,0xc9,0x64 = daddiu $9, $6, -15001
33
- 0x67,0x45,0xc9,0x60 = daddi $9, $6, 17767
34
- 0x67,0x45,0x29,0x61 = daddi $9, $9, 17767
35
- 0x67,0xc5,0xc9,0x64 = daddiu $9, $6, -15001
36
- 0x67,0xc5,0x29,0x65 = daddiu $9, $9, -15001
37
- 0x2d,0x48,0xc7,0x00 = daddu $9, $6, $7
38
- 0x3a,0x4d,0x26,0x00 = drotr $9, $6, 20
39
- 0x3e,0x4d,0x26,0x00 = drotr32 $9, $6, 52
40
- 0x00,0x00,0xc7,0x70 = madd $6, $7
41
- 0x01,0x00,0xc7,0x70 = maddu $6, $7
42
- 0x04,0x00,0xc7,0x70 = msub $6, $7
43
- 0x05,0x00,0xc7,0x70 = msubu $6, $7
44
- 0x18,0x00,0x65,0x00 = mult $3, $5
45
- 0x19,0x00,0x65,0x00 = multu $3, $5
46
- 0x2f,0x20,0x65,0x00 = dsubu $4, $3, $5
47
- 0x2d,0x38,0x00,0x01 = move $7, $8
data/test/MC/Mips/mips64-instructions.s.cs DELETED
@@ -1,3 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS64, None
2
- 0x81,0x00,0x42,0x4d = ldxc1 $f2, $2($10)
3
- 0x09,0x40,0x24,0x4f = sdxc1 $f8, $4($25)
data/test/MC/Mips/mips64-register-names.s.cs DELETED
@@ -1,33 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
2
- 0x64,0x00,0x00,0x00 = daddiu $zero, $zero, 0
3
- 0x64,0x01,0x00,0x00 = daddiu $at, $zero, 0
4
- 0x64,0x02,0x00,0x00 = daddiu $v0, $zero, 0
5
- 0x64,0x03,0x00,0x00 = daddiu $v1, $zero, 0
6
- 0x64,0x04,0x00,0x00 = daddiu $a0, $zero, 0
7
- 0x64,0x05,0x00,0x00 = daddiu $a1, $zero, 0
8
- 0x64,0x06,0x00,0x00 = daddiu $a2, $zero, 0
9
- 0x64,0x07,0x00,0x00 = daddiu $a2, $zero, 0
10
- 0x64,0x08,0x00,0x00 = daddiu $a4, $zero, 0
11
- 0x64,0x09,0x00,0x00 = daddiu $a5, $zero, 0
12
- 0x64,0x0a,0x00,0x00 = daddiu $a6, $zero, 0
13
- 0x64,0x0b,0x00,0x00 = daddiu $a7, $zero, 0
14
- 0x64,0x0c,0x00,0x00 = daddiu $t4, $zero, 0
15
- 0x64,0x0d,0x00,0x00 = daddiu $t5, $zero, 0
16
- 0x64,0x0e,0x00,0x00 = daddiu $t6, $zero, 0
17
- 0x64,0x0f,0x00,0x00 = daddiu $t7, $zero, 0
18
- 0x64,0x10,0x00,0x00 = daddiu $s0, $zero, 0
19
- 0x64,0x11,0x00,0x00 = daddiu $s1, $zero, 0
20
- 0x64,0x12,0x00,0x00 = daddiu $s2, $zero, 0
21
- 0x64,0x13,0x00,0x00 = daddiu $s3, $zero, 0
22
- 0x64,0x14,0x00,0x00 = daddiu $s4, $zero, 0
23
- 0x64,0x15,0x00,0x00 = daddiu $s5, $zero, 0
24
- 0x64,0x16,0x00,0x00 = daddiu $s6, $zero, 0
25
- 0x64,0x17,0x00,0x00 = daddiu $s7, $zero, 0
26
- 0x64,0x18,0x00,0x00 = daddiu $t8, $zero, 0
27
- 0x64,0x19,0x00,0x00 = daddiu $t9, $zero, 0
28
- 0x64,0x1a,0x00,0x00 = daddiu $kt0, $zero, 0
29
- 0x64,0x1b,0x00,0x00 = daddiu $kt1, $zero, 0
30
- 0x64,0x1c,0x00,0x00 = daddiu $gp, $zero, 0
31
- 0x64,0x1d,0x00,0x00 = daddiu $sp, $zero, 0
32
- 0x64,0x1e,0x00,0x00 = daddiu $s8, $zero, 0
33
- 0x64,0x1f,0x00,0x00 = daddiu $ra, $zero, 0
data/test/MC/Mips/mips_directives.s.cs DELETED
@@ -1,12 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
2
- 0x10,0x00,0x01,0x4d = b 1332
3
- 0x08,0x00,0x01,0x4c = j 1328
4
- 0x0c,0x00,0x01,0x4c = jal 1328
5
- 0x10,0x00,0x01,0x4d = b 1332
6
- 0x00,0x00,0x00,0x00 = nop
7
- 0x08,0x00,0x01,0x4c = j 1328
8
- 0x00,0x00,0x00,0x00 = nop
9
- 0x0c,0x00,0x01,0x4c = jal 1328
10
- 0x00,0x00,0x00,0x00 = nop
11
- 0x46,0x00,0x39,0x85 = abs.s $f6, $f7
12
- 0x01,0xef,0x18,0x24 = and $3, $15, $15
data/test/MC/Mips/nabi-regs.s.cs DELETED
@@ -1,12 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
2
- 0x02,0x04,0x80,0x20 = add $16, $16, $4
3
- 0x02,0x06,0x80,0x20 = add $16, $16, $6
4
- 0x02,0x07,0x80,0x20 = add $16, $16, $7
5
- 0x02,0x08,0x80,0x20 = add $16, $16, $8
6
- 0x02,0x09,0x80,0x20 = add $16, $16, $9
7
- 0x02,0x0a,0x80,0x20 = add $16, $16, $10
8
- 0x02,0x0b,0x80,0x20 = add $16, $16, $11
9
- 0x02,0x0c,0x80,0x20 = add $16, $16, $12
10
- 0x02,0x0d,0x80,0x20 = add $16, $16, $13
11
- 0x02,0x0e,0x80,0x20 = add $16, $16, $14
12
- 0x02,0x0f,0x80,0x20 = add $16, $16, $15
data/test/MC/Mips/set-at-directive.s.cs DELETED
@@ -1,6 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32, None
2
- 0x08,0x00,0x60,0x00 = jr $3
3
- 0x08,0x00,0x80,0x03 = jr $gp
4
- 0x08,0x00,0xc0,0x03 = jr $fp
5
- 0x08,0x00,0xa0,0x03 = jr $sp
6
- 0x08,0x00,0xe0,0x03 = jr $ra
data/test/MC/Mips/test_2r.s.cs DELETED
@@ -1,16 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
2
- 0x7b,0x00,0x4f,0x9e = fill.b $w30, $9
3
- 0x7b,0x01,0xbf,0xde = fill.h $w31, $23
4
- 0x7b,0x02,0xc4,0x1e = fill.w $w16, $24
5
- 0x7b,0x08,0x05,0x5e = nloc.b $w21, $w0
6
- 0x7b,0x09,0xfc,0x9e = nloc.h $w18, $w31
7
- 0x7b,0x0a,0xb8,0x9e = nloc.w $w2, $w23
8
- 0x7b,0x0b,0x51,0x1e = nloc.d $w4, $w10
9
- 0x7b,0x0c,0x17,0xde = nlzc.b $w31, $w2
10
- 0x7b,0x0d,0xb6,0xde = nlzc.h $w27, $w22
11
- 0x7b,0x0e,0xea,0x9e = nlzc.w $w10, $w29
12
- 0x7b,0x0f,0x4e,0x5e = nlzc.d $w25, $w9
13
- 0x7b,0x04,0x95,0x1e = pcnt.b $w20, $w18
14
- 0x7b,0x05,0x40,0x1e = pcnt.h $w0, $w8
15
- 0x7b,0x06,0x4d,0xde = pcnt.w $w23, $w9
16
- 0x7b,0x07,0xc5,0x5e = pcnt.d $w21, $w24
data/test/MC/Mips/test_2rf.s.cs DELETED
@@ -1,33 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
2
- 0x7b,0x20,0x66,0x9e = fclass.w $w26, $w12
3
- 0x7b,0x21,0x8e,0x1e = fclass.d $w24, $w17
4
- 0x7b,0x30,0x02,0x1e = fexupl.w $w8, $w0
5
- 0x7b,0x31,0xec,0x5e = fexupl.d $w17, $w29
6
- 0x7b,0x32,0x23,0x5e = fexupr.w $w13, $w4
7
- 0x7b,0x33,0x11,0x5e = fexupr.d $w5, $w2
8
- 0x7b,0x3c,0xed,0x1e = ffint_s.w $w20, $w29
9
- 0x7b,0x3d,0x7b,0x1e = ffint_s.d $w12, $w15
10
- 0x7b,0x3e,0xd9,0xde = ffint_u.w $w7, $w27
11
- 0x7b,0x3f,0x84,0xde = ffint_u.d $w19, $w16
12
- 0x7b,0x34,0x6f,0xde = ffql.w $w31, $w13
13
- 0x7b,0x35,0x6b,0x1e = ffql.d $w12, $w13
14
- 0x7b,0x36,0xf6,0xde = ffqr.w $w27, $w30
15
- 0x7b,0x37,0x7f,0x9e = ffqr.d $w30, $w15
16
- 0x7b,0x2e,0xfe,0x5e = flog2.w $w25, $w31
17
- 0x7b,0x2f,0x54,0x9e = flog2.d $w18, $w10
18
- 0x7b,0x2c,0x79,0xde = frint.w $w7, $w15
19
- 0x7b,0x2d,0xb5,0x5e = frint.d $w21, $w22
20
- 0x7b,0x2a,0x04,0xde = frcp.w $w19, $w0
21
- 0x7b,0x2b,0x71,0x1e = frcp.d $w4, $w14
22
- 0x7b,0x28,0x8b,0x1e = frsqrt.w $w12, $w17
23
- 0x7b,0x29,0x5d,0xde = frsqrt.d $w23, $w11
24
- 0x7b,0x26,0x58,0x1e = fsqrt.w $w0, $w11
25
- 0x7b,0x27,0x63,0xde = fsqrt.d $w15, $w12
26
- 0x7b,0x38,0x2f,0x9e = ftint_s.w $w30, $w5
27
- 0x7b,0x39,0xb9,0x5e = ftint_s.d $w5, $w23
28
- 0x7b,0x3a,0x75,0x1e = ftint_u.w $w20, $w14
29
- 0x7b,0x3b,0xad,0xde = ftint_u.d $w23, $w21
30
- 0x7b,0x22,0x8f,0x5e = ftrunc_s.w $w29, $w17
31
- 0x7b,0x23,0xdb,0x1e = ftrunc_s.d $w12, $w27
32
- 0x7b,0x24,0x7c,0x5e = ftrunc_u.w $w17, $w15
33
- 0x7b,0x25,0xd9,0x5e = ftrunc_u.d $w5, $w27