crabstone 3.0.3 → 4.0.4

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (347) hide show
  1. checksums.yaml +5 -5
  2. data/CHANGES.md +59 -42
  3. data/README.md +37 -39
  4. data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
  5. data/lib/crabstone/arch/3/arm64.rb +124 -0
  6. data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
  7. data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
  8. data/lib/crabstone/arch/3/mips.rb +57 -0
  9. data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
  10. data/lib/crabstone/arch/3/ppc.rb +73 -0
  11. data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
  12. data/lib/crabstone/arch/3/sparc.rb +60 -0
  13. data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
  14. data/lib/crabstone/arch/3/sysz.rb +67 -0
  15. data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
  16. data/lib/crabstone/arch/3/x86.rb +82 -0
  17. data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
  18. data/lib/crabstone/arch/3/xcore.rb +59 -0
  19. data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
  20. data/lib/crabstone/arch/4/arm.rb +110 -0
  21. data/lib/crabstone/arch/4/arm64.rb +125 -0
  22. data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
  23. data/lib/crabstone/arch/4/arm_const.rb +785 -0
  24. data/lib/crabstone/arch/4/evm.rb +20 -0
  25. data/lib/crabstone/arch/4/evm_const.rb +161 -0
  26. data/lib/crabstone/arch/4/m680x.rb +106 -0
  27. data/lib/crabstone/arch/4/m680x_const.rb +426 -0
  28. data/lib/crabstone/arch/4/m68k.rb +129 -0
  29. data/lib/crabstone/arch/4/m68k_const.rb +496 -0
  30. data/lib/crabstone/arch/4/mips.rb +57 -0
  31. data/lib/crabstone/arch/4/mips_const.rb +869 -0
  32. data/lib/crabstone/arch/4/ppc.rb +73 -0
  33. data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
  34. data/lib/crabstone/arch/4/sparc.rb +60 -0
  35. data/lib/crabstone/arch/4/sparc_const.rb +439 -0
  36. data/lib/crabstone/arch/4/sysz.rb +67 -0
  37. data/lib/crabstone/arch/4/sysz_const.rb +763 -0
  38. data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
  39. data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
  40. data/lib/crabstone/arch/4/x86.rb +91 -0
  41. data/lib/crabstone/arch/4/x86_const.rb +1972 -0
  42. data/lib/crabstone/arch/4/xcore.rb +59 -0
  43. data/lib/crabstone/arch/4/xcore_const.rb +171 -0
  44. data/lib/crabstone/arch/extension.rb +27 -0
  45. data/lib/crabstone/arch/register.rb +34 -0
  46. data/lib/crabstone/arch.rb +37 -0
  47. data/lib/crabstone/binding/3/detail.rb +36 -0
  48. data/lib/crabstone/binding/3/instruction.rb +23 -0
  49. data/lib/crabstone/binding/4/detail.rb +40 -0
  50. data/lib/crabstone/binding/4/instruction.rb +23 -0
  51. data/lib/crabstone/binding/structs.rb +32 -0
  52. data/lib/crabstone/binding.rb +59 -0
  53. data/lib/crabstone/constants.rb +110 -0
  54. data/lib/crabstone/cs_version.rb +57 -0
  55. data/lib/crabstone/disassembler.rb +147 -0
  56. data/lib/crabstone/error.rb +74 -0
  57. data/lib/crabstone/instruction.rb +178 -0
  58. data/lib/crabstone/version.rb +5 -0
  59. data/lib/crabstone.rb +5 -557
  60. metadata +142 -331
  61. data/MANIFEST +0 -312
  62. data/Rakefile +0 -27
  63. data/bin/genconst +0 -66
  64. data/bin/genreg +0 -99
  65. data/crabstone.gemspec +0 -27
  66. data/examples/hello_world.rb +0 -43
  67. data/lib/arch/arm64.rb +0 -167
  68. data/lib/arch/arm64_registers.rb +0 -295
  69. data/lib/arch/arm_registers.rb +0 -149
  70. data/lib/arch/mips.rb +0 -78
  71. data/lib/arch/mips_registers.rb +0 -208
  72. data/lib/arch/ppc.rb +0 -90
  73. data/lib/arch/ppc_registers.rb +0 -209
  74. data/lib/arch/sparc.rb +0 -79
  75. data/lib/arch/sparc_registers.rb +0 -121
  76. data/lib/arch/systemz.rb +0 -79
  77. data/lib/arch/sysz_registers.rb +0 -66
  78. data/lib/arch/x86.rb +0 -107
  79. data/lib/arch/x86_registers.rb +0 -265
  80. data/lib/arch/xcore.rb +0 -78
  81. data/lib/arch/xcore_registers.rb +0 -57
  82. data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
  83. data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
  84. data/test/MC/AArch64/neon-2velem.s.cs +0 -113
  85. data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
  86. data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
  87. data/test/MC/AArch64/neon-across.s.cs +0 -40
  88. data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
  89. data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
  90. data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
  91. data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
  92. data/test/MC/AArch64/neon-crypto.s.cs +0 -15
  93. data/test/MC/AArch64/neon-extract.s.cs +0 -3
  94. data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
  95. data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
  96. data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
  97. data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
  98. data/test/MC/AArch64/neon-max-min.s.cs +0 -37
  99. data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
  100. data/test/MC/AArch64/neon-mov.s.cs +0 -74
  101. data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
  102. data/test/MC/AArch64/neon-perm.s.cs +0 -43
  103. data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
  104. data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
  105. data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
  106. data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
  107. data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
  108. data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
  109. data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
  110. data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
  111. data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
  112. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
  113. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
  114. data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
  115. data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
  116. data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
  117. data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
  118. data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
  119. data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
  120. data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
  121. data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
  122. data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
  123. data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
  124. data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
  125. data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
  126. data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
  127. data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
  128. data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
  129. data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
  130. data/test/MC/AArch64/neon-shift.s.cs +0 -22
  131. data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
  132. data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
  133. data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
  134. data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
  135. data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
  136. data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
  137. data/test/MC/AArch64/neon-tbl.s.cs +0 -21
  138. data/test/MC/AArch64/trace-regs.s.cs +0 -383
  139. data/test/MC/ARM/arm-aliases.s.cs +0 -7
  140. data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
  141. data/test/MC/ARM/arm-it-block.s.cs +0 -2
  142. data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
  143. data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
  144. data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
  145. data/test/MC/ARM/arm-trustzone.s.cs +0 -3
  146. data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
  147. data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
  148. data/test/MC/ARM/arm_instructions.s.cs +0 -25
  149. data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
  150. data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
  151. data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
  152. data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
  153. data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
  154. data/test/MC/ARM/crc32-thumb.s.cs +0 -7
  155. data/test/MC/ARM/crc32.s.cs +0 -7
  156. data/test/MC/ARM/dot-req.s.cs +0 -3
  157. data/test/MC/ARM/fp-armv8.s.cs +0 -52
  158. data/test/MC/ARM/idiv-thumb.s.cs +0 -3
  159. data/test/MC/ARM/idiv.s.cs +0 -3
  160. data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
  161. data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
  162. data/test/MC/ARM/mode-switch.s.cs +0 -7
  163. data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
  164. data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
  165. data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
  166. data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
  167. data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
  168. data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
  169. data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
  170. data/test/MC/ARM/neon-crypto.s.cs +0 -16
  171. data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
  172. data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
  173. data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
  174. data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
  175. data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
  176. data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
  177. data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
  178. data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
  179. data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
  180. data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
  181. data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
  182. data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
  183. data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
  184. data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
  185. data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
  186. data/test/MC/ARM/neon-v8.s.cs +0 -38
  187. data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
  188. data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
  189. data/test/MC/ARM/neon-vswp.s.cs +0 -3
  190. data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
  191. data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
  192. data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
  193. data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
  194. data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
  195. data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
  196. data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
  197. data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
  198. data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
  199. data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
  200. data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
  201. data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
  202. data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
  203. data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
  204. data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
  205. data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
  206. data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
  207. data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
  208. data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
  209. data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
  210. data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
  211. data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
  212. data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
  213. data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
  214. data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
  215. data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
  216. data/test/MC/ARM/thumb-hints.s.cs +0 -12
  217. data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
  218. data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
  219. data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
  220. data/test/MC/ARM/thumb.s.cs +0 -19
  221. data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
  222. data/test/MC/ARM/thumb2-branches.s.cs +0 -85
  223. data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
  224. data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
  225. data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
  226. data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
  227. data/test/MC/ARM/vfp4.s.cs +0 -13
  228. data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
  229. data/test/MC/ARM/vpush-vpop.s.cs +0 -9
  230. data/test/MC/Mips/hilo-addressing.s.cs +0 -4
  231. data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
  232. data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
  233. data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
  234. data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
  235. data/test/MC/Mips/micromips-expansions.s.cs +0 -20
  236. data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
  237. data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
  238. data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
  239. data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
  240. data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
  241. data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
  242. data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
  243. data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
  244. data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
  245. data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
  246. data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
  247. data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
  248. data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
  249. data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
  250. data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
  251. data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
  252. data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
  253. data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
  254. data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
  255. data/test/MC/Mips/mips-expansions.s.cs +0 -20
  256. data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
  257. data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
  258. data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
  259. data/test/MC/Mips/mips-register-names.s.cs +0 -33
  260. data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
  261. data/test/MC/Mips/mips64-instructions.s.cs +0 -3
  262. data/test/MC/Mips/mips64-register-names.s.cs +0 -33
  263. data/test/MC/Mips/mips_directives.s.cs +0 -12
  264. data/test/MC/Mips/nabi-regs.s.cs +0 -12
  265. data/test/MC/Mips/set-at-directive.s.cs +0 -6
  266. data/test/MC/Mips/test_2r.s.cs +0 -16
  267. data/test/MC/Mips/test_2rf.s.cs +0 -33
  268. data/test/MC/Mips/test_3r.s.cs +0 -243
  269. data/test/MC/Mips/test_3rf.s.cs +0 -83
  270. data/test/MC/Mips/test_bit.s.cs +0 -49
  271. data/test/MC/Mips/test_cbranch.s.cs +0 -11
  272. data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
  273. data/test/MC/Mips/test_elm.s.cs +0 -16
  274. data/test/MC/Mips/test_elm_insert.s.cs +0 -4
  275. data/test/MC/Mips/test_elm_insve.s.cs +0 -5
  276. data/test/MC/Mips/test_i10.s.cs +0 -5
  277. data/test/MC/Mips/test_i5.s.cs +0 -45
  278. data/test/MC/Mips/test_i8.s.cs +0 -11
  279. data/test/MC/Mips/test_lsa.s.cs +0 -5
  280. data/test/MC/Mips/test_mi10.s.cs +0 -24
  281. data/test/MC/Mips/test_vec.s.cs +0 -8
  282. data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
  283. data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
  284. data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
  285. data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
  286. data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
  287. data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
  288. data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
  289. data/test/MC/README +0 -6
  290. data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
  291. data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
  292. data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
  293. data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
  294. data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
  295. data/test/MC/Sparc/sparc-vis.s.cs +0 -2
  296. data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
  297. data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
  298. data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
  299. data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
  300. data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
  301. data/test/MC/SystemZ/insn-good.s.cs +0 -2265
  302. data/test/MC/SystemZ/regs-good.s.cs +0 -45
  303. data/test/MC/X86/3DNow.s.cs +0 -29
  304. data/test/MC/X86/address-size.s.cs +0 -5
  305. data/test/MC/X86/avx512-encodings.s.cs +0 -12
  306. data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
  307. data/test/MC/X86/x86-32-avx.s.cs +0 -833
  308. data/test/MC/X86/x86-32-fma3.s.cs +0 -169
  309. data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
  310. data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
  311. data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
  312. data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
  313. data/test/MC/X86/x86_64-encoding.s.cs +0 -59
  314. data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
  315. data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
  316. data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
  317. data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
  318. data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
  319. data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
  320. data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
  321. data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
  322. data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
  323. data/test/README +0 -6
  324. data/test/test.rb +0 -205
  325. data/test/test.rb.SPEC +0 -235
  326. data/test/test_arm.rb +0 -202
  327. data/test/test_arm.rb.SPEC +0 -275
  328. data/test/test_arm64.rb +0 -150
  329. data/test/test_arm64.rb.SPEC +0 -116
  330. data/test/test_detail.rb +0 -228
  331. data/test/test_detail.rb.SPEC +0 -322
  332. data/test/test_exhaustive.rb +0 -80
  333. data/test/test_mips.rb +0 -118
  334. data/test/test_mips.rb.SPEC +0 -91
  335. data/test/test_ppc.rb +0 -137
  336. data/test/test_ppc.rb.SPEC +0 -84
  337. data/test/test_sanity.rb +0 -83
  338. data/test/test_skipdata.rb +0 -111
  339. data/test/test_skipdata.rb.SPEC +0 -58
  340. data/test/test_sparc.rb +0 -113
  341. data/test/test_sparc.rb.SPEC +0 -116
  342. data/test/test_sysz.rb +0 -111
  343. data/test/test_sysz.rb.SPEC +0 -61
  344. data/test/test_x86.rb +0 -189
  345. data/test/test_x86.rb.SPEC +0 -579
  346. data/test/test_xcore.rb +0 -100
  347. data/test/test_xcore.rb.SPEC +0 -75
data/test/MC/ARM/arm-arithmetic-aliases.s.cs DELETED
@@ -1,50 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x06,0x20,0x42,0xe2 = sub r2, r2, #6
3
- 0x06,0x20,0x42,0xe2 = sub r2, r2, #6
4
- 0x03,0x20,0x42,0xe0 = sub r2, r2, r3
5
- 0x03,0x20,0x42,0xe0 = sub r2, r2, r3
6
- 0x06,0x20,0x82,0xe2 = add r2, r2, #6
7
- 0x06,0x20,0x82,0xe2 = add r2, r2, #6
8
- 0x03,0x20,0x82,0xe0 = add r2, r2, r3
9
- 0x03,0x20,0x82,0xe0 = add r2, r2, r3
10
- 0x06,0x20,0x02,0xe2 = and r2, r2, #6
11
- 0x06,0x20,0x02,0xe2 = and r2, r2, #6
12
- 0x03,0x20,0x02,0xe0 = and r2, r2, r3
13
- 0x03,0x20,0x02,0xe0 = and r2, r2, r3
14
- 0x06,0x20,0x82,0xe3 = orr r2, r2, #6
15
- 0x06,0x20,0x82,0xe3 = orr r2, r2, #6
16
- 0x03,0x20,0x82,0xe1 = orr r2, r2, r3
17
- 0x03,0x20,0x82,0xe1 = orr r2, r2, r3
18
- 0x06,0x20,0x22,0xe2 = eor r2, r2, #6
19
- 0x06,0x20,0x22,0xe2 = eor r2, r2, #6
20
- 0x03,0x20,0x22,0xe0 = eor r2, r2, r3
21
- 0x03,0x20,0x22,0xe0 = eor r2, r2, r3
22
- 0x06,0x20,0xc2,0xe3 = bic r2, r2, #6
23
- 0x06,0x20,0xc2,0xe3 = bic r2, r2, #6
24
- 0x03,0x20,0xc2,0xe1 = bic r2, r2, r3
25
- 0x03,0x20,0xc2,0xe1 = bic r2, r2, r3
26
- 0x06,0x20,0x52,0x02 = subseq r2, r2, #6
27
- 0x06,0x20,0x52,0x02 = subseq r2, r2, #6
28
- 0x03,0x20,0x52,0x00 = subseq r2, r2, r3
29
- 0x03,0x20,0x52,0x00 = subseq r2, r2, r3
30
- 0x06,0x20,0x92,0x02 = addseq r2, r2, #6
31
- 0x06,0x20,0x92,0x02 = addseq r2, r2, #6
32
- 0x03,0x20,0x92,0x00 = addseq r2, r2, r3
33
- 0x03,0x20,0x92,0x00 = addseq r2, r2, r3
34
- 0x06,0x20,0x12,0x02 = andseq r2, r2, #6
35
- 0x06,0x20,0x12,0x02 = andseq r2, r2, #6
36
- 0x03,0x20,0x12,0x00 = andseq r2, r2, r3
37
- 0x03,0x20,0x12,0x00 = andseq r2, r2, r3
38
- 0x06,0x20,0x92,0x03 = orrseq r2, r2, #6
39
- 0x06,0x20,0x92,0x03 = orrseq r2, r2, #6
40
- 0x03,0x20,0x92,0x01 = orrseq r2, r2, r3
41
- 0x03,0x20,0x92,0x01 = orrseq r2, r2, r3
42
- 0x06,0x20,0x32,0x02 = eorseq r2, r2, #6
43
- 0x06,0x20,0x32,0x02 = eorseq r2, r2, #6
44
- 0x03,0x20,0x32,0x00 = eorseq r2, r2, r3
45
- 0x03,0x20,0x32,0x00 = eorseq r2, r2, r3
46
- 0x06,0x20,0xd2,0x03 = bicseq r2, r2, #6
47
- 0x06,0x20,0xd2,0x03 = bicseq r2, r2, #6
48
- 0x03,0x20,0xd2,0x01 = bicseq r2, r2, r3
49
- 0x03,0x20,0xd2,0x01 = bicseq r2, r2, r3
50
- 0x7b,0x00,0x8f,0xe2 = add r0, pc, #123
data/test/MC/ARM/arm-it-block.s.cs DELETED
@@ -1,2 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x03,0x20,0xa0,0x01 = moveq r2, r3
data/test/MC/ARM/arm-memory-instructions.s.cs DELETED
@@ -1,138 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x00,0x50,0x97,0xe5 = ldr r5, [r7]
3
- 0x3f,0x60,0x93,0xe5 = ldr r6, [r3, #63]
4
- 0xff,0x2f,0xb4,0xe5 = ldr r2, [r4, #4095]!
5
- 0x1e,0x10,0x92,0xe4 = ldr r1, [r2], #30
6
- 0x1e,0x30,0x11,0xe4 = ldr r3, [r1], #-30
7
- 0x00,0x90,0x12,0xe4 = ldr r9, [r2], #-0
8
- 0x01,0x30,0x98,0xe7 = ldr r3, [r8, r1]
9
- 0x03,0x20,0x15,0xe7 = ldr r2, [r5, -r3]
10
- 0x09,0x10,0xb5,0xe7 = ldr r1, [r5, r9]!
11
- 0x08,0x60,0x37,0xe7 = ldr r6, [r7, -r8]!
12
- 0xa2,0x11,0xb0,0xe7 = ldr r1, [r0, r2, lsr #3]!
13
- 0x02,0x50,0x99,0xe6 = ldr r5, [r9], r2
14
- 0x06,0x40,0x13,0xe6 = ldr r4, [r3], -r6
15
- 0x82,0x37,0x18,0xe7 = ldr r3, [r8, -r2, lsl #15]
16
- 0xc3,0x17,0x95,0xe6 = ldr r1, [r5], r3, asr #15
17
- 0x00,0x30,0xd8,0xe5 = ldrb r3, [r8]
18
- 0x3f,0x10,0xdd,0xe5 = ldrb r1, [sp, #63]
19
- 0xff,0x9f,0xf3,0xe5 = ldrb r9, [r3, #4095]!
20
- 0x16,0x80,0xd1,0xe4 = ldrb r8, [r1], #22
21
- 0x13,0x20,0x57,0xe4 = ldrb r2, [r7], #-19
22
- 0x05,0x90,0xd8,0xe7 = ldrb r9, [r8, r5]
23
- 0x01,0x10,0x55,0xe7 = ldrb r1, [r5, -r1]
24
- 0x02,0x30,0xf5,0xe7 = ldrb r3, [r5, r2]!
25
- 0x03,0x60,0x79,0xe7 = ldrb r6, [r9, -r3]!
26
- 0x04,0x20,0xd1,0xe6 = ldrb r2, [r1], r4
27
- 0x05,0x80,0x54,0xe6 = ldrb r8, [r4], -r5
28
- 0x81,0x77,0x5c,0xe7 = ldrb r7, [r12, -r1, lsl #15]
29
- 0xc9,0x57,0xd2,0xe6 = ldrb r5, [r2], r9, asr #15
30
- 0x04,0x30,0xf1,0xe4 = ldrbt r3, [r1], #4
31
- 0x08,0x20,0x78,0xe4 = ldrbt r2, [r8], #-8
32
- 0x06,0x80,0xf7,0xe6 = ldrbt r8, [r7], r6
33
- 0x06,0x16,0x72,0xe6 = ldrbt r1, [r2], -r6, lsl #12
34
- 0xd0,0x20,0xc5,0xe1 = ldrd r2, r3, [r5]
35
- 0xdf,0x60,0xc2,0xe1 = ldrd r6, r7, [r2, #15]
36
- 0xd0,0x02,0xe9,0xe1 = ldrd r0, r1, [r9, #32]!
37
- 0xd8,0x60,0xc1,0xe0 = ldrd r6, r7, [r1], #8
38
- 0xd0,0x00,0xc8,0xe0 = ldrd r0, r1, [r8], #0
39
- 0xd0,0x00,0xc8,0xe0 = ldrd r0, r1, [r8], #0
40
- 0xd0,0x00,0x48,0xe0 = ldrd r0, r1, [r8], #-0
41
- 0xd3,0x40,0x81,0xe1 = ldrd r4, r5, [r1, r3]
42
- 0xd2,0x40,0xa7,0xe1 = ldrd r4, r5, [r7, r2]!
43
- 0xdc,0x00,0x88,0xe0 = ldrd r0, r1, [r8], r12
44
- 0xdc,0x00,0x08,0xe0 = ldrd r0, r1, [r8], -r12
45
- 0xb0,0x30,0xd4,0xe1 = ldrh r3, [r4]
46
- 0xb4,0x20,0xd7,0xe1 = ldrh r2, [r7, #4]
47
- 0xb0,0x14,0xf8,0xe1 = ldrh r1, [r8, #64]!
48
- 0xb4,0xc0,0xdd,0xe0 = ldrh r12, [sp], #4
49
- 0xb4,0x60,0x95,0xe1 = ldrh r6, [r5, r4]
50
- 0xbb,0x30,0xb8,0xe1 = ldrh r3, [r8, r11]!
51
- 0xb1,0x10,0x32,0xe1 = ldrh r1, [r2, -r1]!
52
- 0xb2,0x90,0x97,0xe0 = ldrh r9, [r7], r2
53
- 0xb2,0x40,0x13,0xe0 = ldrh r4, [r3], -r2
54
- 0xb0,0x98,0xf7,0xe0 = ldrht r9, [r7], #128
55
- 0xbb,0x44,0x73,0xe0 = ldrht r4, [r3], #-75
56
- 0xb2,0x90,0xb7,0xe0 = ldrht r9, [r7], r2
57
- 0xb2,0x40,0x33,0xe0 = ldrht r4, [r3], -r2
58
- 0xd0,0x30,0xd4,0xe1 = ldrsb r3, [r4]
59
- 0xd1,0x21,0xd7,0xe1 = ldrsb r2, [r7, #17]
60
- 0xdf,0x1f,0xf8,0xe1 = ldrsb r1, [r8, #255]!
61
- 0xd9,0xc0,0xdd,0xe0 = ldrsb r12, [sp], #9
62
- 0xd4,0x60,0x95,0xe1 = ldrsb r6, [r5, r4]
63
- 0xdb,0x30,0xb8,0xe1 = ldrsb r3, [r8, r11]!
64
- 0xd1,0x10,0x32,0xe1 = ldrsb r1, [r2, -r1]!
65
- 0xd2,0x90,0x97,0xe0 = ldrsb r9, [r7], r2
66
- 0xd2,0x40,0x13,0xe0 = ldrsb r4, [r3], -r2
67
- 0xd1,0x50,0xf6,0xe0 = ldrsbt r5, [r6], #1
68
- 0xdc,0x30,0x78,0xe0 = ldrsbt r3, [r8], #-12
69
- 0xd5,0x80,0xb9,0xe0 = ldrsbt r8, [r9], r5
70
- 0xd4,0x20,0x31,0xe0 = ldrsbt r2, [r1], -r4
71
- 0xf0,0x50,0xd9,0xe1 = ldrsh r5, [r9]
72
- 0xf7,0x40,0xd5,0xe1 = ldrsh r4, [r5, #7]
73
- 0xf7,0x33,0xf6,0xe1 = ldrsh r3, [r6, #55]!
74
- 0xf9,0x20,0x57,0xe0 = ldrsh r2, [r7], #-9
75
- 0xf5,0x30,0x91,0xe1 = ldrsh r3, [r1, r5]
76
- 0xf1,0x40,0xb6,0xe1 = ldrsh r4, [r6, r1]!
77
- 0xf6,0x50,0x33,0xe1 = ldrsh r5, [r3, -r6]!
78
- 0xf8,0x60,0x99,0xe0 = ldrsh r6, [r9], r8
79
- 0xf3,0x70,0x18,0xe0 = ldrsh r7, [r8], -r3
80
- 0xf1,0x50,0xf6,0xe0 = ldrsht r5, [r6], #1
81
- 0xfc,0x30,0x78,0xe0 = ldrsht r3, [r8], #-12
82
- 0xf5,0x80,0xb9,0xe0 = ldrsht r8, [r9], r5
83
- 0xf4,0x20,0x31,0xe0 = ldrsht r2, [r1], -r4
84
- 0x00,0x80,0x8c,0xe5 = str r8, [r12]
85
- 0x0c,0x70,0x81,0xe5 = str r7, [r1, #12]
86
- 0x28,0x30,0xa5,0xe5 = str r3, [r5, #40]!
87
- 0xff,0x9f,0x8d,0xe4 = str r9, [sp], #4095
88
- 0x80,0x10,0x07,0xe4 = str r1, [r7], #-128
89
- 0x00,0x10,0x00,0xe4 = str r1, [r0], #-0
90
- 0x03,0x90,0x86,0xe7 = str r9, [r6, r3]
91
- 0x02,0x80,0x00,0xe7 = str r8, [r0, -r2]
92
- 0x06,0x70,0xa1,0xe7 = str r7, [r1, r6]!
93
- 0x01,0x60,0x2d,0xe7 = str r6, [sp, -r1]!
94
- 0x09,0x50,0x83,0xe6 = str r5, [r3], r9
95
- 0x05,0x40,0x02,0xe6 = str r4, [r2], -r5
96
- 0x02,0x31,0x04,0xe7 = str r3, [r4, -r2, lsl #2]
97
- 0x43,0x2c,0x87,0xe6 = str r2, [r7], r3, asr #24
98
- 0x00,0x90,0xc2,0xe5 = strb r9, [r2]
99
- 0x03,0x70,0xc1,0xe5 = strb r7, [r1, #3]
100
- 0x95,0x61,0xe4,0xe5 = strb r6, [r4, #405]!
101
- 0x48,0x50,0xc7,0xe4 = strb r5, [r7], #72
102
- 0x01,0x10,0x4d,0xe4 = strb r1, [sp], #-1
103
- 0x09,0x10,0xc2,0xe7 = strb r1, [r2, r9]
104
- 0x08,0x20,0x43,0xe7 = strb r2, [r3, -r8]
105
- 0x07,0x30,0xe4,0xe7 = strb r3, [r4, r7]!
106
- 0x06,0x40,0x65,0xe7 = strb r4, [r5, -r6]!
107
- 0x05,0x50,0xc6,0xe6 = strb r5, [r6], r5
108
- 0x04,0x60,0x42,0xe6 = strb r6, [r2], -r4
109
- 0x83,0x72,0x4c,0xe7 = strb r7, [r12, -r3, lsl #5]
110
- 0x42,0xd6,0xc7,0xe6 = strb sp, [r7], r2, asr #12
111
- 0x0c,0x60,0xe2,0xe4 = strbt r6, [r2], #12
112
- 0x0d,0x50,0x66,0xe4 = strbt r5, [r6], #-13
113
- 0x05,0x40,0xe9,0xe6 = strbt r4, [r9], r5
114
- 0x82,0x31,0x68,0xe6 = strbt r3, [r8], -r2, lsl #3
115
- 0xf0,0x10,0xc4,0xe1 = strd r1, r2, [r4]
116
- 0xf1,0x20,0xc6,0xe1 = strd r2, r3, [r6, #1]
117
- 0xf6,0x31,0xe7,0xe1 = strd r3, r4, [r7, #22]!
118
- 0xf7,0x40,0xc8,0xe0 = strd r4, r5, [r8], #7
119
- 0xf0,0x50,0xcd,0xe0 = strd r5, r6, [sp], #0
120
- 0xf0,0x60,0xce,0xe0 = strd r6, r7, [lr], #0
121
- 0xf0,0x70,0x49,0xe0 = strd r7, r8, [r9], #-0
122
- 0xf1,0x80,0x84,0xe1 = strd r8, r9, [r4, r1]
123
- 0xf9,0x70,0xa3,0xe1 = strd r7, r8, [r3, r9]!
124
- 0xf8,0x60,0x85,0xe0 = strd r6, r7, [r5], r8
125
- 0xfa,0x50,0x0c,0xe0 = strd r5, r6, [r12], -r10
126
- 0xb0,0x30,0xc4,0xe1 = strh r3, [r4]
127
- 0xb4,0x20,0xc7,0xe1 = strh r2, [r7, #4]
128
- 0xb0,0x14,0xe8,0xe1 = strh r1, [r8, #64]!
129
- 0xb4,0xc0,0xcd,0xe0 = strh r12, [sp], #4
130
- 0xb4,0x60,0x85,0xe1 = strh r6, [r5, r4]
131
- 0xbb,0x30,0xa8,0xe1 = strh r3, [r8, r11]!
132
- 0xb1,0x10,0x22,0xe1 = strh r1, [r2, -r1]!
133
- 0xb2,0x90,0x87,0xe0 = strh r9, [r7], r2
134
- 0xb2,0x40,0x03,0xe0 = strh r4, [r3], -r2
135
- 0xbc,0x24,0xe5,0xe0 = strht r2, [r5], #76
136
- 0xb9,0x81,0x61,0xe0 = strht r8, [r1], #-25
137
- 0xb4,0x50,0xa3,0xe0 = strht r5, [r3], r4
138
- 0xb0,0x60,0x28,0xe0 = strht r6, [r8], -r0
data/test/MC/ARM/arm-shift-encoding.s.cs DELETED
@@ -1,50 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0]
3
- 0x20,0x00,0x90,0xe7 = ldr r0, [r0, r0, lsr #32]
4
- 0x20,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsr #16]
5
- 0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0]
6
- 0x00,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsl #16]
7
- 0x40,0x00,0x90,0xe7 = ldr r0, [r0, r0, asr #32]
8
- 0x40,0x08,0x90,0xe7 = ldr r0, [r0, r0, asr #16]
9
- 0x60,0x00,0x90,0xe7 = ldr r0, [r0, r0, rrx]
10
- 0x60,0x08,0x90,0xe7 = ldr r0, [r0, r0, ror #16]
11
- 0x00,0xf0,0xd0,0xf7 = pld [r0, r0]
12
- 0x20,0xf0,0xd0,0xf7 = pld [r0, r0, lsr #32]
13
- 0x20,0xf8,0xd0,0xf7 = pld [r0, r0, lsr #16]
14
- 0x00,0xf0,0xd0,0xf7 = pld [r0, r0]
15
- 0x00,0xf8,0xd0,0xf7 = pld [r0, r0, lsl #16]
16
- 0x40,0xf0,0xd0,0xf7 = pld [r0, r0, asr #32]
17
- 0x40,0xf8,0xd0,0xf7 = pld [r0, r0, asr #16]
18
- 0x60,0xf0,0xd0,0xf7 = pld [r0, r0, rrx]
19
- 0x60,0xf8,0xd0,0xf7 = pld [r0, r0, ror #16]
20
- 0x00,0x00,0x80,0xe7 = str r0, [r0, r0]
21
- 0x20,0x00,0x80,0xe7 = str r0, [r0, r0, lsr #32]
22
- 0x20,0x08,0x80,0xe7 = str r0, [r0, r0, lsr #16]
23
- 0x00,0x00,0x80,0xe7 = str r0, [r0, r0]
24
- 0x00,0x08,0x80,0xe7 = str r0, [r0, r0, lsl #16]
25
- 0x40,0x00,0x80,0xe7 = str r0, [r0, r0, asr #32]
26
- 0x40,0x08,0x80,0xe7 = str r0, [r0, r0, asr #16]
27
- 0x60,0x00,0x80,0xe7 = str r0, [r0, r0, rrx]
28
- 0x60,0x08,0x80,0xe7 = str r0, [r0, r0, ror #16]
29
- 0x62,0x00,0x91,0xe6 = ldr r0, [r1], r2, rrx
30
- 0x05,0x30,0x94,0xe6 = ldr r3, [r4], r5
31
- 0x08,0x60,0x87,0xe6 = str r6, [r7], r8
32
- 0x0b,0x90,0x8a,0xe6 = str r9, [r10], r11
33
- 0x0f,0xd0,0xae,0xe0 = adc sp, lr, pc
34
- 0x29,0x10,0xa8,0xe0 = adc r1, r8, r9, lsr #32
35
- 0x2f,0x28,0xa7,0xe0 = adc r2, r7, pc, lsr #16
36
- 0x0a,0x30,0xa6,0xe0 = adc r3, r6, r10
37
- 0x0e,0x48,0xa5,0xe0 = adc r4, r5, lr, lsl #16
38
- 0x4b,0x50,0xa4,0xe0 = adc r5, r4, r11, asr #32
39
- 0x4d,0x68,0xa3,0xe0 = adc r6, r3, sp, asr #16
40
- 0x6c,0x70,0xa2,0xe0 = adc r7, r2, r12, rrx
41
- 0x60,0x88,0xa1,0xe0 = adc r8, r1, r0, ror #16
42
- 0x0e,0x00,0x5d,0xe1 = cmp sp, lr
43
- 0x28,0x00,0x51,0xe1 = cmp r1, r8, lsr #32
44
- 0x27,0x08,0x52,0xe1 = cmp r2, r7, lsr #16
45
- 0x06,0x00,0x53,0xe1 = cmp r3, r6
46
- 0x05,0x08,0x54,0xe1 = cmp r4, r5, lsl #16
47
- 0x44,0x00,0x55,0xe1 = cmp r5, r4, asr #32
48
- 0x43,0x08,0x56,0xe1 = cmp r6, r3, asr #16
49
- 0x62,0x00,0x57,0xe1 = cmp r7, r2, rrx
50
- 0x61,0x08,0x58,0xe1 = cmp r8, r1, ror #16
data/test/MC/ARM/arm-thumb-trustzone.s.cs DELETED
@@ -1,3 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_THUMB, None
2
- 0xff,0xf7,0x00,0x80 = smc #15
3
- 0x0c,0xbf = ite eq
data/test/MC/ARM/arm-trustzone.s.cs DELETED
@@ -1,3 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x7f,0x00,0x60,0xe1 = smc #15
3
- 0x70,0x00,0x60,0x01 = smceq #0
data/test/MC/ARM/arm_addrmode2.s.cs DELETED
@@ -1,15 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x02,0x10,0xb0,0xe6 = ldrt r1, [r0], r2
3
- 0xa2,0x11,0xb0,0xe6 = ldrt r1, [r0], r2, lsr #3
4
- 0x04,0x10,0xb0,0xe4 = ldrt r1, [r0], #4
5
- 0x02,0x10,0xf0,0xe6 = ldrbt r1, [r0], r2
6
- 0xa2,0x11,0xf0,0xe6 = ldrbt r1, [r0], r2, lsr #3
7
- 0x04,0x10,0xf0,0xe4 = ldrbt r1, [r0], #4
8
- 0x02,0x10,0xa0,0xe6 = strt r1, [r0], r2
9
- 0xa2,0x11,0xa0,0xe6 = strt r1, [r0], r2, lsr #3
10
- 0x04,0x10,0xa0,0xe4 = strt r1, [r0], #4
11
- 0x02,0x10,0xe0,0xe6 = strbt r1, [r0], r2
12
- 0xa2,0x11,0xe0,0xe6 = strbt r1, [r0], r2, lsr #3
13
- 0x04,0x10,0xe0,0xe4 = strbt r1, [r0], #4
14
- 0xa2,0x11,0xb0,0xe7 = ldr r1, [r0, r2, lsr #3]!
15
- 0xa2,0x11,0xf0,0xe7 = ldrb r1, [r0, r2, lsr #3]!
data/test/MC/ARM/arm_addrmode3.s.cs DELETED
@@ -1,9 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0xd2,0x10,0xb0,0xe0 = ldrsbt r1, [r0], r2
3
- 0xd4,0x10,0xf0,0xe0 = ldrsbt r1, [r0], #4
4
- 0xf2,0x10,0xb0,0xe0 = ldrsht r1, [r0], r2
5
- 0xf4,0x10,0xf0,0xe0 = ldrsht r1, [r0], #4
6
- 0xb2,0x10,0xb0,0xe0 = ldrht r1, [r0], r2
7
- 0xb4,0x10,0xf0,0xe0 = ldrht r1, [r0], #4
8
- 0xb2,0x10,0xa0,0xe0 = strht r1, [r0], r2
9
- 0xb4,0x10,0xe0,0xe0 = strht r1, [r0], #4
data/test/MC/ARM/arm_instructions.s.cs DELETED
@@ -1,25 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x1e,0xff,0x2f,0xe1 = bx lr
3
- 0xa0,0x0d,0xe1,0xf2 = vqdmull.s32 q8, d17, d16
4
- 0x03,0x10,0x02,0xe0 = and r1, r2, r3
5
- 0x03,0x10,0x12,0xe0 = ands r1, r2, r3
6
- 0x03,0x10,0x22,0xe0 = eor r1, r2, r3
7
- 0x03,0x10,0x32,0xe0 = eors r1, r2, r3
8
- 0x03,0x10,0x42,0xe0 = sub r1, r2, r3
9
- 0x03,0x10,0x52,0xe0 = subs r1, r2, r3
10
- 0x03,0x10,0x82,0xe0 = add r1, r2, r3
11
- 0x03,0x10,0x92,0xe0 = adds r1, r2, r3
12
- 0x03,0x10,0xa2,0xe0 = adc r1, r2, r3
13
- 0x03,0x10,0xc2,0xe1 = bic r1, r2, r3
14
- 0x03,0x10,0xd2,0xe1 = bics r1, r2, r3
15
- 0x02,0x10,0xa0,0xe1 = mov r1, r2
16
- 0x02,0x10,0xe0,0xe1 = mvn r1, r2
17
- 0x02,0x10,0xf0,0xe1 = mvns r1, r2
18
- 0x90,0x02,0xcb,0xe7 = bfi r0, r0, #5, #7
19
- 0x7a,0x00,0x20,0xe1 = bkpt #10
20
- 0x81,0x17,0x11,0xee = cdp p7, #1, c1, c1, c1, #4
21
- 0x81,0x17,0x11,0xfe = cdp2 p7, #1, c1, c1, c1, #4
22
- 0x13,0x14,0x82,0xe0 = add r1, r2, r3, lsl r4
23
- 0x30,0x0f,0xa6,0xe6 = ssat16 r0, #7, r0
24
- 0x00,0x00,0x0a,0xf1 = cpsie none, #0
25
- 0xb0,0x30,0x42,0xe1 = strh r3, [r2, #-0]
data/test/MC/ARM/basic-arm-instructions-v8.s.cs DELETED
@@ -1,10 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None
2
- 0x59,0xf0,0x7f,0xf5 = dmb ishld
3
- 0x51,0xf0,0x7f,0xf5 = dmb oshld
4
- 0x55,0xf0,0x7f,0xf5 = dmb nshld
5
- 0x5d,0xf0,0x7f,0xf5 = dmb ld
6
- 0x49,0xf0,0x7f,0xf5 = dsb ishld
7
- 0x41,0xf0,0x7f,0xf5 = dsb oshld
8
- 0x45,0xf0,0x7f,0xf5 = dsb nshld
9
- 0x4d,0xf0,0x7f,0xf5 = dsb ld
10
- 0x05,0xf0,0x20,0xe3 = sevl