crabstone 3.0.3 → 4.0.4

data/lib/arch/arm64.rb

@@ -1,167 +0,0 @@
-# Library by Nguyen Anh Quynh
-# Original binding by Nguyen Anh Quynh and Tan Sheng Di
-# Additional binding work by Ben Nagy
-# (c) 2013 COSEINC. All Rights Reserved.
-
-require 'ffi'
-
-require_relative 'arm64_const'
-
-module Crabstone
-    module ARM64
-
-
-        class OperandShift < FFI::Struct
-            layout(
-                :type, :uint,
-                :value, :uint
-            )
-        end
-
-        class MemoryOperand < FFI::Struct
-            layout(
-                :base, :uint,
-                :index, :uint,
-                :disp, :int32
-            )
-        end
-
-        class OperandValue < FFI::Union
-            layout(
-                :reg, :uint,
-                :imm, :int64,
-                :fp, :double,
-                :mem, MemoryOperand,
-                :pstate, :int,
-                :sys, :uint,
-                :prefetch, :int,
-                :barrier, :int
-            )
-        end
-
-        class Operand < FFI::Struct
-
-            layout(
-                :vector_index, :int,
-                :vas, :int,
-                :vess, :int,
-                :shift, OperandShift,
-                :ext, :uint,
-                :type, :uint,
-                :value, OperandValue
-            )
-
-            def value
-                case self[:type]
-                when *[OP_REG, OP_REG_MRS, OP_REG_MSR]  # Register operand.
-                    self[:value][:reg]
-                when *[OP_IMM, OP_CIMM]                 # Immediate operand.
-                    self[:value][:imm]
-                when OP_FP                              # Floating-Point immediate operand.
-                    self[:value][:fp]
-                when OP_MEM                             # Memory operand
-                    self[:value][:mem]
-                when OP_PSTATE                          # PState operand.
-                    self[:value][:pstate]
-                when OP_SYS                             # SYS operand for IC/DC/AT/TLBI instructions.
-                    self[:value][:sys]
-                when OP_PREFETCH                        # Prefetch operand (PRFM).
-                    self[:value][:prefetch]
-                when OP_BARRIER                         # Memory barrier operand (ISB/DMB/DSB instructions).
-                    self[:value][:barrier]
-                else
-                    nil
-                end
-            end
-
-            def shift_type
-                self[:shift][:type]
-            end
-
-            def shift_value
-                self[:shift][:value]
-            end
-
-            def shift?
-                self[:shift][:type] != SFT_INVALID
-            end
-
-            def ext?
-                self[:ext] != EXT_INVALID
-            end
-
-            def reg?
-                self[:type] == OP_REG
-            end
-
-            def imm?
-                self[:type] == OP_IMM
-            end
-
-            def cimm?
-                self[:type] == OP_CIMM
-            end
-
-            def mem?
-                self[:type] == OP_MEM
-            end
-
-            def fp?
-                self[:type] == OP_FP
-            end
-
-            def pstate?
-                self[:type] == OP_PSTATE
-            end
-
-            def msr?
-                self[:type] == OP_REG_MSR
-            end
-
-            def mrs?
-                self[:type] == OP_REG_MRS
-            end
-
-            def barrier?
-                self[:type] == OP_BARRIER
-            end
-
-            def prefetch?
-                self[:type] == OP_PREFETCH
-            end
-
-            def valid?
-                [
-                    OP_INVALID,
-                    OP_REG,
-                    OP_CIMM,
-                    OP_IMM,
-                    OP_FP,
-                    OP_MEM,
-                    OP_REG_MRS,
-                    OP_REG_MSR,
-                    OP_PSTATE,
-                    OP_SYS,
-                    OP_PREFETCH,
-                    OP_BARRIER
-                ].include? self[:type]
-            end
-
-        end
-
-        class Instruction < FFI::Struct
-            layout(
-                :cc, :uint,
-                :update_flags, :bool,
-                :writeback, :bool,
-                :op_count, :uint8,
-                :operands, [Operand, 8]
-            )
-
-            def operands
-                self[:operands].take_while {|op| op[:type].nonzero?}
-            end
-
-        end
-    end
-end

data/lib/arch/arm64_registers.rb

@@ -1,295 +0,0 @@
-# Library by Nguyen Anh Quynh
-# Original binding by Nguyen Anh Quynh and Tan Sheng Di
-# Additional binding work by Ben Nagy
-# (c) 2013 COSEINC. All Rights Reserved.
-
-# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
-# Command: ./genreg /Users/ben/src/capstone/bindings/python/capstone/
-# 2015-05-02T13:24:07+12:00
-
-module Crabstone
-  module ARM64
-    REG_LOOKUP = {
-      'INVALID' => 0,
-      'X29' => 1,
-      'X30' => 2,
-      'NZCV' => 3,
-      'SP' => 4,
-      'WSP' => 5,
-      'WZR' => 6,
-      'XZR' => 7,
-      'B0' => 8,
-      'B1' => 9,
-      'B2' => 10,
-      'B3' => 11,
-      'B4' => 12,
-      'B5' => 13,
-      'B6' => 14,
-      'B7' => 15,
-      'B8' => 16,
-      'B9' => 17,
-      'B10' => 18,
-      'B11' => 19,
-      'B12' => 20,
-      'B13' => 21,
-      'B14' => 22,
-      'B15' => 23,
-      'B16' => 24,
-      'B17' => 25,
-      'B18' => 26,
-      'B19' => 27,
-      'B20' => 28,
-      'B21' => 29,
-      'B22' => 30,
-      'B23' => 31,
-      'B24' => 32,
-      'B25' => 33,
-      'B26' => 34,
-      'B27' => 35,
-      'B28' => 36,
-      'B29' => 37,
-      'B30' => 38,
-      'B31' => 39,
-      'D0' => 40,
-      'D1' => 41,
-      'D2' => 42,
-      'D3' => 43,
-      'D4' => 44,
-      'D5' => 45,
-      'D6' => 46,
-      'D7' => 47,
-      'D8' => 48,
-      'D9' => 49,
-      'D10' => 50,
-      'D11' => 51,
-      'D12' => 52,
-      'D13' => 53,
-      'D14' => 54,
-      'D15' => 55,
-      'D16' => 56,
-      'D17' => 57,
-      'D18' => 58,
-      'D19' => 59,
-      'D20' => 60,
-      'D21' => 61,
-      'D22' => 62,
-      'D23' => 63,
-      'D24' => 64,
-      'D25' => 65,
-      'D26' => 66,
-      'D27' => 67,
-      'D28' => 68,
-      'D29' => 69,
-      'D30' => 70,
-      'D31' => 71,
-      'H0' => 72,
-      'H1' => 73,
-      'H2' => 74,
-      'H3' => 75,
-      'H4' => 76,
-      'H5' => 77,
-      'H6' => 78,
-      'H7' => 79,
-      'H8' => 80,
-      'H9' => 81,
-      'H10' => 82,
-      'H11' => 83,
-      'H12' => 84,
-      'H13' => 85,
-      'H14' => 86,
-      'H15' => 87,
-      'H16' => 88,
-      'H17' => 89,
-      'H18' => 90,
-      'H19' => 91,
-      'H20' => 92,
-      'H21' => 93,
-      'H22' => 94,
-      'H23' => 95,
-      'H24' => 96,
-      'H25' => 97,
-      'H26' => 98,
-      'H27' => 99,
-      'H28' => 100,
-      'H29' => 101,
-      'H30' => 102,
-      'H31' => 103,
-      'Q0' => 104,
-      'Q1' => 105,
-      'Q2' => 106,
-      'Q3' => 107,
-      'Q4' => 108,
-      'Q5' => 109,
-      'Q6' => 110,
-      'Q7' => 111,
-      'Q8' => 112,
-      'Q9' => 113,
-      'Q10' => 114,
-      'Q11' => 115,
-      'Q12' => 116,
-      'Q13' => 117,
-      'Q14' => 118,
-      'Q15' => 119,
-      'Q16' => 120,
-      'Q17' => 121,
-      'Q18' => 122,
-      'Q19' => 123,
-      'Q20' => 124,
-      'Q21' => 125,
-      'Q22' => 126,
-      'Q23' => 127,
-      'Q24' => 128,
-      'Q25' => 129,
-      'Q26' => 130,
-      'Q27' => 131,
-      'Q28' => 132,
-      'Q29' => 133,
-      'Q30' => 134,
-      'Q31' => 135,
-      'S0' => 136,
-      'S1' => 137,
-      'S2' => 138,
-      'S3' => 139,
-      'S4' => 140,
-      'S5' => 141,
-      'S6' => 142,
-      'S7' => 143,
-      'S8' => 144,
-      'S9' => 145,
-      'S10' => 146,
-      'S11' => 147,
-      'S12' => 148,
-      'S13' => 149,
-      'S14' => 150,
-      'S15' => 151,
-      'S16' => 152,
-      'S17' => 153,
-      'S18' => 154,
-      'S19' => 155,
-      'S20' => 156,
-      'S21' => 157,
-      'S22' => 158,
-      'S23' => 159,
-      'S24' => 160,
-      'S25' => 161,
-      'S26' => 162,
-      'S27' => 163,
-      'S28' => 164,
-      'S29' => 165,
-      'S30' => 166,
-      'S31' => 167,
-      'W0' => 168,
-      'W1' => 169,
-      'W2' => 170,
-      'W3' => 171,
-      'W4' => 172,
-      'W5' => 173,
-      'W6' => 174,
-      'W7' => 175,
-      'W8' => 176,
-      'W9' => 177,
-      'W10' => 178,
-      'W11' => 179,
-      'W12' => 180,
-      'W13' => 181,
-      'W14' => 182,
-      'W15' => 183,
-      'W16' => 184,
-      'W17' => 185,
-      'W18' => 186,
-      'W19' => 187,
-      'W20' => 188,
-      'W21' => 189,
-      'W22' => 190,
-      'W23' => 191,
-      'W24' => 192,
-      'W25' => 193,
-      'W26' => 194,
-      'W27' => 195,
-      'W28' => 196,
-      'W29' => 197,
-      'W30' => 198,
-      'X0' => 199,
-      'X1' => 200,
-      'X2' => 201,
-      'X3' => 202,
-      'X4' => 203,
-      'X5' => 204,
-      'X6' => 205,
-      'X7' => 206,
-      'X8' => 207,
-      'X9' => 208,
-      'X10' => 209,
-      'X11' => 210,
-      'X12' => 211,
-      'X13' => 212,
-      'X14' => 213,
-      'X15' => 214,
-      'X16' => 215,
-      'X17' => 216,
-      'X18' => 217,
-      'X19' => 218,
-      'X20' => 219,
-      'X21' => 220,
-      'X22' => 221,
-      'X23' => 222,
-      'X24' => 223,
-      'X25' => 224,
-      'X26' => 225,
-      'X27' => 226,
-      'X28' => 227,
-      'V0' => 228,
-      'V1' => 229,
-      'V2' => 230,
-      'V3' => 231,
-      'V4' => 232,
-      'V5' => 233,
-      'V6' => 234,
-      'V7' => 235,
-      'V8' => 236,
-      'V9' => 237,
-      'V10' => 238,
-      'V11' => 239,
-      'V12' => 240,
-      'V13' => 241,
-      'V14' => 242,
-      'V15' => 243,
-      'V16' => 244,
-      'V17' => 245,
-      'V18' => 246,
-      'V19' => 247,
-      'V20' => 248,
-      'V21' => 249,
-      'V22' => 250,
-      'V23' => 251,
-      'V24' => 252,
-      'V25' => 253,
-      'V26' => 254,
-      'V27' => 255,
-      'V28' => 256,
-      'V29' => 257,
-      'V30' => 258,
-      'V31' => 259
-    }
-
-    ID_LOOKUP = REG_LOOKUP.invert
-
-    # alias registers
-    REG_LOOKUP['IP1'] = REG_LOOKUP['X16']
-    REG_LOOKUP['IP0'] = REG_LOOKUP['X17']
-    REG_LOOKUP['FP'] = REG_LOOKUP['X29']
-    REG_LOOKUP['LR'] = REG_LOOKUP['X30']
-
-    SYM_LOOKUP = Hash[REG_LOOKUP.map {|k,v| [k.downcase.to_sym,v]}]
-
-    def self.register reg
-      return reg if ID_LOOKUP[reg]
-      return SYM_LOOKUP[reg] if SYM_LOOKUP[reg]
-      if reg.respond_to? :upcase
-        return REG_LOOKUP[reg.upcase] || REG_LOOKUP['INVALID']
-      end
-      REG_LOOKUP['INVALID']
-    end
-
-  end
-end

data/lib/arch/arm_registers.rb

@@ -1,149 +0,0 @@
-# Library by Nguyen Anh Quynh
-# Original binding by Nguyen Anh Quynh and Tan Sheng Di
-# Additional binding work by Ben Nagy
-# (c) 2013 COSEINC. All Rights Reserved.
-
-# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
-# Command: ./genreg /Users/ben/src/capstone/bindings/python/capstone/
-# 2015-05-02T13:24:07+12:00
-
-module Crabstone
-  module ARM
-    REG_LOOKUP = {
-      'INVALID' => 0,
-      'APSR' => 1,
-      'APSR_NZCV' => 2,
-      'CPSR' => 3,
-      'FPEXC' => 4,
-      'FPINST' => 5,
-      'FPSCR' => 6,
-      'FPSCR_NZCV' => 7,
-      'FPSID' => 8,
-      'ITSTATE' => 9,
-      'LR' => 10,
-      'PC' => 11,
-      'SP' => 12,
-      'SPSR' => 13,
-      'D0' => 14,
-      'D1' => 15,
-      'D2' => 16,
-      'D3' => 17,
-      'D4' => 18,
-      'D5' => 19,
-      'D6' => 20,
-      'D7' => 21,
-      'D8' => 22,
-      'D9' => 23,
-      'D10' => 24,
-      'D11' => 25,
-      'D12' => 26,
-      'D13' => 27,
-      'D14' => 28,
-      'D15' => 29,
-      'D16' => 30,
-      'D17' => 31,
-      'D18' => 32,
-      'D19' => 33,
-      'D20' => 34,
-      'D21' => 35,
-      'D22' => 36,
-      'D23' => 37,
-      'D24' => 38,
-      'D25' => 39,
-      'D26' => 40,
-      'D27' => 41,
-      'D28' => 42,
-      'D29' => 43,
-      'D30' => 44,
-      'D31' => 45,
-      'FPINST2' => 46,
-      'MVFR0' => 47,
-      'MVFR1' => 48,
-      'MVFR2' => 49,
-      'Q0' => 50,
-      'Q1' => 51,
-      'Q2' => 52,
-      'Q3' => 53,
-      'Q4' => 54,
-      'Q5' => 55,
-      'Q6' => 56,
-      'Q7' => 57,
-      'Q8' => 58,
-      'Q9' => 59,
-      'Q10' => 60,
-      'Q11' => 61,
-      'Q12' => 62,
-      'Q13' => 63,
-      'Q14' => 64,
-      'Q15' => 65,
-      'R0' => 66,
-      'R1' => 67,
-      'R2' => 68,
-      'R3' => 69,
-      'R4' => 70,
-      'R5' => 71,
-      'R6' => 72,
-      'R7' => 73,
-      'R8' => 74,
-      'R9' => 75,
-      'R10' => 76,
-      'R11' => 77,
-      'R12' => 78,
-      'S0' => 79,
-      'S1' => 80,
-      'S2' => 81,
-      'S3' => 82,
-      'S4' => 83,
-      'S5' => 84,
-      'S6' => 85,
-      'S7' => 86,
-      'S8' => 87,
-      'S9' => 88,
-      'S10' => 89,
-      'S11' => 90,
-      'S12' => 91,
-      'S13' => 92,
-      'S14' => 93,
-      'S15' => 94,
-      'S16' => 95,
-      'S17' => 96,
-      'S18' => 97,
-      'S19' => 98,
-      'S20' => 99,
-      'S21' => 100,
-      'S22' => 101,
-      'S23' => 102,
-      'S24' => 103,
-      'S25' => 104,
-      'S26' => 105,
-      'S27' => 106,
-      'S28' => 107,
-      'S29' => 108,
-      'S30' => 109,
-      'S31' => 110
-    }
-
-    ID_LOOKUP = REG_LOOKUP.invert
-
-    # alias registers
-    REG_LOOKUP['R13'] = REG_LOOKUP['SP']
-    REG_LOOKUP['R14'] = REG_LOOKUP['LR']
-    REG_LOOKUP['R15'] = REG_LOOKUP['PC']
-    REG_LOOKUP['SB'] = REG_LOOKUP['R9']
-    REG_LOOKUP['SL'] = REG_LOOKUP['R10']
-    REG_LOOKUP['FP'] = REG_LOOKUP['R11']
-    REG_LOOKUP['IP'] = REG_LOOKUP['R12']
-
-    SYM_LOOKUP = Hash[REG_LOOKUP.map {|k,v| [k.downcase.to_sym,v]}]
-
-    def self.register reg
-      return reg if ID_LOOKUP[reg]
-      return SYM_LOOKUP[reg] if SYM_LOOKUP[reg]
-      if reg.respond_to? :upcase
-        return REG_LOOKUP[reg.upcase] || REG_LOOKUP['INVALID']
-      end
-      REG_LOOKUP['INVALID']
-    end
-
-  end
-end

data/lib/arch/mips.rb

@@ -1,78 +0,0 @@
-# Library by Nguyen Anh Quynh
-# Original binding by Nguyen Anh Quynh and Tan Sheng Di
-# Additional binding work by Ben Nagy
-# (c) 2013 COSEINC. All Rights Reserved.
-
-require 'ffi'
-
-require_relative 'mips_const'
-
-module Crabstone
-    module MIPS
-
-        class MemoryOperand < FFI::Struct
-            layout(
-                :base, :uint,
-                :disp, :int64
-            )
-        end
-
-        class OperandValue < FFI::Union
-            layout(
-                :reg, :uint,
-                :imm, :long_long,
-                :mem, MemoryOperand
-            )
-        end
-
-        class Operand < FFI::Struct
-            layout(
-                :type, :uint,
-                :value, OperandValue
-            )
-
-            def value
-                case self[:type]
-                when OP_REG
-                    self[:value][:reg]
-                when OP_IMM
-                    self[:value][:imm]
-                when OP_MEM
-                    self[:value][:mem]
-                when OP_FP
-                    self[:value][:fp]
-                else
-                    nil
-                end
-            end
-
-            def reg?
-                self[:type] == OP_REG
-            end
-
-            def imm?
-                self[:type] == OP_IMM
-            end
-
-            def mem?
-                self[:type] == OP_MEM
-            end
-
-            def valid?
-                [OP_MEM, OP_IMM, OP_REG].include? self[:type]
-            end
-        end
-
-        class Instruction < FFI::Struct
-            layout(
-                :op_count, :uint8,
-                :operands, [Operand, 8]
-            )
-
-            def operands
-                self[:operands].take_while {|op| op[:type].nonzero?}
-            end
-
-        end
-    end
-end