ceedling 0.0.1

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Files changed (991) hide show
  1. data/.gitignore +4 -0
  2. data/.vim +1 -0
  3. data/Gemfile +3 -0
  4. data/LICENSE +19 -0
  5. data/Rakefile +18 -0
  6. data/bin/ceedling +39 -0
  7. data/ceedling.gemspec +23 -0
  8. data/lib/ceedling/version.rb +10 -0
  9. data/lib/ceedling/version.rb.erb +10 -0
  10. data/lib/ceedling.rb +5 -0
  11. data/new_project_template/build/.gitkeep +0 -0
  12. data/new_project_template/project.yml +65 -0
  13. data/new_project_template/rakefile.rb +4 -0
  14. data/new_project_template/src/.gitkeep +0 -0
  15. data/new_project_template/test/.gitkeep +0 -0
  16. data/new_project_template/test/support/.gitkeep +0 -0
  17. data/new_project_template/vendor/ceedling/config/test_environment.rb +12 -0
  18. data/new_project_template/vendor/ceedling/docs/Ceedling Packet.odt +0 -0
  19. data/new_project_template/vendor/ceedling/docs/Ceedling Packet.pdf +0 -0
  20. data/new_project_template/vendor/ceedling/docs/CeedlingLogo.png +0 -0
  21. data/new_project_template/vendor/ceedling/examples/temp_sensor/gcc.yml +42 -0
  22. data/new_project_template/vendor/ceedling/examples/temp_sensor/iar_v4.yml +91 -0
  23. data/new_project_template/vendor/ceedling/examples/temp_sensor/iar_v5.yml +80 -0
  24. data/new_project_template/vendor/ceedling/examples/temp_sensor/project.yml +65 -0
  25. data/new_project_template/vendor/ceedling/examples/temp_sensor/rakefile.rb +5 -0
  26. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcConductor.c +42 -0
  27. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcConductor.h +13 -0
  28. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardware.c +27 -0
  29. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardware.h +11 -0
  30. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardwareConfigurator.c +18 -0
  31. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardwareConfigurator.h +10 -0
  32. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcModel.c +33 -0
  33. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcModel.h +13 -0
  34. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcTemperatureSensor.c +51 -0
  35. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcTemperatureSensor.h +10 -0
  36. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Executor.c +25 -0
  37. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Executor.h +9 -0
  38. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/IntrinsicsWrapper.c +18 -0
  39. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/IntrinsicsWrapper.h +7 -0
  40. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Main.c +46 -0
  41. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Main.h +7 -0
  42. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Model.c +10 -0
  43. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Model.h +8 -0
  44. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/ModelConfig.h +7 -0
  45. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TaskScheduler.c +72 -0
  46. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TaskScheduler.h +11 -0
  47. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureCalculator.c +27 -0
  48. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureCalculator.h +8 -0
  49. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureFilter.c +39 -0
  50. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureFilter.h +10 -0
  51. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConductor.c +15 -0
  52. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConductor.h +9 -0
  53. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConfigurator.c +51 -0
  54. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConfigurator.h +15 -0
  55. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerHardware.c +15 -0
  56. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerHardware.h +8 -0
  57. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptConfigurator.c +55 -0
  58. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptConfigurator.h +13 -0
  59. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptHandler.c +25 -0
  60. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptHandler.h +10 -0
  61. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerModel.c +9 -0
  62. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerModel.h +8 -0
  63. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Types.h +90 -0
  64. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartBaudRateRegisterCalculator.c +18 -0
  65. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartBaudRateRegisterCalculator.h +8 -0
  66. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConductor.c +21 -0
  67. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConductor.h +7 -0
  68. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConfigurator.c +39 -0
  69. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConfigurator.h +13 -0
  70. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartHardware.c +22 -0
  71. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartHardware.h +9 -0
  72. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartModel.c +34 -0
  73. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartModel.h +10 -0
  74. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartPutChar.c +16 -0
  75. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartPutChar.h +8 -0
  76. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartTransmitBufferStatus.c +7 -0
  77. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartTransmitBufferStatus.h +8 -0
  78. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcConductor.c +121 -0
  79. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcHardware.c +44 -0
  80. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcModel.c +33 -0
  81. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestExecutor.c +36 -0
  82. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestMain.c +24 -0
  83. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestModel.c +20 -0
  84. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTaskScheduler.c +104 -0
  85. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTemperatureCalculator.c +33 -0
  86. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTemperatureFilter.c +69 -0
  87. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerConductor.c +32 -0
  88. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerHardware.c +26 -0
  89. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerModel.c +18 -0
  90. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartBaudRateRegisterCalculator.c +21 -0
  91. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartConductor.c +40 -0
  92. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartHardware.c +36 -0
  93. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartModel.c +40 -0
  94. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/support/UnityHelper.c +12 -0
  95. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/support/UnityHelper.h +8 -0
  96. data/new_project_template/vendor/ceedling/lib/cacheinator.rb +42 -0
  97. data/new_project_template/vendor/ceedling/lib/cacheinator_helper.rb +12 -0
  98. data/new_project_template/vendor/ceedling/lib/cmock_builder.rb +15 -0
  99. data/new_project_template/vendor/ceedling/lib/configurator.rb +254 -0
  100. data/new_project_template/vendor/ceedling/lib/configurator_builder.rb +408 -0
  101. data/new_project_template/vendor/ceedling/lib/configurator_plugins.rb +96 -0
  102. data/new_project_template/vendor/ceedling/lib/configurator_setup.rb +114 -0
  103. data/new_project_template/vendor/ceedling/lib/configurator_validator.rb +154 -0
  104. data/new_project_template/vendor/ceedling/lib/constants.rb +66 -0
  105. data/new_project_template/vendor/ceedling/lib/defaults.rb +349 -0
  106. data/new_project_template/vendor/ceedling/lib/dependinator.rb +92 -0
  107. data/new_project_template/vendor/ceedling/lib/file_finder.rb +132 -0
  108. data/new_project_template/vendor/ceedling/lib/file_finder_helper.rb +54 -0
  109. data/new_project_template/vendor/ceedling/lib/file_path_utils.rb +177 -0
  110. data/new_project_template/vendor/ceedling/lib/file_system_utils.rb +59 -0
  111. data/new_project_template/vendor/ceedling/lib/file_wrapper.rb +74 -0
  112. data/new_project_template/vendor/ceedling/lib/generator.rb +131 -0
  113. data/new_project_template/vendor/ceedling/lib/generator_test_results.rb +90 -0
  114. data/new_project_template/vendor/ceedling/lib/generator_test_results_sanity_checker.rb +62 -0
  115. data/new_project_template/vendor/ceedling/lib/generator_test_runner.rb +206 -0
  116. data/new_project_template/vendor/ceedling/lib/loginator.rb +31 -0
  117. data/new_project_template/vendor/ceedling/lib/makefile.rb +46 -0
  118. data/new_project_template/vendor/ceedling/lib/objects.yml +278 -0
  119. data/new_project_template/vendor/ceedling/lib/plugin.rb +63 -0
  120. data/new_project_template/vendor/ceedling/lib/plugin_manager.rb +85 -0
  121. data/new_project_template/vendor/ceedling/lib/plugin_manager_helper.rb +19 -0
  122. data/new_project_template/vendor/ceedling/lib/plugin_reportinator.rb +75 -0
  123. data/new_project_template/vendor/ceedling/lib/plugin_reportinator_helper.rb +52 -0
  124. data/new_project_template/vendor/ceedling/lib/preprocessinator.rb +43 -0
  125. data/new_project_template/vendor/ceedling/lib/preprocessinator_extractor.rb +27 -0
  126. data/new_project_template/vendor/ceedling/lib/preprocessinator_file_handler.rb +21 -0
  127. data/new_project_template/vendor/ceedling/lib/preprocessinator_helper.rb +46 -0
  128. data/new_project_template/vendor/ceedling/lib/preprocessinator_includes_handler.rb +55 -0
  129. data/new_project_template/vendor/ceedling/lib/project_config_manager.rb +38 -0
  130. data/new_project_template/vendor/ceedling/lib/project_file_loader.rb +64 -0
  131. data/new_project_template/vendor/ceedling/lib/rake_utils.rb +17 -0
  132. data/new_project_template/vendor/ceedling/lib/rake_wrapper.rb +31 -0
  133. data/new_project_template/vendor/ceedling/lib/rakefile.rb +60 -0
  134. data/new_project_template/vendor/ceedling/lib/release_invoker.rb +29 -0
  135. data/new_project_template/vendor/ceedling/lib/release_invoker_helper.rb +16 -0
  136. data/new_project_template/vendor/ceedling/lib/reportinator.rb +9 -0
  137. data/new_project_template/vendor/ceedling/lib/rules_cmock.rake +9 -0
  138. data/new_project_template/vendor/ceedling/lib/rules_preprocess.rake +26 -0
  139. data/new_project_template/vendor/ceedling/lib/rules_release.rake +63 -0
  140. data/new_project_template/vendor/ceedling/lib/rules_release_aux_dependencies.rake +15 -0
  141. data/new_project_template/vendor/ceedling/lib/rules_tests.rake +49 -0
  142. data/new_project_template/vendor/ceedling/lib/rules_tests_aux_dependencies.rake +15 -0
  143. data/new_project_template/vendor/ceedling/lib/setupinator.rb +45 -0
  144. data/new_project_template/vendor/ceedling/lib/stream_wrapper.rb +20 -0
  145. data/new_project_template/vendor/ceedling/lib/streaminator.rb +41 -0
  146. data/new_project_template/vendor/ceedling/lib/streaminator_helper.rb +15 -0
  147. data/new_project_template/vendor/ceedling/lib/system_wrapper.rb +67 -0
  148. data/new_project_template/vendor/ceedling/lib/task_invoker.rb +85 -0
  149. data/new_project_template/vendor/ceedling/lib/tasks_base.rake +104 -0
  150. data/new_project_template/vendor/ceedling/lib/tasks_filesystem.rake +89 -0
  151. data/new_project_template/vendor/ceedling/lib/tasks_release.rake +22 -0
  152. data/new_project_template/vendor/ceedling/lib/tasks_tests.rake +49 -0
  153. data/new_project_template/vendor/ceedling/lib/tasks_vendor.rake +36 -0
  154. data/new_project_template/vendor/ceedling/lib/test_includes_extractor.rb +81 -0
  155. data/new_project_template/vendor/ceedling/lib/test_invoker.rb +72 -0
  156. data/new_project_template/vendor/ceedling/lib/test_invoker_helper.rb +41 -0
  157. data/new_project_template/vendor/ceedling/lib/tool_executor.rb +178 -0
  158. data/new_project_template/vendor/ceedling/lib/tool_executor_helper.rb +57 -0
  159. data/new_project_template/vendor/ceedling/lib/verbosinator.rb +10 -0
  160. data/new_project_template/vendor/ceedling/lib/yaml_wrapper.rb +16 -0
  161. data/new_project_template/vendor/ceedling/plugins/stdout_ide_tests_report/stdout_ide_tests_report.rb +44 -0
  162. data/new_project_template/vendor/ceedling/plugins/stdout_ide_tests_report/stdout_ide_tests_report.yml +4 -0
  163. data/new_project_template/vendor/ceedling/plugins/stdout_pretty_tests_report/stdout_pretty_tests_report.rb +108 -0
  164. data/new_project_template/vendor/ceedling/plugins/stdout_pretty_tests_report/stdout_pretty_tests_report.yml +4 -0
  165. data/new_project_template/vendor/ceedling/plugins/xml_tests_report/xml_tests_report.rb +106 -0
  166. data/new_project_template/vendor/ceedling/rakefile.rb +59 -0
  167. data/new_project_template/vendor/ceedling/rakefile_helper.rb +23 -0
  168. data/new_project_template/vendor/ceedling/release/build.info +1 -0
  169. data/new_project_template/vendor/ceedling/release/version.info +1 -0
  170. data/new_project_template/vendor/ceedling/test/integration/paths.yml +17 -0
  171. data/new_project_template/vendor/ceedling/test/integration/paths_test.rb +80 -0
  172. data/new_project_template/vendor/ceedling/test/integration/rake_rules_aux_dependencies_test.rb +75 -0
  173. data/new_project_template/vendor/ceedling/test/integration/rake_rules_cmock_test.rb +74 -0
  174. data/new_project_template/vendor/ceedling/test/integration/rake_rules_preprocess_test.rb +178 -0
  175. data/new_project_template/vendor/ceedling/test/integration/rake_rules_test.rb +268 -0
  176. data/new_project_template/vendor/ceedling/test/integration/rake_tasks_test.rb +103 -0
  177. data/new_project_template/vendor/ceedling/test/integration_test_helper.rb +34 -0
  178. data/new_project_template/vendor/ceedling/test/rakefile_rules.rb +10 -0
  179. data/new_project_template/vendor/ceedling/test/rakefile_rules_aux_dependencies.rb +10 -0
  180. data/new_project_template/vendor/ceedling/test/rakefile_rules_cmock.rb +10 -0
  181. data/new_project_template/vendor/ceedling/test/rakefile_rules_preprocess.rb +10 -0
  182. data/new_project_template/vendor/ceedling/test/rakefile_tasks.rb +10 -0
  183. data/new_project_template/vendor/ceedling/test/system/file_system_dependencies.yml +20 -0
  184. data/new_project_template/vendor/ceedling/test/system/file_system_kitchen_sink.yml +20 -0
  185. data/new_project_template/vendor/ceedling/test/system/file_system_mocks.yml +20 -0
  186. data/new_project_template/vendor/ceedling/test/system/file_system_preprocess.yml +20 -0
  187. data/new_project_template/vendor/ceedling/test/system/file_system_simple.yml +20 -0
  188. data/new_project_template/vendor/ceedling/test/system/file_system_test.rb +78 -0
  189. data/new_project_template/vendor/ceedling/test/system/mocks/include/a_file.h +2 -0
  190. data/new_project_template/vendor/ceedling/test/system/mocks/include/other_stuff.h +2 -0
  191. data/new_project_template/vendor/ceedling/test/system/mocks/include/stuff.h +3 -0
  192. data/new_project_template/vendor/ceedling/test/system/mocks/source/a_file.c +9 -0
  193. data/new_project_template/vendor/ceedling/test/system/mocks/test/test_a_file.c +41 -0
  194. data/new_project_template/vendor/ceedling/test/system/mocks/test/test_no_file.c +14 -0
  195. data/new_project_template/vendor/ceedling/test/system/project_mocks.yml +43 -0
  196. data/new_project_template/vendor/ceedling/test/system/project_mocks_test.rb +38 -0
  197. data/new_project_template/vendor/ceedling/test/system/project_simple.yml +36 -0
  198. data/new_project_template/vendor/ceedling/test/system/project_simple_test.rb +39 -0
  199. data/new_project_template/vendor/ceedling/test/system/rule_mocks_test.rb +44 -0
  200. data/new_project_template/vendor/ceedling/test/system/rule_runners_test.rb +44 -0
  201. data/new_project_template/vendor/ceedling/test/system/simple/include/other_stuff.h +2 -0
  202. data/new_project_template/vendor/ceedling/test/system/simple/include/stuff.h +3 -0
  203. data/new_project_template/vendor/ceedling/test/system/simple/source/other_stuff.c +6 -0
  204. data/new_project_template/vendor/ceedling/test/system/simple/source/stuff.c +7 -0
  205. data/new_project_template/vendor/ceedling/test/system/simple/test/test_other_stuff.c +30 -0
  206. data/new_project_template/vendor/ceedling/test/system/simple/test/test_stuff.c +51 -0
  207. data/new_project_template/vendor/ceedling/test/system_test_helper.rb +73 -0
  208. data/new_project_template/vendor/ceedling/test/test_helper.rb +93 -0
  209. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_builder_test.rb +571 -0
  210. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_helper_test.rb +234 -0
  211. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_test.rb +232 -0
  212. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_validator_test.rb +169 -0
  213. data/new_project_template/vendor/ceedling/test/unit/busted/deep_merge_fix_test.rb +55 -0
  214. data/new_project_template/vendor/ceedling/test/unit/busted/dependinator_test.rb +129 -0
  215. data/new_project_template/vendor/ceedling/test/unit/busted/file_finder_helper_test.rb +45 -0
  216. data/new_project_template/vendor/ceedling/test/unit/busted/file_finder_test.rb +114 -0
  217. data/new_project_template/vendor/ceedling/test/unit/busted/file_path_utils_test.rb +97 -0
  218. data/new_project_template/vendor/ceedling/test/unit/busted/file_system_utils_test.rb +21 -0
  219. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test.rb +187 -0
  220. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test_results_test.rb +129 -0
  221. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test_runner_test.rb +478 -0
  222. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_extractor_test.rb +729 -0
  223. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_file_handler_test.rb +38 -0
  224. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_helper_test.rb +156 -0
  225. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_includes_handler_test.rb +93 -0
  226. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_test.rb +57 -0
  227. data/new_project_template/vendor/ceedling/test/unit/busted/project_file_loader_test.rb +142 -0
  228. data/new_project_template/vendor/ceedling/test/unit/busted/setupinator_test.rb +45 -0
  229. data/new_project_template/vendor/ceedling/test/unit/busted/streaminator_test.rb +49 -0
  230. data/new_project_template/vendor/ceedling/test/unit/busted/task_invoker_test.rb +69 -0
  231. data/new_project_template/vendor/ceedling/test/unit/busted/test_includes_extractor_test.rb +111 -0
  232. data/new_project_template/vendor/ceedling/test/unit/busted/test_invoker_helper_test.rb +62 -0
  233. data/new_project_template/vendor/ceedling/test/unit/busted/test_invoker_test.rb +47 -0
  234. data/new_project_template/vendor/ceedling/test/unit/busted/tool_executor_helper_test.rb +100 -0
  235. data/new_project_template/vendor/ceedling/test/unit/busted/tool_executor_test.rb +351 -0
  236. data/new_project_template/vendor/ceedling/test/unit/busted/verbosinator_test.rb +65 -0
  237. data/new_project_template/vendor/ceedling/test/unit_test_helper.rb +16 -0
  238. data/new_project_template/vendor/ceedling/vendor/behaviors/Manifest.txt +9 -0
  239. data/new_project_template/vendor/ceedling/vendor/behaviors/Rakefile +19 -0
  240. data/new_project_template/vendor/ceedling/vendor/behaviors/lib/behaviors/reporttask.rb +158 -0
  241. data/new_project_template/vendor/ceedling/vendor/behaviors/lib/behaviors.rb +76 -0
  242. data/new_project_template/vendor/ceedling/vendor/behaviors/test/behaviors_tasks_test.rb +73 -0
  243. data/new_project_template/vendor/ceedling/vendor/behaviors/test/behaviors_test.rb +50 -0
  244. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/Rakefile +19 -0
  245. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/lib/user.rb +2 -0
  246. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/test/user_test.rb +17 -0
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@@ -0,0 +1,2268 @@
1
+ // ----------------------------------------------------------------------------
2
+ // ATMEL Microcontroller Software Support - ROUSSET -
3
+ // ----------------------------------------------------------------------------
4
+ // DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
5
+ // IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6
+ // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
7
+ // DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
8
+ // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
9
+ // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
10
+ // OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
11
+ // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
12
+ // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
13
+ // EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
14
+ // ----------------------------------------------------------------------------
15
+ // File Name : AT91SAM7X256.h
16
+ // Object : AT91SAM7X256 definitions
17
+ // Generated : AT91 SW Application Group 01/16/2006 (16:36:22)
18
+ //
19
+ // CVS Reference : /AT91SAM7X256.pl/1.15/Wed Nov 2 13:56:49 2005//
20
+ // CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
21
+ // CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
22
+ // CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
23
+ // CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 14:57:50 2005//
24
+ // CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
25
+ // CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
26
+ // CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
27
+ // CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
28
+ // CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
29
+ // CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
30
+ // CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
31
+ // CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
32
+ // CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
33
+ // CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
34
+ // CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
35
+ // CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
36
+ // CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:19:19 2005//
37
+ // CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
38
+ // CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
39
+ // CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
40
+ // CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:05:35 2005//
41
+ // CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
42
+ // ----------------------------------------------------------------------------
43
+
44
+ // Hardware register definition
45
+
46
+ // *****************************************************************************
47
+ // SOFTWARE API DEFINITION FOR System Peripherals
48
+ // *****************************************************************************
49
+
50
+ // *****************************************************************************
51
+ // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
52
+ // *****************************************************************************
53
+ // *** Register offset in AT91S_AIC structure ***
54
+ #define AIC_SMR ( 0) // Source Mode Register
55
+ #define AIC_SVR (128) // Source Vector Register
56
+ #define AIC_IVR (256) // IRQ Vector Register
57
+ #define AIC_FVR (260) // FIQ Vector Register
58
+ #define AIC_ISR (264) // Interrupt Status Register
59
+ #define AIC_IPR (268) // Interrupt Pending Register
60
+ #define AIC_IMR (272) // Interrupt Mask Register
61
+ #define AIC_CISR (276) // Core Interrupt Status Register
62
+ #define AIC_IECR (288) // Interrupt Enable Command Register
63
+ #define AIC_IDCR (292) // Interrupt Disable Command Register
64
+ #define AIC_ICCR (296) // Interrupt Clear Command Register
65
+ #define AIC_ISCR (300) // Interrupt Set Command Register
66
+ #define AIC_EOICR (304) // End of Interrupt Command Register
67
+ #define AIC_SPU (308) // Spurious Vector Register
68
+ #define AIC_DCR (312) // Debug Control Register (Protect)
69
+ #define AIC_FFER (320) // Fast Forcing Enable Register
70
+ #define AIC_FFDR (324) // Fast Forcing Disable Register
71
+ #define AIC_FFSR (328) // Fast Forcing Status Register
72
+ // -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
73
+ #define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
74
+ #define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
75
+ #define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
76
+ #define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
77
+ #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
78
+ #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
79
+ #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
80
+ #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
81
+ #define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
82
+ #define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
83
+ // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
84
+ #define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
85
+ #define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
86
+ // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
87
+ #define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
88
+ #define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
89
+
90
+ // *****************************************************************************
91
+ // SOFTWARE API DEFINITION FOR Peripheral DMA Controller
92
+ // *****************************************************************************
93
+ // *** Register offset in AT91S_PDC structure ***
94
+ #define PDC_RPR ( 0) // Receive Pointer Register
95
+ #define PDC_RCR ( 4) // Receive Counter Register
96
+ #define PDC_TPR ( 8) // Transmit Pointer Register
97
+ #define PDC_TCR (12) // Transmit Counter Register
98
+ #define PDC_RNPR (16) // Receive Next Pointer Register
99
+ #define PDC_RNCR (20) // Receive Next Counter Register
100
+ #define PDC_TNPR (24) // Transmit Next Pointer Register
101
+ #define PDC_TNCR (28) // Transmit Next Counter Register
102
+ #define PDC_PTCR (32) // PDC Transfer Control Register
103
+ #define PDC_PTSR (36) // PDC Transfer Status Register
104
+ // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
105
+ #define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
106
+ #define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
107
+ #define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
108
+ #define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
109
+ // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
110
+
111
+ // *****************************************************************************
112
+ // SOFTWARE API DEFINITION FOR Debug Unit
113
+ // *****************************************************************************
114
+ // *** Register offset in AT91S_DBGU structure ***
115
+ #define DBGU_CR ( 0) // Control Register
116
+ #define DBGU_MR ( 4) // Mode Register
117
+ #define DBGU_IER ( 8) // Interrupt Enable Register
118
+ #define DBGU_IDR (12) // Interrupt Disable Register
119
+ #define DBGU_IMR (16) // Interrupt Mask Register
120
+ #define DBGU_CSR (20) // Channel Status Register
121
+ #define DBGU_RHR (24) // Receiver Holding Register
122
+ #define DBGU_THR (28) // Transmitter Holding Register
123
+ #define DBGU_BRGR (32) // Baud Rate Generator Register
124
+ #define DBGU_CIDR (64) // Chip ID Register
125
+ #define DBGU_EXID (68) // Chip ID Extension Register
126
+ #define DBGU_FNTR (72) // Force NTRST Register
127
+ #define DBGU_RPR (256) // Receive Pointer Register
128
+ #define DBGU_RCR (260) // Receive Counter Register
129
+ #define DBGU_TPR (264) // Transmit Pointer Register
130
+ #define DBGU_TCR (268) // Transmit Counter Register
131
+ #define DBGU_RNPR (272) // Receive Next Pointer Register
132
+ #define DBGU_RNCR (276) // Receive Next Counter Register
133
+ #define DBGU_TNPR (280) // Transmit Next Pointer Register
134
+ #define DBGU_TNCR (284) // Transmit Next Counter Register
135
+ #define DBGU_PTCR (288) // PDC Transfer Control Register
136
+ #define DBGU_PTSR (292) // PDC Transfer Status Register
137
+ // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
138
+ #define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
139
+ #define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
140
+ #define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
141
+ #define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
142
+ #define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
143
+ #define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
144
+ #define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
145
+ // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
146
+ #define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
147
+ #define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
148
+ #define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
149
+ #define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
150
+ #define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
151
+ #define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
152
+ #define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
153
+ #define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
154
+ #define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
155
+ #define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
156
+ #define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
157
+ #define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
158
+ // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
159
+ #define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
160
+ #define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
161
+ #define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
162
+ #define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
163
+ #define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
164
+ #define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
165
+ #define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
166
+ #define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
167
+ #define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
168
+ #define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
169
+ #define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
170
+ #define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
171
+ // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
172
+ // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
173
+ // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
174
+ // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
175
+ #define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
176
+
177
+ // *****************************************************************************
178
+ // SOFTWARE API DEFINITION FOR Parallel Input Output Controler
179
+ // *****************************************************************************
180
+ // *** Register offset in AT91S_PIO structure ***
181
+ #define PIO_PER ( 0) // PIO Enable Register
182
+ #define PIO_PDR ( 4) // PIO Disable Register
183
+ #define PIO_PSR ( 8) // PIO Status Register
184
+ #define PIO_OER (16) // Output Enable Register
185
+ #define PIO_ODR (20) // Output Disable Registerr
186
+ #define PIO_OSR (24) // Output Status Register
187
+ #define PIO_IFER (32) // Input Filter Enable Register
188
+ #define PIO_IFDR (36) // Input Filter Disable Register
189
+ #define PIO_IFSR (40) // Input Filter Status Register
190
+ #define PIO_SODR (48) // Set Output Data Register
191
+ #define PIO_CODR (52) // Clear Output Data Register
192
+ #define PIO_ODSR (56) // Output Data Status Register
193
+ #define PIO_PDSR (60) // Pin Data Status Register
194
+ #define PIO_IER (64) // Interrupt Enable Register
195
+ #define PIO_IDR (68) // Interrupt Disable Register
196
+ #define PIO_IMR (72) // Interrupt Mask Register
197
+ #define PIO_ISR (76) // Interrupt Status Register
198
+ #define PIO_MDER (80) // Multi-driver Enable Register
199
+ #define PIO_MDDR (84) // Multi-driver Disable Register
200
+ #define PIO_MDSR (88) // Multi-driver Status Register
201
+ #define PIO_PPUDR (96) // Pull-up Disable Register
202
+ #define PIO_PPUER (100) // Pull-up Enable Register
203
+ #define PIO_PPUSR (104) // Pull-up Status Register
204
+ #define PIO_ASR (112) // Select A Register
205
+ #define PIO_BSR (116) // Select B Register
206
+ #define PIO_ABSR (120) // AB Select Status Register
207
+ #define PIO_OWER (160) // Output Write Enable Register
208
+ #define PIO_OWDR (164) // Output Write Disable Register
209
+ #define PIO_OWSR (168) // Output Write Status Register
210
+
211
+ // *****************************************************************************
212
+ // SOFTWARE API DEFINITION FOR Clock Generator Controler
213
+ // *****************************************************************************
214
+ // *** Register offset in AT91S_CKGR structure ***
215
+ #define CKGR_MOR ( 0) // Main Oscillator Register
216
+ #define CKGR_MCFR ( 4) // Main Clock Frequency Register
217
+ #define CKGR_PLLR (12) // PLL Register
218
+ // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
219
+ #define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
220
+ #define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
221
+ #define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
222
+ // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
223
+ #define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
224
+ #define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
225
+ // -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
226
+ #define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
227
+ #define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
228
+ #define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
229
+ #define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
230
+ #define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
231
+ #define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
232
+ #define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
233
+ #define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
234
+ #define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
235
+ #define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
236
+ #define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
237
+ #define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
238
+ #define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
239
+ #define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
240
+
241
+ // *****************************************************************************
242
+ // SOFTWARE API DEFINITION FOR Power Management Controler
243
+ // *****************************************************************************
244
+ // *** Register offset in AT91S_PMC structure ***
245
+ #define PMC_SCER ( 0) // System Clock Enable Register
246
+ #define PMC_SCDR ( 4) // System Clock Disable Register
247
+ #define PMC_SCSR ( 8) // System Clock Status Register
248
+ #define PMC_PCER (16) // Peripheral Clock Enable Register
249
+ #define PMC_PCDR (20) // Peripheral Clock Disable Register
250
+ #define PMC_PCSR (24) // Peripheral Clock Status Register
251
+ #define PMC_MOR (32) // Main Oscillator Register
252
+ #define PMC_MCFR (36) // Main Clock Frequency Register
253
+ #define PMC_PLLR (44) // PLL Register
254
+ #define PMC_MCKR (48) // Master Clock Register
255
+ #define PMC_PCKR (64) // Programmable Clock Register
256
+ #define PMC_IER (96) // Interrupt Enable Register
257
+ #define PMC_IDR (100) // Interrupt Disable Register
258
+ #define PMC_SR (104) // Status Register
259
+ #define PMC_IMR (108) // Interrupt Mask Register
260
+ // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
261
+ #define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
262
+ #define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
263
+ #define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
264
+ #define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
265
+ #define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
266
+ #define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
267
+ // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
268
+ // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
269
+ // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
270
+ // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
271
+ // -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
272
+ // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
273
+ #define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
274
+ #define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
275
+ #define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
276
+ #define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
277
+ #define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
278
+ #define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
279
+ #define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
280
+ #define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
281
+ #define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
282
+ #define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
283
+ #define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
284
+ #define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
285
+ // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
286
+ // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
287
+ #define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
288
+ #define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
289
+ #define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
290
+ #define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
291
+ #define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
292
+ #define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
293
+ #define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
294
+ // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
295
+ // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
296
+ // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
297
+
298
+ // *****************************************************************************
299
+ // SOFTWARE API DEFINITION FOR Reset Controller Interface
300
+ // *****************************************************************************
301
+ // *** Register offset in AT91S_RSTC structure ***
302
+ #define RSTC_RCR ( 0) // Reset Control Register
303
+ #define RSTC_RSR ( 4) // Reset Status Register
304
+ #define RSTC_RMR ( 8) // Reset Mode Register
305
+ // -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
306
+ #define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
307
+ #define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
308
+ #define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
309
+ #define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
310
+ // -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
311
+ #define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
312
+ #define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
313
+ #define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
314
+ #define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
315
+ #define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
316
+ #define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
317
+ #define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
318
+ #define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
319
+ #define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
320
+ #define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
321
+ #define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
322
+ // -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
323
+ #define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
324
+ #define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
325
+ #define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length
326
+ #define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
327
+
328
+ // *****************************************************************************
329
+ // SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
330
+ // *****************************************************************************
331
+ // *** Register offset in AT91S_RTTC structure ***
332
+ #define RTTC_RTMR ( 0) // Real-time Mode Register
333
+ #define RTTC_RTAR ( 4) // Real-time Alarm Register
334
+ #define RTTC_RTVR ( 8) // Real-time Value Register
335
+ #define RTTC_RTSR (12) // Real-time Status Register
336
+ // -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
337
+ #define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
338
+ #define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
339
+ #define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
340
+ #define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
341
+ // -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
342
+ #define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
343
+ // -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
344
+ #define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
345
+ // -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
346
+ #define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
347
+ #define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
348
+
349
+ // *****************************************************************************
350
+ // SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
351
+ // *****************************************************************************
352
+ // *** Register offset in AT91S_PITC structure ***
353
+ #define PITC_PIMR ( 0) // Period Interval Mode Register
354
+ #define PITC_PISR ( 4) // Period Interval Status Register
355
+ #define PITC_PIVR ( 8) // Period Interval Value Register
356
+ #define PITC_PIIR (12) // Period Interval Image Register
357
+ // -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
358
+ #define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
359
+ #define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
360
+ #define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
361
+ // -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
362
+ #define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
363
+ // -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
364
+ #define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
365
+ #define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
366
+ // -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
367
+
368
+ // *****************************************************************************
369
+ // SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
370
+ // *****************************************************************************
371
+ // *** Register offset in AT91S_WDTC structure ***
372
+ #define WDTC_WDCR ( 0) // Watchdog Control Register
373
+ #define WDTC_WDMR ( 4) // Watchdog Mode Register
374
+ #define WDTC_WDSR ( 8) // Watchdog Status Register
375
+ // -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
376
+ #define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
377
+ #define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
378
+ // -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
379
+ #define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
380
+ #define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
381
+ #define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
382
+ #define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
383
+ #define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
384
+ #define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
385
+ #define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
386
+ #define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
387
+ // -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
388
+ #define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
389
+ #define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
390
+
391
+ // *****************************************************************************
392
+ // SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
393
+ // *****************************************************************************
394
+ // *** Register offset in AT91S_VREG structure ***
395
+ #define VREG_MR ( 0) // Voltage Regulator Mode Register
396
+ // -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
397
+ #define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
398
+
399
+ // *****************************************************************************
400
+ // SOFTWARE API DEFINITION FOR Memory Controller Interface
401
+ // *****************************************************************************
402
+ // *** Register offset in AT91S_MC structure ***
403
+ #define MC_RCR ( 0) // MC Remap Control Register
404
+ #define MC_ASR ( 4) // MC Abort Status Register
405
+ #define MC_AASR ( 8) // MC Abort Address Status Register
406
+ #define MC_FMR (96) // MC Flash Mode Register
407
+ #define MC_FCR (100) // MC Flash Command Register
408
+ #define MC_FSR (104) // MC Flash Status Register
409
+ // -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
410
+ #define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
411
+ // -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
412
+ #define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
413
+ #define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
414
+ #define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
415
+ #define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
416
+ #define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
417
+ #define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
418
+ #define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
419
+ #define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
420
+ #define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
421
+ #define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
422
+ #define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
423
+ #define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
424
+ #define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
425
+ #define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
426
+ // -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
427
+ #define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
428
+ #define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
429
+ #define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
430
+ #define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
431
+ #define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
432
+ #define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
433
+ #define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
434
+ #define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
435
+ #define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
436
+ #define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
437
+ // -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
438
+ #define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
439
+ #define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
440
+ #define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
441
+ #define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
442
+ #define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
443
+ #define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
444
+ #define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
445
+ #define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
446
+ #define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
447
+ #define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
448
+ #define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
449
+ // -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
450
+ #define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
451
+ #define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
452
+ #define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
453
+ #define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
454
+ #define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
455
+ #define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
456
+ #define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
457
+ #define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
458
+ #define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
459
+ #define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
460
+ #define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
461
+ #define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
462
+ #define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
463
+ #define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
464
+ #define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
465
+ #define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
466
+ #define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
467
+ #define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
468
+ #define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
469
+ #define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
470
+ #define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
471
+ #define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
472
+ #define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
473
+ #define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
474
+ #define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
475
+
476
+ // *****************************************************************************
477
+ // SOFTWARE API DEFINITION FOR Serial Parallel Interface
478
+ // *****************************************************************************
479
+ // *** Register offset in AT91S_SPI structure ***
480
+ #define SPI_CR ( 0) // Control Register
481
+ #define SPI_MR ( 4) // Mode Register
482
+ #define SPI_RDR ( 8) // Receive Data Register
483
+ #define SPI_TDR (12) // Transmit Data Register
484
+ #define SPI_SR (16) // Status Register
485
+ #define SPI_IER (20) // Interrupt Enable Register
486
+ #define SPI_IDR (24) // Interrupt Disable Register
487
+ #define SPI_IMR (28) // Interrupt Mask Register
488
+ #define SPI_CSR (48) // Chip Select Register
489
+ #define SPI_RPR (256) // Receive Pointer Register
490
+ #define SPI_RCR (260) // Receive Counter Register
491
+ #define SPI_TPR (264) // Transmit Pointer Register
492
+ #define SPI_TCR (268) // Transmit Counter Register
493
+ #define SPI_RNPR (272) // Receive Next Pointer Register
494
+ #define SPI_RNCR (276) // Receive Next Counter Register
495
+ #define SPI_TNPR (280) // Transmit Next Pointer Register
496
+ #define SPI_TNCR (284) // Transmit Next Counter Register
497
+ #define SPI_PTCR (288) // PDC Transfer Control Register
498
+ #define SPI_PTSR (292) // PDC Transfer Status Register
499
+ // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
500
+ #define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
501
+ #define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
502
+ #define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
503
+ #define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
504
+ // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
505
+ #define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
506
+ #define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
507
+ #define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
508
+ #define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
509
+ #define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
510
+ #define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
511
+ #define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
512
+ #define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
513
+ #define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
514
+ #define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
515
+ // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
516
+ #define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
517
+ #define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
518
+ // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
519
+ #define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
520
+ #define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
521
+ // -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
522
+ #define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
523
+ #define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
524
+ #define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
525
+ #define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
526
+ #define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
527
+ #define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
528
+ #define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
529
+ #define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
530
+ #define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
531
+ #define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
532
+ #define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
533
+ // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
534
+ // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
535
+ // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
536
+ // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
537
+ #define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
538
+ #define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
539
+ #define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
540
+ #define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
541
+ #define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
542
+ #define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
543
+ #define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
544
+ #define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
545
+ #define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
546
+ #define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
547
+ #define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
548
+ #define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
549
+ #define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
550
+ #define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
551
+ #define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
552
+ #define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
553
+
554
+ // *****************************************************************************
555
+ // SOFTWARE API DEFINITION FOR Usart
556
+ // *****************************************************************************
557
+ // *** Register offset in AT91S_USART structure ***
558
+ #define US_CR ( 0) // Control Register
559
+ #define US_MR ( 4) // Mode Register
560
+ #define US_IER ( 8) // Interrupt Enable Register
561
+ #define US_IDR (12) // Interrupt Disable Register
562
+ #define US_IMR (16) // Interrupt Mask Register
563
+ #define US_CSR (20) // Channel Status Register
564
+ #define US_RHR (24) // Receiver Holding Register
565
+ #define US_THR (28) // Transmitter Holding Register
566
+ #define US_BRGR (32) // Baud Rate Generator Register
567
+ #define US_RTOR (36) // Receiver Time-out Register
568
+ #define US_TTGR (40) // Transmitter Time-guard Register
569
+ #define US_FIDI (64) // FI_DI_Ratio Register
570
+ #define US_NER (68) // Nb Errors Register
571
+ #define US_IF (76) // IRDA_FILTER Register
572
+ #define US_RPR (256) // Receive Pointer Register
573
+ #define US_RCR (260) // Receive Counter Register
574
+ #define US_TPR (264) // Transmit Pointer Register
575
+ #define US_TCR (268) // Transmit Counter Register
576
+ #define US_RNPR (272) // Receive Next Pointer Register
577
+ #define US_RNCR (276) // Receive Next Counter Register
578
+ #define US_TNPR (280) // Transmit Next Pointer Register
579
+ #define US_TNCR (284) // Transmit Next Counter Register
580
+ #define US_PTCR (288) // PDC Transfer Control Register
581
+ #define US_PTSR (292) // PDC Transfer Status Register
582
+ // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
583
+ #define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
584
+ #define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
585
+ #define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
586
+ #define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
587
+ #define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
588
+ #define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
589
+ #define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
590
+ #define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
591
+ #define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
592
+ #define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
593
+ #define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
594
+ // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
595
+ #define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
596
+ #define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
597
+ #define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
598
+ #define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
599
+ #define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
600
+ #define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
601
+ #define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
602
+ #define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
603
+ #define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
604
+ #define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
605
+ #define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
606
+ #define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
607
+ #define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
608
+ #define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
609
+ #define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
610
+ #define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
611
+ #define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
612
+ #define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
613
+ #define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
614
+ #define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
615
+ #define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
616
+ #define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
617
+ #define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
618
+ #define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
619
+ #define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
620
+ #define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
621
+ #define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
622
+ #define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
623
+ #define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
624
+ #define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
625
+ #define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
626
+ #define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
627
+ // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
628
+ #define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
629
+ #define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
630
+ #define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
631
+ #define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
632
+ #define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
633
+ #define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
634
+ #define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
635
+ #define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
636
+ // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
637
+ // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
638
+ // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
639
+ #define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
640
+ #define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
641
+ #define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
642
+ #define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
643
+
644
+ // *****************************************************************************
645
+ // SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
646
+ // *****************************************************************************
647
+ // *** Register offset in AT91S_SSC structure ***
648
+ #define SSC_CR ( 0) // Control Register
649
+ #define SSC_CMR ( 4) // Clock Mode Register
650
+ #define SSC_RCMR (16) // Receive Clock ModeRegister
651
+ #define SSC_RFMR (20) // Receive Frame Mode Register
652
+ #define SSC_TCMR (24) // Transmit Clock Mode Register
653
+ #define SSC_TFMR (28) // Transmit Frame Mode Register
654
+ #define SSC_RHR (32) // Receive Holding Register
655
+ #define SSC_THR (36) // Transmit Holding Register
656
+ #define SSC_RSHR (48) // Receive Sync Holding Register
657
+ #define SSC_TSHR (52) // Transmit Sync Holding Register
658
+ #define SSC_SR (64) // Status Register
659
+ #define SSC_IER (68) // Interrupt Enable Register
660
+ #define SSC_IDR (72) // Interrupt Disable Register
661
+ #define SSC_IMR (76) // Interrupt Mask Register
662
+ #define SSC_RPR (256) // Receive Pointer Register
663
+ #define SSC_RCR (260) // Receive Counter Register
664
+ #define SSC_TPR (264) // Transmit Pointer Register
665
+ #define SSC_TCR (268) // Transmit Counter Register
666
+ #define SSC_RNPR (272) // Receive Next Pointer Register
667
+ #define SSC_RNCR (276) // Receive Next Counter Register
668
+ #define SSC_TNPR (280) // Transmit Next Pointer Register
669
+ #define SSC_TNCR (284) // Transmit Next Counter Register
670
+ #define SSC_PTCR (288) // PDC Transfer Control Register
671
+ #define SSC_PTSR (292) // PDC Transfer Status Register
672
+ // -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
673
+ #define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
674
+ #define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
675
+ #define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
676
+ #define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
677
+ #define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
678
+ // -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
679
+ #define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
680
+ #define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
681
+ #define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
682
+ #define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
683
+ #define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
684
+ #define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
685
+ #define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
686
+ #define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
687
+ #define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
688
+ #define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
689
+ #define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
690
+ #define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
691
+ #define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
692
+ #define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
693
+ #define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
694
+ #define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
695
+ #define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
696
+ #define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
697
+ #define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
698
+ #define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
699
+ #define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
700
+ #define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
701
+ #define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
702
+ #define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection
703
+ #define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
704
+ #define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
705
+ // -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
706
+ #define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
707
+ #define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
708
+ #define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
709
+ #define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
710
+ #define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
711
+ #define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
712
+ #define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
713
+ #define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
714
+ #define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
715
+ #define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
716
+ #define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
717
+ #define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
718
+ #define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
719
+ // -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
720
+ // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
721
+ #define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
722
+ #define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
723
+ // -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
724
+ #define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
725
+ #define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
726
+ #define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
727
+ #define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
728
+ #define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
729
+ #define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
730
+ #define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
731
+ #define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
732
+ #define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0
733
+ #define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1
734
+ #define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
735
+ #define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
736
+ #define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
737
+ #define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
738
+ // -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
739
+ // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
740
+ // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
741
+
742
+ // *****************************************************************************
743
+ // SOFTWARE API DEFINITION FOR Two-wire Interface
744
+ // *****************************************************************************
745
+ // *** Register offset in AT91S_TWI structure ***
746
+ #define TWI_CR ( 0) // Control Register
747
+ #define TWI_MMR ( 4) // Master Mode Register
748
+ #define TWI_IADR (12) // Internal Address Register
749
+ #define TWI_CWGR (16) // Clock Waveform Generator Register
750
+ #define TWI_SR (32) // Status Register
751
+ #define TWI_IER (36) // Interrupt Enable Register
752
+ #define TWI_IDR (40) // Interrupt Disable Register
753
+ #define TWI_IMR (44) // Interrupt Mask Register
754
+ #define TWI_RHR (48) // Receive Holding Register
755
+ #define TWI_THR (52) // Transmit Holding Register
756
+ // -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
757
+ #define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
758
+ #define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
759
+ #define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
760
+ #define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
761
+ #define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
762
+ // -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
763
+ #define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
764
+ #define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
765
+ #define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
766
+ #define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
767
+ #define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
768
+ #define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
769
+ #define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
770
+ // -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
771
+ #define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
772
+ #define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
773
+ #define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
774
+ // -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
775
+ #define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
776
+ #define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
777
+ #define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
778
+ #define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
779
+ #define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
780
+ #define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
781
+ // -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
782
+ // -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
783
+ // -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
784
+
785
+ // *****************************************************************************
786
+ // SOFTWARE API DEFINITION FOR PWMC Channel Interface
787
+ // *****************************************************************************
788
+ // *** Register offset in AT91S_PWMC_CH structure ***
789
+ #define PWMC_CMR ( 0) // Channel Mode Register
790
+ #define PWMC_CDTYR ( 4) // Channel Duty Cycle Register
791
+ #define PWMC_CPRDR ( 8) // Channel Period Register
792
+ #define PWMC_CCNTR (12) // Channel Counter Register
793
+ #define PWMC_CUPDR (16) // Channel Update Register
794
+ #define PWMC_Reserved (20) // Reserved
795
+ // -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
796
+ #define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
797
+ #define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
798
+ #define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
799
+ #define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
800
+ #define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
801
+ #define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
802
+ #define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
803
+ // -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
804
+ #define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
805
+ // -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
806
+ #define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
807
+ // -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
808
+ #define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
809
+ // -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
810
+ #define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
811
+
812
+ // *****************************************************************************
813
+ // SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
814
+ // *****************************************************************************
815
+ // *** Register offset in AT91S_PWMC structure ***
816
+ #define PWMC_MR ( 0) // PWMC Mode Register
817
+ #define PWMC_ENA ( 4) // PWMC Enable Register
818
+ #define PWMC_DIS ( 8) // PWMC Disable Register
819
+ #define PWMC_SR (12) // PWMC Status Register
820
+ #define PWMC_IER (16) // PWMC Interrupt Enable Register
821
+ #define PWMC_IDR (20) // PWMC Interrupt Disable Register
822
+ #define PWMC_IMR (24) // PWMC Interrupt Mask Register
823
+ #define PWMC_ISR (28) // PWMC Interrupt Status Register
824
+ #define PWMC_VR (252) // PWMC Version Register
825
+ #define PWMC_CH (512) // PWMC Channel
826
+ // -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
827
+ #define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
828
+ #define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
829
+ #define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
830
+ #define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
831
+ #define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
832
+ #define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
833
+ // -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
834
+ #define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
835
+ #define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
836
+ #define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
837
+ #define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
838
+ // -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
839
+ // -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
840
+ // -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
841
+ // -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
842
+ // -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
843
+ // -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
844
+
845
+ // *****************************************************************************
846
+ // SOFTWARE API DEFINITION FOR USB Device Interface
847
+ // *****************************************************************************
848
+ // *** Register offset in AT91S_UDP structure ***
849
+ #define UDP_NUM ( 0) // Frame Number Register
850
+ #define UDP_GLBSTATE ( 4) // Global State Register
851
+ #define UDP_FADDR ( 8) // Function Address Register
852
+ #define UDP_IER (16) // Interrupt Enable Register
853
+ #define UDP_IDR (20) // Interrupt Disable Register
854
+ #define UDP_IMR (24) // Interrupt Mask Register
855
+ #define UDP_ISR (28) // Interrupt Status Register
856
+ #define UDP_ICR (32) // Interrupt Clear Register
857
+ #define UDP_RSTEP (40) // Reset Endpoint Register
858
+ #define UDP_CSR (48) // Endpoint Control and Status Register
859
+ #define UDP_FDR (80) // Endpoint FIFO Data Register
860
+ #define UDP_TXVC (116) // Transceiver Control Register
861
+ // -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
862
+ #define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
863
+ #define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
864
+ #define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
865
+ // -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
866
+ #define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
867
+ #define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
868
+ #define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
869
+ #define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
870
+ #define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
871
+ // -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
872
+ #define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
873
+ #define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
874
+ // -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
875
+ #define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
876
+ #define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
877
+ #define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
878
+ #define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
879
+ #define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
880
+ #define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
881
+ #define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
882
+ #define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
883
+ #define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
884
+ #define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
885
+ #define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
886
+ // -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
887
+ // -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
888
+ // -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
889
+ #define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
890
+ // -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
891
+ // -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
892
+ #define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
893
+ #define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
894
+ #define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
895
+ #define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
896
+ #define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
897
+ #define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
898
+ // -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
899
+ #define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
900
+ #define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
901
+ #define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
902
+ #define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
903
+ #define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
904
+ #define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
905
+ #define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
906
+ #define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
907
+ #define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
908
+ #define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
909
+ #define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
910
+ #define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
911
+ #define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
912
+ #define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
913
+ #define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
914
+ #define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
915
+ #define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
916
+ #define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
917
+ #define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
918
+ // -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
919
+ #define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
920
+ #define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON
921
+
922
+ // *****************************************************************************
923
+ // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
924
+ // *****************************************************************************
925
+ // *** Register offset in AT91S_TC structure ***
926
+ #define TC_CCR ( 0) // Channel Control Register
927
+ #define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
928
+ #define TC_CV (16) // Counter Value
929
+ #define TC_RA (20) // Register A
930
+ #define TC_RB (24) // Register B
931
+ #define TC_RC (28) // Register C
932
+ #define TC_SR (32) // Status Register
933
+ #define TC_IER (36) // Interrupt Enable Register
934
+ #define TC_IDR (40) // Interrupt Disable Register
935
+ #define TC_IMR (44) // Interrupt Mask Register
936
+ // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
937
+ #define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
938
+ #define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
939
+ #define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
940
+ // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
941
+ #define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
942
+ #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
943
+ #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
944
+ #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
945
+ #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
946
+ #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
947
+ #define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
948
+ #define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
949
+ #define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
950
+ #define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
951
+ #define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
952
+ #define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
953
+ #define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
954
+ #define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
955
+ #define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
956
+ #define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
957
+ #define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
958
+ #define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
959
+ #define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
960
+ #define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
961
+ #define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
962
+ #define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
963
+ #define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
964
+ #define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
965
+ #define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
966
+ #define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
967
+ #define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
968
+ #define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
969
+ #define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
970
+ #define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
971
+ #define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
972
+ #define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
973
+ #define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
974
+ #define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
975
+ #define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
976
+ #define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
977
+ #define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
978
+ #define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
979
+ #define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
980
+ #define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
981
+ #define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
982
+ #define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
983
+ #define AT91C_TC_WAVE (0x1 << 15) // (TC)
984
+ #define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
985
+ #define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
986
+ #define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
987
+ #define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
988
+ #define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
989
+ #define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
990
+ #define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
991
+ #define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
992
+ #define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
993
+ #define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
994
+ #define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
995
+ #define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
996
+ #define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
997
+ #define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
998
+ #define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
999
+ #define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
1000
+ #define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
1001
+ #define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
1002
+ #define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
1003
+ #define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
1004
+ #define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
1005
+ #define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
1006
+ #define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
1007
+ #define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
1008
+ #define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
1009
+ #define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
1010
+ #define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
1011
+ #define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
1012
+ #define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
1013
+ #define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
1014
+ #define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
1015
+ #define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
1016
+ #define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
1017
+ #define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
1018
+ #define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
1019
+ #define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
1020
+ #define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
1021
+ #define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
1022
+ #define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
1023
+ #define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
1024
+ #define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
1025
+ #define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
1026
+ #define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
1027
+ #define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
1028
+ #define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
1029
+ #define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
1030
+ #define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
1031
+ #define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
1032
+ #define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
1033
+ #define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
1034
+ // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
1035
+ #define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
1036
+ #define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
1037
+ #define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
1038
+ #define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
1039
+ #define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
1040
+ #define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
1041
+ #define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
1042
+ #define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
1043
+ #define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
1044
+ #define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
1045
+ #define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
1046
+ // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
1047
+ // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
1048
+ // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
1049
+
1050
+ // *****************************************************************************
1051
+ // SOFTWARE API DEFINITION FOR Timer Counter Interface
1052
+ // *****************************************************************************
1053
+ // *** Register offset in AT91S_TCB structure ***
1054
+ #define TCB_TC0 ( 0) // TC Channel 0
1055
+ #define TCB_TC1 (64) // TC Channel 1
1056
+ #define TCB_TC2 (128) // TC Channel 2
1057
+ #define TCB_BCR (192) // TC Block Control Register
1058
+ #define TCB_BMR (196) // TC Block Mode Register
1059
+ // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
1060
+ #define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
1061
+ // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
1062
+ #define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
1063
+ #define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
1064
+ #define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
1065
+ #define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
1066
+ #define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
1067
+ #define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
1068
+ #define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
1069
+ #define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
1070
+ #define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
1071
+ #define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
1072
+ #define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
1073
+ #define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
1074
+ #define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
1075
+ #define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
1076
+ #define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
1077
+
1078
+ // *****************************************************************************
1079
+ // SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
1080
+ // *****************************************************************************
1081
+ // *** Register offset in AT91S_CAN_MB structure ***
1082
+ #define CAN_MB_MMR ( 0) // MailBox Mode Register
1083
+ #define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register
1084
+ #define CAN_MB_MID ( 8) // MailBox ID Register
1085
+ #define CAN_MB_MFID (12) // MailBox Family ID Register
1086
+ #define CAN_MB_MSR (16) // MailBox Status Register
1087
+ #define CAN_MB_MDL (20) // MailBox Data Low Register
1088
+ #define CAN_MB_MDH (24) // MailBox Data High Register
1089
+ #define CAN_MB_MCR (28) // MailBox Control Register
1090
+ // -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
1091
+ #define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark
1092
+ #define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority
1093
+ #define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type
1094
+ #define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB)
1095
+ #define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB)
1096
+ #define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB)
1097
+ #define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB)
1098
+ #define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB)
1099
+ #define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB)
1100
+ // -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
1101
+ #define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
1102
+ #define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
1103
+ #define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version
1104
+ // -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
1105
+ // -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
1106
+ // -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
1107
+ #define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value
1108
+ #define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code
1109
+ #define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
1110
+ #define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort
1111
+ #define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready
1112
+ #define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
1113
+ // -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
1114
+ // -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
1115
+ // -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
1116
+ #define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
1117
+ #define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
1118
+
1119
+ // *****************************************************************************
1120
+ // SOFTWARE API DEFINITION FOR Control Area Network Interface
1121
+ // *****************************************************************************
1122
+ // *** Register offset in AT91S_CAN structure ***
1123
+ #define CAN_MR ( 0) // Mode Register
1124
+ #define CAN_IER ( 4) // Interrupt Enable Register
1125
+ #define CAN_IDR ( 8) // Interrupt Disable Register
1126
+ #define CAN_IMR (12) // Interrupt Mask Register
1127
+ #define CAN_SR (16) // Status Register
1128
+ #define CAN_BR (20) // Baudrate Register
1129
+ #define CAN_TIM (24) // Timer Register
1130
+ #define CAN_TIMESTP (28) // Time Stamp Register
1131
+ #define CAN_ECR (32) // Error Counter Register
1132
+ #define CAN_TCR (36) // Transfer Command Register
1133
+ #define CAN_ACR (40) // Abort Command Register
1134
+ #define CAN_VR (252) // Version Register
1135
+ #define CAN_MB0 (512) // CAN Mailbox 0
1136
+ #define CAN_MB1 (544) // CAN Mailbox 1
1137
+ #define CAN_MB2 (576) // CAN Mailbox 2
1138
+ #define CAN_MB3 (608) // CAN Mailbox 3
1139
+ #define CAN_MB4 (640) // CAN Mailbox 4
1140
+ #define CAN_MB5 (672) // CAN Mailbox 5
1141
+ #define CAN_MB6 (704) // CAN Mailbox 6
1142
+ #define CAN_MB7 (736) // CAN Mailbox 7
1143
+ #define CAN_MB8 (768) // CAN Mailbox 8
1144
+ #define CAN_MB9 (800) // CAN Mailbox 9
1145
+ #define CAN_MB10 (832) // CAN Mailbox 10
1146
+ #define CAN_MB11 (864) // CAN Mailbox 11
1147
+ #define CAN_MB12 (896) // CAN Mailbox 12
1148
+ #define CAN_MB13 (928) // CAN Mailbox 13
1149
+ #define CAN_MB14 (960) // CAN Mailbox 14
1150
+ #define CAN_MB15 (992) // CAN Mailbox 15
1151
+ // -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
1152
+ #define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable
1153
+ #define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode
1154
+ #define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
1155
+ #define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame
1156
+ #define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
1157
+ #define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
1158
+ #define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze
1159
+ #define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat
1160
+ // -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
1161
+ #define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag
1162
+ #define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag
1163
+ #define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag
1164
+ #define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag
1165
+ #define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag
1166
+ #define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag
1167
+ #define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag
1168
+ #define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag
1169
+ #define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag
1170
+ #define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag
1171
+ #define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag
1172
+ #define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag
1173
+ #define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag
1174
+ #define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag
1175
+ #define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag
1176
+ #define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag
1177
+ #define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag
1178
+ #define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag
1179
+ #define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag
1180
+ #define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag
1181
+ #define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag
1182
+ #define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag
1183
+ #define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag
1184
+ #define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag
1185
+ #define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error
1186
+ #define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error
1187
+ #define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error
1188
+ #define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error
1189
+ #define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error
1190
+ // -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
1191
+ // -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
1192
+ // -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
1193
+ #define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy
1194
+ #define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy
1195
+ #define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy
1196
+ // -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
1197
+ #define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment
1198
+ #define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment
1199
+ #define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment
1200
+ #define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment
1201
+ #define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler
1202
+ #define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode
1203
+ // -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
1204
+ #define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field
1205
+ // -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
1206
+ // -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
1207
+ #define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter
1208
+ #define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter
1209
+ // -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
1210
+ #define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field
1211
+ // -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
1212
+
1213
+ // *****************************************************************************
1214
+ // SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
1215
+ // *****************************************************************************
1216
+ // *** Register offset in AT91S_EMAC structure ***
1217
+ #define EMAC_NCR ( 0) // Network Control Register
1218
+ #define EMAC_NCFGR ( 4) // Network Configuration Register
1219
+ #define EMAC_NSR ( 8) // Network Status Register
1220
+ #define EMAC_TSR (20) // Transmit Status Register
1221
+ #define EMAC_RBQP (24) // Receive Buffer Queue Pointer
1222
+ #define EMAC_TBQP (28) // Transmit Buffer Queue Pointer
1223
+ #define EMAC_RSR (32) // Receive Status Register
1224
+ #define EMAC_ISR (36) // Interrupt Status Register
1225
+ #define EMAC_IER (40) // Interrupt Enable Register
1226
+ #define EMAC_IDR (44) // Interrupt Disable Register
1227
+ #define EMAC_IMR (48) // Interrupt Mask Register
1228
+ #define EMAC_MAN (52) // PHY Maintenance Register
1229
+ #define EMAC_PTR (56) // Pause Time Register
1230
+ #define EMAC_PFR (60) // Pause Frames received Register
1231
+ #define EMAC_FTO (64) // Frames Transmitted OK Register
1232
+ #define EMAC_SCF (68) // Single Collision Frame Register
1233
+ #define EMAC_MCF (72) // Multiple Collision Frame Register
1234
+ #define EMAC_FRO (76) // Frames Received OK Register
1235
+ #define EMAC_FCSE (80) // Frame Check Sequence Error Register
1236
+ #define EMAC_ALE (84) // Alignment Error Register
1237
+ #define EMAC_DTF (88) // Deferred Transmission Frame Register
1238
+ #define EMAC_LCOL (92) // Late Collision Register
1239
+ #define EMAC_ECOL (96) // Excessive Collision Register
1240
+ #define EMAC_TUND (100) // Transmit Underrun Error Register
1241
+ #define EMAC_CSE (104) // Carrier Sense Error Register
1242
+ #define EMAC_RRE (108) // Receive Ressource Error Register
1243
+ #define EMAC_ROV (112) // Receive Overrun Errors Register
1244
+ #define EMAC_RSE (116) // Receive Symbol Errors Register
1245
+ #define EMAC_ELE (120) // Excessive Length Errors Register
1246
+ #define EMAC_RJA (124) // Receive Jabbers Register
1247
+ #define EMAC_USF (128) // Undersize Frames Register
1248
+ #define EMAC_STE (132) // SQE Test Error Register
1249
+ #define EMAC_RLE (136) // Receive Length Field Mismatch Register
1250
+ #define EMAC_TPF (140) // Transmitted Pause Frames Register
1251
+ #define EMAC_HRB (144) // Hash Address Bottom[31:0]
1252
+ #define EMAC_HRT (148) // Hash Address Top[63:32]
1253
+ #define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes
1254
+ #define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes
1255
+ #define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes
1256
+ #define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes
1257
+ #define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes
1258
+ #define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes
1259
+ #define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes
1260
+ #define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes
1261
+ #define EMAC_TID (184) // Type ID Checking Register
1262
+ #define EMAC_TPQ (188) // Transmit Pause Quantum Register
1263
+ #define EMAC_USRIO (192) // USER Input/Output Register
1264
+ #define EMAC_WOL (196) // Wake On LAN Register
1265
+ #define EMAC_REV (252) // Revision Register
1266
+ // -------- EMAC_NCR : (EMAC Offset: 0x0) --------
1267
+ #define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
1268
+ #define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local.
1269
+ #define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable.
1270
+ #define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable.
1271
+ #define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable.
1272
+ #define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers.
1273
+ #define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers.
1274
+ #define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers.
1275
+ #define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure.
1276
+ #define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission.
1277
+ #define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt.
1278
+ #define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame
1279
+ #define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
1280
+ // -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
1281
+ #define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed.
1282
+ #define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex.
1283
+ #define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames.
1284
+ #define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames.
1285
+ #define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast.
1286
+ #define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable
1287
+ #define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable.
1288
+ #define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes.
1289
+ #define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable.
1290
+ #define AT91C_EMAC_CLK (0x3 << 10) // (EMAC)
1291
+ #define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8
1292
+ #define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16
1293
+ #define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32
1294
+ #define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64
1295
+ #define AT91C_EMAC_RTY (0x1 << 12) // (EMAC)
1296
+ #define AT91C_EMAC_PAE (0x1 << 13) // (EMAC)
1297
+ #define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC)
1298
+ #define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer
1299
+ #define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
1300
+ #define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
1301
+ #define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
1302
+ #define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable
1303
+ #define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS
1304
+ #define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC)
1305
+ #define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS
1306
+ // -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
1307
+ #define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC)
1308
+ #define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC)
1309
+ #define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC)
1310
+ // -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
1311
+ #define AT91C_EMAC_UBR (0x1 << 0) // (EMAC)
1312
+ #define AT91C_EMAC_COL (0x1 << 1) // (EMAC)
1313
+ #define AT91C_EMAC_RLES (0x1 << 2) // (EMAC)
1314
+ #define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go
1315
+ #define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame
1316
+ #define AT91C_EMAC_COMP (0x1 << 5) // (EMAC)
1317
+ #define AT91C_EMAC_UND (0x1 << 6) // (EMAC)
1318
+ // -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
1319
+ #define AT91C_EMAC_BNA (0x1 << 0) // (EMAC)
1320
+ #define AT91C_EMAC_REC (0x1 << 1) // (EMAC)
1321
+ #define AT91C_EMAC_OVR (0x1 << 2) // (EMAC)
1322
+ // -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
1323
+ #define AT91C_EMAC_MFD (0x1 << 0) // (EMAC)
1324
+ #define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC)
1325
+ #define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC)
1326
+ #define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC)
1327
+ #define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC)
1328
+ #define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC)
1329
+ #define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC)
1330
+ #define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC)
1331
+ #define AT91C_EMAC_LINK (0x1 << 9) // (EMAC)
1332
+ #define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC)
1333
+ #define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC)
1334
+ #define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC)
1335
+ #define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC)
1336
+ // -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
1337
+ // -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
1338
+ // -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
1339
+ // -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
1340
+ #define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC)
1341
+ #define AT91C_EMAC_CODE (0x3 << 16) // (EMAC)
1342
+ #define AT91C_EMAC_REGA (0x1F << 18) // (EMAC)
1343
+ #define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC)
1344
+ #define AT91C_EMAC_RW (0x3 << 28) // (EMAC)
1345
+ #define AT91C_EMAC_SOF (0x3 << 30) // (EMAC)
1346
+ // -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
1347
+ #define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII
1348
+ #define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable
1349
+ // -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
1350
+ #define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address
1351
+ #define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable
1352
+ #define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable
1353
+ #define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable
1354
+ // -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
1355
+ #define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC)
1356
+ #define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC)
1357
+
1358
+ // *****************************************************************************
1359
+ // SOFTWARE API DEFINITION FOR Analog to Digital Convertor
1360
+ // *****************************************************************************
1361
+ // *** Register offset in AT91S_ADC structure ***
1362
+ #define ADC_CR ( 0) // ADC Control Register
1363
+ #define ADC_MR ( 4) // ADC Mode Register
1364
+ #define ADC_CHER (16) // ADC Channel Enable Register
1365
+ #define ADC_CHDR (20) // ADC Channel Disable Register
1366
+ #define ADC_CHSR (24) // ADC Channel Status Register
1367
+ #define ADC_SR (28) // ADC Status Register
1368
+ #define ADC_LCDR (32) // ADC Last Converted Data Register
1369
+ #define ADC_IER (36) // ADC Interrupt Enable Register
1370
+ #define ADC_IDR (40) // ADC Interrupt Disable Register
1371
+ #define ADC_IMR (44) // ADC Interrupt Mask Register
1372
+ #define ADC_CDR0 (48) // ADC Channel Data Register 0
1373
+ #define ADC_CDR1 (52) // ADC Channel Data Register 1
1374
+ #define ADC_CDR2 (56) // ADC Channel Data Register 2
1375
+ #define ADC_CDR3 (60) // ADC Channel Data Register 3
1376
+ #define ADC_CDR4 (64) // ADC Channel Data Register 4
1377
+ #define ADC_CDR5 (68) // ADC Channel Data Register 5
1378
+ #define ADC_CDR6 (72) // ADC Channel Data Register 6
1379
+ #define ADC_CDR7 (76) // ADC Channel Data Register 7
1380
+ #define ADC_RPR (256) // Receive Pointer Register
1381
+ #define ADC_RCR (260) // Receive Counter Register
1382
+ #define ADC_TPR (264) // Transmit Pointer Register
1383
+ #define ADC_TCR (268) // Transmit Counter Register
1384
+ #define ADC_RNPR (272) // Receive Next Pointer Register
1385
+ #define ADC_RNCR (276) // Receive Next Counter Register
1386
+ #define ADC_TNPR (280) // Transmit Next Pointer Register
1387
+ #define ADC_TNCR (284) // Transmit Next Counter Register
1388
+ #define ADC_PTCR (288) // PDC Transfer Control Register
1389
+ #define ADC_PTSR (292) // PDC Transfer Status Register
1390
+ // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
1391
+ #define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
1392
+ #define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
1393
+ // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
1394
+ #define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
1395
+ #define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
1396
+ #define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
1397
+ #define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
1398
+ #define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
1399
+ #define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
1400
+ #define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
1401
+ #define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
1402
+ #define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
1403
+ #define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
1404
+ #define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
1405
+ #define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
1406
+ #define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
1407
+ #define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
1408
+ #define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
1409
+ #define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
1410
+ #define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
1411
+ #define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
1412
+ #define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
1413
+ #define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
1414
+ // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
1415
+ #define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
1416
+ #define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
1417
+ #define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
1418
+ #define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
1419
+ #define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
1420
+ #define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
1421
+ #define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
1422
+ #define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
1423
+ // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
1424
+ // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
1425
+ // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
1426
+ #define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
1427
+ #define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
1428
+ #define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
1429
+ #define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
1430
+ #define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
1431
+ #define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
1432
+ #define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
1433
+ #define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
1434
+ #define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
1435
+ #define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
1436
+ #define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
1437
+ #define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
1438
+ #define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
1439
+ #define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
1440
+ #define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
1441
+ #define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
1442
+ #define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
1443
+ #define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
1444
+ #define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
1445
+ #define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
1446
+ // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
1447
+ #define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
1448
+ // -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
1449
+ // -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
1450
+ // -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
1451
+ // -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
1452
+ #define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
1453
+ // -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
1454
+ // -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
1455
+ // -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
1456
+ // -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
1457
+ // -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
1458
+ // -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
1459
+ // -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
1460
+
1461
+ // *****************************************************************************
1462
+ // REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
1463
+ // *****************************************************************************
1464
+ // ========== Register definition for SYS peripheral ==========
1465
+ // ========== Register definition for AIC peripheral ==========
1466
+ #define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register
1467
+ #define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register
1468
+ #define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register
1469
+ #define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register
1470
+ #define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register
1471
+ #define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect)
1472
+ #define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register
1473
+ #define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register
1474
+ #define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register
1475
+ #define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register
1476
+ #define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register
1477
+ #define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register
1478
+ #define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register
1479
+ #define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register
1480
+ #define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register
1481
+ #define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register
1482
+ #define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register
1483
+ #define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register
1484
+ // ========== Register definition for PDC_DBGU peripheral ==========
1485
+ #define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
1486
+ #define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
1487
+ #define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
1488
+ #define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
1489
+ #define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
1490
+ #define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
1491
+ #define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
1492
+ #define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
1493
+ #define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
1494
+ #define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
1495
+ // ========== Register definition for DBGU peripheral ==========
1496
+ #define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register
1497
+ #define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register
1498
+ #define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register
1499
+ #define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register
1500
+ #define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register
1501
+ #define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register
1502
+ #define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register
1503
+ #define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register
1504
+ #define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register
1505
+ #define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register
1506
+ #define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register
1507
+ #define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register
1508
+ // ========== Register definition for PIOA peripheral ==========
1509
+ #define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register
1510
+ #define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register
1511
+ #define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register
1512
+ #define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register
1513
+ #define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register
1514
+ #define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register
1515
+ #define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register
1516
+ #define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register
1517
+ #define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register
1518
+ #define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register
1519
+ #define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register
1520
+ #define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register
1521
+ #define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register
1522
+ #define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register
1523
+ #define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr
1524
+ #define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register
1525
+ #define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register
1526
+ #define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register
1527
+ #define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register
1528
+ #define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register
1529
+ #define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register
1530
+ #define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register
1531
+ #define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register
1532
+ #define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register
1533
+ #define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register
1534
+ #define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register
1535
+ #define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register
1536
+ #define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register
1537
+ #define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register
1538
+ // ========== Register definition for PIOB peripheral ==========
1539
+ #define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register
1540
+ #define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register
1541
+ #define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register
1542
+ #define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register
1543
+ #define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register
1544
+ #define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register
1545
+ #define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register
1546
+ #define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register
1547
+ #define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register
1548
+ #define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register
1549
+ #define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register
1550
+ #define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register
1551
+ #define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register
1552
+ #define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr
1553
+ #define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register
1554
+ #define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register
1555
+ #define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register
1556
+ #define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register
1557
+ #define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register
1558
+ #define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register
1559
+ #define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register
1560
+ #define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register
1561
+ #define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register
1562
+ #define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register
1563
+ #define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register
1564
+ #define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register
1565
+ #define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register
1566
+ #define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register
1567
+ #define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register
1568
+ // ========== Register definition for CKGR peripheral ==========
1569
+ #define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register
1570
+ #define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register
1571
+ #define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register
1572
+ // ========== Register definition for PMC peripheral ==========
1573
+ #define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register
1574
+ #define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register
1575
+ #define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register
1576
+ #define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register
1577
+ #define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
1578
+ #define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register
1579
+ #define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register
1580
+ #define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register
1581
+ #define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register
1582
+ #define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register
1583
+ #define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
1584
+ #define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
1585
+ #define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register
1586
+ #define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register
1587
+ #define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register
1588
+ // ========== Register definition for RSTC peripheral ==========
1589
+ #define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register
1590
+ #define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register
1591
+ #define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register
1592
+ // ========== Register definition for RTTC peripheral ==========
1593
+ #define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register
1594
+ #define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register
1595
+ #define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register
1596
+ #define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register
1597
+ // ========== Register definition for PITC peripheral ==========
1598
+ #define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register
1599
+ #define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register
1600
+ #define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register
1601
+ #define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register
1602
+ // ========== Register definition for WDTC peripheral ==========
1603
+ #define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register
1604
+ #define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register
1605
+ #define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register
1606
+ // ========== Register definition for VREG peripheral ==========
1607
+ #define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
1608
+ // ========== Register definition for MC peripheral ==========
1609
+ #define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register
1610
+ #define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register
1611
+ #define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register
1612
+ #define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register
1613
+ #define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register
1614
+ #define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register
1615
+ // ========== Register definition for PDC_SPI1 peripheral ==========
1616
+ #define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
1617
+ #define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
1618
+ #define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
1619
+ #define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
1620
+ #define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register
1621
+ #define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
1622
+ #define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
1623
+ #define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
1624
+ #define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
1625
+ #define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
1626
+ // ========== Register definition for SPI1 peripheral ==========
1627
+ #define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register
1628
+ #define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register
1629
+ #define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register
1630
+ #define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register
1631
+ #define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register
1632
+ #define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register
1633
+ #define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register
1634
+ #define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register
1635
+ #define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register
1636
+ // ========== Register definition for PDC_SPI0 peripheral ==========
1637
+ #define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
1638
+ #define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
1639
+ #define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
1640
+ #define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
1641
+ #define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
1642
+ #define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
1643
+ #define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
1644
+ #define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
1645
+ #define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
1646
+ #define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register
1647
+ // ========== Register definition for SPI0 peripheral ==========
1648
+ #define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register
1649
+ #define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register
1650
+ #define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register
1651
+ #define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register
1652
+ #define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register
1653
+ #define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register
1654
+ #define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register
1655
+ #define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register
1656
+ #define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register
1657
+ // ========== Register definition for PDC_US1 peripheral ==========
1658
+ #define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
1659
+ #define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
1660
+ #define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
1661
+ #define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register
1662
+ #define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register
1663
+ #define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
1664
+ #define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
1665
+ #define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
1666
+ #define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
1667
+ #define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register
1668
+ // ========== Register definition for US1 peripheral ==========
1669
+ #define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register
1670
+ #define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register
1671
+ #define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register
1672
+ #define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register
1673
+ #define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register
1674
+ #define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register
1675
+ #define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register
1676
+ #define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register
1677
+ #define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register
1678
+ #define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register
1679
+ #define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register
1680
+ #define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register
1681
+ #define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register
1682
+ #define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register
1683
+ // ========== Register definition for PDC_US0 peripheral ==========
1684
+ #define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
1685
+ #define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
1686
+ #define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
1687
+ #define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
1688
+ #define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register
1689
+ #define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
1690
+ #define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
1691
+ #define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
1692
+ #define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register
1693
+ #define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register
1694
+ // ========== Register definition for US0 peripheral ==========
1695
+ #define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register
1696
+ #define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register
1697
+ #define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register
1698
+ #define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register
1699
+ #define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register
1700
+ #define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register
1701
+ #define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register
1702
+ #define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register
1703
+ #define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register
1704
+ #define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register
1705
+ #define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register
1706
+ #define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register
1707
+ #define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register
1708
+ #define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register
1709
+ // ========== Register definition for PDC_SSC peripheral ==========
1710
+ #define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
1711
+ #define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
1712
+ #define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
1713
+ #define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
1714
+ #define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
1715
+ #define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
1716
+ #define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
1717
+ #define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
1718
+ #define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
1719
+ #define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register
1720
+ // ========== Register definition for SSC peripheral ==========
1721
+ #define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register
1722
+ #define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register
1723
+ #define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register
1724
+ #define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register
1725
+ #define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register
1726
+ #define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register
1727
+ #define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register
1728
+ #define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister
1729
+ #define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register
1730
+ #define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register
1731
+ #define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register
1732
+ #define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register
1733
+ #define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register
1734
+ #define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register
1735
+ // ========== Register definition for TWI peripheral ==========
1736
+ #define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register
1737
+ #define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register
1738
+ #define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register
1739
+ #define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register
1740
+ #define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register
1741
+ #define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register
1742
+ #define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register
1743
+ #define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register
1744
+ #define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register
1745
+ #define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register
1746
+ // ========== Register definition for PWMC_CH3 peripheral ==========
1747
+ #define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register
1748
+ #define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register
1749
+ #define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
1750
+ #define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved
1751
+ #define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
1752
+ #define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
1753
+ // ========== Register definition for PWMC_CH2 peripheral ==========
1754
+ #define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register
1755
+ #define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register
1756
+ #define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
1757
+ #define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved
1758
+ #define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
1759
+ #define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
1760
+ // ========== Register definition for PWMC_CH1 peripheral ==========
1761
+ #define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register
1762
+ #define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register
1763
+ #define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
1764
+ #define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved
1765
+ #define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
1766
+ #define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
1767
+ // ========== Register definition for PWMC_CH0 peripheral ==========
1768
+ #define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register
1769
+ #define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register
1770
+ #define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
1771
+ #define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved
1772
+ #define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
1773
+ #define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
1774
+ // ========== Register definition for PWMC peripheral ==========
1775
+ #define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register
1776
+ #define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
1777
+ #define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
1778
+ #define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register
1779
+ #define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register
1780
+ #define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
1781
+ #define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register
1782
+ #define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register
1783
+ #define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
1784
+ // ========== Register definition for UDP peripheral ==========
1785
+ #define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register
1786
+ #define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register
1787
+ #define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register
1788
+ #define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register
1789
+ #define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register
1790
+ #define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register
1791
+ #define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register
1792
+ #define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register
1793
+ #define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register
1794
+ #define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register
1795
+ #define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register
1796
+ #define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
1797
+ // ========== Register definition for TC0 peripheral ==========
1798
+ #define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register
1799
+ #define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register
1800
+ #define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C
1801
+ #define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A
1802
+ #define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
1803
+ #define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register
1804
+ #define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register
1805
+ #define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B
1806
+ #define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value
1807
+ #define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register
1808
+ // ========== Register definition for TC1 peripheral ==========
1809
+ #define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register
1810
+ #define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register
1811
+ #define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C
1812
+ #define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A
1813
+ #define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
1814
+ #define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register
1815
+ #define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register
1816
+ #define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B
1817
+ #define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value
1818
+ #define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register
1819
+ // ========== Register definition for TC2 peripheral ==========
1820
+ #define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register
1821
+ #define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register
1822
+ #define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C
1823
+ #define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A
1824
+ #define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
1825
+ #define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register
1826
+ #define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register
1827
+ #define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B
1828
+ #define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value
1829
+ #define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register
1830
+ // ========== Register definition for TCB peripheral ==========
1831
+ #define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register
1832
+ #define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register
1833
+ // ========== Register definition for CAN_MB0 peripheral ==========
1834
+ #define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register
1835
+ #define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
1836
+ #define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
1837
+ #define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
1838
+ #define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register
1839
+ #define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register
1840
+ #define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register
1841
+ #define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register
1842
+ // ========== Register definition for CAN_MB1 peripheral ==========
1843
+ #define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register
1844
+ #define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
1845
+ #define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
1846
+ #define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
1847
+ #define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register
1848
+ #define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register
1849
+ #define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register
1850
+ #define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register
1851
+ // ========== Register definition for CAN_MB2 peripheral ==========
1852
+ #define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register
1853
+ #define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
1854
+ #define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
1855
+ #define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
1856
+ #define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register
1857
+ #define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register
1858
+ #define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register
1859
+ #define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register
1860
+ // ========== Register definition for CAN_MB3 peripheral ==========
1861
+ #define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register
1862
+ #define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
1863
+ #define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
1864
+ #define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
1865
+ #define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register
1866
+ #define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register
1867
+ #define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register
1868
+ #define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register
1869
+ // ========== Register definition for CAN_MB4 peripheral ==========
1870
+ #define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register
1871
+ #define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
1872
+ #define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
1873
+ #define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
1874
+ #define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register
1875
+ #define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register
1876
+ #define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register
1877
+ #define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register
1878
+ // ========== Register definition for CAN_MB5 peripheral ==========
1879
+ #define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register
1880
+ #define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
1881
+ #define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
1882
+ #define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
1883
+ #define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
1884
+ #define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register
1885
+ #define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register
1886
+ #define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
1887
+ // ========== Register definition for CAN_MB6 peripheral ==========
1888
+ #define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
1889
+ #define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
1890
+ #define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register
1891
+ #define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register
1892
+ #define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
1893
+ #define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register
1894
+ #define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
1895
+ #define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
1896
+ // ========== Register definition for CAN_MB7 peripheral ==========
1897
+ #define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
1898
+ #define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register
1899
+ #define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register
1900
+ #define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
1901
+ #define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register
1902
+ #define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
1903
+ #define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
1904
+ #define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
1905
+ // ========== Register definition for CAN peripheral ==========
1906
+ #define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register
1907
+ #define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register
1908
+ #define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register
1909
+ #define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register
1910
+ #define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register
1911
+ #define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register
1912
+ #define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register
1913
+ #define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register
1914
+ #define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register
1915
+ #define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register
1916
+ #define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register
1917
+ #define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register
1918
+ // ========== Register definition for EMAC peripheral ==========
1919
+ #define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register
1920
+ #define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
1921
+ #define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register
1922
+ #define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register
1923
+ #define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register
1924
+ #define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
1925
+ #define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
1926
+ #define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
1927
+ #define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
1928
+ #define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register
1929
+ #define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
1930
+ #define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register
1931
+ #define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
1932
+ #define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register
1933
+ #define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register
1934
+ #define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register
1935
+ #define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register
1936
+ #define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
1937
+ #define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register
1938
+ #define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register
1939
+ #define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
1940
+ #define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register
1941
+ #define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register
1942
+ #define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
1943
+ #define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register
1944
+ #define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register
1945
+ #define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
1946
+ #define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register
1947
+ #define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register
1948
+ #define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register
1949
+ #define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register
1950
+ #define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
1951
+ #define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register
1952
+ #define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32]
1953
+ #define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register
1954
+ #define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register
1955
+ #define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
1956
+ #define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register
1957
+ #define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register
1958
+ #define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register
1959
+ #define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
1960
+ #define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register
1961
+ #define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register
1962
+ #define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
1963
+ #define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register
1964
+ #define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register
1965
+ #define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register
1966
+ #define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
1967
+ #define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register
1968
+ // ========== Register definition for PDC_ADC peripheral ==========
1969
+ #define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
1970
+ #define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
1971
+ #define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
1972
+ #define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
1973
+ #define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
1974
+ #define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
1975
+ #define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
1976
+ #define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
1977
+ #define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
1978
+ #define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register
1979
+ // ========== Register definition for ADC peripheral ==========
1980
+ #define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
1981
+ #define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4
1982
+ #define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2
1983
+ #define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0
1984
+ #define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7
1985
+ #define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1
1986
+ #define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3
1987
+ #define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5
1988
+ #define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register
1989
+ #define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6
1990
+ #define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register
1991
+ #define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register
1992
+ #define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register
1993
+ #define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
1994
+ #define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register
1995
+ #define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register
1996
+ #define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
1997
+ #define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register
1998
+
1999
+ // *****************************************************************************
2000
+ // PIO DEFINITIONS FOR AT91SAM7X256
2001
+ // *****************************************************************************
2002
+ #define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
2003
+ #define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data
2004
+ #define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
2005
+ #define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data
2006
+ #define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
2007
+ #define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data
2008
+ #define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
2009
+ #define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock
2010
+ #define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
2011
+ #define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
2012
+ #define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
2013
+ #define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
2014
+ #define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1
2015
+ #define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
2016
+ #define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
2017
+ #define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1
2018
+ #define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
2019
+ #define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
2020
+ #define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input
2021
+ #define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
2022
+ #define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave
2023
+ #define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
2024
+ #define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave
2025
+ #define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
2026
+ #define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock
2027
+ #define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
2028
+ #define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive
2029
+ #define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
2030
+ #define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
2031
+ #define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
2032
+ #define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
2033
+ #define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit
2034
+ #define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
2035
+ #define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync
2036
+ #define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
2037
+ #define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
2038
+ #define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock
2039
+ #define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock
2040
+ #define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
2041
+ #define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data
2042
+ #define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave
2043
+ #define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
2044
+ #define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data
2045
+ #define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave
2046
+ #define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
2047
+ #define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock
2048
+ #define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
2049
+ #define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
2050
+ #define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync
2051
+ #define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
2052
+ #define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
2053
+ #define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data
2054
+ #define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3
2055
+ #define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
2056
+ #define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data
2057
+ #define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
2058
+ #define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input
2059
+ #define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
2060
+ #define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
2061
+ #define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send
2062
+ #define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
2063
+ #define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
2064
+ #define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0
2065
+ #define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2
2066
+ #define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
2067
+ #define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send
2068
+ #define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
2069
+ #define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
2070
+ #define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data
2071
+ #define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
2072
+ #define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data
2073
+ #define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
2074
+ #define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock
2075
+ #define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
2076
+ #define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
2077
+ #define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send
2078
+ #define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
2079
+ #define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
2080
+ #define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send
2081
+ #define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
2082
+ #define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
2083
+ #define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
2084
+ #define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0
2085
+ #define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
2086
+ #define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
2087
+ #define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
2088
+ #define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
2089
+ #define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
2090
+ #define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
2091
+ #define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
2092
+ #define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
2093
+ #define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
2094
+ #define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
2095
+ #define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input
2096
+ #define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
2097
+ #define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
2098
+ #define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
2099
+ #define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
2100
+ #define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
2101
+ #define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
2102
+ #define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
2103
+ #define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
2104
+ #define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
2105
+ #define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected
2106
+ #define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
2107
+ #define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
2108
+ #define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock
2109
+ #define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
2110
+ #define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
2111
+ #define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
2112
+ #define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger
2113
+ #define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
2114
+ #define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0
2115
+ #define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input
2116
+ #define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
2117
+ #define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
2118
+ #define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
2119
+ #define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1
2120
+ #define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0
2121
+ #define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
2122
+ #define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2
2123
+ #define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1
2124
+ #define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
2125
+ #define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3
2126
+ #define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2
2127
+ #define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
2128
+ #define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
2129
+ #define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect
2130
+ #define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
2131
+ #define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
2132
+ #define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready
2133
+ #define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
2134
+ #define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
2135
+ #define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready
2136
+ #define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
2137
+ #define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
2138
+ #define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator
2139
+ #define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
2140
+ #define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
2141
+ #define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0
2142
+ #define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
2143
+ #define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
2144
+ #define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1
2145
+ #define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
2146
+ #define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1
2147
+ #define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2
2148
+ #define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
2149
+ #define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
2150
+ #define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
2151
+ #define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2
2152
+ #define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3
2153
+ #define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
2154
+ #define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
2155
+ #define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
2156
+ #define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
2157
+ #define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
2158
+ #define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
2159
+ #define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
2160
+ #define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error
2161
+ #define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
2162
+ #define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
2163
+ #define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
2164
+ #define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
2165
+
2166
+ // *****************************************************************************
2167
+ // PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
2168
+ // *****************************************************************************
2169
+ #define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
2170
+ #define AT91C_ID_SYS ( 1) // System Peripheral
2171
+ #define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
2172
+ #define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
2173
+ #define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0
2174
+ #define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1
2175
+ #define AT91C_ID_US0 ( 6) // USART 0
2176
+ #define AT91C_ID_US1 ( 7) // USART 1
2177
+ #define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
2178
+ #define AT91C_ID_TWI ( 9) // Two-Wire Interface
2179
+ #define AT91C_ID_PWMC (10) // PWM Controller
2180
+ #define AT91C_ID_UDP (11) // USB Device Port
2181
+ #define AT91C_ID_TC0 (12) // Timer Counter 0
2182
+ #define AT91C_ID_TC1 (13) // Timer Counter 1
2183
+ #define AT91C_ID_TC2 (14) // Timer Counter 2
2184
+ #define AT91C_ID_CAN (15) // Control Area Network Controller
2185
+ #define AT91C_ID_EMAC (16) // Ethernet MAC
2186
+ #define AT91C_ID_ADC (17) // Analog-to-Digital Converter
2187
+ #define AT91C_ID_18_Reserved (18) // Reserved
2188
+ #define AT91C_ID_19_Reserved (19) // Reserved
2189
+ #define AT91C_ID_20_Reserved (20) // Reserved
2190
+ #define AT91C_ID_21_Reserved (21) // Reserved
2191
+ #define AT91C_ID_22_Reserved (22) // Reserved
2192
+ #define AT91C_ID_23_Reserved (23) // Reserved
2193
+ #define AT91C_ID_24_Reserved (24) // Reserved
2194
+ #define AT91C_ID_25_Reserved (25) // Reserved
2195
+ #define AT91C_ID_26_Reserved (26) // Reserved
2196
+ #define AT91C_ID_27_Reserved (27) // Reserved
2197
+ #define AT91C_ID_28_Reserved (28) // Reserved
2198
+ #define AT91C_ID_29_Reserved (29) // Reserved
2199
+ #define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
2200
+ #define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
2201
+ #define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS
2202
+
2203
+ // *****************************************************************************
2204
+ // BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
2205
+ // *****************************************************************************
2206
+ #define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address
2207
+ #define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address
2208
+ #define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address
2209
+ #define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address
2210
+ #define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address
2211
+ #define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address
2212
+ #define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address
2213
+ #define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address
2214
+ #define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address
2215
+ #define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address
2216
+ #define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address
2217
+ #define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address
2218
+ #define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address
2219
+ #define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address
2220
+ #define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address
2221
+ #define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address
2222
+ #define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address
2223
+ #define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address
2224
+ #define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address
2225
+ #define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
2226
+ #define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address
2227
+ #define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
2228
+ #define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address
2229
+ #define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address
2230
+ #define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address
2231
+ #define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address
2232
+ #define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address
2233
+ #define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address
2234
+ #define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address
2235
+ #define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address
2236
+ #define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address
2237
+ #define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address
2238
+ #define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address
2239
+ #define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address
2240
+ #define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address
2241
+ #define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address
2242
+ #define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address
2243
+ #define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address
2244
+ #define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address
2245
+ #define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address
2246
+ #define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address
2247
+ #define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address
2248
+ #define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address
2249
+ #define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address
2250
+ #define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address
2251
+ #define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address
2252
+ #define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address
2253
+
2254
+ // *****************************************************************************
2255
+ // MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
2256
+ // *****************************************************************************
2257
+ // ISRAM
2258
+ #define AT91C_ISRAM (0x00200000) // Internal SRAM base address
2259
+ #define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes)
2260
+ // IFLASH
2261
+ #define AT91C_IFLASH (0x00100000) // Internal FLASH base address
2262
+ #define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes)
2263
+ #define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes
2264
+ #define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes
2265
+ #define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes
2266
+ #define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes
2267
+
2268
+