ceedling 0.0.1

data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/Resource/SAM7_FLASH.mac

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+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+//  File Name           : SAM7_FLASH.mac
+//  Object              : Generic Macro File for IAR
+//  1.0 17/Aug/05 FBr   : Creation
+//  ----------------------------------------------------------------------------
+
+/*********************************************************************
+*
+*       _InitRSTC()
+*
+* Function description
+*   Initializes the RSTC (Reset controller).
+*   This makes sense since the default is to not allow user resets, which makes it impossible to
+*   apply a second RESET via J-Link
+*/
+_InitRSTC() {
+    __writeMemory32(0xA5000001, 0xFFFFFD08,"Memory");    // Allow user reset
+}
+
+/*********************************************************************
+*
+*       _InitPLL()
+* Function description
+*   Initializes the PMC.
+*   1. Enable the Main Oscillator
+*   2. Configure PLL to 96MHz
+*   3. Switch Master Clock (MCK) on PLL/2 = 48MHz
+*/
+    _InitPLL() {
+
+    __message "Enable Main Oscillator";
+    __writeMemory32(0x00000601,0xFFFFFc20,"Memory");    // MOSC
+    while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x1)  );
+
+    __message "Set PLL to 96MHz";
+    __writeMemory32(0x10191c05,0xFFFFFc2c,"Memory");    // LOCK
+    while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x4)  );
+
+    __message "Set Master Clock to 48MHz";
+    __writeMemory32(0x00000004,0xFFFFFc30,"Memory");    // MCKRDY
+    while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x8)  );
+    __writeMemory32(0x00000007,0xFFFFFc30,"Memory");    // MCKRDY
+    while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x8)  );
+}
+
+/*********************************************************************
+*
+*       execUserReset() : JTAG set initially to Full Speed
+*/
+execUserReset() {
+    __message "execUserReset()";
+    __emulatorSpeed(30000);             // Set JTAG speed to 30kHz to make a hardware reset
+    __hwReset(0);                       // Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
+    _InitPLL();                         // Allow to debug at JTAG Full Speed
+    _InitRSTC();                        // Enable User Reset to allow execUserReset() execution
+    __emulatorSpeed(0);                 // Set JTAG speed to full speed
+}
+

data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/Resource/SAM7_RAM.mac

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+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+//  File Name           : SAM7_RAM.mac
+//  Object              : Generic Macro File for IAR
+//  1.0 17/Aug/05 FBr   : Creation
+//  ----------------------------------------------------------------------------
+
+/*********************************************************************
+*
+*       _MapRAMAt0()
+*
+* Function description
+*   Maps RAM at 0.
+*/
+_MapRAMAt0(){
+    __message "Changing mapping: RAM mapped to 0";
+    __writeMemory32(0x00000001,0xFFFFFF00,"Memory");
+}
+
+/*********************************************************************
+*
+*       _InitRSTC()
+*
+* Function description
+*   Initializes the RSTC (Reset controller).
+*   This makes sense since the default is to not allow user resets, which makes it impossible to
+*   apply a second RESET via J-Link
+*/
+_InitRSTC() {
+    __writeMemory32(0xA5000001, 0xFFFFFD08,"Memory");    // Allow user reset
+}
+
+/*********************************************************************
+*
+*       _InitPLL()
+* Function description
+*   Initializes the PMC.
+*   1. Enable the Main Oscillator
+*   2. Configure PLL to 96MHz
+*   3. Switch Master Clock (MCK) on PLL/2 = 48MHz
+*/
+    _InitPLL() {
+
+    __message "Set Main Oscillator";
+    __writeMemory32(0x00004001,0xFFFFFc20,"Memory");    // MOSC
+    while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x1)  );
+
+    __message "Set PLL to 96MHz";
+    __writeMemory32(0x10483f0e,0xFFFFFc2c,"Memory");    // LOCK
+    while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x4)  );
+
+    __message "Set Master Clock to 48MHz";
+    __writeMemory32(0x00000004,0xFFFFFc30,"Memory");    // MCKRDY
+    while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x8)  );
+    __writeMemory32(0x00000007,0xFFFFFc30,"Memory");    // MCKRDY
+    while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x8)  );
+}
+
+/*********************************************************************
+*
+*       execUserReset() : JTAG set initially to Full Speed
+*/
+execUserReset() {
+    __message "execUserReset()";
+    __emulatorSpeed(30000);             // Set JTAG speed to 30kHz to make a hardware reset
+    __hwReset(0);                       // Hardware Reset: CPU is automatically halted after the reset
+    _InitPLL();                         // Allow to debug at JTAG Full Speed
+    _MapRAMAt0();                       // Remap RAM to address 0
+    __emulatorSpeed(0);                 // Set JTAG speed to full speed
+}
+
+/*********************************************************************
+*
+*       execUserPreload() : JTAG set initially to 32kHz
+*/
+execUserPreload() {
+    __message "execUserPreload()";
+    __hwReset(0);                       // Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
+    _InitPLL();                         // Allow to load Code at JTAG Full Speed
+    _MapRAMAt0();                       // Remap RAM to address 0
+    _InitRSTC();                        // Enable User Reset to allow execUserReset() execution
+}

data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/Resource/SAM7_SIM.mac

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+//=========================================================
+// Simulation setup file for esc07_demo project
+//=========================================================
+
+__var _timer0_interrupt_ID;
+
+irqBreak()
+{
+  __var __AIC_SMR;
+  __var __AIC_IECR;
+  __var __AIC_IVR;
+
+  // read AIC_IECR instead, since not fully supported by simulator
+  __AIC_IECR = __readMemory32(0xFFFFF120, "Memory");
+  if(__AIC_IECR & 0x1000)
+  {
+    __AIC_SMR = __readMemory32(0xFFFFF060, "Memory");
+    __AIC_IVR = __readMemory32(0xFFFFF0B0, "Memory"); //AIC_IVR = AIC_SVR[x]
+    __writeMemory32(__AIC_IVR, 0xFFFFF100, "Memory"); //AIC_IVR
+    __writeMemory32(0x1000, 0xFFFFF10C, "Memory");    //AIC_IPR
+    __writeMemory32(0x2, 0xFFFFF114, "Memory");       //AIC_CISR
+  }
+
+  return 0;
+}
+
+setupProcessorRegisters()
+{
+  // Write TC0_SR.CPCS with correct status for ISR (Clock enabled; RC Compare Flag = TRUE)
+  __writeMemory32(0x00010010, 0xfffa0020, "Memory");
+
+  // Set TX ready flag in USART0 status register
+  // USART0_BASE->US_CSR = AT91C_US_TXRDY
+  __writeMemory32(0x00000002, 0xfffc0014, "Memory");
+}
+
+configureTimer0Interrupt()
+{
+  __var _master_clock_frequency;
+  __var _timer0_period_cycles;
+
+  // Calculate timer0 frequency in master clock cycles
+  _master_clock_frequency = 48054857;
+  _timer0_period_cycles = _master_clock_frequency / 100;
+  if((_master_clock_frequency % 100) >= 50)
+  {
+    _timer0_period_cycles++;
+  }
+
+  __cancelAllInterrupts();
+  __enableInterrupts();
+
+  _timer0_interrupt_ID = __orderInterrupt("IRQ", _timer0_period_cycles, _timer0_period_cycles, 0, 0, 0, 100);
+
+  if(-1 == _timer0_interrupt_ID)
+  {
+    __message "ERROR: failed to order timer 0 interrupt";
+  }
+
+  __setCodeBreak("0x18", 0, "irqBreak()", "TRUE", "");
+}
+
+execUserReset()
+{
+  setupProcessorRegisters();
+  configureTimer0Interrupt();
+}

data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/Resource/at91SAM7X256_FLASH.icf

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+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__      = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__  = 0x00000100;
+define symbol __ICFEDIT_region_ROM_end__    = 0x0003FFFF;
+define symbol __ICFEDIT_region_RAM_start__  = 0x00200000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x0020FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_svcstack__ = 0x100;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x40;
+define symbol __ICFEDIT_size_undstack__ = 0x40;
+define symbol __ICFEDIT_size_abtstack__ = 0x40;
+define symbol __ICFEDIT_size_heap__     = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__    { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+                        block UND_STACK, block ABT_STACK, block HEAP };
+

data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/Resource/at91SAM7X256_RAM.icf

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+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__      = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__  = 0x00;
+define symbol __ICFEDIT_region_ROM_end__    = 0x00;
+define symbol __ICFEDIT_region_RAM_start__  = 0x00000100;
+define symbol __ICFEDIT_region_RAM_end__    = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_svcstack__ = 0x100;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x40;
+define symbol __ICFEDIT_size_undstack__ = 0x40;
+define symbol __ICFEDIT_size_abtstack__ = 0x40;
+define symbol __ICFEDIT_size_heap__     = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__    { readonly section .intvec };
+
+place in RAM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+                        block UND_STACK, block ABT_STACK, block HEAP };
+