ceedling 0.0.1

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Files changed (991) hide show
  1. data/.gitignore +4 -0
  2. data/.vim +1 -0
  3. data/Gemfile +3 -0
  4. data/LICENSE +19 -0
  5. data/Rakefile +18 -0
  6. data/bin/ceedling +39 -0
  7. data/ceedling.gemspec +23 -0
  8. data/lib/ceedling/version.rb +10 -0
  9. data/lib/ceedling/version.rb.erb +10 -0
  10. data/lib/ceedling.rb +5 -0
  11. data/new_project_template/build/.gitkeep +0 -0
  12. data/new_project_template/project.yml +65 -0
  13. data/new_project_template/rakefile.rb +4 -0
  14. data/new_project_template/src/.gitkeep +0 -0
  15. data/new_project_template/test/.gitkeep +0 -0
  16. data/new_project_template/test/support/.gitkeep +0 -0
  17. data/new_project_template/vendor/ceedling/config/test_environment.rb +12 -0
  18. data/new_project_template/vendor/ceedling/docs/Ceedling Packet.odt +0 -0
  19. data/new_project_template/vendor/ceedling/docs/Ceedling Packet.pdf +0 -0
  20. data/new_project_template/vendor/ceedling/docs/CeedlingLogo.png +0 -0
  21. data/new_project_template/vendor/ceedling/examples/temp_sensor/gcc.yml +42 -0
  22. data/new_project_template/vendor/ceedling/examples/temp_sensor/iar_v4.yml +91 -0
  23. data/new_project_template/vendor/ceedling/examples/temp_sensor/iar_v5.yml +80 -0
  24. data/new_project_template/vendor/ceedling/examples/temp_sensor/project.yml +65 -0
  25. data/new_project_template/vendor/ceedling/examples/temp_sensor/rakefile.rb +5 -0
  26. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcConductor.c +42 -0
  27. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcConductor.h +13 -0
  28. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardware.c +27 -0
  29. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardware.h +11 -0
  30. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardwareConfigurator.c +18 -0
  31. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardwareConfigurator.h +10 -0
  32. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcModel.c +33 -0
  33. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcModel.h +13 -0
  34. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcTemperatureSensor.c +51 -0
  35. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcTemperatureSensor.h +10 -0
  36. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Executor.c +25 -0
  37. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Executor.h +9 -0
  38. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/IntrinsicsWrapper.c +18 -0
  39. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/IntrinsicsWrapper.h +7 -0
  40. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Main.c +46 -0
  41. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Main.h +7 -0
  42. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Model.c +10 -0
  43. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Model.h +8 -0
  44. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/ModelConfig.h +7 -0
  45. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TaskScheduler.c +72 -0
  46. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TaskScheduler.h +11 -0
  47. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureCalculator.c +27 -0
  48. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureCalculator.h +8 -0
  49. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureFilter.c +39 -0
  50. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureFilter.h +10 -0
  51. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConductor.c +15 -0
  52. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConductor.h +9 -0
  53. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConfigurator.c +51 -0
  54. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConfigurator.h +15 -0
  55. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerHardware.c +15 -0
  56. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerHardware.h +8 -0
  57. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptConfigurator.c +55 -0
  58. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptConfigurator.h +13 -0
  59. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptHandler.c +25 -0
  60. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptHandler.h +10 -0
  61. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerModel.c +9 -0
  62. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerModel.h +8 -0
  63. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Types.h +90 -0
  64. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartBaudRateRegisterCalculator.c +18 -0
  65. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartBaudRateRegisterCalculator.h +8 -0
  66. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConductor.c +21 -0
  67. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConductor.h +7 -0
  68. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConfigurator.c +39 -0
  69. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConfigurator.h +13 -0
  70. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartHardware.c +22 -0
  71. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartHardware.h +9 -0
  72. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartModel.c +34 -0
  73. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartModel.h +10 -0
  74. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartPutChar.c +16 -0
  75. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartPutChar.h +8 -0
  76. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartTransmitBufferStatus.c +7 -0
  77. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartTransmitBufferStatus.h +8 -0
  78. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcConductor.c +121 -0
  79. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcHardware.c +44 -0
  80. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcModel.c +33 -0
  81. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestExecutor.c +36 -0
  82. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestMain.c +24 -0
  83. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestModel.c +20 -0
  84. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTaskScheduler.c +104 -0
  85. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTemperatureCalculator.c +33 -0
  86. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTemperatureFilter.c +69 -0
  87. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerConductor.c +32 -0
  88. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerHardware.c +26 -0
  89. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerModel.c +18 -0
  90. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartBaudRateRegisterCalculator.c +21 -0
  91. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartConductor.c +40 -0
  92. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartHardware.c +36 -0
  93. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartModel.c +40 -0
  94. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/support/UnityHelper.c +12 -0
  95. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/support/UnityHelper.h +8 -0
  96. data/new_project_template/vendor/ceedling/lib/cacheinator.rb +42 -0
  97. data/new_project_template/vendor/ceedling/lib/cacheinator_helper.rb +12 -0
  98. data/new_project_template/vendor/ceedling/lib/cmock_builder.rb +15 -0
  99. data/new_project_template/vendor/ceedling/lib/configurator.rb +254 -0
  100. data/new_project_template/vendor/ceedling/lib/configurator_builder.rb +408 -0
  101. data/new_project_template/vendor/ceedling/lib/configurator_plugins.rb +96 -0
  102. data/new_project_template/vendor/ceedling/lib/configurator_setup.rb +114 -0
  103. data/new_project_template/vendor/ceedling/lib/configurator_validator.rb +154 -0
  104. data/new_project_template/vendor/ceedling/lib/constants.rb +66 -0
  105. data/new_project_template/vendor/ceedling/lib/defaults.rb +349 -0
  106. data/new_project_template/vendor/ceedling/lib/dependinator.rb +92 -0
  107. data/new_project_template/vendor/ceedling/lib/file_finder.rb +132 -0
  108. data/new_project_template/vendor/ceedling/lib/file_finder_helper.rb +54 -0
  109. data/new_project_template/vendor/ceedling/lib/file_path_utils.rb +177 -0
  110. data/new_project_template/vendor/ceedling/lib/file_system_utils.rb +59 -0
  111. data/new_project_template/vendor/ceedling/lib/file_wrapper.rb +74 -0
  112. data/new_project_template/vendor/ceedling/lib/generator.rb +131 -0
  113. data/new_project_template/vendor/ceedling/lib/generator_test_results.rb +90 -0
  114. data/new_project_template/vendor/ceedling/lib/generator_test_results_sanity_checker.rb +62 -0
  115. data/new_project_template/vendor/ceedling/lib/generator_test_runner.rb +206 -0
  116. data/new_project_template/vendor/ceedling/lib/loginator.rb +31 -0
  117. data/new_project_template/vendor/ceedling/lib/makefile.rb +46 -0
  118. data/new_project_template/vendor/ceedling/lib/objects.yml +278 -0
  119. data/new_project_template/vendor/ceedling/lib/plugin.rb +63 -0
  120. data/new_project_template/vendor/ceedling/lib/plugin_manager.rb +85 -0
  121. data/new_project_template/vendor/ceedling/lib/plugin_manager_helper.rb +19 -0
  122. data/new_project_template/vendor/ceedling/lib/plugin_reportinator.rb +75 -0
  123. data/new_project_template/vendor/ceedling/lib/plugin_reportinator_helper.rb +52 -0
  124. data/new_project_template/vendor/ceedling/lib/preprocessinator.rb +43 -0
  125. data/new_project_template/vendor/ceedling/lib/preprocessinator_extractor.rb +27 -0
  126. data/new_project_template/vendor/ceedling/lib/preprocessinator_file_handler.rb +21 -0
  127. data/new_project_template/vendor/ceedling/lib/preprocessinator_helper.rb +46 -0
  128. data/new_project_template/vendor/ceedling/lib/preprocessinator_includes_handler.rb +55 -0
  129. data/new_project_template/vendor/ceedling/lib/project_config_manager.rb +38 -0
  130. data/new_project_template/vendor/ceedling/lib/project_file_loader.rb +64 -0
  131. data/new_project_template/vendor/ceedling/lib/rake_utils.rb +17 -0
  132. data/new_project_template/vendor/ceedling/lib/rake_wrapper.rb +31 -0
  133. data/new_project_template/vendor/ceedling/lib/rakefile.rb +60 -0
  134. data/new_project_template/vendor/ceedling/lib/release_invoker.rb +29 -0
  135. data/new_project_template/vendor/ceedling/lib/release_invoker_helper.rb +16 -0
  136. data/new_project_template/vendor/ceedling/lib/reportinator.rb +9 -0
  137. data/new_project_template/vendor/ceedling/lib/rules_cmock.rake +9 -0
  138. data/new_project_template/vendor/ceedling/lib/rules_preprocess.rake +26 -0
  139. data/new_project_template/vendor/ceedling/lib/rules_release.rake +63 -0
  140. data/new_project_template/vendor/ceedling/lib/rules_release_aux_dependencies.rake +15 -0
  141. data/new_project_template/vendor/ceedling/lib/rules_tests.rake +49 -0
  142. data/new_project_template/vendor/ceedling/lib/rules_tests_aux_dependencies.rake +15 -0
  143. data/new_project_template/vendor/ceedling/lib/setupinator.rb +45 -0
  144. data/new_project_template/vendor/ceedling/lib/stream_wrapper.rb +20 -0
  145. data/new_project_template/vendor/ceedling/lib/streaminator.rb +41 -0
  146. data/new_project_template/vendor/ceedling/lib/streaminator_helper.rb +15 -0
  147. data/new_project_template/vendor/ceedling/lib/system_wrapper.rb +67 -0
  148. data/new_project_template/vendor/ceedling/lib/task_invoker.rb +85 -0
  149. data/new_project_template/vendor/ceedling/lib/tasks_base.rake +104 -0
  150. data/new_project_template/vendor/ceedling/lib/tasks_filesystem.rake +89 -0
  151. data/new_project_template/vendor/ceedling/lib/tasks_release.rake +22 -0
  152. data/new_project_template/vendor/ceedling/lib/tasks_tests.rake +49 -0
  153. data/new_project_template/vendor/ceedling/lib/tasks_vendor.rake +36 -0
  154. data/new_project_template/vendor/ceedling/lib/test_includes_extractor.rb +81 -0
  155. data/new_project_template/vendor/ceedling/lib/test_invoker.rb +72 -0
  156. data/new_project_template/vendor/ceedling/lib/test_invoker_helper.rb +41 -0
  157. data/new_project_template/vendor/ceedling/lib/tool_executor.rb +178 -0
  158. data/new_project_template/vendor/ceedling/lib/tool_executor_helper.rb +57 -0
  159. data/new_project_template/vendor/ceedling/lib/verbosinator.rb +10 -0
  160. data/new_project_template/vendor/ceedling/lib/yaml_wrapper.rb +16 -0
  161. data/new_project_template/vendor/ceedling/plugins/stdout_ide_tests_report/stdout_ide_tests_report.rb +44 -0
  162. data/new_project_template/vendor/ceedling/plugins/stdout_ide_tests_report/stdout_ide_tests_report.yml +4 -0
  163. data/new_project_template/vendor/ceedling/plugins/stdout_pretty_tests_report/stdout_pretty_tests_report.rb +108 -0
  164. data/new_project_template/vendor/ceedling/plugins/stdout_pretty_tests_report/stdout_pretty_tests_report.yml +4 -0
  165. data/new_project_template/vendor/ceedling/plugins/xml_tests_report/xml_tests_report.rb +106 -0
  166. data/new_project_template/vendor/ceedling/rakefile.rb +59 -0
  167. data/new_project_template/vendor/ceedling/rakefile_helper.rb +23 -0
  168. data/new_project_template/vendor/ceedling/release/build.info +1 -0
  169. data/new_project_template/vendor/ceedling/release/version.info +1 -0
  170. data/new_project_template/vendor/ceedling/test/integration/paths.yml +17 -0
  171. data/new_project_template/vendor/ceedling/test/integration/paths_test.rb +80 -0
  172. data/new_project_template/vendor/ceedling/test/integration/rake_rules_aux_dependencies_test.rb +75 -0
  173. data/new_project_template/vendor/ceedling/test/integration/rake_rules_cmock_test.rb +74 -0
  174. data/new_project_template/vendor/ceedling/test/integration/rake_rules_preprocess_test.rb +178 -0
  175. data/new_project_template/vendor/ceedling/test/integration/rake_rules_test.rb +268 -0
  176. data/new_project_template/vendor/ceedling/test/integration/rake_tasks_test.rb +103 -0
  177. data/new_project_template/vendor/ceedling/test/integration_test_helper.rb +34 -0
  178. data/new_project_template/vendor/ceedling/test/rakefile_rules.rb +10 -0
  179. data/new_project_template/vendor/ceedling/test/rakefile_rules_aux_dependencies.rb +10 -0
  180. data/new_project_template/vendor/ceedling/test/rakefile_rules_cmock.rb +10 -0
  181. data/new_project_template/vendor/ceedling/test/rakefile_rules_preprocess.rb +10 -0
  182. data/new_project_template/vendor/ceedling/test/rakefile_tasks.rb +10 -0
  183. data/new_project_template/vendor/ceedling/test/system/file_system_dependencies.yml +20 -0
  184. data/new_project_template/vendor/ceedling/test/system/file_system_kitchen_sink.yml +20 -0
  185. data/new_project_template/vendor/ceedling/test/system/file_system_mocks.yml +20 -0
  186. data/new_project_template/vendor/ceedling/test/system/file_system_preprocess.yml +20 -0
  187. data/new_project_template/vendor/ceedling/test/system/file_system_simple.yml +20 -0
  188. data/new_project_template/vendor/ceedling/test/system/file_system_test.rb +78 -0
  189. data/new_project_template/vendor/ceedling/test/system/mocks/include/a_file.h +2 -0
  190. data/new_project_template/vendor/ceedling/test/system/mocks/include/other_stuff.h +2 -0
  191. data/new_project_template/vendor/ceedling/test/system/mocks/include/stuff.h +3 -0
  192. data/new_project_template/vendor/ceedling/test/system/mocks/source/a_file.c +9 -0
  193. data/new_project_template/vendor/ceedling/test/system/mocks/test/test_a_file.c +41 -0
  194. data/new_project_template/vendor/ceedling/test/system/mocks/test/test_no_file.c +14 -0
  195. data/new_project_template/vendor/ceedling/test/system/project_mocks.yml +43 -0
  196. data/new_project_template/vendor/ceedling/test/system/project_mocks_test.rb +38 -0
  197. data/new_project_template/vendor/ceedling/test/system/project_simple.yml +36 -0
  198. data/new_project_template/vendor/ceedling/test/system/project_simple_test.rb +39 -0
  199. data/new_project_template/vendor/ceedling/test/system/rule_mocks_test.rb +44 -0
  200. data/new_project_template/vendor/ceedling/test/system/rule_runners_test.rb +44 -0
  201. data/new_project_template/vendor/ceedling/test/system/simple/include/other_stuff.h +2 -0
  202. data/new_project_template/vendor/ceedling/test/system/simple/include/stuff.h +3 -0
  203. data/new_project_template/vendor/ceedling/test/system/simple/source/other_stuff.c +6 -0
  204. data/new_project_template/vendor/ceedling/test/system/simple/source/stuff.c +7 -0
  205. data/new_project_template/vendor/ceedling/test/system/simple/test/test_other_stuff.c +30 -0
  206. data/new_project_template/vendor/ceedling/test/system/simple/test/test_stuff.c +51 -0
  207. data/new_project_template/vendor/ceedling/test/system_test_helper.rb +73 -0
  208. data/new_project_template/vendor/ceedling/test/test_helper.rb +93 -0
  209. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_builder_test.rb +571 -0
  210. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_helper_test.rb +234 -0
  211. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_test.rb +232 -0
  212. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_validator_test.rb +169 -0
  213. data/new_project_template/vendor/ceedling/test/unit/busted/deep_merge_fix_test.rb +55 -0
  214. data/new_project_template/vendor/ceedling/test/unit/busted/dependinator_test.rb +129 -0
  215. data/new_project_template/vendor/ceedling/test/unit/busted/file_finder_helper_test.rb +45 -0
  216. data/new_project_template/vendor/ceedling/test/unit/busted/file_finder_test.rb +114 -0
  217. data/new_project_template/vendor/ceedling/test/unit/busted/file_path_utils_test.rb +97 -0
  218. data/new_project_template/vendor/ceedling/test/unit/busted/file_system_utils_test.rb +21 -0
  219. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test.rb +187 -0
  220. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test_results_test.rb +129 -0
  221. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test_runner_test.rb +478 -0
  222. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_extractor_test.rb +729 -0
  223. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_file_handler_test.rb +38 -0
  224. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_helper_test.rb +156 -0
  225. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_includes_handler_test.rb +93 -0
  226. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_test.rb +57 -0
  227. data/new_project_template/vendor/ceedling/test/unit/busted/project_file_loader_test.rb +142 -0
  228. data/new_project_template/vendor/ceedling/test/unit/busted/setupinator_test.rb +45 -0
  229. data/new_project_template/vendor/ceedling/test/unit/busted/streaminator_test.rb +49 -0
  230. data/new_project_template/vendor/ceedling/test/unit/busted/task_invoker_test.rb +69 -0
  231. data/new_project_template/vendor/ceedling/test/unit/busted/test_includes_extractor_test.rb +111 -0
  232. data/new_project_template/vendor/ceedling/test/unit/busted/test_invoker_helper_test.rb +62 -0
  233. data/new_project_template/vendor/ceedling/test/unit/busted/test_invoker_test.rb +47 -0
  234. data/new_project_template/vendor/ceedling/test/unit/busted/tool_executor_helper_test.rb +100 -0
  235. data/new_project_template/vendor/ceedling/test/unit/busted/tool_executor_test.rb +351 -0
  236. data/new_project_template/vendor/ceedling/test/unit/busted/verbosinator_test.rb +65 -0
  237. data/new_project_template/vendor/ceedling/test/unit_test_helper.rb +16 -0
  238. data/new_project_template/vendor/ceedling/vendor/behaviors/Manifest.txt +9 -0
  239. data/new_project_template/vendor/ceedling/vendor/behaviors/Rakefile +19 -0
  240. data/new_project_template/vendor/ceedling/vendor/behaviors/lib/behaviors/reporttask.rb +158 -0
  241. data/new_project_template/vendor/ceedling/vendor/behaviors/lib/behaviors.rb +76 -0
  242. data/new_project_template/vendor/ceedling/vendor/behaviors/test/behaviors_tasks_test.rb +73 -0
  243. data/new_project_template/vendor/ceedling/vendor/behaviors/test/behaviors_test.rb +50 -0
  244. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/Rakefile +19 -0
  245. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/lib/user.rb +2 -0
  246. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/test/user_test.rb +17 -0
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@@ -0,0 +1,2556 @@
1
+ // ----------------------------------------------------------------------------
2
+ // ATMEL Microcontroller Software Support - ROUSSET -
3
+ // ----------------------------------------------------------------------------
4
+ // DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
5
+ // IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6
+ // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
7
+ // DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
8
+ // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
9
+ // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
10
+ // OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
11
+ // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
12
+ // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
13
+ // EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
14
+ // ----------------------------------------------------------------------------
15
+ // File Name : AT91SAM7X256.h
16
+ // Object : AT91SAM7X256 definitions
17
+ // Generated : AT91 SW Application Group 01/16/2006 (16:36:21)
18
+ //
19
+ // CVS Reference : /AT91SAM7X256.pl/1.15/Wed Nov 2 13:56:49 2005//
20
+ // CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
21
+ // CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
22
+ // CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
23
+ // CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 14:57:50 2005//
24
+ // CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
25
+ // CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
26
+ // CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
27
+ // CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
28
+ // CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
29
+ // CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
30
+ // CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
31
+ // CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
32
+ // CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
33
+ // CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
34
+ // CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
35
+ // CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
36
+ // CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:19:19 2005//
37
+ // CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
38
+ // CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
39
+ // CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
40
+ // CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:05:35 2005//
41
+ // CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
42
+ // ----------------------------------------------------------------------------
43
+
44
+ #ifndef AT91SAM7X256_H
45
+ #define AT91SAM7X256_H
46
+
47
+ typedef volatile unsigned int AT91_REG;// Hardware register definition
48
+
49
+ // *****************************************************************************
50
+ // SOFTWARE API DEFINITION FOR System Peripherals
51
+ // *****************************************************************************
52
+ typedef struct _AT91S_SYS {
53
+ AT91_REG AIC_SMR[32]; // Source Mode Register
54
+ AT91_REG AIC_SVR[32]; // Source Vector Register
55
+ AT91_REG AIC_IVR; // IRQ Vector Register
56
+ AT91_REG AIC_FVR; // FIQ Vector Register
57
+ AT91_REG AIC_ISR; // Interrupt Status Register
58
+ AT91_REG AIC_IPR; // Interrupt Pending Register
59
+ AT91_REG AIC_IMR; // Interrupt Mask Register
60
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
61
+ AT91_REG Reserved0[2]; //
62
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
63
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
64
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
65
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
66
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
67
+ AT91_REG AIC_SPU; // Spurious Vector Register
68
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
69
+ AT91_REG Reserved1[1]; //
70
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
71
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
72
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
73
+ AT91_REG Reserved2[45]; //
74
+ AT91_REG DBGU_CR; // Control Register
75
+ AT91_REG DBGU_MR; // Mode Register
76
+ AT91_REG DBGU_IER; // Interrupt Enable Register
77
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
78
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
79
+ AT91_REG DBGU_CSR; // Channel Status Register
80
+ AT91_REG DBGU_RHR; // Receiver Holding Register
81
+ AT91_REG DBGU_THR; // Transmitter Holding Register
82
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
83
+ AT91_REG Reserved3[7]; //
84
+ AT91_REG DBGU_CIDR; // Chip ID Register
85
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
86
+ AT91_REG DBGU_FNTR; // Force NTRST Register
87
+ AT91_REG Reserved4[45]; //
88
+ AT91_REG DBGU_RPR; // Receive Pointer Register
89
+ AT91_REG DBGU_RCR; // Receive Counter Register
90
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
91
+ AT91_REG DBGU_TCR; // Transmit Counter Register
92
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
93
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
94
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
95
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
96
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
97
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
98
+ AT91_REG Reserved5[54]; //
99
+ AT91_REG PIOA_PER; // PIO Enable Register
100
+ AT91_REG PIOA_PDR; // PIO Disable Register
101
+ AT91_REG PIOA_PSR; // PIO Status Register
102
+ AT91_REG Reserved6[1]; //
103
+ AT91_REG PIOA_OER; // Output Enable Register
104
+ AT91_REG PIOA_ODR; // Output Disable Registerr
105
+ AT91_REG PIOA_OSR; // Output Status Register
106
+ AT91_REG Reserved7[1]; //
107
+ AT91_REG PIOA_IFER; // Input Filter Enable Register
108
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register
109
+ AT91_REG PIOA_IFSR; // Input Filter Status Register
110
+ AT91_REG Reserved8[1]; //
111
+ AT91_REG PIOA_SODR; // Set Output Data Register
112
+ AT91_REG PIOA_CODR; // Clear Output Data Register
113
+ AT91_REG PIOA_ODSR; // Output Data Status Register
114
+ AT91_REG PIOA_PDSR; // Pin Data Status Register
115
+ AT91_REG PIOA_IER; // Interrupt Enable Register
116
+ AT91_REG PIOA_IDR; // Interrupt Disable Register
117
+ AT91_REG PIOA_IMR; // Interrupt Mask Register
118
+ AT91_REG PIOA_ISR; // Interrupt Status Register
119
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register
120
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register
121
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register
122
+ AT91_REG Reserved9[1]; //
123
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register
124
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register
125
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register
126
+ AT91_REG Reserved10[1]; //
127
+ AT91_REG PIOA_ASR; // Select A Register
128
+ AT91_REG PIOA_BSR; // Select B Register
129
+ AT91_REG PIOA_ABSR; // AB Select Status Register
130
+ AT91_REG Reserved11[9]; //
131
+ AT91_REG PIOA_OWER; // Output Write Enable Register
132
+ AT91_REG PIOA_OWDR; // Output Write Disable Register
133
+ AT91_REG PIOA_OWSR; // Output Write Status Register
134
+ AT91_REG Reserved12[85]; //
135
+ AT91_REG PIOB_PER; // PIO Enable Register
136
+ AT91_REG PIOB_PDR; // PIO Disable Register
137
+ AT91_REG PIOB_PSR; // PIO Status Register
138
+ AT91_REG Reserved13[1]; //
139
+ AT91_REG PIOB_OER; // Output Enable Register
140
+ AT91_REG PIOB_ODR; // Output Disable Registerr
141
+ AT91_REG PIOB_OSR; // Output Status Register
142
+ AT91_REG Reserved14[1]; //
143
+ AT91_REG PIOB_IFER; // Input Filter Enable Register
144
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register
145
+ AT91_REG PIOB_IFSR; // Input Filter Status Register
146
+ AT91_REG Reserved15[1]; //
147
+ AT91_REG PIOB_SODR; // Set Output Data Register
148
+ AT91_REG PIOB_CODR; // Clear Output Data Register
149
+ AT91_REG PIOB_ODSR; // Output Data Status Register
150
+ AT91_REG PIOB_PDSR; // Pin Data Status Register
151
+ AT91_REG PIOB_IER; // Interrupt Enable Register
152
+ AT91_REG PIOB_IDR; // Interrupt Disable Register
153
+ AT91_REG PIOB_IMR; // Interrupt Mask Register
154
+ AT91_REG PIOB_ISR; // Interrupt Status Register
155
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register
156
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register
157
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register
158
+ AT91_REG Reserved16[1]; //
159
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register
160
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register
161
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register
162
+ AT91_REG Reserved17[1]; //
163
+ AT91_REG PIOB_ASR; // Select A Register
164
+ AT91_REG PIOB_BSR; // Select B Register
165
+ AT91_REG PIOB_ABSR; // AB Select Status Register
166
+ AT91_REG Reserved18[9]; //
167
+ AT91_REG PIOB_OWER; // Output Write Enable Register
168
+ AT91_REG PIOB_OWDR; // Output Write Disable Register
169
+ AT91_REG PIOB_OWSR; // Output Write Status Register
170
+ AT91_REG Reserved19[341]; //
171
+ AT91_REG PMC_SCER; // System Clock Enable Register
172
+ AT91_REG PMC_SCDR; // System Clock Disable Register
173
+ AT91_REG PMC_SCSR; // System Clock Status Register
174
+ AT91_REG Reserved20[1]; //
175
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
176
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
177
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
178
+ AT91_REG Reserved21[1]; //
179
+ AT91_REG PMC_MOR; // Main Oscillator Register
180
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
181
+ AT91_REG Reserved22[1]; //
182
+ AT91_REG PMC_PLLR; // PLL Register
183
+ AT91_REG PMC_MCKR; // Master Clock Register
184
+ AT91_REG Reserved23[3]; //
185
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
186
+ AT91_REG Reserved24[4]; //
187
+ AT91_REG PMC_IER; // Interrupt Enable Register
188
+ AT91_REG PMC_IDR; // Interrupt Disable Register
189
+ AT91_REG PMC_SR; // Status Register
190
+ AT91_REG PMC_IMR; // Interrupt Mask Register
191
+ AT91_REG Reserved25[36]; //
192
+ AT91_REG RSTC_RCR; // Reset Control Register
193
+ AT91_REG RSTC_RSR; // Reset Status Register
194
+ AT91_REG RSTC_RMR; // Reset Mode Register
195
+ AT91_REG Reserved26[5]; //
196
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
197
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
198
+ AT91_REG RTTC_RTVR; // Real-time Value Register
199
+ AT91_REG RTTC_RTSR; // Real-time Status Register
200
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
201
+ AT91_REG PITC_PISR; // Period Interval Status Register
202
+ AT91_REG PITC_PIVR; // Period Interval Value Register
203
+ AT91_REG PITC_PIIR; // Period Interval Image Register
204
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
205
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
206
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
207
+ AT91_REG Reserved27[5]; //
208
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
209
+ } AT91S_SYS, *AT91PS_SYS;
210
+
211
+
212
+ // *****************************************************************************
213
+ // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
214
+ // *****************************************************************************
215
+ typedef struct _AT91S_AIC {
216
+ AT91_REG AIC_SMR[32]; // Source Mode Register
217
+ AT91_REG AIC_SVR[32]; // Source Vector Register
218
+ AT91_REG AIC_IVR; // IRQ Vector Register
219
+ AT91_REG AIC_FVR; // FIQ Vector Register
220
+ AT91_REG AIC_ISR; // Interrupt Status Register
221
+ AT91_REG AIC_IPR; // Interrupt Pending Register
222
+ AT91_REG AIC_IMR; // Interrupt Mask Register
223
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
224
+ AT91_REG Reserved0[2]; //
225
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
226
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
227
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
228
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
229
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
230
+ AT91_REG AIC_SPU; // Spurious Vector Register
231
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
232
+ AT91_REG Reserved1[1]; //
233
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
234
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
235
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
236
+ } AT91S_AIC, *AT91PS_AIC;
237
+
238
+ // -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
239
+ #define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
240
+ #define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
241
+ #define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
242
+ #define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
243
+ #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
244
+ #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
245
+ #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
246
+ #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
247
+ #define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
248
+ #define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
249
+ // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
250
+ #define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
251
+ #define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
252
+ // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
253
+ #define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
254
+ #define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
255
+
256
+ // *****************************************************************************
257
+ // SOFTWARE API DEFINITION FOR Peripheral DMA Controller
258
+ // *****************************************************************************
259
+ typedef struct _AT91S_PDC {
260
+ AT91_REG PDC_RPR; // Receive Pointer Register
261
+ AT91_REG PDC_RCR; // Receive Counter Register
262
+ AT91_REG PDC_TPR; // Transmit Pointer Register
263
+ AT91_REG PDC_TCR; // Transmit Counter Register
264
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register
265
+ AT91_REG PDC_RNCR; // Receive Next Counter Register
266
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register
267
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register
268
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register
269
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register
270
+ } AT91S_PDC, *AT91PS_PDC;
271
+
272
+ // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
273
+ #define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
274
+ #define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
275
+ #define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
276
+ #define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
277
+ // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
278
+
279
+ // *****************************************************************************
280
+ // SOFTWARE API DEFINITION FOR Debug Unit
281
+ // *****************************************************************************
282
+ typedef struct _AT91S_DBGU {
283
+ AT91_REG DBGU_CR; // Control Register
284
+ AT91_REG DBGU_MR; // Mode Register
285
+ AT91_REG DBGU_IER; // Interrupt Enable Register
286
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
287
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
288
+ AT91_REG DBGU_CSR; // Channel Status Register
289
+ AT91_REG DBGU_RHR; // Receiver Holding Register
290
+ AT91_REG DBGU_THR; // Transmitter Holding Register
291
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
292
+ AT91_REG Reserved0[7]; //
293
+ AT91_REG DBGU_CIDR; // Chip ID Register
294
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
295
+ AT91_REG DBGU_FNTR; // Force NTRST Register
296
+ AT91_REG Reserved1[45]; //
297
+ AT91_REG DBGU_RPR; // Receive Pointer Register
298
+ AT91_REG DBGU_RCR; // Receive Counter Register
299
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
300
+ AT91_REG DBGU_TCR; // Transmit Counter Register
301
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
302
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
303
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
304
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
305
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
306
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
307
+ } AT91S_DBGU, *AT91PS_DBGU;
308
+
309
+ // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
310
+ #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
311
+ #define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
312
+ #define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
313
+ #define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
314
+ #define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
315
+ #define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
316
+ #define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
317
+ // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
318
+ #define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
319
+ #define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
320
+ #define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
321
+ #define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
322
+ #define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
323
+ #define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
324
+ #define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
325
+ #define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
326
+ #define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
327
+ #define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
328
+ #define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
329
+ #define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
330
+ // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
331
+ #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
332
+ #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
333
+ #define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
334
+ #define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
335
+ #define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
336
+ #define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
337
+ #define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
338
+ #define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
339
+ #define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
340
+ #define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
341
+ #define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
342
+ #define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
343
+ // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
344
+ // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
345
+ // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
346
+ // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
347
+ #define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
348
+
349
+ // *****************************************************************************
350
+ // SOFTWARE API DEFINITION FOR Parallel Input Output Controler
351
+ // *****************************************************************************
352
+ typedef struct _AT91S_PIO {
353
+ AT91_REG PIO_PER; // PIO Enable Register
354
+ AT91_REG PIO_PDR; // PIO Disable Register
355
+ AT91_REG PIO_PSR; // PIO Status Register
356
+ AT91_REG Reserved0[1]; //
357
+ AT91_REG PIO_OER; // Output Enable Register
358
+ AT91_REG PIO_ODR; // Output Disable Registerr
359
+ AT91_REG PIO_OSR; // Output Status Register
360
+ AT91_REG Reserved1[1]; //
361
+ AT91_REG PIO_IFER; // Input Filter Enable Register
362
+ AT91_REG PIO_IFDR; // Input Filter Disable Register
363
+ AT91_REG PIO_IFSR; // Input Filter Status Register
364
+ AT91_REG Reserved2[1]; //
365
+ AT91_REG PIO_SODR; // Set Output Data Register
366
+ AT91_REG PIO_CODR; // Clear Output Data Register
367
+ AT91_REG PIO_ODSR; // Output Data Status Register
368
+ AT91_REG PIO_PDSR; // Pin Data Status Register
369
+ AT91_REG PIO_IER; // Interrupt Enable Register
370
+ AT91_REG PIO_IDR; // Interrupt Disable Register
371
+ AT91_REG PIO_IMR; // Interrupt Mask Register
372
+ AT91_REG PIO_ISR; // Interrupt Status Register
373
+ AT91_REG PIO_MDER; // Multi-driver Enable Register
374
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register
375
+ AT91_REG PIO_MDSR; // Multi-driver Status Register
376
+ AT91_REG Reserved3[1]; //
377
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register
378
+ AT91_REG PIO_PPUER; // Pull-up Enable Register
379
+ AT91_REG PIO_PPUSR; // Pull-up Status Register
380
+ AT91_REG Reserved4[1]; //
381
+ AT91_REG PIO_ASR; // Select A Register
382
+ AT91_REG PIO_BSR; // Select B Register
383
+ AT91_REG PIO_ABSR; // AB Select Status Register
384
+ AT91_REG Reserved5[9]; //
385
+ AT91_REG PIO_OWER; // Output Write Enable Register
386
+ AT91_REG PIO_OWDR; // Output Write Disable Register
387
+ AT91_REG PIO_OWSR; // Output Write Status Register
388
+ } AT91S_PIO, *AT91PS_PIO;
389
+
390
+
391
+ // *****************************************************************************
392
+ // SOFTWARE API DEFINITION FOR Clock Generator Controler
393
+ // *****************************************************************************
394
+ typedef struct _AT91S_CKGR {
395
+ AT91_REG CKGR_MOR; // Main Oscillator Register
396
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
397
+ AT91_REG Reserved0[1]; //
398
+ AT91_REG CKGR_PLLR; // PLL Register
399
+ } AT91S_CKGR, *AT91PS_CKGR;
400
+
401
+ // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
402
+ #define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
403
+ #define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
404
+ #define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
405
+ // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
406
+ #define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
407
+ #define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
408
+ // -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
409
+ #define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
410
+ #define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
411
+ #define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
412
+ #define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
413
+ #define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
414
+ #define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
415
+ #define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
416
+ #define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
417
+ #define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
418
+ #define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
419
+ #define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
420
+ #define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
421
+ #define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
422
+ #define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
423
+
424
+ // *****************************************************************************
425
+ // SOFTWARE API DEFINITION FOR Power Management Controler
426
+ // *****************************************************************************
427
+ typedef struct _AT91S_PMC {
428
+ AT91_REG PMC_SCER; // System Clock Enable Register
429
+ AT91_REG PMC_SCDR; // System Clock Disable Register
430
+ AT91_REG PMC_SCSR; // System Clock Status Register
431
+ AT91_REG Reserved0[1]; //
432
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
433
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
434
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
435
+ AT91_REG Reserved1[1]; //
436
+ AT91_REG PMC_MOR; // Main Oscillator Register
437
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
438
+ AT91_REG Reserved2[1]; //
439
+ AT91_REG PMC_PLLR; // PLL Register
440
+ AT91_REG PMC_MCKR; // Master Clock Register
441
+ AT91_REG Reserved3[3]; //
442
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
443
+ AT91_REG Reserved4[4]; //
444
+ AT91_REG PMC_IER; // Interrupt Enable Register
445
+ AT91_REG PMC_IDR; // Interrupt Disable Register
446
+ AT91_REG PMC_SR; // Status Register
447
+ AT91_REG PMC_IMR; // Interrupt Mask Register
448
+ } AT91S_PMC, *AT91PS_PMC;
449
+
450
+ // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
451
+ #define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
452
+ #define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
453
+ #define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
454
+ #define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
455
+ #define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
456
+ #define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
457
+ // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
458
+ // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
459
+ // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
460
+ // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
461
+ // -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
462
+ // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
463
+ #define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
464
+ #define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
465
+ #define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
466
+ #define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
467
+ #define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
468
+ #define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
469
+ #define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
470
+ #define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
471
+ #define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
472
+ #define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
473
+ #define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
474
+ #define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
475
+ // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
476
+ // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
477
+ #define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
478
+ #define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
479
+ #define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
480
+ #define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
481
+ #define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
482
+ #define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
483
+ #define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
484
+ // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
485
+ // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
486
+ // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
487
+
488
+ // *****************************************************************************
489
+ // SOFTWARE API DEFINITION FOR Reset Controller Interface
490
+ // *****************************************************************************
491
+ typedef struct _AT91S_RSTC {
492
+ AT91_REG RSTC_RCR; // Reset Control Register
493
+ AT91_REG RSTC_RSR; // Reset Status Register
494
+ AT91_REG RSTC_RMR; // Reset Mode Register
495
+ } AT91S_RSTC, *AT91PS_RSTC;
496
+
497
+ // -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
498
+ #define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
499
+ #define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
500
+ #define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
501
+ #define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
502
+ // -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
503
+ #define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
504
+ #define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
505
+ #define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
506
+ #define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
507
+ #define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
508
+ #define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
509
+ #define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
510
+ #define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
511
+ #define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
512
+ #define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
513
+ #define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
514
+ // -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
515
+ #define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
516
+ #define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
517
+ #define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Length
518
+ #define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
519
+
520
+ // *****************************************************************************
521
+ // SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
522
+ // *****************************************************************************
523
+ typedef struct _AT91S_RTTC {
524
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
525
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
526
+ AT91_REG RTTC_RTVR; // Real-time Value Register
527
+ AT91_REG RTTC_RTSR; // Real-time Status Register
528
+ } AT91S_RTTC, *AT91PS_RTTC;
529
+
530
+ // -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
531
+ #define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
532
+ #define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
533
+ #define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
534
+ #define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
535
+ // -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
536
+ #define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
537
+ // -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
538
+ #define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
539
+ // -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
540
+ #define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
541
+ #define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
542
+
543
+ // *****************************************************************************
544
+ // SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
545
+ // *****************************************************************************
546
+ typedef struct _AT91S_PITC {
547
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
548
+ AT91_REG PITC_PISR; // Period Interval Status Register
549
+ AT91_REG PITC_PIVR; // Period Interval Value Register
550
+ AT91_REG PITC_PIIR; // Period Interval Image Register
551
+ } AT91S_PITC, *AT91PS_PITC;
552
+
553
+ // -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
554
+ #define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
555
+ #define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
556
+ #define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
557
+ // -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
558
+ #define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
559
+ // -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
560
+ #define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
561
+ #define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
562
+ // -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
563
+
564
+ // *****************************************************************************
565
+ // SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
566
+ // *****************************************************************************
567
+ typedef struct _AT91S_WDTC {
568
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
569
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
570
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
571
+ } AT91S_WDTC, *AT91PS_WDTC;
572
+
573
+ // -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
574
+ #define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
575
+ #define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
576
+ // -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
577
+ #define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
578
+ #define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
579
+ #define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
580
+ #define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
581
+ #define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
582
+ #define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
583
+ #define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
584
+ #define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
585
+ // -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
586
+ #define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
587
+ #define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
588
+
589
+ // *****************************************************************************
590
+ // SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
591
+ // *****************************************************************************
592
+ typedef struct _AT91S_VREG {
593
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
594
+ } AT91S_VREG, *AT91PS_VREG;
595
+
596
+ // -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
597
+ #define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
598
+
599
+ // *****************************************************************************
600
+ // SOFTWARE API DEFINITION FOR Memory Controller Interface
601
+ // *****************************************************************************
602
+ typedef struct _AT91S_MC {
603
+ AT91_REG MC_RCR; // MC Remap Control Register
604
+ AT91_REG MC_ASR; // MC Abort Status Register
605
+ AT91_REG MC_AASR; // MC Abort Address Status Register
606
+ AT91_REG Reserved0[21]; //
607
+ AT91_REG MC_FMR; // MC Flash Mode Register
608
+ AT91_REG MC_FCR; // MC Flash Command Register
609
+ AT91_REG MC_FSR; // MC Flash Status Register
610
+ } AT91S_MC, *AT91PS_MC;
611
+
612
+ // -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
613
+ #define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
614
+ // -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
615
+ #define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
616
+ #define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
617
+ #define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
618
+ #define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
619
+ #define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
620
+ #define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
621
+ #define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
622
+ #define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
623
+ #define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
624
+ #define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
625
+ #define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
626
+ #define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
627
+ #define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
628
+ #define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
629
+ // -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
630
+ #define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
631
+ #define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
632
+ #define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
633
+ #define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
634
+ #define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
635
+ #define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
636
+ #define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
637
+ #define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
638
+ #define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
639
+ #define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
640
+ // -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
641
+ #define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
642
+ #define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
643
+ #define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
644
+ #define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
645
+ #define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
646
+ #define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
647
+ #define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
648
+ #define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
649
+ #define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
650
+ #define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
651
+ #define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
652
+ // -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
653
+ #define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
654
+ #define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
655
+ #define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
656
+ #define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
657
+ #define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
658
+ #define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
659
+ #define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
660
+ #define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
661
+ #define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
662
+ #define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
663
+ #define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
664
+ #define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
665
+ #define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
666
+ #define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
667
+ #define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
668
+ #define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
669
+ #define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
670
+ #define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
671
+ #define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
672
+ #define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
673
+ #define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
674
+ #define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
675
+ #define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
676
+ #define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
677
+ #define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
678
+
679
+ // *****************************************************************************
680
+ // SOFTWARE API DEFINITION FOR Serial Parallel Interface
681
+ // *****************************************************************************
682
+ typedef struct _AT91S_SPI {
683
+ AT91_REG SPI_CR; // Control Register
684
+ AT91_REG SPI_MR; // Mode Register
685
+ AT91_REG SPI_RDR; // Receive Data Register
686
+ AT91_REG SPI_TDR; // Transmit Data Register
687
+ AT91_REG SPI_SR; // Status Register
688
+ AT91_REG SPI_IER; // Interrupt Enable Register
689
+ AT91_REG SPI_IDR; // Interrupt Disable Register
690
+ AT91_REG SPI_IMR; // Interrupt Mask Register
691
+ AT91_REG Reserved0[4]; //
692
+ AT91_REG SPI_CSR[4]; // Chip Select Register
693
+ AT91_REG Reserved1[48]; //
694
+ AT91_REG SPI_RPR; // Receive Pointer Register
695
+ AT91_REG SPI_RCR; // Receive Counter Register
696
+ AT91_REG SPI_TPR; // Transmit Pointer Register
697
+ AT91_REG SPI_TCR; // Transmit Counter Register
698
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register
699
+ AT91_REG SPI_RNCR; // Receive Next Counter Register
700
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register
701
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register
702
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register
703
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register
704
+ } AT91S_SPI, *AT91PS_SPI;
705
+
706
+ // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
707
+ #define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
708
+ #define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
709
+ #define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
710
+ #define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
711
+ // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
712
+ #define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
713
+ #define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
714
+ #define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
715
+ #define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
716
+ #define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
717
+ #define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
718
+ #define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
719
+ #define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
720
+ #define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
721
+ #define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
722
+ // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
723
+ #define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
724
+ #define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
725
+ // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
726
+ #define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
727
+ #define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
728
+ // -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
729
+ #define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
730
+ #define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
731
+ #define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
732
+ #define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
733
+ #define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
734
+ #define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
735
+ #define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
736
+ #define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
737
+ #define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
738
+ #define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
739
+ #define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
740
+ // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
741
+ // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
742
+ // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
743
+ // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
744
+ #define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
745
+ #define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
746
+ #define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
747
+ #define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
748
+ #define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
749
+ #define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
750
+ #define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
751
+ #define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
752
+ #define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
753
+ #define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
754
+ #define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
755
+ #define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
756
+ #define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
757
+ #define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
758
+ #define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
759
+ #define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
760
+
761
+ // *****************************************************************************
762
+ // SOFTWARE API DEFINITION FOR Usart
763
+ // *****************************************************************************
764
+ typedef struct _AT91S_USART {
765
+ AT91_REG US_CR; // Control Register
766
+ AT91_REG US_MR; // Mode Register
767
+ AT91_REG US_IER; // Interrupt Enable Register
768
+ AT91_REG US_IDR; // Interrupt Disable Register
769
+ AT91_REG US_IMR; // Interrupt Mask Register
770
+ AT91_REG US_CSR; // Channel Status Register
771
+ AT91_REG US_RHR; // Receiver Holding Register
772
+ AT91_REG US_THR; // Transmitter Holding Register
773
+ AT91_REG US_BRGR; // Baud Rate Generator Register
774
+ AT91_REG US_RTOR; // Receiver Time-out Register
775
+ AT91_REG US_TTGR; // Transmitter Time-guard Register
776
+ AT91_REG Reserved0[5]; //
777
+ AT91_REG US_FIDI; // FI_DI_Ratio Register
778
+ AT91_REG US_NER; // Nb Errors Register
779
+ AT91_REG Reserved1[1]; //
780
+ AT91_REG US_IF; // IRDA_FILTER Register
781
+ AT91_REG Reserved2[44]; //
782
+ AT91_REG US_RPR; // Receive Pointer Register
783
+ AT91_REG US_RCR; // Receive Counter Register
784
+ AT91_REG US_TPR; // Transmit Pointer Register
785
+ AT91_REG US_TCR; // Transmit Counter Register
786
+ AT91_REG US_RNPR; // Receive Next Pointer Register
787
+ AT91_REG US_RNCR; // Receive Next Counter Register
788
+ AT91_REG US_TNPR; // Transmit Next Pointer Register
789
+ AT91_REG US_TNCR; // Transmit Next Counter Register
790
+ AT91_REG US_PTCR; // PDC Transfer Control Register
791
+ AT91_REG US_PTSR; // PDC Transfer Status Register
792
+ } AT91S_USART, *AT91PS_USART;
793
+
794
+ // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
795
+ #define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
796
+ #define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
797
+ #define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
798
+ #define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
799
+ #define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
800
+ #define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
801
+ #define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
802
+ #define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
803
+ #define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
804
+ #define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
805
+ #define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
806
+ // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
807
+ #define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
808
+ #define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
809
+ #define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
810
+ #define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
811
+ #define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
812
+ #define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
813
+ #define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
814
+ #define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
815
+ #define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
816
+ #define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
817
+ #define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
818
+ #define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
819
+ #define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
820
+ #define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
821
+ #define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
822
+ #define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
823
+ #define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
824
+ #define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
825
+ #define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
826
+ #define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
827
+ #define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
828
+ #define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
829
+ #define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
830
+ #define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
831
+ #define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
832
+ #define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
833
+ #define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
834
+ #define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
835
+ #define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
836
+ #define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
837
+ #define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
838
+ #define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
839
+ // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
840
+ #define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
841
+ #define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
842
+ #define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
843
+ #define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
844
+ #define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
845
+ #define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
846
+ #define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
847
+ #define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
848
+ // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
849
+ // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
850
+ // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
851
+ #define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
852
+ #define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
853
+ #define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
854
+ #define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
855
+
856
+ // *****************************************************************************
857
+ // SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
858
+ // *****************************************************************************
859
+ typedef struct _AT91S_SSC {
860
+ AT91_REG SSC_CR; // Control Register
861
+ AT91_REG SSC_CMR; // Clock Mode Register
862
+ AT91_REG Reserved0[2]; //
863
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister
864
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register
865
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register
866
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register
867
+ AT91_REG SSC_RHR; // Receive Holding Register
868
+ AT91_REG SSC_THR; // Transmit Holding Register
869
+ AT91_REG Reserved1[2]; //
870
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register
871
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register
872
+ AT91_REG Reserved2[2]; //
873
+ AT91_REG SSC_SR; // Status Register
874
+ AT91_REG SSC_IER; // Interrupt Enable Register
875
+ AT91_REG SSC_IDR; // Interrupt Disable Register
876
+ AT91_REG SSC_IMR; // Interrupt Mask Register
877
+ AT91_REG Reserved3[44]; //
878
+ AT91_REG SSC_RPR; // Receive Pointer Register
879
+ AT91_REG SSC_RCR; // Receive Counter Register
880
+ AT91_REG SSC_TPR; // Transmit Pointer Register
881
+ AT91_REG SSC_TCR; // Transmit Counter Register
882
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register
883
+ AT91_REG SSC_RNCR; // Receive Next Counter Register
884
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register
885
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register
886
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register
887
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register
888
+ } AT91S_SSC, *AT91PS_SSC;
889
+
890
+ // -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
891
+ #define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
892
+ #define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
893
+ #define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
894
+ #define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
895
+ #define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
896
+ // -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
897
+ #define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
898
+ #define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
899
+ #define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
900
+ #define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
901
+ #define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
902
+ #define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
903
+ #define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
904
+ #define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
905
+ #define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
906
+ #define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
907
+ #define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
908
+ #define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
909
+ #define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
910
+ #define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
911
+ #define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
912
+ #define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
913
+ #define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
914
+ #define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
915
+ #define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
916
+ #define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
917
+ #define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
918
+ #define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
919
+ #define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
920
+ #define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection
921
+ #define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
922
+ #define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
923
+ // -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
924
+ #define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
925
+ #define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
926
+ #define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
927
+ #define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
928
+ #define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
929
+ #define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
930
+ #define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
931
+ #define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
932
+ #define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
933
+ #define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
934
+ #define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
935
+ #define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
936
+ #define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
937
+ // -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
938
+ // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
939
+ #define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
940
+ #define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
941
+ // -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
942
+ #define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
943
+ #define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
944
+ #define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
945
+ #define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
946
+ #define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
947
+ #define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
948
+ #define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
949
+ #define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
950
+ #define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0
951
+ #define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1
952
+ #define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
953
+ #define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
954
+ #define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
955
+ #define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
956
+ // -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
957
+ // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
958
+ // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
959
+
960
+ // *****************************************************************************
961
+ // SOFTWARE API DEFINITION FOR Two-wire Interface
962
+ // *****************************************************************************
963
+ typedef struct _AT91S_TWI {
964
+ AT91_REG TWI_CR; // Control Register
965
+ AT91_REG TWI_MMR; // Master Mode Register
966
+ AT91_REG Reserved0[1]; //
967
+ AT91_REG TWI_IADR; // Internal Address Register
968
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register
969
+ AT91_REG Reserved1[3]; //
970
+ AT91_REG TWI_SR; // Status Register
971
+ AT91_REG TWI_IER; // Interrupt Enable Register
972
+ AT91_REG TWI_IDR; // Interrupt Disable Register
973
+ AT91_REG TWI_IMR; // Interrupt Mask Register
974
+ AT91_REG TWI_RHR; // Receive Holding Register
975
+ AT91_REG TWI_THR; // Transmit Holding Register
976
+ } AT91S_TWI, *AT91PS_TWI;
977
+
978
+ // -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
979
+ #define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
980
+ #define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
981
+ #define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
982
+ #define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
983
+ #define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
984
+ // -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
985
+ #define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
986
+ #define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
987
+ #define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
988
+ #define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
989
+ #define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
990
+ #define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
991
+ #define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
992
+ // -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
993
+ #define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
994
+ #define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
995
+ #define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
996
+ // -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
997
+ #define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
998
+ #define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
999
+ #define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
1000
+ #define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
1001
+ #define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
1002
+ #define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
1003
+ // -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
1004
+ // -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
1005
+ // -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
1006
+
1007
+ // *****************************************************************************
1008
+ // SOFTWARE API DEFINITION FOR PWMC Channel Interface
1009
+ // *****************************************************************************
1010
+ typedef struct _AT91S_PWMC_CH {
1011
+ AT91_REG PWMC_CMR; // Channel Mode Register
1012
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
1013
+ AT91_REG PWMC_CPRDR; // Channel Period Register
1014
+ AT91_REG PWMC_CCNTR; // Channel Counter Register
1015
+ AT91_REG PWMC_CUPDR; // Channel Update Register
1016
+ AT91_REG PWMC_Reserved[3]; // Reserved
1017
+ } AT91S_PWMC_CH, *AT91PS_PWMC_CH;
1018
+
1019
+ // -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
1020
+ #define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
1021
+ #define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
1022
+ #define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
1023
+ #define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
1024
+ #define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
1025
+ #define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
1026
+ #define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
1027
+ // -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
1028
+ #define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
1029
+ // -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
1030
+ #define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
1031
+ // -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
1032
+ #define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
1033
+ // -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
1034
+ #define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
1035
+
1036
+ // *****************************************************************************
1037
+ // SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
1038
+ // *****************************************************************************
1039
+ typedef struct _AT91S_PWMC {
1040
+ AT91_REG PWMC_MR; // PWMC Mode Register
1041
+ AT91_REG PWMC_ENA; // PWMC Enable Register
1042
+ AT91_REG PWMC_DIS; // PWMC Disable Register
1043
+ AT91_REG PWMC_SR; // PWMC Status Register
1044
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
1045
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
1046
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
1047
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
1048
+ AT91_REG Reserved0[55]; //
1049
+ AT91_REG PWMC_VR; // PWMC Version Register
1050
+ AT91_REG Reserved1[64]; //
1051
+ AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
1052
+ } AT91S_PWMC, *AT91PS_PWMC;
1053
+
1054
+ // -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
1055
+ #define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
1056
+ #define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
1057
+ #define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
1058
+ #define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
1059
+ #define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
1060
+ #define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
1061
+ // -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
1062
+ #define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
1063
+ #define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
1064
+ #define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
1065
+ #define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
1066
+ // -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
1067
+ // -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
1068
+ // -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
1069
+ // -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
1070
+ // -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
1071
+ // -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
1072
+
1073
+ // *****************************************************************************
1074
+ // SOFTWARE API DEFINITION FOR USB Device Interface
1075
+ // *****************************************************************************
1076
+ typedef struct _AT91S_UDP {
1077
+ AT91_REG UDP_NUM; // Frame Number Register
1078
+ AT91_REG UDP_GLBSTATE; // Global State Register
1079
+ AT91_REG UDP_FADDR; // Function Address Register
1080
+ AT91_REG Reserved0[1]; //
1081
+ AT91_REG UDP_IER; // Interrupt Enable Register
1082
+ AT91_REG UDP_IDR; // Interrupt Disable Register
1083
+ AT91_REG UDP_IMR; // Interrupt Mask Register
1084
+ AT91_REG UDP_ISR; // Interrupt Status Register
1085
+ AT91_REG UDP_ICR; // Interrupt Clear Register
1086
+ AT91_REG Reserved1[1]; //
1087
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register
1088
+ AT91_REG Reserved2[1]; //
1089
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
1090
+ AT91_REG Reserved3[2]; //
1091
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
1092
+ AT91_REG Reserved4[3]; //
1093
+ AT91_REG UDP_TXVC; // Transceiver Control Register
1094
+ } AT91S_UDP, *AT91PS_UDP;
1095
+
1096
+ // -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
1097
+ #define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
1098
+ #define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
1099
+ #define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
1100
+ // -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
1101
+ #define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
1102
+ #define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
1103
+ #define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
1104
+ #define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
1105
+ #define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
1106
+ // -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
1107
+ #define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
1108
+ #define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
1109
+ // -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
1110
+ #define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
1111
+ #define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
1112
+ #define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
1113
+ #define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
1114
+ #define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
1115
+ #define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
1116
+ #define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
1117
+ #define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
1118
+ #define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
1119
+ #define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
1120
+ #define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
1121
+ // -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
1122
+ // -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
1123
+ // -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
1124
+ #define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
1125
+ // -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
1126
+ // -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
1127
+ #define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
1128
+ #define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
1129
+ #define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
1130
+ #define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
1131
+ #define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
1132
+ #define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
1133
+ // -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
1134
+ #define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
1135
+ #define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
1136
+ #define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
1137
+ #define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
1138
+ #define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
1139
+ #define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
1140
+ #define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
1141
+ #define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
1142
+ #define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
1143
+ #define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
1144
+ #define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
1145
+ #define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
1146
+ #define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
1147
+ #define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
1148
+ #define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
1149
+ #define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
1150
+ #define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
1151
+ #define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
1152
+ #define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
1153
+ // -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
1154
+ #define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
1155
+ #define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
1156
+
1157
+ // *****************************************************************************
1158
+ // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
1159
+ // *****************************************************************************
1160
+ typedef struct _AT91S_TC {
1161
+ AT91_REG TC_CCR; // Channel Control Register
1162
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
1163
+ AT91_REG Reserved0[2]; //
1164
+ AT91_REG TC_CV; // Counter Value
1165
+ AT91_REG TC_RA; // Register A
1166
+ AT91_REG TC_RB; // Register B
1167
+ AT91_REG TC_RC; // Register C
1168
+ AT91_REG TC_SR; // Status Register
1169
+ AT91_REG TC_IER; // Interrupt Enable Register
1170
+ AT91_REG TC_IDR; // Interrupt Disable Register
1171
+ AT91_REG TC_IMR; // Interrupt Mask Register
1172
+ } AT91S_TC, *AT91PS_TC;
1173
+
1174
+ // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
1175
+ #define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
1176
+ #define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
1177
+ #define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
1178
+ // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
1179
+ #define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
1180
+ #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
1181
+ #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
1182
+ #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
1183
+ #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
1184
+ #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
1185
+ #define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
1186
+ #define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
1187
+ #define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
1188
+ #define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
1189
+ #define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
1190
+ #define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
1191
+ #define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
1192
+ #define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
1193
+ #define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
1194
+ #define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
1195
+ #define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
1196
+ #define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
1197
+ #define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
1198
+ #define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
1199
+ #define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
1200
+ #define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
1201
+ #define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
1202
+ #define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
1203
+ #define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
1204
+ #define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
1205
+ #define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
1206
+ #define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
1207
+ #define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
1208
+ #define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
1209
+ #define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
1210
+ #define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
1211
+ #define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
1212
+ #define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
1213
+ #define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
1214
+ #define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
1215
+ #define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
1216
+ #define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
1217
+ #define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
1218
+ #define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
1219
+ #define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
1220
+ #define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
1221
+ #define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
1222
+ #define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
1223
+ #define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
1224
+ #define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
1225
+ #define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
1226
+ #define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
1227
+ #define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
1228
+ #define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
1229
+ #define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
1230
+ #define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
1231
+ #define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
1232
+ #define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
1233
+ #define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
1234
+ #define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
1235
+ #define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
1236
+ #define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
1237
+ #define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
1238
+ #define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
1239
+ #define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
1240
+ #define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
1241
+ #define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
1242
+ #define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
1243
+ #define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
1244
+ #define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
1245
+ #define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
1246
+ #define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
1247
+ #define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
1248
+ #define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
1249
+ #define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
1250
+ #define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
1251
+ #define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
1252
+ #define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
1253
+ #define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
1254
+ #define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
1255
+ #define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
1256
+ #define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
1257
+ #define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
1258
+ #define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
1259
+ #define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
1260
+ #define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
1261
+ #define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
1262
+ #define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
1263
+ #define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
1264
+ #define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
1265
+ #define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
1266
+ #define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
1267
+ #define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
1268
+ #define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
1269
+ #define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
1270
+ #define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
1271
+ #define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
1272
+ // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
1273
+ #define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
1274
+ #define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
1275
+ #define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
1276
+ #define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
1277
+ #define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
1278
+ #define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
1279
+ #define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
1280
+ #define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
1281
+ #define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
1282
+ #define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
1283
+ #define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
1284
+ // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
1285
+ // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
1286
+ // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
1287
+
1288
+ // *****************************************************************************
1289
+ // SOFTWARE API DEFINITION FOR Timer Counter Interface
1290
+ // *****************************************************************************
1291
+ typedef struct _AT91S_TCB {
1292
+ AT91S_TC TCB_TC0; // TC Channel 0
1293
+ AT91_REG Reserved0[4]; //
1294
+ AT91S_TC TCB_TC1; // TC Channel 1
1295
+ AT91_REG Reserved1[4]; //
1296
+ AT91S_TC TCB_TC2; // TC Channel 2
1297
+ AT91_REG Reserved2[4]; //
1298
+ AT91_REG TCB_BCR; // TC Block Control Register
1299
+ AT91_REG TCB_BMR; // TC Block Mode Register
1300
+ } AT91S_TCB, *AT91PS_TCB;
1301
+
1302
+ // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
1303
+ #define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
1304
+ // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
1305
+ #define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
1306
+ #define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
1307
+ #define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
1308
+ #define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
1309
+ #define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
1310
+ #define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
1311
+ #define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
1312
+ #define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
1313
+ #define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
1314
+ #define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
1315
+ #define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
1316
+ #define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
1317
+ #define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
1318
+ #define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
1319
+ #define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
1320
+
1321
+ // *****************************************************************************
1322
+ // SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
1323
+ // *****************************************************************************
1324
+ typedef struct _AT91S_CAN_MB {
1325
+ AT91_REG CAN_MB_MMR; // MailBox Mode Register
1326
+ AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
1327
+ AT91_REG CAN_MB_MID; // MailBox ID Register
1328
+ AT91_REG CAN_MB_MFID; // MailBox Family ID Register
1329
+ AT91_REG CAN_MB_MSR; // MailBox Status Register
1330
+ AT91_REG CAN_MB_MDL; // MailBox Data Low Register
1331
+ AT91_REG CAN_MB_MDH; // MailBox Data High Register
1332
+ AT91_REG CAN_MB_MCR; // MailBox Control Register
1333
+ } AT91S_CAN_MB, *AT91PS_CAN_MB;
1334
+
1335
+ // -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
1336
+ #define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
1337
+ #define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
1338
+ #define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
1339
+ #define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
1340
+ #define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
1341
+ #define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
1342
+ #define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB)
1343
+ #define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB)
1344
+ #define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB)
1345
+ // -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
1346
+ #define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
1347
+ #define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
1348
+ #define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
1349
+ // -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
1350
+ // -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
1351
+ // -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
1352
+ #define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value
1353
+ #define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
1354
+ #define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
1355
+ #define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
1356
+ #define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
1357
+ #define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
1358
+ // -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
1359
+ // -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
1360
+ // -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
1361
+ #define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
1362
+ #define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
1363
+
1364
+ // *****************************************************************************
1365
+ // SOFTWARE API DEFINITION FOR Control Area Network Interface
1366
+ // *****************************************************************************
1367
+ typedef struct _AT91S_CAN {
1368
+ AT91_REG CAN_MR; // Mode Register
1369
+ AT91_REG CAN_IER; // Interrupt Enable Register
1370
+ AT91_REG CAN_IDR; // Interrupt Disable Register
1371
+ AT91_REG CAN_IMR; // Interrupt Mask Register
1372
+ AT91_REG CAN_SR; // Status Register
1373
+ AT91_REG CAN_BR; // Baudrate Register
1374
+ AT91_REG CAN_TIM; // Timer Register
1375
+ AT91_REG CAN_TIMESTP; // Time Stamp Register
1376
+ AT91_REG CAN_ECR; // Error Counter Register
1377
+ AT91_REG CAN_TCR; // Transfer Command Register
1378
+ AT91_REG CAN_ACR; // Abort Command Register
1379
+ AT91_REG Reserved0[52]; //
1380
+ AT91_REG CAN_VR; // Version Register
1381
+ AT91_REG Reserved1[64]; //
1382
+ AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
1383
+ AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
1384
+ AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
1385
+ AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
1386
+ AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
1387
+ AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
1388
+ AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
1389
+ AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
1390
+ AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
1391
+ AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
1392
+ AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
1393
+ AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
1394
+ AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
1395
+ AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
1396
+ AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
1397
+ AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
1398
+ } AT91S_CAN, *AT91PS_CAN;
1399
+
1400
+ // -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
1401
+ #define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable
1402
+ #define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode
1403
+ #define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
1404
+ #define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame
1405
+ #define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
1406
+ #define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
1407
+ #define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze
1408
+ #define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat
1409
+ // -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
1410
+ #define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag
1411
+ #define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag
1412
+ #define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag
1413
+ #define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag
1414
+ #define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag
1415
+ #define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag
1416
+ #define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag
1417
+ #define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag
1418
+ #define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag
1419
+ #define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag
1420
+ #define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
1421
+ #define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
1422
+ #define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
1423
+ #define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
1424
+ #define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
1425
+ #define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
1426
+ #define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
1427
+ #define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
1428
+ #define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
1429
+ #define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
1430
+ #define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
1431
+ #define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
1432
+ #define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
1433
+ #define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
1434
+ #define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error
1435
+ #define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
1436
+ #define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
1437
+ #define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error
1438
+ #define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error
1439
+ // -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
1440
+ // -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
1441
+ // -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
1442
+ #define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
1443
+ #define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
1444
+ #define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
1445
+ // -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
1446
+ #define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment
1447
+ #define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment
1448
+ #define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment
1449
+ #define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
1450
+ #define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
1451
+ #define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
1452
+ // -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
1453
+ #define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field
1454
+ // -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
1455
+ // -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
1456
+ #define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter
1457
+ #define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
1458
+ // -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
1459
+ #define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
1460
+ // -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
1461
+
1462
+ // *****************************************************************************
1463
+ // SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
1464
+ // *****************************************************************************
1465
+ typedef struct _AT91S_EMAC {
1466
+ AT91_REG EMAC_NCR; // Network Control Register
1467
+ AT91_REG EMAC_NCFGR; // Network Configuration Register
1468
+ AT91_REG EMAC_NSR; // Network Status Register
1469
+ AT91_REG Reserved0[2]; //
1470
+ AT91_REG EMAC_TSR; // Transmit Status Register
1471
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
1472
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
1473
+ AT91_REG EMAC_RSR; // Receive Status Register
1474
+ AT91_REG EMAC_ISR; // Interrupt Status Register
1475
+ AT91_REG EMAC_IER; // Interrupt Enable Register
1476
+ AT91_REG EMAC_IDR; // Interrupt Disable Register
1477
+ AT91_REG EMAC_IMR; // Interrupt Mask Register
1478
+ AT91_REG EMAC_MAN; // PHY Maintenance Register
1479
+ AT91_REG EMAC_PTR; // Pause Time Register
1480
+ AT91_REG EMAC_PFR; // Pause Frames received Register
1481
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register
1482
+ AT91_REG EMAC_SCF; // Single Collision Frame Register
1483
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register
1484
+ AT91_REG EMAC_FRO; // Frames Received OK Register
1485
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
1486
+ AT91_REG EMAC_ALE; // Alignment Error Register
1487
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
1488
+ AT91_REG EMAC_LCOL; // Late Collision Register
1489
+ AT91_REG EMAC_ECOL; // Excessive Collision Register
1490
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register
1491
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register
1492
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register
1493
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register
1494
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register
1495
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register
1496
+ AT91_REG EMAC_RJA; // Receive Jabbers Register
1497
+ AT91_REG EMAC_USF; // Undersize Frames Register
1498
+ AT91_REG EMAC_STE; // SQE Test Error Register
1499
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
1500
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
1501
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
1502
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]
1503
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
1504
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
1505
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
1506
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
1507
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
1508
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
1509
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
1510
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
1511
+ AT91_REG EMAC_TID; // Type ID Checking Register
1512
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
1513
+ AT91_REG EMAC_USRIO; // USER Input/Output Register
1514
+ AT91_REG EMAC_WOL; // Wake On LAN Register
1515
+ AT91_REG Reserved1[13]; //
1516
+ AT91_REG EMAC_REV; // Revision Register
1517
+ } AT91S_EMAC, *AT91PS_EMAC;
1518
+
1519
+ // -------- EMAC_NCR : (EMAC Offset: 0x0) --------
1520
+ #define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
1521
+ #define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
1522
+ #define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
1523
+ #define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
1524
+ #define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
1525
+ #define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
1526
+ #define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
1527
+ #define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
1528
+ #define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
1529
+ #define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission.
1530
+ #define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
1531
+ #define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
1532
+ #define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
1533
+ // -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
1534
+ #define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
1535
+ #define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
1536
+ #define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames.
1537
+ #define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
1538
+ #define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
1539
+ #define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable
1540
+ #define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
1541
+ #define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
1542
+ #define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
1543
+ #define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
1544
+ #define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
1545
+ #define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
1546
+ #define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
1547
+ #define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
1548
+ #define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
1549
+ #define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC)
1550
+ #define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC)
1551
+ #define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
1552
+ #define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
1553
+ #define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
1554
+ #define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
1555
+ #define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
1556
+ #define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
1557
+ #define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC)
1558
+ #define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
1559
+ // -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
1560
+ #define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC)
1561
+ #define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
1562
+ #define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
1563
+ // -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
1564
+ #define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC)
1565
+ #define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
1566
+ #define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC)
1567
+ #define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go
1568
+ #define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame
1569
+ #define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
1570
+ #define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
1571
+ // -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
1572
+ #define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
1573
+ #define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
1574
+ #define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC)
1575
+ // -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
1576
+ #define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC)
1577
+ #define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC)
1578
+ #define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC)
1579
+ #define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC)
1580
+ #define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC)
1581
+ #define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC)
1582
+ #define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC)
1583
+ #define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC)
1584
+ #define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
1585
+ #define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
1586
+ #define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
1587
+ #define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC)
1588
+ #define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC)
1589
+ // -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
1590
+ // -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
1591
+ // -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
1592
+ // -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
1593
+ #define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
1594
+ #define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
1595
+ #define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
1596
+ #define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
1597
+ #define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
1598
+ #define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC)
1599
+ // -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
1600
+ #define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII
1601
+ #define AT91C_EMAC_CLKEN ((unsigned int) 0x1 << 1) // (EMAC) Clock Enable
1602
+ // -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
1603
+ #define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address
1604
+ #define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
1605
+ #define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
1606
+ #define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
1607
+ // -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
1608
+ #define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC)
1609
+ #define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC)
1610
+
1611
+ // *****************************************************************************
1612
+ // SOFTWARE API DEFINITION FOR Analog to Digital Convertor
1613
+ // *****************************************************************************
1614
+ typedef struct _AT91S_ADC {
1615
+ AT91_REG ADC_CR; // ADC Control Register
1616
+ AT91_REG ADC_MR; // ADC Mode Register
1617
+ AT91_REG Reserved0[2]; //
1618
+ AT91_REG ADC_CHER; // ADC Channel Enable Register
1619
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register
1620
+ AT91_REG ADC_CHSR; // ADC Channel Status Register
1621
+ AT91_REG ADC_SR; // ADC Status Register
1622
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register
1623
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register
1624
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register
1625
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register
1626
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0
1627
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1
1628
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2
1629
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3
1630
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4
1631
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5
1632
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6
1633
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7
1634
+ AT91_REG Reserved1[44]; //
1635
+ AT91_REG ADC_RPR; // Receive Pointer Register
1636
+ AT91_REG ADC_RCR; // Receive Counter Register
1637
+ AT91_REG ADC_TPR; // Transmit Pointer Register
1638
+ AT91_REG ADC_TCR; // Transmit Counter Register
1639
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register
1640
+ AT91_REG ADC_RNCR; // Receive Next Counter Register
1641
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register
1642
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register
1643
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register
1644
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register
1645
+ } AT91S_ADC, *AT91PS_ADC;
1646
+
1647
+ // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
1648
+ #define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
1649
+ #define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
1650
+ // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
1651
+ #define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
1652
+ #define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
1653
+ #define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
1654
+ #define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
1655
+ #define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
1656
+ #define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
1657
+ #define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
1658
+ #define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
1659
+ #define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
1660
+ #define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
1661
+ #define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
1662
+ #define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
1663
+ #define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
1664
+ #define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
1665
+ #define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
1666
+ #define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
1667
+ #define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
1668
+ #define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
1669
+ #define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
1670
+ #define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
1671
+ // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
1672
+ #define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
1673
+ #define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
1674
+ #define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
1675
+ #define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
1676
+ #define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
1677
+ #define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
1678
+ #define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
1679
+ #define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
1680
+ // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
1681
+ // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
1682
+ // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
1683
+ #define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
1684
+ #define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
1685
+ #define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
1686
+ #define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
1687
+ #define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
1688
+ #define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
1689
+ #define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
1690
+ #define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
1691
+ #define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
1692
+ #define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
1693
+ #define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
1694
+ #define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
1695
+ #define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
1696
+ #define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
1697
+ #define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
1698
+ #define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
1699
+ #define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
1700
+ #define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
1701
+ #define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
1702
+ #define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
1703
+ // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
1704
+ #define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
1705
+ // -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
1706
+ // -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
1707
+ // -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
1708
+ // -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
1709
+ #define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
1710
+ // -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
1711
+ // -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
1712
+ // -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
1713
+ // -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
1714
+ // -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
1715
+ // -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
1716
+ // -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
1717
+
1718
+ // *****************************************************************************
1719
+ // REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
1720
+ // *****************************************************************************
1721
+ // ========== Register definition for SYS peripheral ==========
1722
+ // ========== Register definition for AIC peripheral ==========
1723
+ #define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
1724
+ #define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
1725
+ #define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
1726
+ #define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
1727
+ #define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
1728
+ #define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
1729
+ #define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
1730
+ #define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
1731
+ #define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
1732
+ #define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
1733
+ #define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
1734
+ #define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
1735
+ #define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
1736
+ #define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
1737
+ #define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
1738
+ #define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
1739
+ #define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
1740
+ #define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
1741
+ // ========== Register definition for PDC_DBGU peripheral ==========
1742
+ #define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
1743
+ #define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
1744
+ #define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
1745
+ #define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
1746
+ #define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
1747
+ #define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
1748
+ #define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
1749
+ #define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
1750
+ #define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
1751
+ #define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
1752
+ // ========== Register definition for DBGU peripheral ==========
1753
+ #define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
1754
+ #define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
1755
+ #define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
1756
+ #define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
1757
+ #define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
1758
+ #define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
1759
+ #define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
1760
+ #define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
1761
+ #define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
1762
+ #define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
1763
+ #define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
1764
+ #define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
1765
+ // ========== Register definition for PIOA peripheral ==========
1766
+ #define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
1767
+ #define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
1768
+ #define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
1769
+ #define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
1770
+ #define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
1771
+ #define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
1772
+ #define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
1773
+ #define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
1774
+ #define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
1775
+ #define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
1776
+ #define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
1777
+ #define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
1778
+ #define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
1779
+ #define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
1780
+ #define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
1781
+ #define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
1782
+ #define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
1783
+ #define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
1784
+ #define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
1785
+ #define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
1786
+ #define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
1787
+ #define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
1788
+ #define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
1789
+ #define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
1790
+ #define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
1791
+ #define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
1792
+ #define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
1793
+ #define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
1794
+ #define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
1795
+ // ========== Register definition for PIOB peripheral ==========
1796
+ #define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
1797
+ #define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
1798
+ #define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
1799
+ #define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
1800
+ #define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
1801
+ #define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
1802
+ #define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
1803
+ #define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
1804
+ #define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
1805
+ #define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
1806
+ #define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
1807
+ #define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
1808
+ #define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
1809
+ #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
1810
+ #define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
1811
+ #define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
1812
+ #define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
1813
+ #define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
1814
+ #define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
1815
+ #define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
1816
+ #define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
1817
+ #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
1818
+ #define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
1819
+ #define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
1820
+ #define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
1821
+ #define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
1822
+ #define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
1823
+ #define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
1824
+ #define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
1825
+ // ========== Register definition for CKGR peripheral ==========
1826
+ #define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
1827
+ #define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
1828
+ #define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
1829
+ // ========== Register definition for PMC peripheral ==========
1830
+ #define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
1831
+ #define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
1832
+ #define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
1833
+ #define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
1834
+ #define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
1835
+ #define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
1836
+ #define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
1837
+ #define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
1838
+ #define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
1839
+ #define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
1840
+ #define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
1841
+ #define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
1842
+ #define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
1843
+ #define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
1844
+ #define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
1845
+ // ========== Register definition for RSTC peripheral ==========
1846
+ #define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
1847
+ #define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
1848
+ #define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
1849
+ // ========== Register definition for RTTC peripheral ==========
1850
+ #define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
1851
+ #define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
1852
+ #define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
1853
+ #define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
1854
+ // ========== Register definition for PITC peripheral ==========
1855
+ #define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
1856
+ #define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
1857
+ #define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
1858
+ #define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
1859
+ // ========== Register definition for WDTC peripheral ==========
1860
+ #define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
1861
+ #define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
1862
+ #define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
1863
+ // ========== Register definition for VREG peripheral ==========
1864
+ #define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
1865
+ // ========== Register definition for MC peripheral ==========
1866
+ #define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
1867
+ #define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
1868
+ #define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
1869
+ #define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
1870
+ #define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
1871
+ #define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
1872
+ // ========== Register definition for PDC_SPI1 peripheral ==========
1873
+ #define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
1874
+ #define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
1875
+ #define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
1876
+ #define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
1877
+ #define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
1878
+ #define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
1879
+ #define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
1880
+ #define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
1881
+ #define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
1882
+ #define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
1883
+ // ========== Register definition for SPI1 peripheral ==========
1884
+ #define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
1885
+ #define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
1886
+ #define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
1887
+ #define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
1888
+ #define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
1889
+ #define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
1890
+ #define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
1891
+ #define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
1892
+ #define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
1893
+ // ========== Register definition for PDC_SPI0 peripheral ==========
1894
+ #define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
1895
+ #define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
1896
+ #define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
1897
+ #define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
1898
+ #define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
1899
+ #define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
1900
+ #define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
1901
+ #define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
1902
+ #define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
1903
+ #define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
1904
+ // ========== Register definition for SPI0 peripheral ==========
1905
+ #define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
1906
+ #define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
1907
+ #define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
1908
+ #define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
1909
+ #define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
1910
+ #define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
1911
+ #define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
1912
+ #define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
1913
+ #define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
1914
+ // ========== Register definition for PDC_US1 peripheral ==========
1915
+ #define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
1916
+ #define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
1917
+ #define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
1918
+ #define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
1919
+ #define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
1920
+ #define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
1921
+ #define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
1922
+ #define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
1923
+ #define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
1924
+ #define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
1925
+ // ========== Register definition for US1 peripheral ==========
1926
+ #define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
1927
+ #define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
1928
+ #define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
1929
+ #define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
1930
+ #define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
1931
+ #define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
1932
+ #define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
1933
+ #define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
1934
+ #define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
1935
+ #define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
1936
+ #define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
1937
+ #define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
1938
+ #define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
1939
+ #define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
1940
+ // ========== Register definition for PDC_US0 peripheral ==========
1941
+ #define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
1942
+ #define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
1943
+ #define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
1944
+ #define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
1945
+ #define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
1946
+ #define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
1947
+ #define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
1948
+ #define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
1949
+ #define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
1950
+ #define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
1951
+ // ========== Register definition for US0 peripheral ==========
1952
+ #define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
1953
+ #define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
1954
+ #define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
1955
+ #define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
1956
+ #define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
1957
+ #define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
1958
+ #define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
1959
+ #define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
1960
+ #define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
1961
+ #define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
1962
+ #define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
1963
+ #define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
1964
+ #define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
1965
+ #define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
1966
+ // ========== Register definition for PDC_SSC peripheral ==========
1967
+ #define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
1968
+ #define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
1969
+ #define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
1970
+ #define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
1971
+ #define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
1972
+ #define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
1973
+ #define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
1974
+ #define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
1975
+ #define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
1976
+ #define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
1977
+ // ========== Register definition for SSC peripheral ==========
1978
+ #define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
1979
+ #define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
1980
+ #define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
1981
+ #define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
1982
+ #define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
1983
+ #define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
1984
+ #define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
1985
+ #define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
1986
+ #define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
1987
+ #define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
1988
+ #define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
1989
+ #define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
1990
+ #define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
1991
+ #define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
1992
+ // ========== Register definition for TWI peripheral ==========
1993
+ #define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
1994
+ #define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
1995
+ #define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
1996
+ #define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
1997
+ #define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
1998
+ #define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
1999
+ #define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
2000
+ #define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
2001
+ #define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
2002
+ #define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
2003
+ // ========== Register definition for PWMC_CH3 peripheral ==========
2004
+ #define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
2005
+ #define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
2006
+ #define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
2007
+ #define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
2008
+ #define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
2009
+ #define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
2010
+ // ========== Register definition for PWMC_CH2 peripheral ==========
2011
+ #define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
2012
+ #define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
2013
+ #define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
2014
+ #define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
2015
+ #define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
2016
+ #define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
2017
+ // ========== Register definition for PWMC_CH1 peripheral ==========
2018
+ #define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
2019
+ #define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
2020
+ #define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
2021
+ #define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
2022
+ #define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
2023
+ #define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
2024
+ // ========== Register definition for PWMC_CH0 peripheral ==========
2025
+ #define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
2026
+ #define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
2027
+ #define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
2028
+ #define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
2029
+ #define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
2030
+ #define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
2031
+ // ========== Register definition for PWMC peripheral ==========
2032
+ #define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
2033
+ #define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
2034
+ #define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
2035
+ #define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
2036
+ #define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
2037
+ #define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
2038
+ #define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
2039
+ #define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
2040
+ #define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
2041
+ // ========== Register definition for UDP peripheral ==========
2042
+ #define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
2043
+ #define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
2044
+ #define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
2045
+ #define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
2046
+ #define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
2047
+ #define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
2048
+ #define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
2049
+ #define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
2050
+ #define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
2051
+ #define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
2052
+ #define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
2053
+ #define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
2054
+ // ========== Register definition for TC0 peripheral ==========
2055
+ #define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
2056
+ #define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
2057
+ #define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
2058
+ #define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
2059
+ #define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
2060
+ #define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
2061
+ #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
2062
+ #define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
2063
+ #define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
2064
+ #define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
2065
+ // ========== Register definition for TC1 peripheral ==========
2066
+ #define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
2067
+ #define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
2068
+ #define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
2069
+ #define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
2070
+ #define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
2071
+ #define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
2072
+ #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
2073
+ #define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
2074
+ #define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
2075
+ #define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
2076
+ // ========== Register definition for TC2 peripheral ==========
2077
+ #define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
2078
+ #define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
2079
+ #define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
2080
+ #define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
2081
+ #define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
2082
+ #define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
2083
+ #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
2084
+ #define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
2085
+ #define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
2086
+ #define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
2087
+ // ========== Register definition for TCB peripheral ==========
2088
+ #define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
2089
+ #define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
2090
+ // ========== Register definition for CAN_MB0 peripheral ==========
2091
+ #define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
2092
+ #define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
2093
+ #define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
2094
+ #define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
2095
+ #define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
2096
+ #define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
2097
+ #define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
2098
+ #define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
2099
+ // ========== Register definition for CAN_MB1 peripheral ==========
2100
+ #define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
2101
+ #define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
2102
+ #define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
2103
+ #define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
2104
+ #define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
2105
+ #define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
2106
+ #define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
2107
+ #define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
2108
+ // ========== Register definition for CAN_MB2 peripheral ==========
2109
+ #define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
2110
+ #define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
2111
+ #define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
2112
+ #define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
2113
+ #define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
2114
+ #define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
2115
+ #define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
2116
+ #define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
2117
+ // ========== Register definition for CAN_MB3 peripheral ==========
2118
+ #define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
2119
+ #define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
2120
+ #define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
2121
+ #define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
2122
+ #define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
2123
+ #define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
2124
+ #define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
2125
+ #define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
2126
+ // ========== Register definition for CAN_MB4 peripheral ==========
2127
+ #define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
2128
+ #define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
2129
+ #define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
2130
+ #define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
2131
+ #define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
2132
+ #define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
2133
+ #define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
2134
+ #define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
2135
+ // ========== Register definition for CAN_MB5 peripheral ==========
2136
+ #define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
2137
+ #define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
2138
+ #define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
2139
+ #define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
2140
+ #define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
2141
+ #define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
2142
+ #define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
2143
+ #define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
2144
+ // ========== Register definition for CAN_MB6 peripheral ==========
2145
+ #define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
2146
+ #define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
2147
+ #define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
2148
+ #define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
2149
+ #define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
2150
+ #define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
2151
+ #define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
2152
+ #define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
2153
+ // ========== Register definition for CAN_MB7 peripheral ==========
2154
+ #define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
2155
+ #define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
2156
+ #define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
2157
+ #define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
2158
+ #define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
2159
+ #define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
2160
+ #define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
2161
+ #define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
2162
+ // ========== Register definition for CAN peripheral ==========
2163
+ #define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
2164
+ #define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
2165
+ #define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
2166
+ #define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
2167
+ #define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
2168
+ #define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
2169
+ #define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
2170
+ #define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
2171
+ #define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
2172
+ #define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
2173
+ #define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
2174
+ #define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
2175
+ // ========== Register definition for EMAC peripheral ==========
2176
+ #define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
2177
+ #define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
2178
+ #define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
2179
+ #define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
2180
+ #define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
2181
+ #define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
2182
+ #define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
2183
+ #define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
2184
+ #define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
2185
+ #define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
2186
+ #define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
2187
+ #define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
2188
+ #define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
2189
+ #define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
2190
+ #define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
2191
+ #define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
2192
+ #define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
2193
+ #define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
2194
+ #define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
2195
+ #define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
2196
+ #define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
2197
+ #define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
2198
+ #define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
2199
+ #define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
2200
+ #define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
2201
+ #define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
2202
+ #define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
2203
+ #define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
2204
+ #define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
2205
+ #define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
2206
+ #define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
2207
+ #define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
2208
+ #define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
2209
+ #define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
2210
+ #define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
2211
+ #define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
2212
+ #define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
2213
+ #define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
2214
+ #define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
2215
+ #define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
2216
+ #define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
2217
+ #define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
2218
+ #define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
2219
+ #define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
2220
+ #define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
2221
+ #define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
2222
+ #define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
2223
+ #define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
2224
+ #define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
2225
+ // ========== Register definition for PDC_ADC peripheral ==========
2226
+ #define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
2227
+ #define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
2228
+ #define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
2229
+ #define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
2230
+ #define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
2231
+ #define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
2232
+ #define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
2233
+ #define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
2234
+ #define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
2235
+ #define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
2236
+ // ========== Register definition for ADC peripheral ==========
2237
+ #define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
2238
+ #define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
2239
+ #define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
2240
+ #define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
2241
+ #define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
2242
+ #define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
2243
+ #define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
2244
+ #define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
2245
+ #define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
2246
+ #define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
2247
+ #define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
2248
+ #define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
2249
+ #define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
2250
+ #define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
2251
+ #define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
2252
+ #define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
2253
+ #define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
2254
+ #define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
2255
+
2256
+ // *****************************************************************************
2257
+ // PIO DEFINITIONS FOR AT91SAM7X256
2258
+ // *****************************************************************************
2259
+ #define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
2260
+ #define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
2261
+ #define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
2262
+ #define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
2263
+ #define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
2264
+ #define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
2265
+ #define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
2266
+ #define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
2267
+ #define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
2268
+ #define AT91C_PA12_SPI0_NPCS0 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
2269
+ #define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
2270
+ #define AT91C_PA13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
2271
+ #define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
2272
+ #define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
2273
+ #define AT91C_PA14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
2274
+ #define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
2275
+ #define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
2276
+ #define AT91C_PA15_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
2277
+ #define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
2278
+ #define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
2279
+ #define AT91C_PA16_SPI0_MISO ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
2280
+ #define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
2281
+ #define AT91C_PA17_SPI0_MOSI ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
2282
+ #define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
2283
+ #define AT91C_PA18_SPI0_SPCK ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
2284
+ #define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
2285
+ #define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
2286
+ #define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
2287
+ #define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
2288
+ #define AT91C_PA2_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
2289
+ #define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
2290
+ #define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
2291
+ #define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
2292
+ #define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
2293
+ #define AT91C_PA21_SPI1_NPCS0 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
2294
+ #define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
2295
+ #define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
2296
+ #define AT91C_PA22_SPI1_SPCK ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
2297
+ #define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
2298
+ #define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
2299
+ #define AT91C_PA23_SPI1_MOSI ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
2300
+ #define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
2301
+ #define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
2302
+ #define AT91C_PA24_SPI1_MISO ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
2303
+ #define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
2304
+ #define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
2305
+ #define AT91C_PA25_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
2306
+ #define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
2307
+ #define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
2308
+ #define AT91C_PA26_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
2309
+ #define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
2310
+ #define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
2311
+ #define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
2312
+ #define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
2313
+ #define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
2314
+ #define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
2315
+ #define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
2316
+ #define AT91C_PA29_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
2317
+ #define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
2318
+ #define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
2319
+ #define AT91C_PA3_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
2320
+ #define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
2321
+ #define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
2322
+ #define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
2323
+ #define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
2324
+ #define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
2325
+ #define AT91C_PA4_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
2326
+ #define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
2327
+ #define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
2328
+ #define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
2329
+ #define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
2330
+ #define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
2331
+ #define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
2332
+ #define AT91C_PA7_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
2333
+ #define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
2334
+ #define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
2335
+ #define AT91C_PA8_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
2336
+ #define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
2337
+ #define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
2338
+ #define AT91C_PA9_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
2339
+ #define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
2340
+ #define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
2341
+ #define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
2342
+ #define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
2343
+ #define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
2344
+ #define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
2345
+ #define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
2346
+ #define AT91C_PB10_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
2347
+ #define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
2348
+ #define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
2349
+ #define AT91C_PB11_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
2350
+ #define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
2351
+ #define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
2352
+ #define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
2353
+ #define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
2354
+ #define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
2355
+ #define AT91C_PB13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
2356
+ #define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
2357
+ #define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
2358
+ #define AT91C_PB14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
2359
+ #define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
2360
+ #define AT91C_PB15_ERXDV_ECRSDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
2361
+ #define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
2362
+ #define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
2363
+ #define AT91C_PB16_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
2364
+ #define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
2365
+ #define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
2366
+ #define AT91C_PB17_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
2367
+ #define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
2368
+ #define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
2369
+ #define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
2370
+ #define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
2371
+ #define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
2372
+ #define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
2373
+ #define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
2374
+ #define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
2375
+ #define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
2376
+ #define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
2377
+ #define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
2378
+ #define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
2379
+ #define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
2380
+ #define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
2381
+ #define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
2382
+ #define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
2383
+ #define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
2384
+ #define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
2385
+ #define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
2386
+ #define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
2387
+ #define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
2388
+ #define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
2389
+ #define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
2390
+ #define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
2391
+ #define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
2392
+ #define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
2393
+ #define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
2394
+ #define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
2395
+ #define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
2396
+ #define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
2397
+ #define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
2398
+ #define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
2399
+ #define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
2400
+ #define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
2401
+ #define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
2402
+ #define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
2403
+ #define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
2404
+ #define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
2405
+ #define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
2406
+ #define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
2407
+ #define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
2408
+ #define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
2409
+ #define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
2410
+ #define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
2411
+ #define AT91C_PB4_ECRS ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
2412
+ #define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
2413
+ #define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
2414
+ #define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
2415
+ #define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
2416
+ #define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
2417
+ #define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
2418
+ #define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
2419
+ #define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
2420
+ #define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
2421
+ #define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
2422
+
2423
+ // *****************************************************************************
2424
+ // PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
2425
+ // *****************************************************************************
2426
+ #define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
2427
+ #define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
2428
+ #define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
2429
+ #define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
2430
+ #define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0
2431
+ #define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1
2432
+ #define AT91C_ID_US0 ((unsigned int) 6) // USART 0
2433
+ #define AT91C_ID_US1 ((unsigned int) 7) // USART 1
2434
+ #define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
2435
+ #define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
2436
+ #define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
2437
+ #define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
2438
+ #define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
2439
+ #define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
2440
+ #define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
2441
+ #define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller
2442
+ #define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC
2443
+ #define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter
2444
+ #define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved
2445
+ #define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved
2446
+ #define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
2447
+ #define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
2448
+ #define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
2449
+ #define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
2450
+ #define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
2451
+ #define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
2452
+ #define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
2453
+ #define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
2454
+ #define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
2455
+ #define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
2456
+ #define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
2457
+ #define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
2458
+ #define AT91C_ALL_INT ((unsigned int) 0xC003FFFF) // ALL VALID INTERRUPTS
2459
+
2460
+ // *****************************************************************************
2461
+ // BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
2462
+ // *****************************************************************************
2463
+
2464
+ #ifdef TEST
2465
+
2466
+ extern AT91S_AIC AicPeripheral;
2467
+ extern AT91S_PIO PioAPeripheral;
2468
+ extern AT91S_PIO PioBPeripheral;
2469
+ extern AT91S_PMC PmcPeripheral;
2470
+ extern AT91S_USART Usart0Peripheral;
2471
+ extern AT91S_TC TimerCounter0Peripheral;
2472
+ extern AT91S_ADC AdcPeripheral;
2473
+
2474
+ #define AIC_ADDR &AicPeripheral
2475
+ #define PIOA_ADDR &PioAPeripheral
2476
+ #define PIOB_ADDR &PioBPeripheral
2477
+ #define PMC_ADDR &PmcPeripheral
2478
+ #define US0_ADDR &Usart0Peripheral
2479
+ #define TC0_ADDR &TimerCounter0Peripheral
2480
+ #define ADC_ADDR &AdcPeripheral
2481
+
2482
+ #else
2483
+
2484
+ #define AIC_ADDR 0xFFFFF000
2485
+ #define PIOA_ADDR 0xFFFFF400
2486
+ #define PIOB_ADDR 0xFFFFF600
2487
+ #define PMC_ADDR 0xFFFFFC00
2488
+ #define US0_ADDR 0xFFFC0000
2489
+ #define TC0_ADDR 0xFFFA0000
2490
+ #define ADC_ADDR 0xFFFD8000
2491
+
2492
+ #endif // TEST
2493
+
2494
+ #define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
2495
+ #define AT91C_BASE_AIC ((AT91PS_AIC) AIC_ADDR) // (AIC) Base Address
2496
+ #define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
2497
+ #define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
2498
+ #define AT91C_BASE_PIOA ((AT91PS_PIO) PIOA_ADDR) // (PIOA) Base Address
2499
+ #define AT91C_BASE_PIOB ((AT91PS_PIO) PIOB_ADDR) // (PIOB) Base Address
2500
+ #define AT91C_BASE_PMC ((AT91PS_PMC) PMC_ADDR) // (PMC) Base Address
2501
+ #define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
2502
+ #define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
2503
+ #define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
2504
+ #define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
2505
+ #define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
2506
+ #define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
2507
+ #define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
2508
+ #define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
2509
+ #define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
2510
+ #define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
2511
+ #define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
2512
+ #define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
2513
+ #define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
2514
+ #define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
2515
+ #define AT91C_BASE_US0 ((AT91PS_USART) US0_ADDR) // (US0) Base Address
2516
+ #define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
2517
+ #define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
2518
+ #define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
2519
+ #define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
2520
+ #define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
2521
+ #define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
2522
+ #define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
2523
+ #define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
2524
+ #define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
2525
+ #define AT91C_BASE_TC0 ((AT91PS_TC) TC0_ADDR) // (TC0) Base Address
2526
+ #define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
2527
+ #define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
2528
+ #define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
2529
+ #define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
2530
+ #define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
2531
+ #define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
2532
+ #define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
2533
+ #define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
2534
+ #define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
2535
+ #define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
2536
+ #define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
2537
+ #define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
2538
+ #define AT91C_BASE_ADC ((AT91PS_ADC) ADC_ADDR) // (ADC) Base Address
2539
+ #define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
2540
+ #define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
2541
+
2542
+ // *****************************************************************************
2543
+ // MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
2544
+ // *****************************************************************************
2545
+ // ISRAM
2546
+ #define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
2547
+ #define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbytes)
2548
+ // IFLASH
2549
+ #define AT91C_IFLASH ((char *) 0x00100000) // Internal FLASH base address
2550
+ #define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal FLASH size in byte (256 Kbytes)
2551
+ #define AT91C_IFLASH_PAGE_SIZE ((unsigned int) 256) // Internal FLASH Page Size: 256 bytes
2552
+ #define AT91C_IFLASH_LOCK_REGION_SIZE ((unsigned int) 16384) // Internal FLASH Lock Region Size: 16 Kbytes
2553
+ #define AT91C_IFLASH_NB_OF_PAGES ((unsigned int) 1024) // Internal FLASH Number of Pages: 1024 bytes
2554
+ #define AT91C_IFLASH_NB_OF_LOCK_BITS ((unsigned int) 16) // Internal FLASH Number of Lock Bits: 16 bytes
2555
+
2556
+ #endif