ceedling 0.0.1

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Files changed (991) hide show
  1. data/.gitignore +4 -0
  2. data/.vim +1 -0
  3. data/Gemfile +3 -0
  4. data/LICENSE +19 -0
  5. data/Rakefile +18 -0
  6. data/bin/ceedling +39 -0
  7. data/ceedling.gemspec +23 -0
  8. data/lib/ceedling/version.rb +10 -0
  9. data/lib/ceedling/version.rb.erb +10 -0
  10. data/lib/ceedling.rb +5 -0
  11. data/new_project_template/build/.gitkeep +0 -0
  12. data/new_project_template/project.yml +65 -0
  13. data/new_project_template/rakefile.rb +4 -0
  14. data/new_project_template/src/.gitkeep +0 -0
  15. data/new_project_template/test/.gitkeep +0 -0
  16. data/new_project_template/test/support/.gitkeep +0 -0
  17. data/new_project_template/vendor/ceedling/config/test_environment.rb +12 -0
  18. data/new_project_template/vendor/ceedling/docs/Ceedling Packet.odt +0 -0
  19. data/new_project_template/vendor/ceedling/docs/Ceedling Packet.pdf +0 -0
  20. data/new_project_template/vendor/ceedling/docs/CeedlingLogo.png +0 -0
  21. data/new_project_template/vendor/ceedling/examples/temp_sensor/gcc.yml +42 -0
  22. data/new_project_template/vendor/ceedling/examples/temp_sensor/iar_v4.yml +91 -0
  23. data/new_project_template/vendor/ceedling/examples/temp_sensor/iar_v5.yml +80 -0
  24. data/new_project_template/vendor/ceedling/examples/temp_sensor/project.yml +65 -0
  25. data/new_project_template/vendor/ceedling/examples/temp_sensor/rakefile.rb +5 -0
  26. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcConductor.c +42 -0
  27. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcConductor.h +13 -0
  28. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardware.c +27 -0
  29. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardware.h +11 -0
  30. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardwareConfigurator.c +18 -0
  31. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardwareConfigurator.h +10 -0
  32. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcModel.c +33 -0
  33. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcModel.h +13 -0
  34. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcTemperatureSensor.c +51 -0
  35. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcTemperatureSensor.h +10 -0
  36. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Executor.c +25 -0
  37. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Executor.h +9 -0
  38. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/IntrinsicsWrapper.c +18 -0
  39. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/IntrinsicsWrapper.h +7 -0
  40. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Main.c +46 -0
  41. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Main.h +7 -0
  42. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Model.c +10 -0
  43. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Model.h +8 -0
  44. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/ModelConfig.h +7 -0
  45. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TaskScheduler.c +72 -0
  46. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TaskScheduler.h +11 -0
  47. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureCalculator.c +27 -0
  48. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureCalculator.h +8 -0
  49. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureFilter.c +39 -0
  50. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureFilter.h +10 -0
  51. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConductor.c +15 -0
  52. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConductor.h +9 -0
  53. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConfigurator.c +51 -0
  54. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConfigurator.h +15 -0
  55. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerHardware.c +15 -0
  56. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerHardware.h +8 -0
  57. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptConfigurator.c +55 -0
  58. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptConfigurator.h +13 -0
  59. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptHandler.c +25 -0
  60. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptHandler.h +10 -0
  61. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerModel.c +9 -0
  62. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerModel.h +8 -0
  63. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Types.h +90 -0
  64. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartBaudRateRegisterCalculator.c +18 -0
  65. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartBaudRateRegisterCalculator.h +8 -0
  66. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConductor.c +21 -0
  67. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConductor.h +7 -0
  68. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConfigurator.c +39 -0
  69. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConfigurator.h +13 -0
  70. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartHardware.c +22 -0
  71. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartHardware.h +9 -0
  72. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartModel.c +34 -0
  73. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartModel.h +10 -0
  74. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartPutChar.c +16 -0
  75. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartPutChar.h +8 -0
  76. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartTransmitBufferStatus.c +7 -0
  77. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartTransmitBufferStatus.h +8 -0
  78. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcConductor.c +121 -0
  79. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcHardware.c +44 -0
  80. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcModel.c +33 -0
  81. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestExecutor.c +36 -0
  82. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestMain.c +24 -0
  83. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestModel.c +20 -0
  84. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTaskScheduler.c +104 -0
  85. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTemperatureCalculator.c +33 -0
  86. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTemperatureFilter.c +69 -0
  87. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerConductor.c +32 -0
  88. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerHardware.c +26 -0
  89. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerModel.c +18 -0
  90. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartBaudRateRegisterCalculator.c +21 -0
  91. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartConductor.c +40 -0
  92. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartHardware.c +36 -0
  93. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartModel.c +40 -0
  94. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/support/UnityHelper.c +12 -0
  95. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/support/UnityHelper.h +8 -0
  96. data/new_project_template/vendor/ceedling/lib/cacheinator.rb +42 -0
  97. data/new_project_template/vendor/ceedling/lib/cacheinator_helper.rb +12 -0
  98. data/new_project_template/vendor/ceedling/lib/cmock_builder.rb +15 -0
  99. data/new_project_template/vendor/ceedling/lib/configurator.rb +254 -0
  100. data/new_project_template/vendor/ceedling/lib/configurator_builder.rb +408 -0
  101. data/new_project_template/vendor/ceedling/lib/configurator_plugins.rb +96 -0
  102. data/new_project_template/vendor/ceedling/lib/configurator_setup.rb +114 -0
  103. data/new_project_template/vendor/ceedling/lib/configurator_validator.rb +154 -0
  104. data/new_project_template/vendor/ceedling/lib/constants.rb +66 -0
  105. data/new_project_template/vendor/ceedling/lib/defaults.rb +349 -0
  106. data/new_project_template/vendor/ceedling/lib/dependinator.rb +92 -0
  107. data/new_project_template/vendor/ceedling/lib/file_finder.rb +132 -0
  108. data/new_project_template/vendor/ceedling/lib/file_finder_helper.rb +54 -0
  109. data/new_project_template/vendor/ceedling/lib/file_path_utils.rb +177 -0
  110. data/new_project_template/vendor/ceedling/lib/file_system_utils.rb +59 -0
  111. data/new_project_template/vendor/ceedling/lib/file_wrapper.rb +74 -0
  112. data/new_project_template/vendor/ceedling/lib/generator.rb +131 -0
  113. data/new_project_template/vendor/ceedling/lib/generator_test_results.rb +90 -0
  114. data/new_project_template/vendor/ceedling/lib/generator_test_results_sanity_checker.rb +62 -0
  115. data/new_project_template/vendor/ceedling/lib/generator_test_runner.rb +206 -0
  116. data/new_project_template/vendor/ceedling/lib/loginator.rb +31 -0
  117. data/new_project_template/vendor/ceedling/lib/makefile.rb +46 -0
  118. data/new_project_template/vendor/ceedling/lib/objects.yml +278 -0
  119. data/new_project_template/vendor/ceedling/lib/plugin.rb +63 -0
  120. data/new_project_template/vendor/ceedling/lib/plugin_manager.rb +85 -0
  121. data/new_project_template/vendor/ceedling/lib/plugin_manager_helper.rb +19 -0
  122. data/new_project_template/vendor/ceedling/lib/plugin_reportinator.rb +75 -0
  123. data/new_project_template/vendor/ceedling/lib/plugin_reportinator_helper.rb +52 -0
  124. data/new_project_template/vendor/ceedling/lib/preprocessinator.rb +43 -0
  125. data/new_project_template/vendor/ceedling/lib/preprocessinator_extractor.rb +27 -0
  126. data/new_project_template/vendor/ceedling/lib/preprocessinator_file_handler.rb +21 -0
  127. data/new_project_template/vendor/ceedling/lib/preprocessinator_helper.rb +46 -0
  128. data/new_project_template/vendor/ceedling/lib/preprocessinator_includes_handler.rb +55 -0
  129. data/new_project_template/vendor/ceedling/lib/project_config_manager.rb +38 -0
  130. data/new_project_template/vendor/ceedling/lib/project_file_loader.rb +64 -0
  131. data/new_project_template/vendor/ceedling/lib/rake_utils.rb +17 -0
  132. data/new_project_template/vendor/ceedling/lib/rake_wrapper.rb +31 -0
  133. data/new_project_template/vendor/ceedling/lib/rakefile.rb +60 -0
  134. data/new_project_template/vendor/ceedling/lib/release_invoker.rb +29 -0
  135. data/new_project_template/vendor/ceedling/lib/release_invoker_helper.rb +16 -0
  136. data/new_project_template/vendor/ceedling/lib/reportinator.rb +9 -0
  137. data/new_project_template/vendor/ceedling/lib/rules_cmock.rake +9 -0
  138. data/new_project_template/vendor/ceedling/lib/rules_preprocess.rake +26 -0
  139. data/new_project_template/vendor/ceedling/lib/rules_release.rake +63 -0
  140. data/new_project_template/vendor/ceedling/lib/rules_release_aux_dependencies.rake +15 -0
  141. data/new_project_template/vendor/ceedling/lib/rules_tests.rake +49 -0
  142. data/new_project_template/vendor/ceedling/lib/rules_tests_aux_dependencies.rake +15 -0
  143. data/new_project_template/vendor/ceedling/lib/setupinator.rb +45 -0
  144. data/new_project_template/vendor/ceedling/lib/stream_wrapper.rb +20 -0
  145. data/new_project_template/vendor/ceedling/lib/streaminator.rb +41 -0
  146. data/new_project_template/vendor/ceedling/lib/streaminator_helper.rb +15 -0
  147. data/new_project_template/vendor/ceedling/lib/system_wrapper.rb +67 -0
  148. data/new_project_template/vendor/ceedling/lib/task_invoker.rb +85 -0
  149. data/new_project_template/vendor/ceedling/lib/tasks_base.rake +104 -0
  150. data/new_project_template/vendor/ceedling/lib/tasks_filesystem.rake +89 -0
  151. data/new_project_template/vendor/ceedling/lib/tasks_release.rake +22 -0
  152. data/new_project_template/vendor/ceedling/lib/tasks_tests.rake +49 -0
  153. data/new_project_template/vendor/ceedling/lib/tasks_vendor.rake +36 -0
  154. data/new_project_template/vendor/ceedling/lib/test_includes_extractor.rb +81 -0
  155. data/new_project_template/vendor/ceedling/lib/test_invoker.rb +72 -0
  156. data/new_project_template/vendor/ceedling/lib/test_invoker_helper.rb +41 -0
  157. data/new_project_template/vendor/ceedling/lib/tool_executor.rb +178 -0
  158. data/new_project_template/vendor/ceedling/lib/tool_executor_helper.rb +57 -0
  159. data/new_project_template/vendor/ceedling/lib/verbosinator.rb +10 -0
  160. data/new_project_template/vendor/ceedling/lib/yaml_wrapper.rb +16 -0
  161. data/new_project_template/vendor/ceedling/plugins/stdout_ide_tests_report/stdout_ide_tests_report.rb +44 -0
  162. data/new_project_template/vendor/ceedling/plugins/stdout_ide_tests_report/stdout_ide_tests_report.yml +4 -0
  163. data/new_project_template/vendor/ceedling/plugins/stdout_pretty_tests_report/stdout_pretty_tests_report.rb +108 -0
  164. data/new_project_template/vendor/ceedling/plugins/stdout_pretty_tests_report/stdout_pretty_tests_report.yml +4 -0
  165. data/new_project_template/vendor/ceedling/plugins/xml_tests_report/xml_tests_report.rb +106 -0
  166. data/new_project_template/vendor/ceedling/rakefile.rb +59 -0
  167. data/new_project_template/vendor/ceedling/rakefile_helper.rb +23 -0
  168. data/new_project_template/vendor/ceedling/release/build.info +1 -0
  169. data/new_project_template/vendor/ceedling/release/version.info +1 -0
  170. data/new_project_template/vendor/ceedling/test/integration/paths.yml +17 -0
  171. data/new_project_template/vendor/ceedling/test/integration/paths_test.rb +80 -0
  172. data/new_project_template/vendor/ceedling/test/integration/rake_rules_aux_dependencies_test.rb +75 -0
  173. data/new_project_template/vendor/ceedling/test/integration/rake_rules_cmock_test.rb +74 -0
  174. data/new_project_template/vendor/ceedling/test/integration/rake_rules_preprocess_test.rb +178 -0
  175. data/new_project_template/vendor/ceedling/test/integration/rake_rules_test.rb +268 -0
  176. data/new_project_template/vendor/ceedling/test/integration/rake_tasks_test.rb +103 -0
  177. data/new_project_template/vendor/ceedling/test/integration_test_helper.rb +34 -0
  178. data/new_project_template/vendor/ceedling/test/rakefile_rules.rb +10 -0
  179. data/new_project_template/vendor/ceedling/test/rakefile_rules_aux_dependencies.rb +10 -0
  180. data/new_project_template/vendor/ceedling/test/rakefile_rules_cmock.rb +10 -0
  181. data/new_project_template/vendor/ceedling/test/rakefile_rules_preprocess.rb +10 -0
  182. data/new_project_template/vendor/ceedling/test/rakefile_tasks.rb +10 -0
  183. data/new_project_template/vendor/ceedling/test/system/file_system_dependencies.yml +20 -0
  184. data/new_project_template/vendor/ceedling/test/system/file_system_kitchen_sink.yml +20 -0
  185. data/new_project_template/vendor/ceedling/test/system/file_system_mocks.yml +20 -0
  186. data/new_project_template/vendor/ceedling/test/system/file_system_preprocess.yml +20 -0
  187. data/new_project_template/vendor/ceedling/test/system/file_system_simple.yml +20 -0
  188. data/new_project_template/vendor/ceedling/test/system/file_system_test.rb +78 -0
  189. data/new_project_template/vendor/ceedling/test/system/mocks/include/a_file.h +2 -0
  190. data/new_project_template/vendor/ceedling/test/system/mocks/include/other_stuff.h +2 -0
  191. data/new_project_template/vendor/ceedling/test/system/mocks/include/stuff.h +3 -0
  192. data/new_project_template/vendor/ceedling/test/system/mocks/source/a_file.c +9 -0
  193. data/new_project_template/vendor/ceedling/test/system/mocks/test/test_a_file.c +41 -0
  194. data/new_project_template/vendor/ceedling/test/system/mocks/test/test_no_file.c +14 -0
  195. data/new_project_template/vendor/ceedling/test/system/project_mocks.yml +43 -0
  196. data/new_project_template/vendor/ceedling/test/system/project_mocks_test.rb +38 -0
  197. data/new_project_template/vendor/ceedling/test/system/project_simple.yml +36 -0
  198. data/new_project_template/vendor/ceedling/test/system/project_simple_test.rb +39 -0
  199. data/new_project_template/vendor/ceedling/test/system/rule_mocks_test.rb +44 -0
  200. data/new_project_template/vendor/ceedling/test/system/rule_runners_test.rb +44 -0
  201. data/new_project_template/vendor/ceedling/test/system/simple/include/other_stuff.h +2 -0
  202. data/new_project_template/vendor/ceedling/test/system/simple/include/stuff.h +3 -0
  203. data/new_project_template/vendor/ceedling/test/system/simple/source/other_stuff.c +6 -0
  204. data/new_project_template/vendor/ceedling/test/system/simple/source/stuff.c +7 -0
  205. data/new_project_template/vendor/ceedling/test/system/simple/test/test_other_stuff.c +30 -0
  206. data/new_project_template/vendor/ceedling/test/system/simple/test/test_stuff.c +51 -0
  207. data/new_project_template/vendor/ceedling/test/system_test_helper.rb +73 -0
  208. data/new_project_template/vendor/ceedling/test/test_helper.rb +93 -0
  209. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_builder_test.rb +571 -0
  210. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_helper_test.rb +234 -0
  211. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_test.rb +232 -0
  212. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_validator_test.rb +169 -0
  213. data/new_project_template/vendor/ceedling/test/unit/busted/deep_merge_fix_test.rb +55 -0
  214. data/new_project_template/vendor/ceedling/test/unit/busted/dependinator_test.rb +129 -0
  215. data/new_project_template/vendor/ceedling/test/unit/busted/file_finder_helper_test.rb +45 -0
  216. data/new_project_template/vendor/ceedling/test/unit/busted/file_finder_test.rb +114 -0
  217. data/new_project_template/vendor/ceedling/test/unit/busted/file_path_utils_test.rb +97 -0
  218. data/new_project_template/vendor/ceedling/test/unit/busted/file_system_utils_test.rb +21 -0
  219. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test.rb +187 -0
  220. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test_results_test.rb +129 -0
  221. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test_runner_test.rb +478 -0
  222. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_extractor_test.rb +729 -0
  223. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_file_handler_test.rb +38 -0
  224. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_helper_test.rb +156 -0
  225. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_includes_handler_test.rb +93 -0
  226. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_test.rb +57 -0
  227. data/new_project_template/vendor/ceedling/test/unit/busted/project_file_loader_test.rb +142 -0
  228. data/new_project_template/vendor/ceedling/test/unit/busted/setupinator_test.rb +45 -0
  229. data/new_project_template/vendor/ceedling/test/unit/busted/streaminator_test.rb +49 -0
  230. data/new_project_template/vendor/ceedling/test/unit/busted/task_invoker_test.rb +69 -0
  231. data/new_project_template/vendor/ceedling/test/unit/busted/test_includes_extractor_test.rb +111 -0
  232. data/new_project_template/vendor/ceedling/test/unit/busted/test_invoker_helper_test.rb +62 -0
  233. data/new_project_template/vendor/ceedling/test/unit/busted/test_invoker_test.rb +47 -0
  234. data/new_project_template/vendor/ceedling/test/unit/busted/tool_executor_helper_test.rb +100 -0
  235. data/new_project_template/vendor/ceedling/test/unit/busted/tool_executor_test.rb +351 -0
  236. data/new_project_template/vendor/ceedling/test/unit/busted/verbosinator_test.rb +65 -0
  237. data/new_project_template/vendor/ceedling/test/unit_test_helper.rb +16 -0
  238. data/new_project_template/vendor/ceedling/vendor/behaviors/Manifest.txt +9 -0
  239. data/new_project_template/vendor/ceedling/vendor/behaviors/Rakefile +19 -0
  240. data/new_project_template/vendor/ceedling/vendor/behaviors/lib/behaviors/reporttask.rb +158 -0
  241. data/new_project_template/vendor/ceedling/vendor/behaviors/lib/behaviors.rb +76 -0
  242. data/new_project_template/vendor/ceedling/vendor/behaviors/test/behaviors_tasks_test.rb +73 -0
  243. data/new_project_template/vendor/ceedling/vendor/behaviors/test/behaviors_test.rb +50 -0
  244. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/Rakefile +19 -0
  245. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/lib/user.rb +2 -0
  246. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/test/user_test.rb +17 -0
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@@ -0,0 +1,2314 @@
1
+ ;- ----------------------------------------------------------------------------
2
+ ;- ATMEL Microcontroller Software Support - ROUSSET -
3
+ ;- ----------------------------------------------------------------------------
4
+ ;- DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
5
+ ;- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6
+ ;- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
7
+ ;- DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
8
+ ;- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
9
+ ;- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
10
+ ;- OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
11
+ ;- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
12
+ ;- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
13
+ ;- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
14
+ ;- ----------------------------------------------------------------------------
15
+ ;- File Name : AT91SAM7X256.h
16
+ ;- Object : AT91SAM7X256 definitions
17
+ ;- Generated : AT91 SW Application Group 11/02/2005 (15:17:24)
18
+ ;-
19
+ ;- CVS Reference : /AT91SAM7X256.pl/1.14/Tue Sep 13 15:06:52 2005//
20
+ ;- CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
21
+ ;- CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
22
+ ;- CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
23
+ ;- CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 14:57:50 2005//
24
+ ;- CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
25
+ ;- CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
26
+ ;- CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
27
+ ;- CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
28
+ ;- CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
29
+ ;- CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
30
+ ;- CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
31
+ ;- CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
32
+ ;- CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
33
+ ;- CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
34
+ ;- CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
35
+ ;- CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
36
+ ;- CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:19:19 2005//
37
+ ;- CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
38
+ ;- CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
39
+ ;- CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
40
+ ;- CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:05:35 2005//
41
+ ;- CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
42
+ ;- ----------------------------------------------------------------------------
43
+
44
+ ;- Hardware register definition
45
+
46
+ ;- *****************************************************************************
47
+ ;- SOFTWARE API DEFINITION FOR System Peripherals
48
+ ;- *****************************************************************************
49
+
50
+ ;- *****************************************************************************
51
+ ;- SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
52
+ ;- *****************************************************************************
53
+ ^ 0 ;- AT91S_AIC
54
+ AIC_SMR # 128 ;- Source Mode Register
55
+ AIC_SVR # 128 ;- Source Vector Register
56
+ AIC_IVR # 4 ;- IRQ Vector Register
57
+ AIC_FVR # 4 ;- FIQ Vector Register
58
+ AIC_ISR # 4 ;- Interrupt Status Register
59
+ AIC_IPR # 4 ;- Interrupt Pending Register
60
+ AIC_IMR # 4 ;- Interrupt Mask Register
61
+ AIC_CISR # 4 ;- Core Interrupt Status Register
62
+ # 8 ;- Reserved
63
+ AIC_IECR # 4 ;- Interrupt Enable Command Register
64
+ AIC_IDCR # 4 ;- Interrupt Disable Command Register
65
+ AIC_ICCR # 4 ;- Interrupt Clear Command Register
66
+ AIC_ISCR # 4 ;- Interrupt Set Command Register
67
+ AIC_EOICR # 4 ;- End of Interrupt Command Register
68
+ AIC_SPU # 4 ;- Spurious Vector Register
69
+ AIC_DCR # 4 ;- Debug Control Register (Protect)
70
+ # 4 ;- Reserved
71
+ AIC_FFER # 4 ;- Fast Forcing Enable Register
72
+ AIC_FFDR # 4 ;- Fast Forcing Disable Register
73
+ AIC_FFSR # 4 ;- Fast Forcing Status Register
74
+ ;- -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
75
+ AT91C_AIC_PRIOR EQU (0x7:SHL:0) ;- (AIC) Priority Level
76
+ AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level
77
+ AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level
78
+ AT91C_AIC_SRCTYPE EQU (0x3:SHL:5) ;- (AIC) Interrupt Source Type
79
+ AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0:SHL:5) ;- (AIC) Internal Sources Code Label High-level Sensitive
80
+ AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0:SHL:5) ;- (AIC) External Sources Code Label Low-level Sensitive
81
+ AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1:SHL:5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
82
+ AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1:SHL:5) ;- (AIC) External Sources Code Label Negative Edge triggered
83
+ AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2:SHL:5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
84
+ AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3:SHL:5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
85
+ ;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
86
+ AT91C_AIC_NFIQ EQU (0x1:SHL:0) ;- (AIC) NFIQ Status
87
+ AT91C_AIC_NIRQ EQU (0x1:SHL:1) ;- (AIC) NIRQ Status
88
+ ;- -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
89
+ AT91C_AIC_DCR_PROT EQU (0x1:SHL:0) ;- (AIC) Protection Mode
90
+ AT91C_AIC_DCR_GMSK EQU (0x1:SHL:1) ;- (AIC) General Mask
91
+
92
+ ;- *****************************************************************************
93
+ ;- SOFTWARE API DEFINITION FOR Peripheral DMA Controller
94
+ ;- *****************************************************************************
95
+ ^ 0 ;- AT91S_PDC
96
+ PDC_RPR # 4 ;- Receive Pointer Register
97
+ PDC_RCR # 4 ;- Receive Counter Register
98
+ PDC_TPR # 4 ;- Transmit Pointer Register
99
+ PDC_TCR # 4 ;- Transmit Counter Register
100
+ PDC_RNPR # 4 ;- Receive Next Pointer Register
101
+ PDC_RNCR # 4 ;- Receive Next Counter Register
102
+ PDC_TNPR # 4 ;- Transmit Next Pointer Register
103
+ PDC_TNCR # 4 ;- Transmit Next Counter Register
104
+ PDC_PTCR # 4 ;- PDC Transfer Control Register
105
+ PDC_PTSR # 4 ;- PDC Transfer Status Register
106
+ ;- -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
107
+ AT91C_PDC_RXTEN EQU (0x1:SHL:0) ;- (PDC) Receiver Transfer Enable
108
+ AT91C_PDC_RXTDIS EQU (0x1:SHL:1) ;- (PDC) Receiver Transfer Disable
109
+ AT91C_PDC_TXTEN EQU (0x1:SHL:8) ;- (PDC) Transmitter Transfer Enable
110
+ AT91C_PDC_TXTDIS EQU (0x1:SHL:9) ;- (PDC) Transmitter Transfer Disable
111
+ ;- -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
112
+
113
+ ;- *****************************************************************************
114
+ ;- SOFTWARE API DEFINITION FOR Debug Unit
115
+ ;- *****************************************************************************
116
+ ^ 0 ;- AT91S_DBGU
117
+ DBGU_CR # 4 ;- Control Register
118
+ DBGU_MR # 4 ;- Mode Register
119
+ DBGU_IER # 4 ;- Interrupt Enable Register
120
+ DBGU_IDR # 4 ;- Interrupt Disable Register
121
+ DBGU_IMR # 4 ;- Interrupt Mask Register
122
+ DBGU_CSR # 4 ;- Channel Status Register
123
+ DBGU_RHR # 4 ;- Receiver Holding Register
124
+ DBGU_THR # 4 ;- Transmitter Holding Register
125
+ DBGU_BRGR # 4 ;- Baud Rate Generator Register
126
+ # 28 ;- Reserved
127
+ DBGU_CIDR # 4 ;- Chip ID Register
128
+ DBGU_EXID # 4 ;- Chip ID Extension Register
129
+ DBGU_FNTR # 4 ;- Force NTRST Register
130
+ # 180 ;- Reserved
131
+ DBGU_RPR # 4 ;- Receive Pointer Register
132
+ DBGU_RCR # 4 ;- Receive Counter Register
133
+ DBGU_TPR # 4 ;- Transmit Pointer Register
134
+ DBGU_TCR # 4 ;- Transmit Counter Register
135
+ DBGU_RNPR # 4 ;- Receive Next Pointer Register
136
+ DBGU_RNCR # 4 ;- Receive Next Counter Register
137
+ DBGU_TNPR # 4 ;- Transmit Next Pointer Register
138
+ DBGU_TNCR # 4 ;- Transmit Next Counter Register
139
+ DBGU_PTCR # 4 ;- PDC Transfer Control Register
140
+ DBGU_PTSR # 4 ;- PDC Transfer Status Register
141
+ ;- -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
142
+ AT91C_US_RSTRX EQU (0x1:SHL:2) ;- (DBGU) Reset Receiver
143
+ AT91C_US_RSTTX EQU (0x1:SHL:3) ;- (DBGU) Reset Transmitter
144
+ AT91C_US_RXEN EQU (0x1:SHL:4) ;- (DBGU) Receiver Enable
145
+ AT91C_US_RXDIS EQU (0x1:SHL:5) ;- (DBGU) Receiver Disable
146
+ AT91C_US_TXEN EQU (0x1:SHL:6) ;- (DBGU) Transmitter Enable
147
+ AT91C_US_TXDIS EQU (0x1:SHL:7) ;- (DBGU) Transmitter Disable
148
+ AT91C_US_RSTSTA EQU (0x1:SHL:8) ;- (DBGU) Reset Status Bits
149
+ ;- -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
150
+ AT91C_US_PAR EQU (0x7:SHL:9) ;- (DBGU) Parity type
151
+ AT91C_US_PAR_EVEN EQU (0x0:SHL:9) ;- (DBGU) Even Parity
152
+ AT91C_US_PAR_ODD EQU (0x1:SHL:9) ;- (DBGU) Odd Parity
153
+ AT91C_US_PAR_SPACE EQU (0x2:SHL:9) ;- (DBGU) Parity forced to 0 (Space)
154
+ AT91C_US_PAR_MARK EQU (0x3:SHL:9) ;- (DBGU) Parity forced to 1 (Mark)
155
+ AT91C_US_PAR_NONE EQU (0x4:SHL:9) ;- (DBGU) No Parity
156
+ AT91C_US_PAR_MULTI_DROP EQU (0x6:SHL:9) ;- (DBGU) Multi-drop mode
157
+ AT91C_US_CHMODE EQU (0x3:SHL:14) ;- (DBGU) Channel Mode
158
+ AT91C_US_CHMODE_NORMAL EQU (0x0:SHL:14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
159
+ AT91C_US_CHMODE_AUTO EQU (0x1:SHL:14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
160
+ AT91C_US_CHMODE_LOCAL EQU (0x2:SHL:14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
161
+ AT91C_US_CHMODE_REMOTE EQU (0x3:SHL:14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
162
+ ;- -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
163
+ AT91C_US_RXRDY EQU (0x1:SHL:0) ;- (DBGU) RXRDY Interrupt
164
+ AT91C_US_TXRDY EQU (0x1:SHL:1) ;- (DBGU) TXRDY Interrupt
165
+ AT91C_US_ENDRX EQU (0x1:SHL:3) ;- (DBGU) End of Receive Transfer Interrupt
166
+ AT91C_US_ENDTX EQU (0x1:SHL:4) ;- (DBGU) End of Transmit Interrupt
167
+ AT91C_US_OVRE EQU (0x1:SHL:5) ;- (DBGU) Overrun Interrupt
168
+ AT91C_US_FRAME EQU (0x1:SHL:6) ;- (DBGU) Framing Error Interrupt
169
+ AT91C_US_PARE EQU (0x1:SHL:7) ;- (DBGU) Parity Error Interrupt
170
+ AT91C_US_TXEMPTY EQU (0x1:SHL:9) ;- (DBGU) TXEMPTY Interrupt
171
+ AT91C_US_TXBUFE EQU (0x1:SHL:11) ;- (DBGU) TXBUFE Interrupt
172
+ AT91C_US_RXBUFF EQU (0x1:SHL:12) ;- (DBGU) RXBUFF Interrupt
173
+ AT91C_US_COMM_TX EQU (0x1:SHL:30) ;- (DBGU) COMM_TX Interrupt
174
+ AT91C_US_COMM_RX EQU (0x1:SHL:31) ;- (DBGU) COMM_RX Interrupt
175
+ ;- -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
176
+ ;- -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
177
+ ;- -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
178
+ ;- -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
179
+ AT91C_US_FORCE_NTRST EQU (0x1:SHL:0) ;- (DBGU) Force NTRST in JTAG
180
+
181
+ ;- *****************************************************************************
182
+ ;- SOFTWARE API DEFINITION FOR Parallel Input Output Controler
183
+ ;- *****************************************************************************
184
+ ^ 0 ;- AT91S_PIO
185
+ PIO_PER # 4 ;- PIO Enable Register
186
+ PIO_PDR # 4 ;- PIO Disable Register
187
+ PIO_PSR # 4 ;- PIO Status Register
188
+ # 4 ;- Reserved
189
+ PIO_OER # 4 ;- Output Enable Register
190
+ PIO_ODR # 4 ;- Output Disable Registerr
191
+ PIO_OSR # 4 ;- Output Status Register
192
+ # 4 ;- Reserved
193
+ PIO_IFER # 4 ;- Input Filter Enable Register
194
+ PIO_IFDR # 4 ;- Input Filter Disable Register
195
+ PIO_IFSR # 4 ;- Input Filter Status Register
196
+ # 4 ;- Reserved
197
+ PIO_SODR # 4 ;- Set Output Data Register
198
+ PIO_CODR # 4 ;- Clear Output Data Register
199
+ PIO_ODSR # 4 ;- Output Data Status Register
200
+ PIO_PDSR # 4 ;- Pin Data Status Register
201
+ PIO_IER # 4 ;- Interrupt Enable Register
202
+ PIO_IDR # 4 ;- Interrupt Disable Register
203
+ PIO_IMR # 4 ;- Interrupt Mask Register
204
+ PIO_ISR # 4 ;- Interrupt Status Register
205
+ PIO_MDER # 4 ;- Multi-driver Enable Register
206
+ PIO_MDDR # 4 ;- Multi-driver Disable Register
207
+ PIO_MDSR # 4 ;- Multi-driver Status Register
208
+ # 4 ;- Reserved
209
+ PIO_PPUDR # 4 ;- Pull-up Disable Register
210
+ PIO_PPUER # 4 ;- Pull-up Enable Register
211
+ PIO_PPUSR # 4 ;- Pull-up Status Register
212
+ # 4 ;- Reserved
213
+ PIO_ASR # 4 ;- Select A Register
214
+ PIO_BSR # 4 ;- Select B Register
215
+ PIO_ABSR # 4 ;- AB Select Status Register
216
+ # 36 ;- Reserved
217
+ PIO_OWER # 4 ;- Output Write Enable Register
218
+ PIO_OWDR # 4 ;- Output Write Disable Register
219
+ PIO_OWSR # 4 ;- Output Write Status Register
220
+
221
+ ;- *****************************************************************************
222
+ ;- SOFTWARE API DEFINITION FOR Clock Generator Controler
223
+ ;- *****************************************************************************
224
+ ^ 0 ;- AT91S_CKGR
225
+ CKGR_MOR # 4 ;- Main Oscillator Register
226
+ CKGR_MCFR # 4 ;- Main Clock Frequency Register
227
+ # 4 ;- Reserved
228
+ CKGR_PLLR # 4 ;- PLL Register
229
+ ;- -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
230
+ AT91C_CKGR_MOSCEN EQU (0x1:SHL:0) ;- (CKGR) Main Oscillator Enable
231
+ AT91C_CKGR_OSCBYPASS EQU (0x1:SHL:1) ;- (CKGR) Main Oscillator Bypass
232
+ AT91C_CKGR_OSCOUNT EQU (0xFF:SHL:8) ;- (CKGR) Main Oscillator Start-up Time
233
+ ;- -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
234
+ AT91C_CKGR_MAINF EQU (0xFFFF:SHL:0) ;- (CKGR) Main Clock Frequency
235
+ AT91C_CKGR_MAINRDY EQU (0x1:SHL:16) ;- (CKGR) Main Clock Ready
236
+ ;- -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
237
+ AT91C_CKGR_DIV EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected
238
+ AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0
239
+ AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed
240
+ AT91C_CKGR_PLLCOUNT EQU (0x3F:SHL:8) ;- (CKGR) PLL Counter
241
+ AT91C_CKGR_OUT EQU (0x3:SHL:14) ;- (CKGR) PLL Output Frequency Range
242
+ AT91C_CKGR_OUT_0 EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
243
+ AT91C_CKGR_OUT_1 EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
244
+ AT91C_CKGR_OUT_2 EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
245
+ AT91C_CKGR_OUT_3 EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
246
+ AT91C_CKGR_MUL EQU (0x7FF:SHL:16) ;- (CKGR) PLL Multiplier
247
+ AT91C_CKGR_USBDIV EQU (0x3:SHL:28) ;- (CKGR) Divider for USB Clocks
248
+ AT91C_CKGR_USBDIV_0 EQU (0x0:SHL:28) ;- (CKGR) Divider output is PLL clock output
249
+ AT91C_CKGR_USBDIV_1 EQU (0x1:SHL:28) ;- (CKGR) Divider output is PLL clock output divided by 2
250
+ AT91C_CKGR_USBDIV_2 EQU (0x2:SHL:28) ;- (CKGR) Divider output is PLL clock output divided by 4
251
+
252
+ ;- *****************************************************************************
253
+ ;- SOFTWARE API DEFINITION FOR Power Management Controler
254
+ ;- *****************************************************************************
255
+ ^ 0 ;- AT91S_PMC
256
+ PMC_SCER # 4 ;- System Clock Enable Register
257
+ PMC_SCDR # 4 ;- System Clock Disable Register
258
+ PMC_SCSR # 4 ;- System Clock Status Register
259
+ # 4 ;- Reserved
260
+ PMC_PCER # 4 ;- Peripheral Clock Enable Register
261
+ PMC_PCDR # 4 ;- Peripheral Clock Disable Register
262
+ PMC_PCSR # 4 ;- Peripheral Clock Status Register
263
+ # 4 ;- Reserved
264
+ PMC_MOR # 4 ;- Main Oscillator Register
265
+ PMC_MCFR # 4 ;- Main Clock Frequency Register
266
+ # 4 ;- Reserved
267
+ PMC_PLLR # 4 ;- PLL Register
268
+ PMC_MCKR # 4 ;- Master Clock Register
269
+ # 12 ;- Reserved
270
+ PMC_PCKR # 16 ;- Programmable Clock Register
271
+ # 16 ;- Reserved
272
+ PMC_IER # 4 ;- Interrupt Enable Register
273
+ PMC_IDR # 4 ;- Interrupt Disable Register
274
+ PMC_SR # 4 ;- Status Register
275
+ PMC_IMR # 4 ;- Interrupt Mask Register
276
+ ;- -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
277
+ AT91C_PMC_PCK EQU (0x1:SHL:0) ;- (PMC) Processor Clock
278
+ AT91C_PMC_UDP EQU (0x1:SHL:7) ;- (PMC) USB Device Port Clock
279
+ AT91C_PMC_PCK0 EQU (0x1:SHL:8) ;- (PMC) Programmable Clock Output
280
+ AT91C_PMC_PCK1 EQU (0x1:SHL:9) ;- (PMC) Programmable Clock Output
281
+ AT91C_PMC_PCK2 EQU (0x1:SHL:10) ;- (PMC) Programmable Clock Output
282
+ AT91C_PMC_PCK3 EQU (0x1:SHL:11) ;- (PMC) Programmable Clock Output
283
+ ;- -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
284
+ ;- -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
285
+ ;- -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
286
+ ;- -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
287
+ ;- -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
288
+ ;- -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
289
+ AT91C_PMC_CSS EQU (0x3:SHL:0) ;- (PMC) Programmable Clock Selection
290
+ AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected
291
+ AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected
292
+ AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected
293
+ AT91C_PMC_PRES EQU (0x7:SHL:2) ;- (PMC) Programmable Clock Prescaler
294
+ AT91C_PMC_PRES_CLK EQU (0x0:SHL:2) ;- (PMC) Selected clock
295
+ AT91C_PMC_PRES_CLK_2 EQU (0x1:SHL:2) ;- (PMC) Selected clock divided by 2
296
+ AT91C_PMC_PRES_CLK_4 EQU (0x2:SHL:2) ;- (PMC) Selected clock divided by 4
297
+ AT91C_PMC_PRES_CLK_8 EQU (0x3:SHL:2) ;- (PMC) Selected clock divided by 8
298
+ AT91C_PMC_PRES_CLK_16 EQU (0x4:SHL:2) ;- (PMC) Selected clock divided by 16
299
+ AT91C_PMC_PRES_CLK_32 EQU (0x5:SHL:2) ;- (PMC) Selected clock divided by 32
300
+ AT91C_PMC_PRES_CLK_64 EQU (0x6:SHL:2) ;- (PMC) Selected clock divided by 64
301
+ ;- -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
302
+ ;- -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
303
+ AT91C_PMC_MOSCS EQU (0x1:SHL:0) ;- (PMC) MOSC Status/Enable/Disable/Mask
304
+ AT91C_PMC_LOCK EQU (0x1:SHL:2) ;- (PMC) PLL Status/Enable/Disable/Mask
305
+ AT91C_PMC_MCKRDY EQU (0x1:SHL:3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
306
+ AT91C_PMC_PCK0RDY EQU (0x1:SHL:8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
307
+ AT91C_PMC_PCK1RDY EQU (0x1:SHL:9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
308
+ AT91C_PMC_PCK2RDY EQU (0x1:SHL:10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
309
+ AT91C_PMC_PCK3RDY EQU (0x1:SHL:11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
310
+ ;- -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
311
+ ;- -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
312
+ ;- -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
313
+
314
+ ;- *****************************************************************************
315
+ ;- SOFTWARE API DEFINITION FOR Reset Controller Interface
316
+ ;- *****************************************************************************
317
+ ^ 0 ;- AT91S_RSTC
318
+ RSTC_RCR # 4 ;- Reset Control Register
319
+ RSTC_RSR # 4 ;- Reset Status Register
320
+ RSTC_RMR # 4 ;- Reset Mode Register
321
+ ;- -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
322
+ AT91C_RSTC_PROCRST EQU (0x1:SHL:0) ;- (RSTC) Processor Reset
323
+ AT91C_RSTC_PERRST EQU (0x1:SHL:2) ;- (RSTC) Peripheral Reset
324
+ AT91C_RSTC_EXTRST EQU (0x1:SHL:3) ;- (RSTC) External Reset
325
+ AT91C_RSTC_KEY EQU (0xFF:SHL:24) ;- (RSTC) Password
326
+ ;- -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
327
+ AT91C_RSTC_URSTS EQU (0x1:SHL:0) ;- (RSTC) User Reset Status
328
+ AT91C_RSTC_BODSTS EQU (0x1:SHL:1) ;- (RSTC) Brownout Detection Status
329
+ AT91C_RSTC_RSTTYP EQU (0x7:SHL:8) ;- (RSTC) Reset Type
330
+ AT91C_RSTC_RSTTYP_POWERUP EQU (0x0:SHL:8) ;- (RSTC) Power-up Reset. VDDCORE rising.
331
+ AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1:SHL:8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
332
+ AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2:SHL:8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
333
+ AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3:SHL:8) ;- (RSTC) Software Reset. Processor reset required by the software.
334
+ AT91C_RSTC_RSTTYP_USER EQU (0x4:SHL:8) ;- (RSTC) User Reset. NRST pin detected low.
335
+ AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5:SHL:8) ;- (RSTC) Brownout Reset occured.
336
+ AT91C_RSTC_NRSTL EQU (0x1:SHL:16) ;- (RSTC) NRST pin level
337
+ AT91C_RSTC_SRCMP EQU (0x1:SHL:17) ;- (RSTC) Software Reset Command in Progress.
338
+ ;- -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
339
+ AT91C_RSTC_URSTEN EQU (0x1:SHL:0) ;- (RSTC) User Reset Enable
340
+ AT91C_RSTC_URSTIEN EQU (0x1:SHL:4) ;- (RSTC) User Reset Interrupt Enable
341
+ AT91C_RSTC_ERSTL EQU (0xF:SHL:8) ;- (RSTC) User Reset Length
342
+ AT91C_RSTC_BODIEN EQU (0x1:SHL:16) ;- (RSTC) Brownout Detection Interrupt Enable
343
+
344
+ ;- *****************************************************************************
345
+ ;- SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
346
+ ;- *****************************************************************************
347
+ ^ 0 ;- AT91S_RTTC
348
+ RTTC_RTMR # 4 ;- Real-time Mode Register
349
+ RTTC_RTAR # 4 ;- Real-time Alarm Register
350
+ RTTC_RTVR # 4 ;- Real-time Value Register
351
+ RTTC_RTSR # 4 ;- Real-time Status Register
352
+ ;- -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
353
+ AT91C_RTTC_RTPRES EQU (0xFFFF:SHL:0) ;- (RTTC) Real-time Timer Prescaler Value
354
+ AT91C_RTTC_ALMIEN EQU (0x1:SHL:16) ;- (RTTC) Alarm Interrupt Enable
355
+ AT91C_RTTC_RTTINCIEN EQU (0x1:SHL:17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
356
+ AT91C_RTTC_RTTRST EQU (0x1:SHL:18) ;- (RTTC) Real Time Timer Restart
357
+ ;- -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
358
+ AT91C_RTTC_ALMV EQU (0x0:SHL:0) ;- (RTTC) Alarm Value
359
+ ;- -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
360
+ AT91C_RTTC_CRTV EQU (0x0:SHL:0) ;- (RTTC) Current Real-time Value
361
+ ;- -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
362
+ AT91C_RTTC_ALMS EQU (0x1:SHL:0) ;- (RTTC) Real-time Alarm Status
363
+ AT91C_RTTC_RTTINC EQU (0x1:SHL:1) ;- (RTTC) Real-time Timer Increment
364
+
365
+ ;- *****************************************************************************
366
+ ;- SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
367
+ ;- *****************************************************************************
368
+ ^ 0 ;- AT91S_PITC
369
+ PITC_PIMR # 4 ;- Period Interval Mode Register
370
+ PITC_PISR # 4 ;- Period Interval Status Register
371
+ PITC_PIVR # 4 ;- Period Interval Value Register
372
+ PITC_PIIR # 4 ;- Period Interval Image Register
373
+ ;- -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
374
+ AT91C_PITC_PIV EQU (0xFFFFF:SHL:0) ;- (PITC) Periodic Interval Value
375
+ AT91C_PITC_PITEN EQU (0x1:SHL:24) ;- (PITC) Periodic Interval Timer Enabled
376
+ AT91C_PITC_PITIEN EQU (0x1:SHL:25) ;- (PITC) Periodic Interval Timer Interrupt Enable
377
+ ;- -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
378
+ AT91C_PITC_PITS EQU (0x1:SHL:0) ;- (PITC) Periodic Interval Timer Status
379
+ ;- -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
380
+ AT91C_PITC_CPIV EQU (0xFFFFF:SHL:0) ;- (PITC) Current Periodic Interval Value
381
+ AT91C_PITC_PICNT EQU (0xFFF:SHL:20) ;- (PITC) Periodic Interval Counter
382
+ ;- -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
383
+
384
+ ;- *****************************************************************************
385
+ ;- SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
386
+ ;- *****************************************************************************
387
+ ^ 0 ;- AT91S_WDTC
388
+ WDTC_WDCR # 4 ;- Watchdog Control Register
389
+ WDTC_WDMR # 4 ;- Watchdog Mode Register
390
+ WDTC_WDSR # 4 ;- Watchdog Status Register
391
+ ;- -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
392
+ AT91C_WDTC_WDRSTT EQU (0x1:SHL:0) ;- (WDTC) Watchdog Restart
393
+ AT91C_WDTC_KEY EQU (0xFF:SHL:24) ;- (WDTC) Watchdog KEY Password
394
+ ;- -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
395
+ AT91C_WDTC_WDV EQU (0xFFF:SHL:0) ;- (WDTC) Watchdog Timer Restart
396
+ AT91C_WDTC_WDFIEN EQU (0x1:SHL:12) ;- (WDTC) Watchdog Fault Interrupt Enable
397
+ AT91C_WDTC_WDRSTEN EQU (0x1:SHL:13) ;- (WDTC) Watchdog Reset Enable
398
+ AT91C_WDTC_WDRPROC EQU (0x1:SHL:14) ;- (WDTC) Watchdog Timer Restart
399
+ AT91C_WDTC_WDDIS EQU (0x1:SHL:15) ;- (WDTC) Watchdog Disable
400
+ AT91C_WDTC_WDD EQU (0xFFF:SHL:16) ;- (WDTC) Watchdog Delta Value
401
+ AT91C_WDTC_WDDBGHLT EQU (0x1:SHL:28) ;- (WDTC) Watchdog Debug Halt
402
+ AT91C_WDTC_WDIDLEHLT EQU (0x1:SHL:29) ;- (WDTC) Watchdog Idle Halt
403
+ ;- -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
404
+ AT91C_WDTC_WDUNF EQU (0x1:SHL:0) ;- (WDTC) Watchdog Underflow
405
+ AT91C_WDTC_WDERR EQU (0x1:SHL:1) ;- (WDTC) Watchdog Error
406
+
407
+ ;- *****************************************************************************
408
+ ;- SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
409
+ ;- *****************************************************************************
410
+ ^ 0 ;- AT91S_VREG
411
+ VREG_MR # 4 ;- Voltage Regulator Mode Register
412
+ ;- -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
413
+ AT91C_VREG_PSTDBY EQU (0x1:SHL:0) ;- (VREG) Voltage Regulator Power Standby Mode
414
+
415
+ ;- *****************************************************************************
416
+ ;- SOFTWARE API DEFINITION FOR Memory Controller Interface
417
+ ;- *****************************************************************************
418
+ ^ 0 ;- AT91S_MC
419
+ MC_RCR # 4 ;- MC Remap Control Register
420
+ MC_ASR # 4 ;- MC Abort Status Register
421
+ MC_AASR # 4 ;- MC Abort Address Status Register
422
+ # 84 ;- Reserved
423
+ MC_FMR # 4 ;- MC Flash Mode Register
424
+ MC_FCR # 4 ;- MC Flash Command Register
425
+ MC_FSR # 4 ;- MC Flash Status Register
426
+ ;- -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
427
+ AT91C_MC_RCB EQU (0x1:SHL:0) ;- (MC) Remap Command Bit
428
+ ;- -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
429
+ AT91C_MC_UNDADD EQU (0x1:SHL:0) ;- (MC) Undefined Addess Abort Status
430
+ AT91C_MC_MISADD EQU (0x1:SHL:1) ;- (MC) Misaligned Addess Abort Status
431
+ AT91C_MC_ABTSZ EQU (0x3:SHL:8) ;- (MC) Abort Size Status
432
+ AT91C_MC_ABTSZ_BYTE EQU (0x0:SHL:8) ;- (MC) Byte
433
+ AT91C_MC_ABTSZ_HWORD EQU (0x1:SHL:8) ;- (MC) Half-word
434
+ AT91C_MC_ABTSZ_WORD EQU (0x2:SHL:8) ;- (MC) Word
435
+ AT91C_MC_ABTTYP EQU (0x3:SHL:10) ;- (MC) Abort Type Status
436
+ AT91C_MC_ABTTYP_DATAR EQU (0x0:SHL:10) ;- (MC) Data Read
437
+ AT91C_MC_ABTTYP_DATAW EQU (0x1:SHL:10) ;- (MC) Data Write
438
+ AT91C_MC_ABTTYP_FETCH EQU (0x2:SHL:10) ;- (MC) Code Fetch
439
+ AT91C_MC_MST0 EQU (0x1:SHL:16) ;- (MC) Master 0 Abort Source
440
+ AT91C_MC_MST1 EQU (0x1:SHL:17) ;- (MC) Master 1 Abort Source
441
+ AT91C_MC_SVMST0 EQU (0x1:SHL:24) ;- (MC) Saved Master 0 Abort Source
442
+ AT91C_MC_SVMST1 EQU (0x1:SHL:25) ;- (MC) Saved Master 1 Abort Source
443
+ ;- -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
444
+ AT91C_MC_FRDY EQU (0x1:SHL:0) ;- (MC) Flash Ready
445
+ AT91C_MC_LOCKE EQU (0x1:SHL:2) ;- (MC) Lock Error
446
+ AT91C_MC_PROGE EQU (0x1:SHL:3) ;- (MC) Programming Error
447
+ AT91C_MC_NEBP EQU (0x1:SHL:7) ;- (MC) No Erase Before Programming
448
+ AT91C_MC_FWS EQU (0x3:SHL:8) ;- (MC) Flash Wait State
449
+ AT91C_MC_FWS_0FWS EQU (0x0:SHL:8) ;- (MC) 1 cycle for Read, 2 for Write operations
450
+ AT91C_MC_FWS_1FWS EQU (0x1:SHL:8) ;- (MC) 2 cycles for Read, 3 for Write operations
451
+ AT91C_MC_FWS_2FWS EQU (0x2:SHL:8) ;- (MC) 3 cycles for Read, 4 for Write operations
452
+ AT91C_MC_FWS_3FWS EQU (0x3:SHL:8) ;- (MC) 4 cycles for Read, 4 for Write operations
453
+ AT91C_MC_FMCN EQU (0xFF:SHL:16) ;- (MC) Flash Microsecond Cycle Number
454
+ ;- -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
455
+ AT91C_MC_FCMD EQU (0xF:SHL:0) ;- (MC) Flash Command
456
+ AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
457
+ AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
458
+ AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
459
+ AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
460
+ AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
461
+ AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits.
462
+ AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
463
+ AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
464
+ AT91C_MC_PAGEN EQU (0x3FF:SHL:8) ;- (MC) Page Number
465
+ AT91C_MC_KEY EQU (0xFF:SHL:24) ;- (MC) Writing Protect Key
466
+ ;- -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
467
+ AT91C_MC_SECURITY EQU (0x1:SHL:4) ;- (MC) Security Bit Status
468
+ AT91C_MC_GPNVM0 EQU (0x1:SHL:8) ;- (MC) Sector 0 Lock Status
469
+ AT91C_MC_GPNVM1 EQU (0x1:SHL:9) ;- (MC) Sector 1 Lock Status
470
+ AT91C_MC_GPNVM2 EQU (0x1:SHL:10) ;- (MC) Sector 2 Lock Status
471
+ AT91C_MC_GPNVM3 EQU (0x1:SHL:11) ;- (MC) Sector 3 Lock Status
472
+ AT91C_MC_GPNVM4 EQU (0x1:SHL:12) ;- (MC) Sector 4 Lock Status
473
+ AT91C_MC_GPNVM5 EQU (0x1:SHL:13) ;- (MC) Sector 5 Lock Status
474
+ AT91C_MC_GPNVM6 EQU (0x1:SHL:14) ;- (MC) Sector 6 Lock Status
475
+ AT91C_MC_GPNVM7 EQU (0x1:SHL:15) ;- (MC) Sector 7 Lock Status
476
+ AT91C_MC_LOCKS0 EQU (0x1:SHL:16) ;- (MC) Sector 0 Lock Status
477
+ AT91C_MC_LOCKS1 EQU (0x1:SHL:17) ;- (MC) Sector 1 Lock Status
478
+ AT91C_MC_LOCKS2 EQU (0x1:SHL:18) ;- (MC) Sector 2 Lock Status
479
+ AT91C_MC_LOCKS3 EQU (0x1:SHL:19) ;- (MC) Sector 3 Lock Status
480
+ AT91C_MC_LOCKS4 EQU (0x1:SHL:20) ;- (MC) Sector 4 Lock Status
481
+ AT91C_MC_LOCKS5 EQU (0x1:SHL:21) ;- (MC) Sector 5 Lock Status
482
+ AT91C_MC_LOCKS6 EQU (0x1:SHL:22) ;- (MC) Sector 6 Lock Status
483
+ AT91C_MC_LOCKS7 EQU (0x1:SHL:23) ;- (MC) Sector 7 Lock Status
484
+ AT91C_MC_LOCKS8 EQU (0x1:SHL:24) ;- (MC) Sector 8 Lock Status
485
+ AT91C_MC_LOCKS9 EQU (0x1:SHL:25) ;- (MC) Sector 9 Lock Status
486
+ AT91C_MC_LOCKS10 EQU (0x1:SHL:26) ;- (MC) Sector 10 Lock Status
487
+ AT91C_MC_LOCKS11 EQU (0x1:SHL:27) ;- (MC) Sector 11 Lock Status
488
+ AT91C_MC_LOCKS12 EQU (0x1:SHL:28) ;- (MC) Sector 12 Lock Status
489
+ AT91C_MC_LOCKS13 EQU (0x1:SHL:29) ;- (MC) Sector 13 Lock Status
490
+ AT91C_MC_LOCKS14 EQU (0x1:SHL:30) ;- (MC) Sector 14 Lock Status
491
+ AT91C_MC_LOCKS15 EQU (0x1:SHL:31) ;- (MC) Sector 15 Lock Status
492
+
493
+ ;- *****************************************************************************
494
+ ;- SOFTWARE API DEFINITION FOR Serial Parallel Interface
495
+ ;- *****************************************************************************
496
+ ^ 0 ;- AT91S_SPI
497
+ SPI_CR # 4 ;- Control Register
498
+ SPI_MR # 4 ;- Mode Register
499
+ SPI_RDR # 4 ;- Receive Data Register
500
+ SPI_TDR # 4 ;- Transmit Data Register
501
+ SPI_SR # 4 ;- Status Register
502
+ SPI_IER # 4 ;- Interrupt Enable Register
503
+ SPI_IDR # 4 ;- Interrupt Disable Register
504
+ SPI_IMR # 4 ;- Interrupt Mask Register
505
+ # 16 ;- Reserved
506
+ SPI_CSR # 16 ;- Chip Select Register
507
+ # 192 ;- Reserved
508
+ SPI_RPR # 4 ;- Receive Pointer Register
509
+ SPI_RCR # 4 ;- Receive Counter Register
510
+ SPI_TPR # 4 ;- Transmit Pointer Register
511
+ SPI_TCR # 4 ;- Transmit Counter Register
512
+ SPI_RNPR # 4 ;- Receive Next Pointer Register
513
+ SPI_RNCR # 4 ;- Receive Next Counter Register
514
+ SPI_TNPR # 4 ;- Transmit Next Pointer Register
515
+ SPI_TNCR # 4 ;- Transmit Next Counter Register
516
+ SPI_PTCR # 4 ;- PDC Transfer Control Register
517
+ SPI_PTSR # 4 ;- PDC Transfer Status Register
518
+ ;- -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
519
+ AT91C_SPI_SPIEN EQU (0x1:SHL:0) ;- (SPI) SPI Enable
520
+ AT91C_SPI_SPIDIS EQU (0x1:SHL:1) ;- (SPI) SPI Disable
521
+ AT91C_SPI_SWRST EQU (0x1:SHL:7) ;- (SPI) SPI Software reset
522
+ AT91C_SPI_LASTXFER EQU (0x1:SHL:24) ;- (SPI) SPI Last Transfer
523
+ ;- -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
524
+ AT91C_SPI_MSTR EQU (0x1:SHL:0) ;- (SPI) Master/Slave Mode
525
+ AT91C_SPI_PS EQU (0x1:SHL:1) ;- (SPI) Peripheral Select
526
+ AT91C_SPI_PS_FIXED EQU (0x0:SHL:1) ;- (SPI) Fixed Peripheral Select
527
+ AT91C_SPI_PS_VARIABLE EQU (0x1:SHL:1) ;- (SPI) Variable Peripheral Select
528
+ AT91C_SPI_PCSDEC EQU (0x1:SHL:2) ;- (SPI) Chip Select Decode
529
+ AT91C_SPI_FDIV EQU (0x1:SHL:3) ;- (SPI) Clock Selection
530
+ AT91C_SPI_MODFDIS EQU (0x1:SHL:4) ;- (SPI) Mode Fault Detection
531
+ AT91C_SPI_LLB EQU (0x1:SHL:7) ;- (SPI) Clock Selection
532
+ AT91C_SPI_PCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select
533
+ AT91C_SPI_DLYBCS EQU (0xFF:SHL:24) ;- (SPI) Delay Between Chip Selects
534
+ ;- -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
535
+ AT91C_SPI_RD EQU (0xFFFF:SHL:0) ;- (SPI) Receive Data
536
+ AT91C_SPI_RPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status
537
+ ;- -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
538
+ AT91C_SPI_TD EQU (0xFFFF:SHL:0) ;- (SPI) Transmit Data
539
+ AT91C_SPI_TPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status
540
+ ;- -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
541
+ AT91C_SPI_RDRF EQU (0x1:SHL:0) ;- (SPI) Receive Data Register Full
542
+ AT91C_SPI_TDRE EQU (0x1:SHL:1) ;- (SPI) Transmit Data Register Empty
543
+ AT91C_SPI_MODF EQU (0x1:SHL:2) ;- (SPI) Mode Fault Error
544
+ AT91C_SPI_OVRES EQU (0x1:SHL:3) ;- (SPI) Overrun Error Status
545
+ AT91C_SPI_ENDRX EQU (0x1:SHL:4) ;- (SPI) End of Receiver Transfer
546
+ AT91C_SPI_ENDTX EQU (0x1:SHL:5) ;- (SPI) End of Receiver Transfer
547
+ AT91C_SPI_RXBUFF EQU (0x1:SHL:6) ;- (SPI) RXBUFF Interrupt
548
+ AT91C_SPI_TXBUFE EQU (0x1:SHL:7) ;- (SPI) TXBUFE Interrupt
549
+ AT91C_SPI_NSSR EQU (0x1:SHL:8) ;- (SPI) NSSR Interrupt
550
+ AT91C_SPI_TXEMPTY EQU (0x1:SHL:9) ;- (SPI) TXEMPTY Interrupt
551
+ AT91C_SPI_SPIENS EQU (0x1:SHL:16) ;- (SPI) Enable Status
552
+ ;- -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
553
+ ;- -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
554
+ ;- -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
555
+ ;- -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
556
+ AT91C_SPI_CPOL EQU (0x1:SHL:0) ;- (SPI) Clock Polarity
557
+ AT91C_SPI_NCPHA EQU (0x1:SHL:1) ;- (SPI) Clock Phase
558
+ AT91C_SPI_CSAAT EQU (0x1:SHL:3) ;- (SPI) Chip Select Active After Transfer
559
+ AT91C_SPI_BITS EQU (0xF:SHL:4) ;- (SPI) Bits Per Transfer
560
+ AT91C_SPI_BITS_8 EQU (0x0:SHL:4) ;- (SPI) 8 Bits Per transfer
561
+ AT91C_SPI_BITS_9 EQU (0x1:SHL:4) ;- (SPI) 9 Bits Per transfer
562
+ AT91C_SPI_BITS_10 EQU (0x2:SHL:4) ;- (SPI) 10 Bits Per transfer
563
+ AT91C_SPI_BITS_11 EQU (0x3:SHL:4) ;- (SPI) 11 Bits Per transfer
564
+ AT91C_SPI_BITS_12 EQU (0x4:SHL:4) ;- (SPI) 12 Bits Per transfer
565
+ AT91C_SPI_BITS_13 EQU (0x5:SHL:4) ;- (SPI) 13 Bits Per transfer
566
+ AT91C_SPI_BITS_14 EQU (0x6:SHL:4) ;- (SPI) 14 Bits Per transfer
567
+ AT91C_SPI_BITS_15 EQU (0x7:SHL:4) ;- (SPI) 15 Bits Per transfer
568
+ AT91C_SPI_BITS_16 EQU (0x8:SHL:4) ;- (SPI) 16 Bits Per transfer
569
+ AT91C_SPI_SCBR EQU (0xFF:SHL:8) ;- (SPI) Serial Clock Baud Rate
570
+ AT91C_SPI_DLYBS EQU (0xFF:SHL:16) ;- (SPI) Delay Before SPCK
571
+ AT91C_SPI_DLYBCT EQU (0xFF:SHL:24) ;- (SPI) Delay Between Consecutive Transfers
572
+
573
+ ;- *****************************************************************************
574
+ ;- SOFTWARE API DEFINITION FOR Usart
575
+ ;- *****************************************************************************
576
+ ^ 0 ;- AT91S_USART
577
+ US_CR # 4 ;- Control Register
578
+ US_MR # 4 ;- Mode Register
579
+ US_IER # 4 ;- Interrupt Enable Register
580
+ US_IDR # 4 ;- Interrupt Disable Register
581
+ US_IMR # 4 ;- Interrupt Mask Register
582
+ US_CSR # 4 ;- Channel Status Register
583
+ US_RHR # 4 ;- Receiver Holding Register
584
+ US_THR # 4 ;- Transmitter Holding Register
585
+ US_BRGR # 4 ;- Baud Rate Generator Register
586
+ US_RTOR # 4 ;- Receiver Time-out Register
587
+ US_TTGR # 4 ;- Transmitter Time-guard Register
588
+ # 20 ;- Reserved
589
+ US_FIDI # 4 ;- FI_DI_Ratio Register
590
+ US_NER # 4 ;- Nb Errors Register
591
+ # 4 ;- Reserved
592
+ US_IF # 4 ;- IRDA_FILTER Register
593
+ # 176 ;- Reserved
594
+ US_RPR # 4 ;- Receive Pointer Register
595
+ US_RCR # 4 ;- Receive Counter Register
596
+ US_TPR # 4 ;- Transmit Pointer Register
597
+ US_TCR # 4 ;- Transmit Counter Register
598
+ US_RNPR # 4 ;- Receive Next Pointer Register
599
+ US_RNCR # 4 ;- Receive Next Counter Register
600
+ US_TNPR # 4 ;- Transmit Next Pointer Register
601
+ US_TNCR # 4 ;- Transmit Next Counter Register
602
+ US_PTCR # 4 ;- PDC Transfer Control Register
603
+ US_PTSR # 4 ;- PDC Transfer Status Register
604
+ ;- -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
605
+ AT91C_US_STTBRK EQU (0x1:SHL:9) ;- (USART) Start Break
606
+ AT91C_US_STPBRK EQU (0x1:SHL:10) ;- (USART) Stop Break
607
+ AT91C_US_STTTO EQU (0x1:SHL:11) ;- (USART) Start Time-out
608
+ AT91C_US_SENDA EQU (0x1:SHL:12) ;- (USART) Send Address
609
+ AT91C_US_RSTIT EQU (0x1:SHL:13) ;- (USART) Reset Iterations
610
+ AT91C_US_RSTNACK EQU (0x1:SHL:14) ;- (USART) Reset Non Acknowledge
611
+ AT91C_US_RETTO EQU (0x1:SHL:15) ;- (USART) Rearm Time-out
612
+ AT91C_US_DTREN EQU (0x1:SHL:16) ;- (USART) Data Terminal ready Enable
613
+ AT91C_US_DTRDIS EQU (0x1:SHL:17) ;- (USART) Data Terminal ready Disable
614
+ AT91C_US_RTSEN EQU (0x1:SHL:18) ;- (USART) Request to Send enable
615
+ AT91C_US_RTSDIS EQU (0x1:SHL:19) ;- (USART) Request to Send Disable
616
+ ;- -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
617
+ AT91C_US_USMODE EQU (0xF:SHL:0) ;- (USART) Usart mode
618
+ AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal
619
+ AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485
620
+ AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking
621
+ AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem
622
+ AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
623
+ AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
624
+ AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA
625
+ AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking
626
+ AT91C_US_CLKS EQU (0x3:SHL:4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
627
+ AT91C_US_CLKS_CLOCK EQU (0x0:SHL:4) ;- (USART) Clock
628
+ AT91C_US_CLKS_FDIV1 EQU (0x1:SHL:4) ;- (USART) fdiv1
629
+ AT91C_US_CLKS_SLOW EQU (0x2:SHL:4) ;- (USART) slow_clock (ARM)
630
+ AT91C_US_CLKS_EXT EQU (0x3:SHL:4) ;- (USART) External (SCK)
631
+ AT91C_US_CHRL EQU (0x3:SHL:6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
632
+ AT91C_US_CHRL_5_BITS EQU (0x0:SHL:6) ;- (USART) Character Length: 5 bits
633
+ AT91C_US_CHRL_6_BITS EQU (0x1:SHL:6) ;- (USART) Character Length: 6 bits
634
+ AT91C_US_CHRL_7_BITS EQU (0x2:SHL:6) ;- (USART) Character Length: 7 bits
635
+ AT91C_US_CHRL_8_BITS EQU (0x3:SHL:6) ;- (USART) Character Length: 8 bits
636
+ AT91C_US_SYNC EQU (0x1:SHL:8) ;- (USART) Synchronous Mode Select
637
+ AT91C_US_NBSTOP EQU (0x3:SHL:12) ;- (USART) Number of Stop bits
638
+ AT91C_US_NBSTOP_1_BIT EQU (0x0:SHL:12) ;- (USART) 1 stop bit
639
+ AT91C_US_NBSTOP_15_BIT EQU (0x1:SHL:12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
640
+ AT91C_US_NBSTOP_2_BIT EQU (0x2:SHL:12) ;- (USART) 2 stop bits
641
+ AT91C_US_MSBF EQU (0x1:SHL:16) ;- (USART) Bit Order
642
+ AT91C_US_MODE9 EQU (0x1:SHL:17) ;- (USART) 9-bit Character length
643
+ AT91C_US_CKLO EQU (0x1:SHL:18) ;- (USART) Clock Output Select
644
+ AT91C_US_OVER EQU (0x1:SHL:19) ;- (USART) Over Sampling Mode
645
+ AT91C_US_INACK EQU (0x1:SHL:20) ;- (USART) Inhibit Non Acknowledge
646
+ AT91C_US_DSNACK EQU (0x1:SHL:21) ;- (USART) Disable Successive NACK
647
+ AT91C_US_MAX_ITER EQU (0x1:SHL:24) ;- (USART) Number of Repetitions
648
+ AT91C_US_FILTER EQU (0x1:SHL:28) ;- (USART) Receive Line Filter
649
+ ;- -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
650
+ AT91C_US_RXBRK EQU (0x1:SHL:2) ;- (USART) Break Received/End of Break
651
+ AT91C_US_TIMEOUT EQU (0x1:SHL:8) ;- (USART) Receiver Time-out
652
+ AT91C_US_ITERATION EQU (0x1:SHL:10) ;- (USART) Max number of Repetitions Reached
653
+ AT91C_US_NACK EQU (0x1:SHL:13) ;- (USART) Non Acknowledge
654
+ AT91C_US_RIIC EQU (0x1:SHL:16) ;- (USART) Ring INdicator Input Change Flag
655
+ AT91C_US_DSRIC EQU (0x1:SHL:17) ;- (USART) Data Set Ready Input Change Flag
656
+ AT91C_US_DCDIC EQU (0x1:SHL:18) ;- (USART) Data Carrier Flag
657
+ AT91C_US_CTSIC EQU (0x1:SHL:19) ;- (USART) Clear To Send Input Change Flag
658
+ ;- -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
659
+ ;- -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
660
+ ;- -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
661
+ AT91C_US_RI EQU (0x1:SHL:20) ;- (USART) Image of RI Input
662
+ AT91C_US_DSR EQU (0x1:SHL:21) ;- (USART) Image of DSR Input
663
+ AT91C_US_DCD EQU (0x1:SHL:22) ;- (USART) Image of DCD Input
664
+ AT91C_US_CTS EQU (0x1:SHL:23) ;- (USART) Image of CTS Input
665
+
666
+ ;- *****************************************************************************
667
+ ;- SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
668
+ ;- *****************************************************************************
669
+ ^ 0 ;- AT91S_SSC
670
+ SSC_CR # 4 ;- Control Register
671
+ SSC_CMR # 4 ;- Clock Mode Register
672
+ # 8 ;- Reserved
673
+ SSC_RCMR # 4 ;- Receive Clock ModeRegister
674
+ SSC_RFMR # 4 ;- Receive Frame Mode Register
675
+ SSC_TCMR # 4 ;- Transmit Clock Mode Register
676
+ SSC_TFMR # 4 ;- Transmit Frame Mode Register
677
+ SSC_RHR # 4 ;- Receive Holding Register
678
+ SSC_THR # 4 ;- Transmit Holding Register
679
+ # 8 ;- Reserved
680
+ SSC_RSHR # 4 ;- Receive Sync Holding Register
681
+ SSC_TSHR # 4 ;- Transmit Sync Holding Register
682
+ # 8 ;- Reserved
683
+ SSC_SR # 4 ;- Status Register
684
+ SSC_IER # 4 ;- Interrupt Enable Register
685
+ SSC_IDR # 4 ;- Interrupt Disable Register
686
+ SSC_IMR # 4 ;- Interrupt Mask Register
687
+ # 176 ;- Reserved
688
+ SSC_RPR # 4 ;- Receive Pointer Register
689
+ SSC_RCR # 4 ;- Receive Counter Register
690
+ SSC_TPR # 4 ;- Transmit Pointer Register
691
+ SSC_TCR # 4 ;- Transmit Counter Register
692
+ SSC_RNPR # 4 ;- Receive Next Pointer Register
693
+ SSC_RNCR # 4 ;- Receive Next Counter Register
694
+ SSC_TNPR # 4 ;- Transmit Next Pointer Register
695
+ SSC_TNCR # 4 ;- Transmit Next Counter Register
696
+ SSC_PTCR # 4 ;- PDC Transfer Control Register
697
+ SSC_PTSR # 4 ;- PDC Transfer Status Register
698
+ ;- -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
699
+ AT91C_SSC_RXEN EQU (0x1:SHL:0) ;- (SSC) Receive Enable
700
+ AT91C_SSC_RXDIS EQU (0x1:SHL:1) ;- (SSC) Receive Disable
701
+ AT91C_SSC_TXEN EQU (0x1:SHL:8) ;- (SSC) Transmit Enable
702
+ AT91C_SSC_TXDIS EQU (0x1:SHL:9) ;- (SSC) Transmit Disable
703
+ AT91C_SSC_SWRST EQU (0x1:SHL:15) ;- (SSC) Software Reset
704
+ ;- -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
705
+ AT91C_SSC_CKS EQU (0x3:SHL:0) ;- (SSC) Receive/Transmit Clock Selection
706
+ AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock
707
+ AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal
708
+ AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin
709
+ AT91C_SSC_CKO EQU (0x7:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
710
+ AT91C_SSC_CKO_NONE EQU (0x0:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
711
+ AT91C_SSC_CKO_CONTINOUS EQU (0x1:SHL:2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
712
+ AT91C_SSC_CKO_DATA_TX EQU (0x2:SHL:2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
713
+ AT91C_SSC_CKI EQU (0x1:SHL:5) ;- (SSC) Receive/Transmit Clock Inversion
714
+ AT91C_SSC_CKG EQU (0x3:SHL:6) ;- (SSC) Receive/Transmit Clock Gating Selection
715
+ AT91C_SSC_CKG_NONE EQU (0x0:SHL:6) ;- (SSC) Receive/Transmit Clock Gating: None, continuous clock
716
+ AT91C_SSC_CKG_LOW EQU (0x1:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF Low
717
+ AT91C_SSC_CKG_HIGH EQU (0x2:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF High
718
+ AT91C_SSC_START EQU (0xF:SHL:8) ;- (SSC) Receive/Transmit Start Selection
719
+ AT91C_SSC_START_CONTINOUS EQU (0x0:SHL:8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
720
+ AT91C_SSC_START_TX EQU (0x1:SHL:8) ;- (SSC) Transmit/Receive start
721
+ AT91C_SSC_START_LOW_RF EQU (0x2:SHL:8) ;- (SSC) Detection of a low level on RF input
722
+ AT91C_SSC_START_HIGH_RF EQU (0x3:SHL:8) ;- (SSC) Detection of a high level on RF input
723
+ AT91C_SSC_START_FALL_RF EQU (0x4:SHL:8) ;- (SSC) Detection of a falling edge on RF input
724
+ AT91C_SSC_START_RISE_RF EQU (0x5:SHL:8) ;- (SSC) Detection of a rising edge on RF input
725
+ AT91C_SSC_START_LEVEL_RF EQU (0x6:SHL:8) ;- (SSC) Detection of any level change on RF input
726
+ AT91C_SSC_START_EDGE_RF EQU (0x7:SHL:8) ;- (SSC) Detection of any edge on RF input
727
+ AT91C_SSC_START_0 EQU (0x8:SHL:8) ;- (SSC) Compare 0
728
+ AT91C_SSC_STOP EQU (0x1:SHL:12) ;- (SSC) Receive Stop Selection
729
+ AT91C_SSC_STTDLY EQU (0xFF:SHL:16) ;- (SSC) Receive/Transmit Start Delay
730
+ AT91C_SSC_PERIOD EQU (0xFF:SHL:24) ;- (SSC) Receive/Transmit Period Divider Selection
731
+ ;- -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
732
+ AT91C_SSC_DATLEN EQU (0x1F:SHL:0) ;- (SSC) Data Length
733
+ AT91C_SSC_LOOP EQU (0x1:SHL:5) ;- (SSC) Loop Mode
734
+ AT91C_SSC_MSBF EQU (0x1:SHL:7) ;- (SSC) Most Significant Bit First
735
+ AT91C_SSC_DATNB EQU (0xF:SHL:8) ;- (SSC) Data Number per Frame
736
+ AT91C_SSC_FSLEN EQU (0xF:SHL:16) ;- (SSC) Receive/Transmit Frame Sync length
737
+ AT91C_SSC_FSOS EQU (0x7:SHL:20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
738
+ AT91C_SSC_FSOS_NONE EQU (0x0:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
739
+ AT91C_SSC_FSOS_NEGATIVE EQU (0x1:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
740
+ AT91C_SSC_FSOS_POSITIVE EQU (0x2:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
741
+ AT91C_SSC_FSOS_LOW EQU (0x3:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
742
+ AT91C_SSC_FSOS_HIGH EQU (0x4:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
743
+ AT91C_SSC_FSOS_TOGGLE EQU (0x5:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
744
+ AT91C_SSC_FSEDGE EQU (0x1:SHL:24) ;- (SSC) Frame Sync Edge Detection
745
+ ;- -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
746
+ ;- -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
747
+ AT91C_SSC_DATDEF EQU (0x1:SHL:5) ;- (SSC) Data Default Value
748
+ AT91C_SSC_FSDEN EQU (0x1:SHL:23) ;- (SSC) Frame Sync Data Enable
749
+ ;- -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
750
+ AT91C_SSC_TXRDY EQU (0x1:SHL:0) ;- (SSC) Transmit Ready
751
+ AT91C_SSC_TXEMPTY EQU (0x1:SHL:1) ;- (SSC) Transmit Empty
752
+ AT91C_SSC_ENDTX EQU (0x1:SHL:2) ;- (SSC) End Of Transmission
753
+ AT91C_SSC_TXBUFE EQU (0x1:SHL:3) ;- (SSC) Transmit Buffer Empty
754
+ AT91C_SSC_RXRDY EQU (0x1:SHL:4) ;- (SSC) Receive Ready
755
+ AT91C_SSC_OVRUN EQU (0x1:SHL:5) ;- (SSC) Receive Overrun
756
+ AT91C_SSC_ENDRX EQU (0x1:SHL:6) ;- (SSC) End of Reception
757
+ AT91C_SSC_RXBUFF EQU (0x1:SHL:7) ;- (SSC) Receive Buffer Full
758
+ AT91C_SSC_CP0 EQU (0x1:SHL:8) ;- (SSC) Compare 0
759
+ AT91C_SSC_CP1 EQU (0x1:SHL:9) ;- (SSC) Compare 1
760
+ AT91C_SSC_TXSYN EQU (0x1:SHL:10) ;- (SSC) Transmit Sync
761
+ AT91C_SSC_RXSYN EQU (0x1:SHL:11) ;- (SSC) Receive Sync
762
+ AT91C_SSC_TXENA EQU (0x1:SHL:16) ;- (SSC) Transmit Enable
763
+ AT91C_SSC_RXENA EQU (0x1:SHL:17) ;- (SSC) Receive Enable
764
+ ;- -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
765
+ ;- -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
766
+ ;- -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
767
+
768
+ ;- *****************************************************************************
769
+ ;- SOFTWARE API DEFINITION FOR Two-wire Interface
770
+ ;- *****************************************************************************
771
+ ^ 0 ;- AT91S_TWI
772
+ TWI_CR # 4 ;- Control Register
773
+ TWI_MMR # 4 ;- Master Mode Register
774
+ # 4 ;- Reserved
775
+ TWI_IADR # 4 ;- Internal Address Register
776
+ TWI_CWGR # 4 ;- Clock Waveform Generator Register
777
+ # 12 ;- Reserved
778
+ TWI_SR # 4 ;- Status Register
779
+ TWI_IER # 4 ;- Interrupt Enable Register
780
+ TWI_IDR # 4 ;- Interrupt Disable Register
781
+ TWI_IMR # 4 ;- Interrupt Mask Register
782
+ TWI_RHR # 4 ;- Receive Holding Register
783
+ TWI_THR # 4 ;- Transmit Holding Register
784
+ ;- -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
785
+ AT91C_TWI_START EQU (0x1:SHL:0) ;- (TWI) Send a START Condition
786
+ AT91C_TWI_STOP EQU (0x1:SHL:1) ;- (TWI) Send a STOP Condition
787
+ AT91C_TWI_MSEN EQU (0x1:SHL:2) ;- (TWI) TWI Master Transfer Enabled
788
+ AT91C_TWI_MSDIS EQU (0x1:SHL:3) ;- (TWI) TWI Master Transfer Disabled
789
+ AT91C_TWI_SWRST EQU (0x1:SHL:7) ;- (TWI) Software Reset
790
+ ;- -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
791
+ AT91C_TWI_IADRSZ EQU (0x3:SHL:8) ;- (TWI) Internal Device Address Size
792
+ AT91C_TWI_IADRSZ_NO EQU (0x0:SHL:8) ;- (TWI) No internal device address
793
+ AT91C_TWI_IADRSZ_1_BYTE EQU (0x1:SHL:8) ;- (TWI) One-byte internal device address
794
+ AT91C_TWI_IADRSZ_2_BYTE EQU (0x2:SHL:8) ;- (TWI) Two-byte internal device address
795
+ AT91C_TWI_IADRSZ_3_BYTE EQU (0x3:SHL:8) ;- (TWI) Three-byte internal device address
796
+ AT91C_TWI_MREAD EQU (0x1:SHL:12) ;- (TWI) Master Read Direction
797
+ AT91C_TWI_DADR EQU (0x7F:SHL:16) ;- (TWI) Device Address
798
+ ;- -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
799
+ AT91C_TWI_CLDIV EQU (0xFF:SHL:0) ;- (TWI) Clock Low Divider
800
+ AT91C_TWI_CHDIV EQU (0xFF:SHL:8) ;- (TWI) Clock High Divider
801
+ AT91C_TWI_CKDIV EQU (0x7:SHL:16) ;- (TWI) Clock Divider
802
+ ;- -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
803
+ AT91C_TWI_TXCOMP EQU (0x1:SHL:0) ;- (TWI) Transmission Completed
804
+ AT91C_TWI_RXRDY EQU (0x1:SHL:1) ;- (TWI) Receive holding register ReaDY
805
+ AT91C_TWI_TXRDY EQU (0x1:SHL:2) ;- (TWI) Transmit holding register ReaDY
806
+ AT91C_TWI_OVRE EQU (0x1:SHL:6) ;- (TWI) Overrun Error
807
+ AT91C_TWI_UNRE EQU (0x1:SHL:7) ;- (TWI) Underrun Error
808
+ AT91C_TWI_NACK EQU (0x1:SHL:8) ;- (TWI) Not Acknowledged
809
+ ;- -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
810
+ ;- -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
811
+ ;- -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
812
+
813
+ ;- *****************************************************************************
814
+ ;- SOFTWARE API DEFINITION FOR PWMC Channel Interface
815
+ ;- *****************************************************************************
816
+ ^ 0 ;- AT91S_PWMC_CH
817
+ PWMC_CMR # 4 ;- Channel Mode Register
818
+ PWMC_CDTYR # 4 ;- Channel Duty Cycle Register
819
+ PWMC_CPRDR # 4 ;- Channel Period Register
820
+ PWMC_CCNTR # 4 ;- Channel Counter Register
821
+ PWMC_CUPDR # 4 ;- Channel Update Register
822
+ PWMC_Reserved # 12 ;- Reserved
823
+ ;- -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
824
+ AT91C_PWMC_CPRE EQU (0xF:SHL:0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
825
+ AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH)
826
+ AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH)
827
+ AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH)
828
+ AT91C_PWMC_CALG EQU (0x1:SHL:8) ;- (PWMC_CH) Channel Alignment
829
+ AT91C_PWMC_CPOL EQU (0x1:SHL:9) ;- (PWMC_CH) Channel Polarity
830
+ AT91C_PWMC_CPD EQU (0x1:SHL:10) ;- (PWMC_CH) Channel Update Period
831
+ ;- -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
832
+ AT91C_PWMC_CDTY EQU (0x0:SHL:0) ;- (PWMC_CH) Channel Duty Cycle
833
+ ;- -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
834
+ AT91C_PWMC_CPRD EQU (0x0:SHL:0) ;- (PWMC_CH) Channel Period
835
+ ;- -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
836
+ AT91C_PWMC_CCNT EQU (0x0:SHL:0) ;- (PWMC_CH) Channel Counter
837
+ ;- -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
838
+ AT91C_PWMC_CUPD EQU (0x0:SHL:0) ;- (PWMC_CH) Channel Update
839
+
840
+ ;- *****************************************************************************
841
+ ;- SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
842
+ ;- *****************************************************************************
843
+ ^ 0 ;- AT91S_PWMC
844
+ PWMC_MR # 4 ;- PWMC Mode Register
845
+ PWMC_ENA # 4 ;- PWMC Enable Register
846
+ PWMC_DIS # 4 ;- PWMC Disable Register
847
+ PWMC_SR # 4 ;- PWMC Status Register
848
+ PWMC_IER # 4 ;- PWMC Interrupt Enable Register
849
+ PWMC_IDR # 4 ;- PWMC Interrupt Disable Register
850
+ PWMC_IMR # 4 ;- PWMC Interrupt Mask Register
851
+ PWMC_ISR # 4 ;- PWMC Interrupt Status Register
852
+ # 220 ;- Reserved
853
+ PWMC_VR # 4 ;- PWMC Version Register
854
+ # 256 ;- Reserved
855
+ PWMC_CH # 96 ;- PWMC Channel
856
+ ;- -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
857
+ AT91C_PWMC_DIVA EQU (0xFF:SHL:0) ;- (PWMC) CLKA divide factor.
858
+ AT91C_PWMC_PREA EQU (0xF:SHL:8) ;- (PWMC) Divider Input Clock Prescaler A
859
+ AT91C_PWMC_PREA_MCK EQU (0x0:SHL:8) ;- (PWMC)
860
+ AT91C_PWMC_DIVB EQU (0xFF:SHL:16) ;- (PWMC) CLKB divide factor.
861
+ AT91C_PWMC_PREB EQU (0xF:SHL:24) ;- (PWMC) Divider Input Clock Prescaler B
862
+ AT91C_PWMC_PREB_MCK EQU (0x0:SHL:24) ;- (PWMC)
863
+ ;- -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
864
+ AT91C_PWMC_CHID0 EQU (0x1:SHL:0) ;- (PWMC) Channel ID 0
865
+ AT91C_PWMC_CHID1 EQU (0x1:SHL:1) ;- (PWMC) Channel ID 1
866
+ AT91C_PWMC_CHID2 EQU (0x1:SHL:2) ;- (PWMC) Channel ID 2
867
+ AT91C_PWMC_CHID3 EQU (0x1:SHL:3) ;- (PWMC) Channel ID 3
868
+ ;- -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
869
+ ;- -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
870
+ ;- -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
871
+ ;- -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
872
+ ;- -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
873
+ ;- -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
874
+
875
+ ;- *****************************************************************************
876
+ ;- SOFTWARE API DEFINITION FOR USB Device Interface
877
+ ;- *****************************************************************************
878
+ ^ 0 ;- AT91S_UDP
879
+ UDP_NUM # 4 ;- Frame Number Register
880
+ UDP_GLBSTATE # 4 ;- Global State Register
881
+ UDP_FADDR # 4 ;- Function Address Register
882
+ # 4 ;- Reserved
883
+ UDP_IER # 4 ;- Interrupt Enable Register
884
+ UDP_IDR # 4 ;- Interrupt Disable Register
885
+ UDP_IMR # 4 ;- Interrupt Mask Register
886
+ UDP_ISR # 4 ;- Interrupt Status Register
887
+ UDP_ICR # 4 ;- Interrupt Clear Register
888
+ # 4 ;- Reserved
889
+ UDP_RSTEP # 4 ;- Reset Endpoint Register
890
+ # 4 ;- Reserved
891
+ UDP_CSR # 24 ;- Endpoint Control and Status Register
892
+ # 8 ;- Reserved
893
+ UDP_FDR # 24 ;- Endpoint FIFO Data Register
894
+ # 12 ;- Reserved
895
+ UDP_TXVC # 4 ;- Transceiver Control Register
896
+ ;- -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
897
+ AT91C_UDP_FRM_NUM EQU (0x7FF:SHL:0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
898
+ AT91C_UDP_FRM_ERR EQU (0x1:SHL:16) ;- (UDP) Frame Error
899
+ AT91C_UDP_FRM_OK EQU (0x1:SHL:17) ;- (UDP) Frame OK
900
+ ;- -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
901
+ AT91C_UDP_FADDEN EQU (0x1:SHL:0) ;- (UDP) Function Address Enable
902
+ AT91C_UDP_CONFG EQU (0x1:SHL:1) ;- (UDP) Configured
903
+ AT91C_UDP_ESR EQU (0x1:SHL:2) ;- (UDP) Enable Send Resume
904
+ AT91C_UDP_RSMINPR EQU (0x1:SHL:3) ;- (UDP) A Resume Has Been Sent to the Host
905
+ AT91C_UDP_RMWUPE EQU (0x1:SHL:4) ;- (UDP) Remote Wake Up Enable
906
+ ;- -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
907
+ AT91C_UDP_FADD EQU (0xFF:SHL:0) ;- (UDP) Function Address Value
908
+ AT91C_UDP_FEN EQU (0x1:SHL:8) ;- (UDP) Function Enable
909
+ ;- -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
910
+ AT91C_UDP_EPINT0 EQU (0x1:SHL:0) ;- (UDP) Endpoint 0 Interrupt
911
+ AT91C_UDP_EPINT1 EQU (0x1:SHL:1) ;- (UDP) Endpoint 0 Interrupt
912
+ AT91C_UDP_EPINT2 EQU (0x1:SHL:2) ;- (UDP) Endpoint 2 Interrupt
913
+ AT91C_UDP_EPINT3 EQU (0x1:SHL:3) ;- (UDP) Endpoint 3 Interrupt
914
+ AT91C_UDP_EPINT4 EQU (0x1:SHL:4) ;- (UDP) Endpoint 4 Interrupt
915
+ AT91C_UDP_EPINT5 EQU (0x1:SHL:5) ;- (UDP) Endpoint 5 Interrupt
916
+ AT91C_UDP_RXSUSP EQU (0x1:SHL:8) ;- (UDP) USB Suspend Interrupt
917
+ AT91C_UDP_RXRSM EQU (0x1:SHL:9) ;- (UDP) USB Resume Interrupt
918
+ AT91C_UDP_EXTRSM EQU (0x1:SHL:10) ;- (UDP) USB External Resume Interrupt
919
+ AT91C_UDP_SOFINT EQU (0x1:SHL:11) ;- (UDP) USB Start Of frame Interrupt
920
+ AT91C_UDP_WAKEUP EQU (0x1:SHL:13) ;- (UDP) USB Resume Interrupt
921
+ ;- -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
922
+ ;- -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
923
+ ;- -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
924
+ AT91C_UDP_ENDBUSRES EQU (0x1:SHL:12) ;- (UDP) USB End Of Bus Reset Interrupt
925
+ ;- -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
926
+ ;- -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
927
+ AT91C_UDP_EP0 EQU (0x1:SHL:0) ;- (UDP) Reset Endpoint 0
928
+ AT91C_UDP_EP1 EQU (0x1:SHL:1) ;- (UDP) Reset Endpoint 1
929
+ AT91C_UDP_EP2 EQU (0x1:SHL:2) ;- (UDP) Reset Endpoint 2
930
+ AT91C_UDP_EP3 EQU (0x1:SHL:3) ;- (UDP) Reset Endpoint 3
931
+ AT91C_UDP_EP4 EQU (0x1:SHL:4) ;- (UDP) Reset Endpoint 4
932
+ AT91C_UDP_EP5 EQU (0x1:SHL:5) ;- (UDP) Reset Endpoint 5
933
+ ;- -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
934
+ AT91C_UDP_TXCOMP EQU (0x1:SHL:0) ;- (UDP) Generates an IN packet with data previously written in the DPR
935
+ AT91C_UDP_RX_DATA_BK0 EQU (0x1:SHL:1) ;- (UDP) Receive Data Bank 0
936
+ AT91C_UDP_RXSETUP EQU (0x1:SHL:2) ;- (UDP) Sends STALL to the Host (Control endpoints)
937
+ AT91C_UDP_ISOERROR EQU (0x1:SHL:3) ;- (UDP) Isochronous error (Isochronous endpoints)
938
+ AT91C_UDP_TXPKTRDY EQU (0x1:SHL:4) ;- (UDP) Transmit Packet Ready
939
+ AT91C_UDP_FORCESTALL EQU (0x1:SHL:5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
940
+ AT91C_UDP_RX_DATA_BK1 EQU (0x1:SHL:6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
941
+ AT91C_UDP_DIR EQU (0x1:SHL:7) ;- (UDP) Transfer Direction
942
+ AT91C_UDP_EPTYPE EQU (0x7:SHL:8) ;- (UDP) Endpoint type
943
+ AT91C_UDP_EPTYPE_CTRL EQU (0x0:SHL:8) ;- (UDP) Control
944
+ AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1:SHL:8) ;- (UDP) Isochronous OUT
945
+ AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2:SHL:8) ;- (UDP) Bulk OUT
946
+ AT91C_UDP_EPTYPE_INT_OUT EQU (0x3:SHL:8) ;- (UDP) Interrupt OUT
947
+ AT91C_UDP_EPTYPE_ISO_IN EQU (0x5:SHL:8) ;- (UDP) Isochronous IN
948
+ AT91C_UDP_EPTYPE_BULK_IN EQU (0x6:SHL:8) ;- (UDP) Bulk IN
949
+ AT91C_UDP_EPTYPE_INT_IN EQU (0x7:SHL:8) ;- (UDP) Interrupt IN
950
+ AT91C_UDP_DTGLE EQU (0x1:SHL:11) ;- (UDP) Data Toggle
951
+ AT91C_UDP_EPEDS EQU (0x1:SHL:15) ;- (UDP) Endpoint Enable Disable
952
+ AT91C_UDP_RXBYTECNT EQU (0x7FF:SHL:16) ;- (UDP) Number Of Bytes Available in the FIFO
953
+ ;- -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
954
+ AT91C_UDP_TXVDIS EQU (0x1:SHL:8) ;- (UDP)
955
+ AT91C_UDP_PUON EQU (0x1:SHL:9) ;- (UDP) Pull-up ON
956
+
957
+ ;- *****************************************************************************
958
+ ;- SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
959
+ ;- *****************************************************************************
960
+ ^ 0 ;- AT91S_TC
961
+ TC_CCR # 4 ;- Channel Control Register
962
+ TC_CMR # 4 ;- Channel Mode Register (Capture Mode / Waveform Mode)
963
+ # 8 ;- Reserved
964
+ TC_CV # 4 ;- Counter Value
965
+ TC_RA # 4 ;- Register A
966
+ TC_RB # 4 ;- Register B
967
+ TC_RC # 4 ;- Register C
968
+ TC_SR # 4 ;- Status Register
969
+ TC_IER # 4 ;- Interrupt Enable Register
970
+ TC_IDR # 4 ;- Interrupt Disable Register
971
+ TC_IMR # 4 ;- Interrupt Mask Register
972
+ ;- -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
973
+ AT91C_TC_CLKEN EQU (0x1:SHL:0) ;- (TC) Counter Clock Enable Command
974
+ AT91C_TC_CLKDIS EQU (0x1:SHL:1) ;- (TC) Counter Clock Disable Command
975
+ AT91C_TC_SWTRG EQU (0x1:SHL:2) ;- (TC) Software Trigger Command
976
+ ;- -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
977
+ AT91C_TC_CLKS EQU (0x7:SHL:0) ;- (TC) Clock Selection
978
+ AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
979
+ AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
980
+ AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
981
+ AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
982
+ AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
983
+ AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0
984
+ AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1
985
+ AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2
986
+ AT91C_TC_CLKI EQU (0x1:SHL:3) ;- (TC) Clock Invert
987
+ AT91C_TC_BURST EQU (0x3:SHL:4) ;- (TC) Burst Signal Selection
988
+ AT91C_TC_BURST_NONE EQU (0x0:SHL:4) ;- (TC) The clock is not gated by an external signal
989
+ AT91C_TC_BURST_XC0 EQU (0x1:SHL:4) ;- (TC) XC0 is ANDed with the selected clock
990
+ AT91C_TC_BURST_XC1 EQU (0x2:SHL:4) ;- (TC) XC1 is ANDed with the selected clock
991
+ AT91C_TC_BURST_XC2 EQU (0x3:SHL:4) ;- (TC) XC2 is ANDed with the selected clock
992
+ AT91C_TC_CPCSTOP EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RC Compare
993
+ AT91C_TC_LDBSTOP EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RB Loading
994
+ AT91C_TC_CPCDIS EQU (0x1:SHL:7) ;- (TC) Counter Clock Disable with RC Compare
995
+ AT91C_TC_LDBDIS EQU (0x1:SHL:7) ;- (TC) Counter Clock Disabled with RB Loading
996
+ AT91C_TC_ETRGEDG EQU (0x3:SHL:8) ;- (TC) External Trigger Edge Selection
997
+ AT91C_TC_ETRGEDG_NONE EQU (0x0:SHL:8) ;- (TC) Edge: None
998
+ AT91C_TC_ETRGEDG_RISING EQU (0x1:SHL:8) ;- (TC) Edge: rising edge
999
+ AT91C_TC_ETRGEDG_FALLING EQU (0x2:SHL:8) ;- (TC) Edge: falling edge
1000
+ AT91C_TC_ETRGEDG_BOTH EQU (0x3:SHL:8) ;- (TC) Edge: each edge
1001
+ AT91C_TC_EEVTEDG EQU (0x3:SHL:8) ;- (TC) External Event Edge Selection
1002
+ AT91C_TC_EEVTEDG_NONE EQU (0x0:SHL:8) ;- (TC) Edge: None
1003
+ AT91C_TC_EEVTEDG_RISING EQU (0x1:SHL:8) ;- (TC) Edge: rising edge
1004
+ AT91C_TC_EEVTEDG_FALLING EQU (0x2:SHL:8) ;- (TC) Edge: falling edge
1005
+ AT91C_TC_EEVTEDG_BOTH EQU (0x3:SHL:8) ;- (TC) Edge: each edge
1006
+ AT91C_TC_EEVT EQU (0x3:SHL:10) ;- (TC) External Event Selection
1007
+ AT91C_TC_EEVT_TIOB EQU (0x0:SHL:10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
1008
+ AT91C_TC_EEVT_XC0 EQU (0x1:SHL:10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
1009
+ AT91C_TC_EEVT_XC1 EQU (0x2:SHL:10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
1010
+ AT91C_TC_EEVT_XC2 EQU (0x3:SHL:10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
1011
+ AT91C_TC_ABETRG EQU (0x1:SHL:10) ;- (TC) TIOA or TIOB External Trigger Selection
1012
+ AT91C_TC_ENETRG EQU (0x1:SHL:12) ;- (TC) External Event Trigger enable
1013
+ AT91C_TC_WAVESEL EQU (0x3:SHL:13) ;- (TC) Waveform Selection
1014
+ AT91C_TC_WAVESEL_UP EQU (0x0:SHL:13) ;- (TC) UP mode without atomatic trigger on RC Compare
1015
+ AT91C_TC_WAVESEL_UPDOWN EQU (0x1:SHL:13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
1016
+ AT91C_TC_WAVESEL_UP_AUTO EQU (0x2:SHL:13) ;- (TC) UP mode with automatic trigger on RC Compare
1017
+ AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3:SHL:13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
1018
+ AT91C_TC_CPCTRG EQU (0x1:SHL:14) ;- (TC) RC Compare Trigger Enable
1019
+ AT91C_TC_WAVE EQU (0x1:SHL:15) ;- (TC)
1020
+ AT91C_TC_ACPA EQU (0x3:SHL:16) ;- (TC) RA Compare Effect on TIOA
1021
+ AT91C_TC_ACPA_NONE EQU (0x0:SHL:16) ;- (TC) Effect: none
1022
+ AT91C_TC_ACPA_SET EQU (0x1:SHL:16) ;- (TC) Effect: set
1023
+ AT91C_TC_ACPA_CLEAR EQU (0x2:SHL:16) ;- (TC) Effect: clear
1024
+ AT91C_TC_ACPA_TOGGLE EQU (0x3:SHL:16) ;- (TC) Effect: toggle
1025
+ AT91C_TC_LDRA EQU (0x3:SHL:16) ;- (TC) RA Loading Selection
1026
+ AT91C_TC_LDRA_NONE EQU (0x0:SHL:16) ;- (TC) Edge: None
1027
+ AT91C_TC_LDRA_RISING EQU (0x1:SHL:16) ;- (TC) Edge: rising edge of TIOA
1028
+ AT91C_TC_LDRA_FALLING EQU (0x2:SHL:16) ;- (TC) Edge: falling edge of TIOA
1029
+ AT91C_TC_LDRA_BOTH EQU (0x3:SHL:16) ;- (TC) Edge: each edge of TIOA
1030
+ AT91C_TC_ACPC EQU (0x3:SHL:18) ;- (TC) RC Compare Effect on TIOA
1031
+ AT91C_TC_ACPC_NONE EQU (0x0:SHL:18) ;- (TC) Effect: none
1032
+ AT91C_TC_ACPC_SET EQU (0x1:SHL:18) ;- (TC) Effect: set
1033
+ AT91C_TC_ACPC_CLEAR EQU (0x2:SHL:18) ;- (TC) Effect: clear
1034
+ AT91C_TC_ACPC_TOGGLE EQU (0x3:SHL:18) ;- (TC) Effect: toggle
1035
+ AT91C_TC_LDRB EQU (0x3:SHL:18) ;- (TC) RB Loading Selection
1036
+ AT91C_TC_LDRB_NONE EQU (0x0:SHL:18) ;- (TC) Edge: None
1037
+ AT91C_TC_LDRB_RISING EQU (0x1:SHL:18) ;- (TC) Edge: rising edge of TIOA
1038
+ AT91C_TC_LDRB_FALLING EQU (0x2:SHL:18) ;- (TC) Edge: falling edge of TIOA
1039
+ AT91C_TC_LDRB_BOTH EQU (0x3:SHL:18) ;- (TC) Edge: each edge of TIOA
1040
+ AT91C_TC_AEEVT EQU (0x3:SHL:20) ;- (TC) External Event Effect on TIOA
1041
+ AT91C_TC_AEEVT_NONE EQU (0x0:SHL:20) ;- (TC) Effect: none
1042
+ AT91C_TC_AEEVT_SET EQU (0x1:SHL:20) ;- (TC) Effect: set
1043
+ AT91C_TC_AEEVT_CLEAR EQU (0x2:SHL:20) ;- (TC) Effect: clear
1044
+ AT91C_TC_AEEVT_TOGGLE EQU (0x3:SHL:20) ;- (TC) Effect: toggle
1045
+ AT91C_TC_ASWTRG EQU (0x3:SHL:22) ;- (TC) Software Trigger Effect on TIOA
1046
+ AT91C_TC_ASWTRG_NONE EQU (0x0:SHL:22) ;- (TC) Effect: none
1047
+ AT91C_TC_ASWTRG_SET EQU (0x1:SHL:22) ;- (TC) Effect: set
1048
+ AT91C_TC_ASWTRG_CLEAR EQU (0x2:SHL:22) ;- (TC) Effect: clear
1049
+ AT91C_TC_ASWTRG_TOGGLE EQU (0x3:SHL:22) ;- (TC) Effect: toggle
1050
+ AT91C_TC_BCPB EQU (0x3:SHL:24) ;- (TC) RB Compare Effect on TIOB
1051
+ AT91C_TC_BCPB_NONE EQU (0x0:SHL:24) ;- (TC) Effect: none
1052
+ AT91C_TC_BCPB_SET EQU (0x1:SHL:24) ;- (TC) Effect: set
1053
+ AT91C_TC_BCPB_CLEAR EQU (0x2:SHL:24) ;- (TC) Effect: clear
1054
+ AT91C_TC_BCPB_TOGGLE EQU (0x3:SHL:24) ;- (TC) Effect: toggle
1055
+ AT91C_TC_BCPC EQU (0x3:SHL:26) ;- (TC) RC Compare Effect on TIOB
1056
+ AT91C_TC_BCPC_NONE EQU (0x0:SHL:26) ;- (TC) Effect: none
1057
+ AT91C_TC_BCPC_SET EQU (0x1:SHL:26) ;- (TC) Effect: set
1058
+ AT91C_TC_BCPC_CLEAR EQU (0x2:SHL:26) ;- (TC) Effect: clear
1059
+ AT91C_TC_BCPC_TOGGLE EQU (0x3:SHL:26) ;- (TC) Effect: toggle
1060
+ AT91C_TC_BEEVT EQU (0x3:SHL:28) ;- (TC) External Event Effect on TIOB
1061
+ AT91C_TC_BEEVT_NONE EQU (0x0:SHL:28) ;- (TC) Effect: none
1062
+ AT91C_TC_BEEVT_SET EQU (0x1:SHL:28) ;- (TC) Effect: set
1063
+ AT91C_TC_BEEVT_CLEAR EQU (0x2:SHL:28) ;- (TC) Effect: clear
1064
+ AT91C_TC_BEEVT_TOGGLE EQU (0x3:SHL:28) ;- (TC) Effect: toggle
1065
+ AT91C_TC_BSWTRG EQU (0x3:SHL:30) ;- (TC) Software Trigger Effect on TIOB
1066
+ AT91C_TC_BSWTRG_NONE EQU (0x0:SHL:30) ;- (TC) Effect: none
1067
+ AT91C_TC_BSWTRG_SET EQU (0x1:SHL:30) ;- (TC) Effect: set
1068
+ AT91C_TC_BSWTRG_CLEAR EQU (0x2:SHL:30) ;- (TC) Effect: clear
1069
+ AT91C_TC_BSWTRG_TOGGLE EQU (0x3:SHL:30) ;- (TC) Effect: toggle
1070
+ ;- -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
1071
+ AT91C_TC_COVFS EQU (0x1:SHL:0) ;- (TC) Counter Overflow
1072
+ AT91C_TC_LOVRS EQU (0x1:SHL:1) ;- (TC) Load Overrun
1073
+ AT91C_TC_CPAS EQU (0x1:SHL:2) ;- (TC) RA Compare
1074
+ AT91C_TC_CPBS EQU (0x1:SHL:3) ;- (TC) RB Compare
1075
+ AT91C_TC_CPCS EQU (0x1:SHL:4) ;- (TC) RC Compare
1076
+ AT91C_TC_LDRAS EQU (0x1:SHL:5) ;- (TC) RA Loading
1077
+ AT91C_TC_LDRBS EQU (0x1:SHL:6) ;- (TC) RB Loading
1078
+ AT91C_TC_ETRGS EQU (0x1:SHL:7) ;- (TC) External Trigger
1079
+ AT91C_TC_CLKSTA EQU (0x1:SHL:16) ;- (TC) Clock Enabling
1080
+ AT91C_TC_MTIOA EQU (0x1:SHL:17) ;- (TC) TIOA Mirror
1081
+ AT91C_TC_MTIOB EQU (0x1:SHL:18) ;- (TC) TIOA Mirror
1082
+ ;- -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
1083
+ ;- -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
1084
+ ;- -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
1085
+
1086
+ ;- *****************************************************************************
1087
+ ;- SOFTWARE API DEFINITION FOR Timer Counter Interface
1088
+ ;- *****************************************************************************
1089
+ ^ 0 ;- AT91S_TCB
1090
+ TCB_TC0 # 48 ;- TC Channel 0
1091
+ # 16 ;- Reserved
1092
+ TCB_TC1 # 48 ;- TC Channel 1
1093
+ # 16 ;- Reserved
1094
+ TCB_TC2 # 48 ;- TC Channel 2
1095
+ # 16 ;- Reserved
1096
+ TCB_BCR # 4 ;- TC Block Control Register
1097
+ TCB_BMR # 4 ;- TC Block Mode Register
1098
+ ;- -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
1099
+ AT91C_TCB_SYNC EQU (0x1:SHL:0) ;- (TCB) Synchro Command
1100
+ ;- -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
1101
+ AT91C_TCB_TC0XC0S EQU (0x3:SHL:0) ;- (TCB) External Clock Signal 0 Selection
1102
+ AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0
1103
+ AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0
1104
+ AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0
1105
+ AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0
1106
+ AT91C_TCB_TC1XC1S EQU (0x3:SHL:2) ;- (TCB) External Clock Signal 1 Selection
1107
+ AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0:SHL:2) ;- (TCB) TCLK1 connected to XC1
1108
+ AT91C_TCB_TC1XC1S_NONE EQU (0x1:SHL:2) ;- (TCB) None signal connected to XC1
1109
+ AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2:SHL:2) ;- (TCB) TIOA0 connected to XC1
1110
+ AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3:SHL:2) ;- (TCB) TIOA2 connected to XC1
1111
+ AT91C_TCB_TC2XC2S EQU (0x3:SHL:4) ;- (TCB) External Clock Signal 2 Selection
1112
+ AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0:SHL:4) ;- (TCB) TCLK2 connected to XC2
1113
+ AT91C_TCB_TC2XC2S_NONE EQU (0x1:SHL:4) ;- (TCB) None signal connected to XC2
1114
+ AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2:SHL:4) ;- (TCB) TIOA0 connected to XC2
1115
+ AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3:SHL:4) ;- (TCB) TIOA2 connected to XC2
1116
+
1117
+ ;- *****************************************************************************
1118
+ ;- SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
1119
+ ;- *****************************************************************************
1120
+ ^ 0 ;- AT91S_CAN_MB
1121
+ CAN_MB_MMR # 4 ;- MailBox Mode Register
1122
+ CAN_MB_MAM # 4 ;- MailBox Acceptance Mask Register
1123
+ CAN_MB_MID # 4 ;- MailBox ID Register
1124
+ CAN_MB_MFID # 4 ;- MailBox Family ID Register
1125
+ CAN_MB_MSR # 4 ;- MailBox Status Register
1126
+ CAN_MB_MDL # 4 ;- MailBox Data Low Register
1127
+ CAN_MB_MDH # 4 ;- MailBox Data High Register
1128
+ CAN_MB_MCR # 4 ;- MailBox Control Register
1129
+ ;- -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
1130
+ AT91C_CAN_MTIMEMARK EQU (0xFFFF:SHL:0) ;- (CAN_MB) Mailbox Timemark
1131
+ AT91C_CAN_PRIOR EQU (0xF:SHL:16) ;- (CAN_MB) Mailbox Priority
1132
+ AT91C_CAN_MOT EQU (0x7:SHL:24) ;- (CAN_MB) Mailbox Object Type
1133
+ AT91C_CAN_MOT_DIS EQU (0x0:SHL:24) ;- (CAN_MB)
1134
+ AT91C_CAN_MOT_RX EQU (0x1:SHL:24) ;- (CAN_MB)
1135
+ AT91C_CAN_MOT_RXOVERWRITE EQU (0x2:SHL:24) ;- (CAN_MB)
1136
+ AT91C_CAN_MOT_TX EQU (0x3:SHL:24) ;- (CAN_MB)
1137
+ AT91C_CAN_MOT_CONSUMER EQU (0x4:SHL:24) ;- (CAN_MB)
1138
+ AT91C_CAN_MOT_PRODUCER EQU (0x5:SHL:24) ;- (CAN_MB)
1139
+ ;- -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
1140
+ AT91C_CAN_MIDvB EQU (0x3FFFF:SHL:0) ;- (CAN_MB) Complementary bits for identifier in extended mode
1141
+ AT91C_CAN_MIDvA EQU (0x7FF:SHL:18) ;- (CAN_MB) Identifier for standard frame mode
1142
+ AT91C_CAN_MIDE EQU (0x1:SHL:29) ;- (CAN_MB) Identifier Version
1143
+ ;- -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
1144
+ ;- -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
1145
+ ;- -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
1146
+ AT91C_CAN_MTIMESTAMP EQU (0xFFFF:SHL:0) ;- (CAN_MB) Timer Value
1147
+ AT91C_CAN_MDLC EQU (0xF:SHL:16) ;- (CAN_MB) Mailbox Data Length Code
1148
+ AT91C_CAN_MRTR EQU (0x1:SHL:20) ;- (CAN_MB) Mailbox Remote Transmission Request
1149
+ AT91C_CAN_MABT EQU (0x1:SHL:22) ;- (CAN_MB) Mailbox Message Abort
1150
+ AT91C_CAN_MRDY EQU (0x1:SHL:23) ;- (CAN_MB) Mailbox Ready
1151
+ AT91C_CAN_MMI EQU (0x1:SHL:24) ;- (CAN_MB) Mailbox Message Ignored
1152
+ ;- -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
1153
+ ;- -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
1154
+ ;- -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
1155
+ AT91C_CAN_MACR EQU (0x1:SHL:22) ;- (CAN_MB) Abort Request for Mailbox
1156
+ AT91C_CAN_MTCR EQU (0x1:SHL:23) ;- (CAN_MB) Mailbox Transfer Command
1157
+
1158
+ ;- *****************************************************************************
1159
+ ;- SOFTWARE API DEFINITION FOR Control Area Network Interface
1160
+ ;- *****************************************************************************
1161
+ ^ 0 ;- AT91S_CAN
1162
+ CAN_MR # 4 ;- Mode Register
1163
+ CAN_IER # 4 ;- Interrupt Enable Register
1164
+ CAN_IDR # 4 ;- Interrupt Disable Register
1165
+ CAN_IMR # 4 ;- Interrupt Mask Register
1166
+ CAN_SR # 4 ;- Status Register
1167
+ CAN_BR # 4 ;- Baudrate Register
1168
+ CAN_TIM # 4 ;- Timer Register
1169
+ CAN_TIMESTP # 4 ;- Time Stamp Register
1170
+ CAN_ECR # 4 ;- Error Counter Register
1171
+ CAN_TCR # 4 ;- Transfer Command Register
1172
+ CAN_ACR # 4 ;- Abort Command Register
1173
+ # 208 ;- Reserved
1174
+ CAN_VR # 4 ;- Version Register
1175
+ # 256 ;- Reserved
1176
+ CAN_MB0 # 32 ;- CAN Mailbox 0
1177
+ CAN_MB1 # 32 ;- CAN Mailbox 1
1178
+ CAN_MB2 # 32 ;- CAN Mailbox 2
1179
+ CAN_MB3 # 32 ;- CAN Mailbox 3
1180
+ CAN_MB4 # 32 ;- CAN Mailbox 4
1181
+ CAN_MB5 # 32 ;- CAN Mailbox 5
1182
+ CAN_MB6 # 32 ;- CAN Mailbox 6
1183
+ CAN_MB7 # 32 ;- CAN Mailbox 7
1184
+ CAN_MB8 # 32 ;- CAN Mailbox 8
1185
+ CAN_MB9 # 32 ;- CAN Mailbox 9
1186
+ CAN_MB10 # 32 ;- CAN Mailbox 10
1187
+ CAN_MB11 # 32 ;- CAN Mailbox 11
1188
+ CAN_MB12 # 32 ;- CAN Mailbox 12
1189
+ CAN_MB13 # 32 ;- CAN Mailbox 13
1190
+ CAN_MB14 # 32 ;- CAN Mailbox 14
1191
+ CAN_MB15 # 32 ;- CAN Mailbox 15
1192
+ ;- -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
1193
+ AT91C_CAN_CANEN EQU (0x1:SHL:0) ;- (CAN) CAN Controller Enable
1194
+ AT91C_CAN_LPM EQU (0x1:SHL:1) ;- (CAN) Disable/Enable Low Power Mode
1195
+ AT91C_CAN_ABM EQU (0x1:SHL:2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
1196
+ AT91C_CAN_OVL EQU (0x1:SHL:3) ;- (CAN) Disable/Enable Overload Frame
1197
+ AT91C_CAN_TEOF EQU (0x1:SHL:4) ;- (CAN) Time Stamp messages at each end of Frame
1198
+ AT91C_CAN_TTM EQU (0x1:SHL:5) ;- (CAN) Disable/Enable Time Trigger Mode
1199
+ AT91C_CAN_TIMFRZ EQU (0x1:SHL:6) ;- (CAN) Enable Timer Freeze
1200
+ AT91C_CAN_DRPT EQU (0x1:SHL:7) ;- (CAN) Disable Repeat
1201
+ ;- -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
1202
+ AT91C_CAN_MB0 EQU (0x1:SHL:0) ;- (CAN) Mailbox 0 Flag
1203
+ AT91C_CAN_MB1 EQU (0x1:SHL:1) ;- (CAN) Mailbox 1 Flag
1204
+ AT91C_CAN_MB2 EQU (0x1:SHL:2) ;- (CAN) Mailbox 2 Flag
1205
+ AT91C_CAN_MB3 EQU (0x1:SHL:3) ;- (CAN) Mailbox 3 Flag
1206
+ AT91C_CAN_MB4 EQU (0x1:SHL:4) ;- (CAN) Mailbox 4 Flag
1207
+ AT91C_CAN_MB5 EQU (0x1:SHL:5) ;- (CAN) Mailbox 5 Flag
1208
+ AT91C_CAN_MB6 EQU (0x1:SHL:6) ;- (CAN) Mailbox 6 Flag
1209
+ AT91C_CAN_MB7 EQU (0x1:SHL:7) ;- (CAN) Mailbox 7 Flag
1210
+ AT91C_CAN_MB8 EQU (0x1:SHL:8) ;- (CAN) Mailbox 8 Flag
1211
+ AT91C_CAN_MB9 EQU (0x1:SHL:9) ;- (CAN) Mailbox 9 Flag
1212
+ AT91C_CAN_MB10 EQU (0x1:SHL:10) ;- (CAN) Mailbox 10 Flag
1213
+ AT91C_CAN_MB11 EQU (0x1:SHL:11) ;- (CAN) Mailbox 11 Flag
1214
+ AT91C_CAN_MB12 EQU (0x1:SHL:12) ;- (CAN) Mailbox 12 Flag
1215
+ AT91C_CAN_MB13 EQU (0x1:SHL:13) ;- (CAN) Mailbox 13 Flag
1216
+ AT91C_CAN_MB14 EQU (0x1:SHL:14) ;- (CAN) Mailbox 14 Flag
1217
+ AT91C_CAN_MB15 EQU (0x1:SHL:15) ;- (CAN) Mailbox 15 Flag
1218
+ AT91C_CAN_ERRA EQU (0x1:SHL:16) ;- (CAN) Error Active Mode Flag
1219
+ AT91C_CAN_WARN EQU (0x1:SHL:17) ;- (CAN) Warning Limit Flag
1220
+ AT91C_CAN_ERRP EQU (0x1:SHL:18) ;- (CAN) Error Passive Mode Flag
1221
+ AT91C_CAN_BOFF EQU (0x1:SHL:19) ;- (CAN) Bus Off Mode Flag
1222
+ AT91C_CAN_SLEEP EQU (0x1:SHL:20) ;- (CAN) Sleep Flag
1223
+ AT91C_CAN_WAKEUP EQU (0x1:SHL:21) ;- (CAN) Wakeup Flag
1224
+ AT91C_CAN_TOVF EQU (0x1:SHL:22) ;- (CAN) Timer Overflow Flag
1225
+ AT91C_CAN_TSTP EQU (0x1:SHL:23) ;- (CAN) Timestamp Flag
1226
+ AT91C_CAN_CERR EQU (0x1:SHL:24) ;- (CAN) CRC Error
1227
+ AT91C_CAN_SERR EQU (0x1:SHL:25) ;- (CAN) Stuffing Error
1228
+ AT91C_CAN_AERR EQU (0x1:SHL:26) ;- (CAN) Acknowledgment Error
1229
+ AT91C_CAN_FERR EQU (0x1:SHL:27) ;- (CAN) Form Error
1230
+ AT91C_CAN_BERR EQU (0x1:SHL:28) ;- (CAN) Bit Error
1231
+ ;- -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
1232
+ ;- -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
1233
+ ;- -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
1234
+ AT91C_CAN_RBSY EQU (0x1:SHL:29) ;- (CAN) Receiver Busy
1235
+ AT91C_CAN_TBSY EQU (0x1:SHL:30) ;- (CAN) Transmitter Busy
1236
+ AT91C_CAN_OVLY EQU (0x1:SHL:31) ;- (CAN) Overload Busy
1237
+ ;- -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
1238
+ AT91C_CAN_PHASE2 EQU (0x7:SHL:0) ;- (CAN) Phase 2 segment
1239
+ AT91C_CAN_PHASE1 EQU (0x7:SHL:4) ;- (CAN) Phase 1 segment
1240
+ AT91C_CAN_PROPAG EQU (0x7:SHL:8) ;- (CAN) Programmation time segment
1241
+ AT91C_CAN_SYNC EQU (0x3:SHL:12) ;- (CAN) Re-synchronization jump width segment
1242
+ AT91C_CAN_BRP EQU (0x7F:SHL:16) ;- (CAN) Baudrate Prescaler
1243
+ AT91C_CAN_SMP EQU (0x1:SHL:24) ;- (CAN) Sampling mode
1244
+ ;- -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
1245
+ AT91C_CAN_TIMER EQU (0xFFFF:SHL:0) ;- (CAN) Timer field
1246
+ ;- -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
1247
+ ;- -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
1248
+ AT91C_CAN_REC EQU (0xFF:SHL:0) ;- (CAN) Receive Error Counter
1249
+ AT91C_CAN_TEC EQU (0xFF:SHL:16) ;- (CAN) Transmit Error Counter
1250
+ ;- -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
1251
+ AT91C_CAN_TIMRST EQU (0x1:SHL:31) ;- (CAN) Timer Reset Field
1252
+ ;- -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
1253
+
1254
+ ;- *****************************************************************************
1255
+ ;- SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
1256
+ ;- *****************************************************************************
1257
+ ^ 0 ;- AT91S_EMAC
1258
+ EMAC_NCR # 4 ;- Network Control Register
1259
+ EMAC_NCFGR # 4 ;- Network Configuration Register
1260
+ EMAC_NSR # 4 ;- Network Status Register
1261
+ # 8 ;- Reserved
1262
+ EMAC_TSR # 4 ;- Transmit Status Register
1263
+ EMAC_RBQP # 4 ;- Receive Buffer Queue Pointer
1264
+ EMAC_TBQP # 4 ;- Transmit Buffer Queue Pointer
1265
+ EMAC_RSR # 4 ;- Receive Status Register
1266
+ EMAC_ISR # 4 ;- Interrupt Status Register
1267
+ EMAC_IER # 4 ;- Interrupt Enable Register
1268
+ EMAC_IDR # 4 ;- Interrupt Disable Register
1269
+ EMAC_IMR # 4 ;- Interrupt Mask Register
1270
+ EMAC_MAN # 4 ;- PHY Maintenance Register
1271
+ EMAC_PTR # 4 ;- Pause Time Register
1272
+ EMAC_PFR # 4 ;- Pause Frames received Register
1273
+ EMAC_FTO # 4 ;- Frames Transmitted OK Register
1274
+ EMAC_SCF # 4 ;- Single Collision Frame Register
1275
+ EMAC_MCF # 4 ;- Multiple Collision Frame Register
1276
+ EMAC_FRO # 4 ;- Frames Received OK Register
1277
+ EMAC_FCSE # 4 ;- Frame Check Sequence Error Register
1278
+ EMAC_ALE # 4 ;- Alignment Error Register
1279
+ EMAC_DTF # 4 ;- Deferred Transmission Frame Register
1280
+ EMAC_LCOL # 4 ;- Late Collision Register
1281
+ EMAC_ECOL # 4 ;- Excessive Collision Register
1282
+ EMAC_TUND # 4 ;- Transmit Underrun Error Register
1283
+ EMAC_CSE # 4 ;- Carrier Sense Error Register
1284
+ EMAC_RRE # 4 ;- Receive Ressource Error Register
1285
+ EMAC_ROV # 4 ;- Receive Overrun Errors Register
1286
+ EMAC_RSE # 4 ;- Receive Symbol Errors Register
1287
+ EMAC_ELE # 4 ;- Excessive Length Errors Register
1288
+ EMAC_RJA # 4 ;- Receive Jabbers Register
1289
+ EMAC_USF # 4 ;- Undersize Frames Register
1290
+ EMAC_STE # 4 ;- SQE Test Error Register
1291
+ EMAC_RLE # 4 ;- Receive Length Field Mismatch Register
1292
+ EMAC_TPF # 4 ;- Transmitted Pause Frames Register
1293
+ EMAC_HRB # 4 ;- Hash Address Bottom[31:0]
1294
+ EMAC_HRT # 4 ;- Hash Address Top[63:32]
1295
+ EMAC_SA1L # 4 ;- Specific Address 1 Bottom, First 4 bytes
1296
+ EMAC_SA1H # 4 ;- Specific Address 1 Top, Last 2 bytes
1297
+ EMAC_SA2L # 4 ;- Specific Address 2 Bottom, First 4 bytes
1298
+ EMAC_SA2H # 4 ;- Specific Address 2 Top, Last 2 bytes
1299
+ EMAC_SA3L # 4 ;- Specific Address 3 Bottom, First 4 bytes
1300
+ EMAC_SA3H # 4 ;- Specific Address 3 Top, Last 2 bytes
1301
+ EMAC_SA4L # 4 ;- Specific Address 4 Bottom, First 4 bytes
1302
+ EMAC_SA4H # 4 ;- Specific Address 4 Top, Last 2 bytes
1303
+ EMAC_TID # 4 ;- Type ID Checking Register
1304
+ EMAC_TPQ # 4 ;- Transmit Pause Quantum Register
1305
+ EMAC_USRIO # 4 ;- USER Input/Output Register
1306
+ EMAC_WOL # 4 ;- Wake On LAN Register
1307
+ # 52 ;- Reserved
1308
+ EMAC_REV # 4 ;- Revision Register
1309
+ ;- -------- EMAC_NCR : (EMAC Offset: 0x0) --------
1310
+ AT91C_EMAC_LB EQU (0x1:SHL:0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
1311
+ AT91C_EMAC_LLB EQU (0x1:SHL:1) ;- (EMAC) Loopback local.
1312
+ AT91C_EMAC_RE EQU (0x1:SHL:2) ;- (EMAC) Receive enable.
1313
+ AT91C_EMAC_TE EQU (0x1:SHL:3) ;- (EMAC) Transmit enable.
1314
+ AT91C_EMAC_MPE EQU (0x1:SHL:4) ;- (EMAC) Management port enable.
1315
+ AT91C_EMAC_CLRSTAT EQU (0x1:SHL:5) ;- (EMAC) Clear statistics registers.
1316
+ AT91C_EMAC_INCSTAT EQU (0x1:SHL:6) ;- (EMAC) Increment statistics registers.
1317
+ AT91C_EMAC_WESTAT EQU (0x1:SHL:7) ;- (EMAC) Write enable for statistics registers.
1318
+ AT91C_EMAC_BP EQU (0x1:SHL:8) ;- (EMAC) Back pressure.
1319
+ AT91C_EMAC_TSTART EQU (0x1:SHL:9) ;- (EMAC) Start Transmission.
1320
+ AT91C_EMAC_THALT EQU (0x1:SHL:10) ;- (EMAC) Transmission Halt.
1321
+ AT91C_EMAC_TPFR EQU (0x1:SHL:11) ;- (EMAC) Transmit pause frame
1322
+ AT91C_EMAC_TZQ EQU (0x1:SHL:12) ;- (EMAC) Transmit zero quantum pause frame
1323
+ ;- -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
1324
+ AT91C_EMAC_SPD EQU (0x1:SHL:0) ;- (EMAC) Speed.
1325
+ AT91C_EMAC_FD EQU (0x1:SHL:1) ;- (EMAC) Full duplex.
1326
+ AT91C_EMAC_JFRAME EQU (0x1:SHL:3) ;- (EMAC) Jumbo Frames.
1327
+ AT91C_EMAC_CAF EQU (0x1:SHL:4) ;- (EMAC) Copy all frames.
1328
+ AT91C_EMAC_NBC EQU (0x1:SHL:5) ;- (EMAC) No broadcast.
1329
+ AT91C_EMAC_MTI EQU (0x1:SHL:6) ;- (EMAC) Multicast hash event enable
1330
+ AT91C_EMAC_UNI EQU (0x1:SHL:7) ;- (EMAC) Unicast hash enable.
1331
+ AT91C_EMAC_BIG EQU (0x1:SHL:8) ;- (EMAC) Receive 1522 bytes.
1332
+ AT91C_EMAC_EAE EQU (0x1:SHL:9) ;- (EMAC) External address match enable.
1333
+ AT91C_EMAC_CLK EQU (0x3:SHL:10) ;- (EMAC)
1334
+ AT91C_EMAC_CLK_HCLK_8 EQU (0x0:SHL:10) ;- (EMAC) HCLK divided by 8
1335
+ AT91C_EMAC_CLK_HCLK_16 EQU (0x1:SHL:10) ;- (EMAC) HCLK divided by 16
1336
+ AT91C_EMAC_CLK_HCLK_32 EQU (0x2:SHL:10) ;- (EMAC) HCLK divided by 32
1337
+ AT91C_EMAC_CLK_HCLK_64 EQU (0x3:SHL:10) ;- (EMAC) HCLK divided by 64
1338
+ AT91C_EMAC_RTY EQU (0x1:SHL:12) ;- (EMAC)
1339
+ AT91C_EMAC_PAE EQU (0x1:SHL:13) ;- (EMAC)
1340
+ AT91C_EMAC_RBOF EQU (0x3:SHL:14) ;- (EMAC)
1341
+ AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0:SHL:14) ;- (EMAC) no offset from start of receive buffer
1342
+ AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1:SHL:14) ;- (EMAC) one byte offset from start of receive buffer
1343
+ AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2:SHL:14) ;- (EMAC) two bytes offset from start of receive buffer
1344
+ AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3:SHL:14) ;- (EMAC) three bytes offset from start of receive buffer
1345
+ AT91C_EMAC_RLCE EQU (0x1:SHL:16) ;- (EMAC) Receive Length field Checking Enable
1346
+ AT91C_EMAC_DRFCS EQU (0x1:SHL:17) ;- (EMAC) Discard Receive FCS
1347
+ AT91C_EMAC_EFRHD EQU (0x1:SHL:18) ;- (EMAC)
1348
+ AT91C_EMAC_IRXFCS EQU (0x1:SHL:19) ;- (EMAC) Ignore RX FCS
1349
+ ;- -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
1350
+ AT91C_EMAC_LINKR EQU (0x1:SHL:0) ;- (EMAC)
1351
+ AT91C_EMAC_MDIO EQU (0x1:SHL:1) ;- (EMAC)
1352
+ AT91C_EMAC_IDLE EQU (0x1:SHL:2) ;- (EMAC)
1353
+ ;- -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
1354
+ AT91C_EMAC_UBR EQU (0x1:SHL:0) ;- (EMAC)
1355
+ AT91C_EMAC_COL EQU (0x1:SHL:1) ;- (EMAC)
1356
+ AT91C_EMAC_RLES EQU (0x1:SHL:2) ;- (EMAC)
1357
+ AT91C_EMAC_TGO EQU (0x1:SHL:3) ;- (EMAC) Transmit Go
1358
+ AT91C_EMAC_BEX EQU (0x1:SHL:4) ;- (EMAC) Buffers exhausted mid frame
1359
+ AT91C_EMAC_COMP EQU (0x1:SHL:5) ;- (EMAC)
1360
+ AT91C_EMAC_UND EQU (0x1:SHL:6) ;- (EMAC)
1361
+ ;- -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
1362
+ AT91C_EMAC_BNA EQU (0x1:SHL:0) ;- (EMAC)
1363
+ AT91C_EMAC_REC EQU (0x1:SHL:1) ;- (EMAC)
1364
+ AT91C_EMAC_OVR EQU (0x1:SHL:2) ;- (EMAC)
1365
+ ;- -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
1366
+ AT91C_EMAC_MFD EQU (0x1:SHL:0) ;- (EMAC)
1367
+ AT91C_EMAC_RCOMP EQU (0x1:SHL:1) ;- (EMAC)
1368
+ AT91C_EMAC_RXUBR EQU (0x1:SHL:2) ;- (EMAC)
1369
+ AT91C_EMAC_TXUBR EQU (0x1:SHL:3) ;- (EMAC)
1370
+ AT91C_EMAC_TUNDR EQU (0x1:SHL:4) ;- (EMAC)
1371
+ AT91C_EMAC_RLEX EQU (0x1:SHL:5) ;- (EMAC)
1372
+ AT91C_EMAC_TXERR EQU (0x1:SHL:6) ;- (EMAC)
1373
+ AT91C_EMAC_TCOMP EQU (0x1:SHL:7) ;- (EMAC)
1374
+ AT91C_EMAC_LINK EQU (0x1:SHL:9) ;- (EMAC)
1375
+ AT91C_EMAC_ROVR EQU (0x1:SHL:10) ;- (EMAC)
1376
+ AT91C_EMAC_HRESP EQU (0x1:SHL:11) ;- (EMAC)
1377
+ AT91C_EMAC_PFRE EQU (0x1:SHL:12) ;- (EMAC)
1378
+ AT91C_EMAC_PTZ EQU (0x1:SHL:13) ;- (EMAC)
1379
+ ;- -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
1380
+ ;- -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
1381
+ ;- -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
1382
+ ;- -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
1383
+ AT91C_EMAC_DATA EQU (0xFFFF:SHL:0) ;- (EMAC)
1384
+ AT91C_EMAC_CODE EQU (0x3:SHL:16) ;- (EMAC)
1385
+ AT91C_EMAC_REGA EQU (0x1F:SHL:18) ;- (EMAC)
1386
+ AT91C_EMAC_PHYA EQU (0x1F:SHL:23) ;- (EMAC)
1387
+ AT91C_EMAC_RW EQU (0x3:SHL:28) ;- (EMAC)
1388
+ AT91C_EMAC_SOF EQU (0x3:SHL:30) ;- (EMAC)
1389
+ ;- -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
1390
+ AT91C_EMAC_RMII EQU (0x1:SHL:0) ;- (EMAC) Reduce MII
1391
+ AT91C_EMAC_CLKEN EQU (0x1:SHL:1) ;- (EMAC) Clock Enable
1392
+ ;- -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
1393
+ AT91C_EMAC_IP EQU (0xFFFF:SHL:0) ;- (EMAC) ARP request IP address
1394
+ AT91C_EMAC_MAG EQU (0x1:SHL:16) ;- (EMAC) Magic packet event enable
1395
+ AT91C_EMAC_ARP EQU (0x1:SHL:17) ;- (EMAC) ARP request event enable
1396
+ AT91C_EMAC_SA1 EQU (0x1:SHL:18) ;- (EMAC) Specific address register 1 event enable
1397
+ ;- -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
1398
+ AT91C_EMAC_REVREF EQU (0xFFFF:SHL:0) ;- (EMAC)
1399
+ AT91C_EMAC_PARTREF EQU (0xFFFF:SHL:16) ;- (EMAC)
1400
+
1401
+ ;- *****************************************************************************
1402
+ ;- SOFTWARE API DEFINITION FOR Analog to Digital Convertor
1403
+ ;- *****************************************************************************
1404
+ ^ 0 ;- AT91S_ADC
1405
+ ADC_CR # 4 ;- ADC Control Register
1406
+ ADC_MR # 4 ;- ADC Mode Register
1407
+ # 8 ;- Reserved
1408
+ ADC_CHER # 4 ;- ADC Channel Enable Register
1409
+ ADC_CHDR # 4 ;- ADC Channel Disable Register
1410
+ ADC_CHSR # 4 ;- ADC Channel Status Register
1411
+ ADC_SR # 4 ;- ADC Status Register
1412
+ ADC_LCDR # 4 ;- ADC Last Converted Data Register
1413
+ ADC_IER # 4 ;- ADC Interrupt Enable Register
1414
+ ADC_IDR # 4 ;- ADC Interrupt Disable Register
1415
+ ADC_IMR # 4 ;- ADC Interrupt Mask Register
1416
+ ADC_CDR0 # 4 ;- ADC Channel Data Register 0
1417
+ ADC_CDR1 # 4 ;- ADC Channel Data Register 1
1418
+ ADC_CDR2 # 4 ;- ADC Channel Data Register 2
1419
+ ADC_CDR3 # 4 ;- ADC Channel Data Register 3
1420
+ ADC_CDR4 # 4 ;- ADC Channel Data Register 4
1421
+ ADC_CDR5 # 4 ;- ADC Channel Data Register 5
1422
+ ADC_CDR6 # 4 ;- ADC Channel Data Register 6
1423
+ ADC_CDR7 # 4 ;- ADC Channel Data Register 7
1424
+ # 176 ;- Reserved
1425
+ ADC_RPR # 4 ;- Receive Pointer Register
1426
+ ADC_RCR # 4 ;- Receive Counter Register
1427
+ ADC_TPR # 4 ;- Transmit Pointer Register
1428
+ ADC_TCR # 4 ;- Transmit Counter Register
1429
+ ADC_RNPR # 4 ;- Receive Next Pointer Register
1430
+ ADC_RNCR # 4 ;- Receive Next Counter Register
1431
+ ADC_TNPR # 4 ;- Transmit Next Pointer Register
1432
+ ADC_TNCR # 4 ;- Transmit Next Counter Register
1433
+ ADC_PTCR # 4 ;- PDC Transfer Control Register
1434
+ ADC_PTSR # 4 ;- PDC Transfer Status Register
1435
+ ;- -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
1436
+ AT91C_ADC_SWRST EQU (0x1:SHL:0) ;- (ADC) Software Reset
1437
+ AT91C_ADC_START EQU (0x1:SHL:1) ;- (ADC) Start Conversion
1438
+ ;- -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
1439
+ AT91C_ADC_TRGEN EQU (0x1:SHL:0) ;- (ADC) Trigger Enable
1440
+ AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
1441
+ AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
1442
+ AT91C_ADC_TRGSEL EQU (0x7:SHL:1) ;- (ADC) Trigger Selection
1443
+ AT91C_ADC_TRGSEL_TIOA0 EQU (0x0:SHL:1) ;- (ADC) Selected TRGSEL = TIAO0
1444
+ AT91C_ADC_TRGSEL_TIOA1 EQU (0x1:SHL:1) ;- (ADC) Selected TRGSEL = TIAO1
1445
+ AT91C_ADC_TRGSEL_TIOA2 EQU (0x2:SHL:1) ;- (ADC) Selected TRGSEL = TIAO2
1446
+ AT91C_ADC_TRGSEL_TIOA3 EQU (0x3:SHL:1) ;- (ADC) Selected TRGSEL = TIAO3
1447
+ AT91C_ADC_TRGSEL_TIOA4 EQU (0x4:SHL:1) ;- (ADC) Selected TRGSEL = TIAO4
1448
+ AT91C_ADC_TRGSEL_TIOA5 EQU (0x5:SHL:1) ;- (ADC) Selected TRGSEL = TIAO5
1449
+ AT91C_ADC_TRGSEL_EXT EQU (0x6:SHL:1) ;- (ADC) Selected TRGSEL = External Trigger
1450
+ AT91C_ADC_LOWRES EQU (0x1:SHL:4) ;- (ADC) Resolution.
1451
+ AT91C_ADC_LOWRES_10_BIT EQU (0x0:SHL:4) ;- (ADC) 10-bit resolution
1452
+ AT91C_ADC_LOWRES_8_BIT EQU (0x1:SHL:4) ;- (ADC) 8-bit resolution
1453
+ AT91C_ADC_SLEEP EQU (0x1:SHL:5) ;- (ADC) Sleep Mode
1454
+ AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0:SHL:5) ;- (ADC) Normal Mode
1455
+ AT91C_ADC_SLEEP_MODE EQU (0x1:SHL:5) ;- (ADC) Sleep Mode
1456
+ AT91C_ADC_PRESCAL EQU (0x3F:SHL:8) ;- (ADC) Prescaler rate selection
1457
+ AT91C_ADC_STARTUP EQU (0x1F:SHL:16) ;- (ADC) Startup Time
1458
+ AT91C_ADC_SHTIM EQU (0xF:SHL:24) ;- (ADC) Sample & Hold Time
1459
+ ;- -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
1460
+ AT91C_ADC_CH0 EQU (0x1:SHL:0) ;- (ADC) Channel 0
1461
+ AT91C_ADC_CH1 EQU (0x1:SHL:1) ;- (ADC) Channel 1
1462
+ AT91C_ADC_CH2 EQU (0x1:SHL:2) ;- (ADC) Channel 2
1463
+ AT91C_ADC_CH3 EQU (0x1:SHL:3) ;- (ADC) Channel 3
1464
+ AT91C_ADC_CH4 EQU (0x1:SHL:4) ;- (ADC) Channel 4
1465
+ AT91C_ADC_CH5 EQU (0x1:SHL:5) ;- (ADC) Channel 5
1466
+ AT91C_ADC_CH6 EQU (0x1:SHL:6) ;- (ADC) Channel 6
1467
+ AT91C_ADC_CH7 EQU (0x1:SHL:7) ;- (ADC) Channel 7
1468
+ ;- -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
1469
+ ;- -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
1470
+ ;- -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
1471
+ AT91C_ADC_EOC0 EQU (0x1:SHL:0) ;- (ADC) End of Conversion
1472
+ AT91C_ADC_EOC1 EQU (0x1:SHL:1) ;- (ADC) End of Conversion
1473
+ AT91C_ADC_EOC2 EQU (0x1:SHL:2) ;- (ADC) End of Conversion
1474
+ AT91C_ADC_EOC3 EQU (0x1:SHL:3) ;- (ADC) End of Conversion
1475
+ AT91C_ADC_EOC4 EQU (0x1:SHL:4) ;- (ADC) End of Conversion
1476
+ AT91C_ADC_EOC5 EQU (0x1:SHL:5) ;- (ADC) End of Conversion
1477
+ AT91C_ADC_EOC6 EQU (0x1:SHL:6) ;- (ADC) End of Conversion
1478
+ AT91C_ADC_EOC7 EQU (0x1:SHL:7) ;- (ADC) End of Conversion
1479
+ AT91C_ADC_OVRE0 EQU (0x1:SHL:8) ;- (ADC) Overrun Error
1480
+ AT91C_ADC_OVRE1 EQU (0x1:SHL:9) ;- (ADC) Overrun Error
1481
+ AT91C_ADC_OVRE2 EQU (0x1:SHL:10) ;- (ADC) Overrun Error
1482
+ AT91C_ADC_OVRE3 EQU (0x1:SHL:11) ;- (ADC) Overrun Error
1483
+ AT91C_ADC_OVRE4 EQU (0x1:SHL:12) ;- (ADC) Overrun Error
1484
+ AT91C_ADC_OVRE5 EQU (0x1:SHL:13) ;- (ADC) Overrun Error
1485
+ AT91C_ADC_OVRE6 EQU (0x1:SHL:14) ;- (ADC) Overrun Error
1486
+ AT91C_ADC_OVRE7 EQU (0x1:SHL:15) ;- (ADC) Overrun Error
1487
+ AT91C_ADC_DRDY EQU (0x1:SHL:16) ;- (ADC) Data Ready
1488
+ AT91C_ADC_GOVRE EQU (0x1:SHL:17) ;- (ADC) General Overrun
1489
+ AT91C_ADC_ENDRX EQU (0x1:SHL:18) ;- (ADC) End of Receiver Transfer
1490
+ AT91C_ADC_RXBUFF EQU (0x1:SHL:19) ;- (ADC) RXBUFF Interrupt
1491
+ ;- -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
1492
+ AT91C_ADC_LDATA EQU (0x3FF:SHL:0) ;- (ADC) Last Data Converted
1493
+ ;- -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
1494
+ ;- -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
1495
+ ;- -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
1496
+ ;- -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
1497
+ AT91C_ADC_DATA EQU (0x3FF:SHL:0) ;- (ADC) Converted Data
1498
+ ;- -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
1499
+ ;- -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
1500
+ ;- -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
1501
+ ;- -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
1502
+ ;- -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
1503
+ ;- -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
1504
+ ;- -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
1505
+
1506
+ ;- *****************************************************************************
1507
+ ;- REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
1508
+ ;- *****************************************************************************
1509
+ ;- ========== Register definition for SYS peripheral ==========
1510
+ ;- ========== Register definition for AIC peripheral ==========
1511
+ AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
1512
+ AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register
1513
+ AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
1514
+ AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
1515
+ AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
1516
+ AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register
1517
+ AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
1518
+ AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
1519
+ AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
1520
+ AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
1521
+ AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
1522
+ AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
1523
+ AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
1524
+ AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
1525
+ AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
1526
+ AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
1527
+ AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
1528
+ AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
1529
+ ;- ========== Register definition for PDC_DBGU peripheral ==========
1530
+ AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
1531
+ AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
1532
+ AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
1533
+ AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
1534
+ AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
1535
+ AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
1536
+ AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
1537
+ AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
1538
+ AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
1539
+ AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
1540
+ ;- ========== Register definition for DBGU peripheral ==========
1541
+ AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
1542
+ AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
1543
+ AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
1544
+ AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
1545
+ AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
1546
+ AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register
1547
+ AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
1548
+ AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register
1549
+ AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
1550
+ AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
1551
+ AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
1552
+ AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
1553
+ ;- ========== Register definition for PIOA peripheral ==========
1554
+ AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
1555
+ AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
1556
+ AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
1557
+ AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
1558
+ AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
1559
+ AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
1560
+ AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
1561
+ AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
1562
+ AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
1563
+ AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
1564
+ AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
1565
+ AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
1566
+ AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
1567
+ AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
1568
+ AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
1569
+ AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register
1570
+ AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
1571
+ AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
1572
+ AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
1573
+ AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
1574
+ AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register
1575
+ AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register
1576
+ AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
1577
+ AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
1578
+ AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
1579
+ AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
1580
+ AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
1581
+ AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
1582
+ AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
1583
+ ;- ========== Register definition for PIOB peripheral ==========
1584
+ AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
1585
+ AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
1586
+ AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
1587
+ AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
1588
+ AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register
1589
+ AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
1590
+ AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
1591
+ AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
1592
+ AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
1593
+ AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
1594
+ AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
1595
+ AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
1596
+ AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
1597
+ AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
1598
+ AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
1599
+ AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
1600
+ AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
1601
+ AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
1602
+ AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
1603
+ AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
1604
+ AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
1605
+ AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
1606
+ AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register
1607
+ AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
1608
+ AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
1609
+ AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register
1610
+ AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
1611
+ AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
1612
+ AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
1613
+ ;- ========== Register definition for CKGR peripheral ==========
1614
+ AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
1615
+ AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
1616
+ AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register
1617
+ ;- ========== Register definition for PMC peripheral ==========
1618
+ AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
1619
+ AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
1620
+ AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register
1621
+ AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
1622
+ AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
1623
+ AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
1624
+ AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
1625
+ AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
1626
+ AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
1627
+ AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
1628
+ AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register
1629
+ AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
1630
+ AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
1631
+ AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
1632
+ AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register
1633
+ ;- ========== Register definition for RSTC peripheral ==========
1634
+ AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
1635
+ AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
1636
+ AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
1637
+ ;- ========== Register definition for RTTC peripheral ==========
1638
+ AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
1639
+ AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
1640
+ AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
1641
+ AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
1642
+ ;- ========== Register definition for PITC peripheral ==========
1643
+ AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
1644
+ AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
1645
+ AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
1646
+ AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
1647
+ ;- ========== Register definition for WDTC peripheral ==========
1648
+ AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
1649
+ AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
1650
+ AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
1651
+ ;- ========== Register definition for VREG peripheral ==========
1652
+ AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
1653
+ ;- ========== Register definition for MC peripheral ==========
1654
+ AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
1655
+ AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
1656
+ AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
1657
+ AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
1658
+ AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
1659
+ AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
1660
+ ;- ========== Register definition for PDC_SPI1 peripheral ==========
1661
+ AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
1662
+ AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
1663
+ AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
1664
+ AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
1665
+ AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
1666
+ AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
1667
+ AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
1668
+ AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
1669
+ AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
1670
+ AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
1671
+ ;- ========== Register definition for SPI1 peripheral ==========
1672
+ AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
1673
+ AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
1674
+ AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register
1675
+ AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
1676
+ AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
1677
+ AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register
1678
+ AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
1679
+ AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register
1680
+ AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
1681
+ ;- ========== Register definition for PDC_SPI0 peripheral ==========
1682
+ AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
1683
+ AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
1684
+ AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
1685
+ AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
1686
+ AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
1687
+ AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
1688
+ AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
1689
+ AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
1690
+ AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
1691
+ AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
1692
+ ;- ========== Register definition for SPI0 peripheral ==========
1693
+ AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
1694
+ AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register
1695
+ AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
1696
+ AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register
1697
+ AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register
1698
+ AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
1699
+ AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
1700
+ AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
1701
+ AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
1702
+ ;- ========== Register definition for PDC_US1 peripheral ==========
1703
+ AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
1704
+ AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
1705
+ AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
1706
+ AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
1707
+ AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
1708
+ AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
1709
+ AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
1710
+ AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
1711
+ AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
1712
+ AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
1713
+ ;- ========== Register definition for US1 peripheral ==========
1714
+ AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
1715
+ AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register
1716
+ AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
1717
+ AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register
1718
+ AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
1719
+ AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
1720
+ AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
1721
+ AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
1722
+ AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
1723
+ AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
1724
+ AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
1725
+ AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
1726
+ AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register
1727
+ AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register
1728
+ ;- ========== Register definition for PDC_US0 peripheral ==========
1729
+ AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
1730
+ AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
1731
+ AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
1732
+ AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
1733
+ AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
1734
+ AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
1735
+ AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
1736
+ AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
1737
+ AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
1738
+ AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
1739
+ ;- ========== Register definition for US0 peripheral ==========
1740
+ AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
1741
+ AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register
1742
+ AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register
1743
+ AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
1744
+ AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
1745
+ AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
1746
+ AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register
1747
+ AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
1748
+ AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register
1749
+ AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
1750
+ AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
1751
+ AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
1752
+ AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
1753
+ AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
1754
+ ;- ========== Register definition for PDC_SSC peripheral ==========
1755
+ AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
1756
+ AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
1757
+ AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
1758
+ AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
1759
+ AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
1760
+ AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
1761
+ AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
1762
+ AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
1763
+ AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
1764
+ AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
1765
+ ;- ========== Register definition for SSC peripheral ==========
1766
+ AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
1767
+ AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
1768
+ AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
1769
+ AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
1770
+ AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
1771
+ AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
1772
+ AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
1773
+ AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
1774
+ AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register
1775
+ AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
1776
+ AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
1777
+ AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register
1778
+ AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
1779
+ AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
1780
+ ;- ========== Register definition for TWI peripheral ==========
1781
+ AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
1782
+ AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register
1783
+ AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register
1784
+ AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
1785
+ AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
1786
+ AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
1787
+ AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register
1788
+ AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register
1789
+ AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
1790
+ AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
1791
+ ;- ========== Register definition for PWMC_CH3 peripheral ==========
1792
+ AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
1793
+ AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
1794
+ AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
1795
+ AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
1796
+ AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
1797
+ AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
1798
+ ;- ========== Register definition for PWMC_CH2 peripheral ==========
1799
+ AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
1800
+ AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
1801
+ AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
1802
+ AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
1803
+ AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
1804
+ AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
1805
+ ;- ========== Register definition for PWMC_CH1 peripheral ==========
1806
+ AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
1807
+ AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
1808
+ AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
1809
+ AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
1810
+ AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
1811
+ AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
1812
+ ;- ========== Register definition for PWMC_CH0 peripheral ==========
1813
+ AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
1814
+ AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
1815
+ AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
1816
+ AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
1817
+ AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
1818
+ AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
1819
+ ;- ========== Register definition for PWMC peripheral ==========
1820
+ AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
1821
+ AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
1822
+ AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
1823
+ AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
1824
+ AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
1825
+ AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
1826
+ AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
1827
+ AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
1828
+ AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
1829
+ ;- ========== Register definition for UDP peripheral ==========
1830
+ AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
1831
+ AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register
1832
+ AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register
1833
+ AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
1834
+ AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
1835
+ AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
1836
+ AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
1837
+ AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
1838
+ AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
1839
+ AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
1840
+ AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register
1841
+ AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
1842
+ ;- ========== Register definition for TC0 peripheral ==========
1843
+ AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register
1844
+ AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C
1845
+ AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B
1846
+ AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register
1847
+ AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
1848
+ AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
1849
+ AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A
1850
+ AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
1851
+ AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value
1852
+ AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
1853
+ ;- ========== Register definition for TC1 peripheral ==========
1854
+ AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B
1855
+ AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register
1856
+ AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
1857
+ AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
1858
+ AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register
1859
+ AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
1860
+ AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A
1861
+ AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C
1862
+ AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
1863
+ AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value
1864
+ ;- ========== Register definition for TC2 peripheral ==========
1865
+ AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
1866
+ AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register
1867
+ AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value
1868
+ AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A
1869
+ AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B
1870
+ AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
1871
+ AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
1872
+ AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C
1873
+ AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
1874
+ AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register
1875
+ ;- ========== Register definition for TCB peripheral ==========
1876
+ AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
1877
+ AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
1878
+ ;- ========== Register definition for CAN_MB0 peripheral ==========
1879
+ AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
1880
+ AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
1881
+ AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
1882
+ AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
1883
+ AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
1884
+ AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
1885
+ AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
1886
+ AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
1887
+ ;- ========== Register definition for CAN_MB1 peripheral ==========
1888
+ AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
1889
+ AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
1890
+ AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
1891
+ AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
1892
+ AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
1893
+ AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
1894
+ AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
1895
+ AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
1896
+ ;- ========== Register definition for CAN_MB2 peripheral ==========
1897
+ AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
1898
+ AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
1899
+ AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
1900
+ AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
1901
+ AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
1902
+ AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
1903
+ AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
1904
+ AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
1905
+ ;- ========== Register definition for CAN_MB3 peripheral ==========
1906
+ AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
1907
+ AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
1908
+ AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
1909
+ AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
1910
+ AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
1911
+ AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
1912
+ AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
1913
+ AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
1914
+ ;- ========== Register definition for CAN_MB4 peripheral ==========
1915
+ AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
1916
+ AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
1917
+ AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
1918
+ AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
1919
+ AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
1920
+ AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
1921
+ AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
1922
+ AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
1923
+ ;- ========== Register definition for CAN_MB5 peripheral ==========
1924
+ AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
1925
+ AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
1926
+ AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
1927
+ AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
1928
+ AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
1929
+ AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
1930
+ AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
1931
+ AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
1932
+ ;- ========== Register definition for CAN_MB6 peripheral ==========
1933
+ AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
1934
+ AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
1935
+ AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
1936
+ AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
1937
+ AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
1938
+ AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
1939
+ AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
1940
+ AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
1941
+ ;- ========== Register definition for CAN_MB7 peripheral ==========
1942
+ AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
1943
+ AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
1944
+ AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
1945
+ AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
1946
+ AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
1947
+ AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
1948
+ AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
1949
+ AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
1950
+ ;- ========== Register definition for CAN peripheral ==========
1951
+ AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
1952
+ AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
1953
+ AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
1954
+ AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register
1955
+ AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
1956
+ AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register
1957
+ AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
1958
+ AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register
1959
+ AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register
1960
+ AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register
1961
+ AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register
1962
+ AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register
1963
+ ;- ========== Register definition for EMAC peripheral ==========
1964
+ AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
1965
+ AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
1966
+ AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
1967
+ AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
1968
+ AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
1969
+ AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
1970
+ AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
1971
+ AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
1972
+ AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
1973
+ AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register
1974
+ AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
1975
+ AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
1976
+ AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
1977
+ AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
1978
+ AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
1979
+ AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
1980
+ AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
1981
+ AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
1982
+ AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
1983
+ AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
1984
+ AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
1985
+ AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
1986
+ AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
1987
+ AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
1988
+ AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
1989
+ AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
1990
+ AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
1991
+ AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
1992
+ AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
1993
+ AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
1994
+ AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
1995
+ AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
1996
+ AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
1997
+ AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
1998
+ AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
1999
+ AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
2000
+ AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
2001
+ AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
2002
+ AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
2003
+ AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
2004
+ AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register
2005
+ AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
2006
+ AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
2007
+ AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
2008
+ AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
2009
+ AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
2010
+ AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
2011
+ AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
2012
+ AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
2013
+ ;- ========== Register definition for PDC_ADC peripheral ==========
2014
+ AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
2015
+ AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
2016
+ AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
2017
+ AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
2018
+ AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
2019
+ AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
2020
+ AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
2021
+ AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
2022
+ AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
2023
+ AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
2024
+ ;- ========== Register definition for ADC peripheral ==========
2025
+ AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
2026
+ AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
2027
+ AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
2028
+ AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
2029
+ AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
2030
+ AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register
2031
+ AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
2032
+ AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
2033
+ AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
2034
+ AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
2035
+ AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register
2036
+ AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
2037
+ AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
2038
+ AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
2039
+ AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
2040
+ AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
2041
+ AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
2042
+ AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
2043
+
2044
+ ;- *****************************************************************************
2045
+ ;- PIO DEFINITIONS FOR AT91SAM7X256
2046
+ ;- *****************************************************************************
2047
+ AT91C_PIO_PA0 EQU (1:SHL:0) ;- Pin Controlled by PA0
2048
+ AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data
2049
+ AT91C_PIO_PA1 EQU (1:SHL:1) ;- Pin Controlled by PA1
2050
+ AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data
2051
+ AT91C_PIO_PA10 EQU (1:SHL:10) ;- Pin Controlled by PA10
2052
+ AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data
2053
+ AT91C_PIO_PA11 EQU (1:SHL:11) ;- Pin Controlled by PA11
2054
+ AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock
2055
+ AT91C_PIO_PA12 EQU (1:SHL:12) ;- Pin Controlled by PA12
2056
+ AT91C_PA12_SPI0_NPCS0 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0
2057
+ AT91C_PIO_PA13 EQU (1:SHL:13) ;- Pin Controlled by PA13
2058
+ AT91C_PA13_SPI0_NPCS1 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1
2059
+ AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1
2060
+ AT91C_PIO_PA14 EQU (1:SHL:14) ;- Pin Controlled by PA14
2061
+ AT91C_PA14_SPI0_NPCS2 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2
2062
+ AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1
2063
+ AT91C_PIO_PA15 EQU (1:SHL:15) ;- Pin Controlled by PA15
2064
+ AT91C_PA15_SPI0_NPCS3 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3
2065
+ AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input
2066
+ AT91C_PIO_PA16 EQU (1:SHL:16) ;- Pin Controlled by PA16
2067
+ AT91C_PA16_SPI0_MISO EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave
2068
+ AT91C_PIO_PA17 EQU (1:SHL:17) ;- Pin Controlled by PA17
2069
+ AT91C_PA17_SPI0_MOSI EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave
2070
+ AT91C_PIO_PA18 EQU (1:SHL:18) ;- Pin Controlled by PA18
2071
+ AT91C_PA18_SPI0_SPCK EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock
2072
+ AT91C_PIO_PA19 EQU (1:SHL:19) ;- Pin Controlled by PA19
2073
+ AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive
2074
+ AT91C_PIO_PA2 EQU (1:SHL:2) ;- Pin Controlled by PA2
2075
+ AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock
2076
+ AT91C_PA2_SPI1_NPCS1 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1
2077
+ AT91C_PIO_PA20 EQU (1:SHL:20) ;- Pin Controlled by PA20
2078
+ AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit
2079
+ AT91C_PIO_PA21 EQU (1:SHL:21) ;- Pin Controlled by PA21
2080
+ AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync
2081
+ AT91C_PA21_SPI1_NPCS0 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0
2082
+ AT91C_PIO_PA22 EQU (1:SHL:22) ;- Pin Controlled by PA22
2083
+ AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock
2084
+ AT91C_PA22_SPI1_SPCK EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock
2085
+ AT91C_PIO_PA23 EQU (1:SHL:23) ;- Pin Controlled by PA23
2086
+ AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data
2087
+ AT91C_PA23_SPI1_MOSI EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave
2088
+ AT91C_PIO_PA24 EQU (1:SHL:24) ;- Pin Controlled by PA24
2089
+ AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data
2090
+ AT91C_PA24_SPI1_MISO EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave
2091
+ AT91C_PIO_PA25 EQU (1:SHL:25) ;- Pin Controlled by PA25
2092
+ AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock
2093
+ AT91C_PA25_SPI1_NPCS1 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1
2094
+ AT91C_PIO_PA26 EQU (1:SHL:26) ;- Pin Controlled by PA26
2095
+ AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync
2096
+ AT91C_PA26_SPI1_NPCS2 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2
2097
+ AT91C_PIO_PA27 EQU (1:SHL:27) ;- Pin Controlled by PA27
2098
+ AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data
2099
+ AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3
2100
+ AT91C_PIO_PA28 EQU (1:SHL:28) ;- Pin Controlled by PA28
2101
+ AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data
2102
+ AT91C_PIO_PA29 EQU (1:SHL:29) ;- Pin Controlled by PA29
2103
+ AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input
2104
+ AT91C_PA29_SPI1_NPCS3 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3
2105
+ AT91C_PIO_PA3 EQU (1:SHL:3) ;- Pin Controlled by PA3
2106
+ AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send
2107
+ AT91C_PA3_SPI1_NPCS2 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2
2108
+ AT91C_PIO_PA30 EQU (1:SHL:30) ;- Pin Controlled by PA30
2109
+ AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0
2110
+ AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2
2111
+ AT91C_PIO_PA4 EQU (1:SHL:4) ;- Pin Controlled by PA4
2112
+ AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send
2113
+ AT91C_PA4_SPI1_NPCS3 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3
2114
+ AT91C_PIO_PA5 EQU (1:SHL:5) ;- Pin Controlled by PA5
2115
+ AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data
2116
+ AT91C_PIO_PA6 EQU (1:SHL:6) ;- Pin Controlled by PA6
2117
+ AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data
2118
+ AT91C_PIO_PA7 EQU (1:SHL:7) ;- Pin Controlled by PA7
2119
+ AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock
2120
+ AT91C_PA7_SPI0_NPCS1 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1
2121
+ AT91C_PIO_PA8 EQU (1:SHL:8) ;- Pin Controlled by PA8
2122
+ AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send
2123
+ AT91C_PA8_SPI0_NPCS2 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2
2124
+ AT91C_PIO_PA9 EQU (1:SHL:9) ;- Pin Controlled by PA9
2125
+ AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send
2126
+ AT91C_PA9_SPI0_NPCS3 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3
2127
+ AT91C_PIO_PB0 EQU (1:SHL:0) ;- Pin Controlled by PB0
2128
+ AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock
2129
+ AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0
2130
+ AT91C_PIO_PB1 EQU (1:SHL:1) ;- Pin Controlled by PB1
2131
+ AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable
2132
+ AT91C_PIO_PB10 EQU (1:SHL:10) ;- Pin Controlled by PB10
2133
+ AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2
2134
+ AT91C_PB10_SPI1_NPCS1 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1
2135
+ AT91C_PIO_PB11 EQU (1:SHL:11) ;- Pin Controlled by PB11
2136
+ AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3
2137
+ AT91C_PB11_SPI1_NPCS2 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2
2138
+ AT91C_PIO_PB12 EQU (1:SHL:12) ;- Pin Controlled by PB12
2139
+ AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error
2140
+ AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input
2141
+ AT91C_PIO_PB13 EQU (1:SHL:13) ;- Pin Controlled by PB13
2142
+ AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2
2143
+ AT91C_PB13_SPI0_NPCS1 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1
2144
+ AT91C_PIO_PB14 EQU (1:SHL:14) ;- Pin Controlled by PB14
2145
+ AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3
2146
+ AT91C_PB14_SPI0_NPCS2 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2
2147
+ AT91C_PIO_PB15 EQU (1:SHL:15) ;- Pin Controlled by PB15
2148
+ AT91C_PB15_ERXDV_ECRSDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid
2149
+ AT91C_PIO_PB16 EQU (1:SHL:16) ;- Pin Controlled by PB16
2150
+ AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected
2151
+ AT91C_PB16_SPI1_NPCS3 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3
2152
+ AT91C_PIO_PB17 EQU (1:SHL:17) ;- Pin Controlled by PB17
2153
+ AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock
2154
+ AT91C_PB17_SPI0_NPCS3 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3
2155
+ AT91C_PIO_PB18 EQU (1:SHL:18) ;- Pin Controlled by PB18
2156
+ AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec
2157
+ AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger
2158
+ AT91C_PIO_PB19 EQU (1:SHL:19) ;- Pin Controlled by PB19
2159
+ AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0
2160
+ AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input
2161
+ AT91C_PIO_PB2 EQU (1:SHL:2) ;- Pin Controlled by PB2
2162
+ AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0
2163
+ AT91C_PIO_PB20 EQU (1:SHL:20) ;- Pin Controlled by PB20
2164
+ AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1
2165
+ AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0
2166
+ AT91C_PIO_PB21 EQU (1:SHL:21) ;- Pin Controlled by PB21
2167
+ AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2
2168
+ AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1
2169
+ AT91C_PIO_PB22 EQU (1:SHL:22) ;- Pin Controlled by PB22
2170
+ AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3
2171
+ AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2
2172
+ AT91C_PIO_PB23 EQU (1:SHL:23) ;- Pin Controlled by PB23
2173
+ AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A
2174
+ AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect
2175
+ AT91C_PIO_PB24 EQU (1:SHL:24) ;- Pin Controlled by PB24
2176
+ AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B
2177
+ AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready
2178
+ AT91C_PIO_PB25 EQU (1:SHL:25) ;- Pin Controlled by PB25
2179
+ AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A
2180
+ AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready
2181
+ AT91C_PIO_PB26 EQU (1:SHL:26) ;- Pin Controlled by PB26
2182
+ AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B
2183
+ AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator
2184
+ AT91C_PIO_PB27 EQU (1:SHL:27) ;- Pin Controlled by PB27
2185
+ AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A
2186
+ AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0
2187
+ AT91C_PIO_PB28 EQU (1:SHL:28) ;- Pin Controlled by PB28
2188
+ AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B
2189
+ AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1
2190
+ AT91C_PIO_PB29 EQU (1:SHL:29) ;- Pin Controlled by PB29
2191
+ AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1
2192
+ AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2
2193
+ AT91C_PIO_PB3 EQU (1:SHL:3) ;- Pin Controlled by PB3
2194
+ AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1
2195
+ AT91C_PIO_PB30 EQU (1:SHL:30) ;- Pin Controlled by PB30
2196
+ AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2
2197
+ AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3
2198
+ AT91C_PIO_PB4 EQU (1:SHL:4) ;- Pin Controlled by PB4
2199
+ AT91C_PB4_ECRS EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
2200
+ AT91C_PIO_PB5 EQU (1:SHL:5) ;- Pin Controlled by PB5
2201
+ AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0
2202
+ AT91C_PIO_PB6 EQU (1:SHL:6) ;- Pin Controlled by PB6
2203
+ AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1
2204
+ AT91C_PIO_PB7 EQU (1:SHL:7) ;- Pin Controlled by PB7
2205
+ AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error
2206
+ AT91C_PIO_PB8 EQU (1:SHL:8) ;- Pin Controlled by PB8
2207
+ AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock
2208
+ AT91C_PIO_PB9 EQU (1:SHL:9) ;- Pin Controlled by PB9
2209
+ AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output
2210
+
2211
+ ;- *****************************************************************************
2212
+ ;- PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
2213
+ ;- *****************************************************************************
2214
+ AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
2215
+ AT91C_ID_SYS EQU ( 1) ;- System Peripheral
2216
+ AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A
2217
+ AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B
2218
+ AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0
2219
+ AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1
2220
+ AT91C_ID_US0 EQU ( 6) ;- USART 0
2221
+ AT91C_ID_US1 EQU ( 7) ;- USART 1
2222
+ AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller
2223
+ AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface
2224
+ AT91C_ID_PWMC EQU (10) ;- PWM Controller
2225
+ AT91C_ID_UDP EQU (11) ;- USB Device Port
2226
+ AT91C_ID_TC0 EQU (12) ;- Timer Counter 0
2227
+ AT91C_ID_TC1 EQU (13) ;- Timer Counter 1
2228
+ AT91C_ID_TC2 EQU (14) ;- Timer Counter 2
2229
+ AT91C_ID_CAN EQU (15) ;- Control Area Network Controller
2230
+ AT91C_ID_EMAC EQU (16) ;- Ethernet MAC
2231
+ AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter
2232
+ AT91C_ID_18_Reserved EQU (18) ;- Reserved
2233
+ AT91C_ID_19_Reserved EQU (19) ;- Reserved
2234
+ AT91C_ID_20_Reserved EQU (20) ;- Reserved
2235
+ AT91C_ID_21_Reserved EQU (21) ;- Reserved
2236
+ AT91C_ID_22_Reserved EQU (22) ;- Reserved
2237
+ AT91C_ID_23_Reserved EQU (23) ;- Reserved
2238
+ AT91C_ID_24_Reserved EQU (24) ;- Reserved
2239
+ AT91C_ID_25_Reserved EQU (25) ;- Reserved
2240
+ AT91C_ID_26_Reserved EQU (26) ;- Reserved
2241
+ AT91C_ID_27_Reserved EQU (27) ;- Reserved
2242
+ AT91C_ID_28_Reserved EQU (28) ;- Reserved
2243
+ AT91C_ID_29_Reserved EQU (29) ;- Reserved
2244
+ AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0)
2245
+ AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1)
2246
+ AT91C_ALL_INT EQU (0xC003FFFF) ;- ALL VALID INTERRUPTS
2247
+
2248
+ ;- *****************************************************************************
2249
+ ;- BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
2250
+ ;- *****************************************************************************
2251
+ AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address
2252
+ AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address
2253
+ AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
2254
+ AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address
2255
+ AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address
2256
+ AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address
2257
+ AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address
2258
+ AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address
2259
+ AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address
2260
+ AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address
2261
+ AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address
2262
+ AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address
2263
+ AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address
2264
+ AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address
2265
+ AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
2266
+ AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address
2267
+ AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
2268
+ AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address
2269
+ AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address
2270
+ AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address
2271
+ AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address
2272
+ AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address
2273
+ AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
2274
+ AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address
2275
+ AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address
2276
+ AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
2277
+ AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
2278
+ AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
2279
+ AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
2280
+ AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address
2281
+ AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address
2282
+ AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address
2283
+ AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address
2284
+ AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address
2285
+ AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address
2286
+ AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
2287
+ AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
2288
+ AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
2289
+ AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
2290
+ AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
2291
+ AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
2292
+ AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
2293
+ AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
2294
+ AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address
2295
+ AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address
2296
+ AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
2297
+ AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address
2298
+
2299
+ ;- *****************************************************************************
2300
+ ;- MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
2301
+ ;- *****************************************************************************
2302
+ ;- ISRAM
2303
+ AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address
2304
+ AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbytes)
2305
+ ;- IFLASH
2306
+ AT91C_IFLASH EQU (0x00100000) ;- Internal FLASH base address
2307
+ AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal FLASH size in byte (256 Kbytes)
2308
+ AT91C_IFLASH_PAGE_SIZE EQU (256) ;- Internal FLASH Page Size: 256 bytes
2309
+ AT91C_IFLASH_LOCK_REGION_SIZE EQU (16384) ;- Internal FLASH Lock Region Size: 16 Kbytes
2310
+ AT91C_IFLASH_NB_OF_PAGES EQU (1024) ;- Internal FLASH Number of Pages: 1024 bytes
2311
+ AT91C_IFLASH_NB_OF_LOCK_BITS EQU (16) ;- Internal FLASH Number of Lock Bits: 16 bytes
2312
+
2313
+
2314
+ END