ceedling 0.0.1

Sign up to get free protection for your applications and to get access to all the features.
Files changed (991) hide show
  1. data/.gitignore +4 -0
  2. data/.vim +1 -0
  3. data/Gemfile +3 -0
  4. data/LICENSE +19 -0
  5. data/Rakefile +18 -0
  6. data/bin/ceedling +39 -0
  7. data/ceedling.gemspec +23 -0
  8. data/lib/ceedling/version.rb +10 -0
  9. data/lib/ceedling/version.rb.erb +10 -0
  10. data/lib/ceedling.rb +5 -0
  11. data/new_project_template/build/.gitkeep +0 -0
  12. data/new_project_template/project.yml +65 -0
  13. data/new_project_template/rakefile.rb +4 -0
  14. data/new_project_template/src/.gitkeep +0 -0
  15. data/new_project_template/test/.gitkeep +0 -0
  16. data/new_project_template/test/support/.gitkeep +0 -0
  17. data/new_project_template/vendor/ceedling/config/test_environment.rb +12 -0
  18. data/new_project_template/vendor/ceedling/docs/Ceedling Packet.odt +0 -0
  19. data/new_project_template/vendor/ceedling/docs/Ceedling Packet.pdf +0 -0
  20. data/new_project_template/vendor/ceedling/docs/CeedlingLogo.png +0 -0
  21. data/new_project_template/vendor/ceedling/examples/temp_sensor/gcc.yml +42 -0
  22. data/new_project_template/vendor/ceedling/examples/temp_sensor/iar_v4.yml +91 -0
  23. data/new_project_template/vendor/ceedling/examples/temp_sensor/iar_v5.yml +80 -0
  24. data/new_project_template/vendor/ceedling/examples/temp_sensor/project.yml +65 -0
  25. data/new_project_template/vendor/ceedling/examples/temp_sensor/rakefile.rb +5 -0
  26. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcConductor.c +42 -0
  27. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcConductor.h +13 -0
  28. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardware.c +27 -0
  29. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardware.h +11 -0
  30. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardwareConfigurator.c +18 -0
  31. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardwareConfigurator.h +10 -0
  32. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcModel.c +33 -0
  33. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcModel.h +13 -0
  34. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcTemperatureSensor.c +51 -0
  35. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcTemperatureSensor.h +10 -0
  36. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Executor.c +25 -0
  37. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Executor.h +9 -0
  38. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/IntrinsicsWrapper.c +18 -0
  39. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/IntrinsicsWrapper.h +7 -0
  40. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Main.c +46 -0
  41. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Main.h +7 -0
  42. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Model.c +10 -0
  43. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Model.h +8 -0
  44. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/ModelConfig.h +7 -0
  45. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TaskScheduler.c +72 -0
  46. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TaskScheduler.h +11 -0
  47. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureCalculator.c +27 -0
  48. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureCalculator.h +8 -0
  49. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureFilter.c +39 -0
  50. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureFilter.h +10 -0
  51. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConductor.c +15 -0
  52. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConductor.h +9 -0
  53. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConfigurator.c +51 -0
  54. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConfigurator.h +15 -0
  55. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerHardware.c +15 -0
  56. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerHardware.h +8 -0
  57. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptConfigurator.c +55 -0
  58. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptConfigurator.h +13 -0
  59. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptHandler.c +25 -0
  60. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptHandler.h +10 -0
  61. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerModel.c +9 -0
  62. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerModel.h +8 -0
  63. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Types.h +90 -0
  64. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartBaudRateRegisterCalculator.c +18 -0
  65. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartBaudRateRegisterCalculator.h +8 -0
  66. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConductor.c +21 -0
  67. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConductor.h +7 -0
  68. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConfigurator.c +39 -0
  69. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConfigurator.h +13 -0
  70. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartHardware.c +22 -0
  71. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartHardware.h +9 -0
  72. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartModel.c +34 -0
  73. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartModel.h +10 -0
  74. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartPutChar.c +16 -0
  75. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartPutChar.h +8 -0
  76. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartTransmitBufferStatus.c +7 -0
  77. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartTransmitBufferStatus.h +8 -0
  78. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcConductor.c +121 -0
  79. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcHardware.c +44 -0
  80. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcModel.c +33 -0
  81. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestExecutor.c +36 -0
  82. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestMain.c +24 -0
  83. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestModel.c +20 -0
  84. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTaskScheduler.c +104 -0
  85. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTemperatureCalculator.c +33 -0
  86. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTemperatureFilter.c +69 -0
  87. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerConductor.c +32 -0
  88. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerHardware.c +26 -0
  89. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerModel.c +18 -0
  90. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartBaudRateRegisterCalculator.c +21 -0
  91. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartConductor.c +40 -0
  92. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartHardware.c +36 -0
  93. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartModel.c +40 -0
  94. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/support/UnityHelper.c +12 -0
  95. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/support/UnityHelper.h +8 -0
  96. data/new_project_template/vendor/ceedling/lib/cacheinator.rb +42 -0
  97. data/new_project_template/vendor/ceedling/lib/cacheinator_helper.rb +12 -0
  98. data/new_project_template/vendor/ceedling/lib/cmock_builder.rb +15 -0
  99. data/new_project_template/vendor/ceedling/lib/configurator.rb +254 -0
  100. data/new_project_template/vendor/ceedling/lib/configurator_builder.rb +408 -0
  101. data/new_project_template/vendor/ceedling/lib/configurator_plugins.rb +96 -0
  102. data/new_project_template/vendor/ceedling/lib/configurator_setup.rb +114 -0
  103. data/new_project_template/vendor/ceedling/lib/configurator_validator.rb +154 -0
  104. data/new_project_template/vendor/ceedling/lib/constants.rb +66 -0
  105. data/new_project_template/vendor/ceedling/lib/defaults.rb +349 -0
  106. data/new_project_template/vendor/ceedling/lib/dependinator.rb +92 -0
  107. data/new_project_template/vendor/ceedling/lib/file_finder.rb +132 -0
  108. data/new_project_template/vendor/ceedling/lib/file_finder_helper.rb +54 -0
  109. data/new_project_template/vendor/ceedling/lib/file_path_utils.rb +177 -0
  110. data/new_project_template/vendor/ceedling/lib/file_system_utils.rb +59 -0
  111. data/new_project_template/vendor/ceedling/lib/file_wrapper.rb +74 -0
  112. data/new_project_template/vendor/ceedling/lib/generator.rb +131 -0
  113. data/new_project_template/vendor/ceedling/lib/generator_test_results.rb +90 -0
  114. data/new_project_template/vendor/ceedling/lib/generator_test_results_sanity_checker.rb +62 -0
  115. data/new_project_template/vendor/ceedling/lib/generator_test_runner.rb +206 -0
  116. data/new_project_template/vendor/ceedling/lib/loginator.rb +31 -0
  117. data/new_project_template/vendor/ceedling/lib/makefile.rb +46 -0
  118. data/new_project_template/vendor/ceedling/lib/objects.yml +278 -0
  119. data/new_project_template/vendor/ceedling/lib/plugin.rb +63 -0
  120. data/new_project_template/vendor/ceedling/lib/plugin_manager.rb +85 -0
  121. data/new_project_template/vendor/ceedling/lib/plugin_manager_helper.rb +19 -0
  122. data/new_project_template/vendor/ceedling/lib/plugin_reportinator.rb +75 -0
  123. data/new_project_template/vendor/ceedling/lib/plugin_reportinator_helper.rb +52 -0
  124. data/new_project_template/vendor/ceedling/lib/preprocessinator.rb +43 -0
  125. data/new_project_template/vendor/ceedling/lib/preprocessinator_extractor.rb +27 -0
  126. data/new_project_template/vendor/ceedling/lib/preprocessinator_file_handler.rb +21 -0
  127. data/new_project_template/vendor/ceedling/lib/preprocessinator_helper.rb +46 -0
  128. data/new_project_template/vendor/ceedling/lib/preprocessinator_includes_handler.rb +55 -0
  129. data/new_project_template/vendor/ceedling/lib/project_config_manager.rb +38 -0
  130. data/new_project_template/vendor/ceedling/lib/project_file_loader.rb +64 -0
  131. data/new_project_template/vendor/ceedling/lib/rake_utils.rb +17 -0
  132. data/new_project_template/vendor/ceedling/lib/rake_wrapper.rb +31 -0
  133. data/new_project_template/vendor/ceedling/lib/rakefile.rb +60 -0
  134. data/new_project_template/vendor/ceedling/lib/release_invoker.rb +29 -0
  135. data/new_project_template/vendor/ceedling/lib/release_invoker_helper.rb +16 -0
  136. data/new_project_template/vendor/ceedling/lib/reportinator.rb +9 -0
  137. data/new_project_template/vendor/ceedling/lib/rules_cmock.rake +9 -0
  138. data/new_project_template/vendor/ceedling/lib/rules_preprocess.rake +26 -0
  139. data/new_project_template/vendor/ceedling/lib/rules_release.rake +63 -0
  140. data/new_project_template/vendor/ceedling/lib/rules_release_aux_dependencies.rake +15 -0
  141. data/new_project_template/vendor/ceedling/lib/rules_tests.rake +49 -0
  142. data/new_project_template/vendor/ceedling/lib/rules_tests_aux_dependencies.rake +15 -0
  143. data/new_project_template/vendor/ceedling/lib/setupinator.rb +45 -0
  144. data/new_project_template/vendor/ceedling/lib/stream_wrapper.rb +20 -0
  145. data/new_project_template/vendor/ceedling/lib/streaminator.rb +41 -0
  146. data/new_project_template/vendor/ceedling/lib/streaminator_helper.rb +15 -0
  147. data/new_project_template/vendor/ceedling/lib/system_wrapper.rb +67 -0
  148. data/new_project_template/vendor/ceedling/lib/task_invoker.rb +85 -0
  149. data/new_project_template/vendor/ceedling/lib/tasks_base.rake +104 -0
  150. data/new_project_template/vendor/ceedling/lib/tasks_filesystem.rake +89 -0
  151. data/new_project_template/vendor/ceedling/lib/tasks_release.rake +22 -0
  152. data/new_project_template/vendor/ceedling/lib/tasks_tests.rake +49 -0
  153. data/new_project_template/vendor/ceedling/lib/tasks_vendor.rake +36 -0
  154. data/new_project_template/vendor/ceedling/lib/test_includes_extractor.rb +81 -0
  155. data/new_project_template/vendor/ceedling/lib/test_invoker.rb +72 -0
  156. data/new_project_template/vendor/ceedling/lib/test_invoker_helper.rb +41 -0
  157. data/new_project_template/vendor/ceedling/lib/tool_executor.rb +178 -0
  158. data/new_project_template/vendor/ceedling/lib/tool_executor_helper.rb +57 -0
  159. data/new_project_template/vendor/ceedling/lib/verbosinator.rb +10 -0
  160. data/new_project_template/vendor/ceedling/lib/yaml_wrapper.rb +16 -0
  161. data/new_project_template/vendor/ceedling/plugins/stdout_ide_tests_report/stdout_ide_tests_report.rb +44 -0
  162. data/new_project_template/vendor/ceedling/plugins/stdout_ide_tests_report/stdout_ide_tests_report.yml +4 -0
  163. data/new_project_template/vendor/ceedling/plugins/stdout_pretty_tests_report/stdout_pretty_tests_report.rb +108 -0
  164. data/new_project_template/vendor/ceedling/plugins/stdout_pretty_tests_report/stdout_pretty_tests_report.yml +4 -0
  165. data/new_project_template/vendor/ceedling/plugins/xml_tests_report/xml_tests_report.rb +106 -0
  166. data/new_project_template/vendor/ceedling/rakefile.rb +59 -0
  167. data/new_project_template/vendor/ceedling/rakefile_helper.rb +23 -0
  168. data/new_project_template/vendor/ceedling/release/build.info +1 -0
  169. data/new_project_template/vendor/ceedling/release/version.info +1 -0
  170. data/new_project_template/vendor/ceedling/test/integration/paths.yml +17 -0
  171. data/new_project_template/vendor/ceedling/test/integration/paths_test.rb +80 -0
  172. data/new_project_template/vendor/ceedling/test/integration/rake_rules_aux_dependencies_test.rb +75 -0
  173. data/new_project_template/vendor/ceedling/test/integration/rake_rules_cmock_test.rb +74 -0
  174. data/new_project_template/vendor/ceedling/test/integration/rake_rules_preprocess_test.rb +178 -0
  175. data/new_project_template/vendor/ceedling/test/integration/rake_rules_test.rb +268 -0
  176. data/new_project_template/vendor/ceedling/test/integration/rake_tasks_test.rb +103 -0
  177. data/new_project_template/vendor/ceedling/test/integration_test_helper.rb +34 -0
  178. data/new_project_template/vendor/ceedling/test/rakefile_rules.rb +10 -0
  179. data/new_project_template/vendor/ceedling/test/rakefile_rules_aux_dependencies.rb +10 -0
  180. data/new_project_template/vendor/ceedling/test/rakefile_rules_cmock.rb +10 -0
  181. data/new_project_template/vendor/ceedling/test/rakefile_rules_preprocess.rb +10 -0
  182. data/new_project_template/vendor/ceedling/test/rakefile_tasks.rb +10 -0
  183. data/new_project_template/vendor/ceedling/test/system/file_system_dependencies.yml +20 -0
  184. data/new_project_template/vendor/ceedling/test/system/file_system_kitchen_sink.yml +20 -0
  185. data/new_project_template/vendor/ceedling/test/system/file_system_mocks.yml +20 -0
  186. data/new_project_template/vendor/ceedling/test/system/file_system_preprocess.yml +20 -0
  187. data/new_project_template/vendor/ceedling/test/system/file_system_simple.yml +20 -0
  188. data/new_project_template/vendor/ceedling/test/system/file_system_test.rb +78 -0
  189. data/new_project_template/vendor/ceedling/test/system/mocks/include/a_file.h +2 -0
  190. data/new_project_template/vendor/ceedling/test/system/mocks/include/other_stuff.h +2 -0
  191. data/new_project_template/vendor/ceedling/test/system/mocks/include/stuff.h +3 -0
  192. data/new_project_template/vendor/ceedling/test/system/mocks/source/a_file.c +9 -0
  193. data/new_project_template/vendor/ceedling/test/system/mocks/test/test_a_file.c +41 -0
  194. data/new_project_template/vendor/ceedling/test/system/mocks/test/test_no_file.c +14 -0
  195. data/new_project_template/vendor/ceedling/test/system/project_mocks.yml +43 -0
  196. data/new_project_template/vendor/ceedling/test/system/project_mocks_test.rb +38 -0
  197. data/new_project_template/vendor/ceedling/test/system/project_simple.yml +36 -0
  198. data/new_project_template/vendor/ceedling/test/system/project_simple_test.rb +39 -0
  199. data/new_project_template/vendor/ceedling/test/system/rule_mocks_test.rb +44 -0
  200. data/new_project_template/vendor/ceedling/test/system/rule_runners_test.rb +44 -0
  201. data/new_project_template/vendor/ceedling/test/system/simple/include/other_stuff.h +2 -0
  202. data/new_project_template/vendor/ceedling/test/system/simple/include/stuff.h +3 -0
  203. data/new_project_template/vendor/ceedling/test/system/simple/source/other_stuff.c +6 -0
  204. data/new_project_template/vendor/ceedling/test/system/simple/source/stuff.c +7 -0
  205. data/new_project_template/vendor/ceedling/test/system/simple/test/test_other_stuff.c +30 -0
  206. data/new_project_template/vendor/ceedling/test/system/simple/test/test_stuff.c +51 -0
  207. data/new_project_template/vendor/ceedling/test/system_test_helper.rb +73 -0
  208. data/new_project_template/vendor/ceedling/test/test_helper.rb +93 -0
  209. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_builder_test.rb +571 -0
  210. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_helper_test.rb +234 -0
  211. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_test.rb +232 -0
  212. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_validator_test.rb +169 -0
  213. data/new_project_template/vendor/ceedling/test/unit/busted/deep_merge_fix_test.rb +55 -0
  214. data/new_project_template/vendor/ceedling/test/unit/busted/dependinator_test.rb +129 -0
  215. data/new_project_template/vendor/ceedling/test/unit/busted/file_finder_helper_test.rb +45 -0
  216. data/new_project_template/vendor/ceedling/test/unit/busted/file_finder_test.rb +114 -0
  217. data/new_project_template/vendor/ceedling/test/unit/busted/file_path_utils_test.rb +97 -0
  218. data/new_project_template/vendor/ceedling/test/unit/busted/file_system_utils_test.rb +21 -0
  219. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test.rb +187 -0
  220. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test_results_test.rb +129 -0
  221. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test_runner_test.rb +478 -0
  222. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_extractor_test.rb +729 -0
  223. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_file_handler_test.rb +38 -0
  224. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_helper_test.rb +156 -0
  225. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_includes_handler_test.rb +93 -0
  226. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_test.rb +57 -0
  227. data/new_project_template/vendor/ceedling/test/unit/busted/project_file_loader_test.rb +142 -0
  228. data/new_project_template/vendor/ceedling/test/unit/busted/setupinator_test.rb +45 -0
  229. data/new_project_template/vendor/ceedling/test/unit/busted/streaminator_test.rb +49 -0
  230. data/new_project_template/vendor/ceedling/test/unit/busted/task_invoker_test.rb +69 -0
  231. data/new_project_template/vendor/ceedling/test/unit/busted/test_includes_extractor_test.rb +111 -0
  232. data/new_project_template/vendor/ceedling/test/unit/busted/test_invoker_helper_test.rb +62 -0
  233. data/new_project_template/vendor/ceedling/test/unit/busted/test_invoker_test.rb +47 -0
  234. data/new_project_template/vendor/ceedling/test/unit/busted/tool_executor_helper_test.rb +100 -0
  235. data/new_project_template/vendor/ceedling/test/unit/busted/tool_executor_test.rb +351 -0
  236. data/new_project_template/vendor/ceedling/test/unit/busted/verbosinator_test.rb +65 -0
  237. data/new_project_template/vendor/ceedling/test/unit_test_helper.rb +16 -0
  238. data/new_project_template/vendor/ceedling/vendor/behaviors/Manifest.txt +9 -0
  239. data/new_project_template/vendor/ceedling/vendor/behaviors/Rakefile +19 -0
  240. data/new_project_template/vendor/ceedling/vendor/behaviors/lib/behaviors/reporttask.rb +158 -0
  241. data/new_project_template/vendor/ceedling/vendor/behaviors/lib/behaviors.rb +76 -0
  242. data/new_project_template/vendor/ceedling/vendor/behaviors/test/behaviors_tasks_test.rb +73 -0
  243. data/new_project_template/vendor/ceedling/vendor/behaviors/test/behaviors_test.rb +50 -0
  244. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/Rakefile +19 -0
  245. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/lib/user.rb +2 -0
  246. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/test/user_test.rb +17 -0
  247. data/new_project_template/vendor/ceedling/vendor/c_exception/docs/CExceptionSummary.odt +0 -0
  248. data/new_project_template/vendor/ceedling/vendor/c_exception/docs/CExceptionSummary.pdf +0 -0
  249. data/new_project_template/vendor/ceedling/vendor/c_exception/docs/license.txt +30 -0
  250. data/new_project_template/vendor/ceedling/vendor/c_exception/docs/readme.txt +236 -0
  251. data/new_project_template/vendor/ceedling/vendor/c_exception/lib/CException.c +39 -0
  252. data/new_project_template/vendor/ceedling/vendor/c_exception/lib/CException.h +70 -0
  253. data/new_project_template/vendor/ceedling/vendor/c_exception/makefile +24 -0
  254. data/new_project_template/vendor/ceedling/vendor/c_exception/rakefile.rb +41 -0
  255. data/new_project_template/vendor/ceedling/vendor/c_exception/release/build.info +2 -0
  256. data/new_project_template/vendor/ceedling/vendor/c_exception/release/version.info +2 -0
  257. data/new_project_template/vendor/ceedling/vendor/c_exception/test/CExceptionConfig.h +27 -0
  258. data/new_project_template/vendor/ceedling/vendor/c_exception/test/TestException.c +291 -0
  259. data/new_project_template/vendor/ceedling/vendor/c_exception/test/TestException_Runner.c +62 -0
  260. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/auto/colour_prompt.rb +94 -0
  261. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/auto/colour_reporter.rb +39 -0
  262. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/auto/generate_config.yml +36 -0
  263. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/auto/generate_module.rb +202 -0
  264. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/auto/generate_test_runner.rb +303 -0
  265. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/auto/test_file_filter.rb +23 -0
  266. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/auto/unity_test_summary.rb +126 -0
  267. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/docs/Unity Summary.odt +0 -0
  268. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/docs/Unity Summary.pdf +0 -0
  269. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/docs/Unity Summary.txt +217 -0
  270. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/docs/license.txt +31 -0
  271. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/examples/helper/UnityHelper.c +10 -0
  272. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/examples/helper/UnityHelper.h +12 -0
  273. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/examples/makefile +40 -0
  274. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/examples/rakefile.rb +32 -0
  275. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/examples/rakefile_helper.rb +260 -0
  276. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/examples/readme.txt +18 -0
  277. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/examples/src/ProductionCode.c +24 -0
  278. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/examples/src/ProductionCode.h +3 -0
  279. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/examples/src/ProductionCode2.c +9 -0
  280. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/examples/src/ProductionCode2.h +2 -0
  281. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/examples/test/TestProductionCode.c +62 -0
  282. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/examples/test/TestProductionCode2.c +26 -0
  283. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/examples/test/no_ruby/TestProductionCode2_Runner.c +46 -0
  284. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/examples/test/no_ruby/TestProductionCode_Runner.c +50 -0
  285. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/build/MakefileWorker.mk +331 -0
  286. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/build/filterGcov.sh +61 -0
  287. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/rakefile.rb +37 -0
  288. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/rakefile_helper.rb +178 -0
  289. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/readme.txt +9 -0
  290. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/src/unity_fixture.c +381 -0
  291. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/src/unity_fixture.h +81 -0
  292. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/src/unity_fixture_internals.h +44 -0
  293. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/src/unity_fixture_malloc_overrides.h +16 -0
  294. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/test/main/AllTests.c +21 -0
  295. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/test/testunity_fixture.c +39 -0
  296. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/test/unity_fixture_Test.c +321 -0
  297. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/test/unity_fixture_TestRunner.c +40 -0
  298. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/test/unity_output_Spy.c +56 -0
  299. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/extras/fixture/test/unity_output_Spy.h +17 -0
  300. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/makefile +35 -0
  301. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/rakefile.rb +48 -0
  302. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/rakefile_helper.rb +243 -0
  303. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/release/build.info +2 -0
  304. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/release/version.info +2 -0
  305. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/src/unity.c +856 -0
  306. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/src/unity.h +213 -0
  307. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/src/unity_internals.h +355 -0
  308. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/targets/gcc.yml +42 -0
  309. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/targets/gcc_64.yml +43 -0
  310. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/targets/hitech_picc18.yml +101 -0
  311. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/targets/iar_arm_v4.yml +89 -0
  312. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/targets/iar_arm_v5.yml +79 -0
  313. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/targets/iar_arm_v5_3.yml +79 -0
  314. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/targets/iar_armcortex_LM3S9B92_v5_4.yml +93 -0
  315. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/targets/iar_cortexm3_v5.yml +83 -0
  316. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/targets/iar_msp430.yml +94 -0
  317. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/targets/iar_sh2a_v6.yml +85 -0
  318. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_cmd.c +54 -0
  319. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_def.c +50 -0
  320. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_cmd.c +76 -0
  321. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_def.c +72 -0
  322. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_new1.c +85 -0
  323. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_new2.c +85 -0
  324. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_param.c +73 -0
  325. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_run1.c +85 -0
  326. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_run2.c +85 -0
  327. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_yaml.c +86 -0
  328. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_new1.c +60 -0
  329. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_new2.c +63 -0
  330. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_param.c +51 -0
  331. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_run1.c +60 -0
  332. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_run2.c +63 -0
  333. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/expectdata/testsample_yaml.c +64 -0
  334. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/test_generate_test_runner.rb +94 -0
  335. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/testdata/mocksample.c +51 -0
  336. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/testdata/sample.yml +9 -0
  337. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/testdata/testsample.c +51 -0
  338. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/testparameterized.c +101 -0
  339. data/new_project_template/vendor/ceedling/vendor/c_exception/vendor/unity/test/testunity.c +1510 -0
  340. data/new_project_template/vendor/ceedling/vendor/cmock/config/production_environment.rb +14 -0
  341. data/new_project_template/vendor/ceedling/vendor/cmock/config/test_environment.rb +16 -0
  342. data/new_project_template/vendor/ceedling/vendor/cmock/docs/CMock Summary.odt +0 -0
  343. data/new_project_template/vendor/ceedling/vendor/cmock/docs/CMock Summary.pdf +0 -0
  344. data/new_project_template/vendor/ceedling/vendor/cmock/docs/license.txt +31 -0
  345. data/new_project_template/vendor/ceedling/vendor/cmock/examples/gcc.yml +43 -0
  346. data/new_project_template/vendor/ceedling/vendor/cmock/examples/iar_v4.yml +91 -0
  347. data/new_project_template/vendor/ceedling/vendor/cmock/examples/iar_v5.yml +80 -0
  348. data/new_project_template/vendor/ceedling/vendor/cmock/examples/rakefile.rb +32 -0
  349. data/new_project_template/vendor/ceedling/vendor/cmock/examples/rakefile_helper.rb +274 -0
  350. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/AT91SAM7X256.h +2556 -0
  351. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/AdcConductor.c +42 -0
  352. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/AdcConductor.h +11 -0
  353. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/AdcHardware.c +27 -0
  354. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/AdcHardware.h +9 -0
  355. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/AdcHardwareConfigurator.c +18 -0
  356. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/AdcHardwareConfigurator.h +10 -0
  357. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/AdcModel.c +33 -0
  358. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/AdcModel.h +13 -0
  359. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/AdcTemperatureSensor.c +51 -0
  360. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/AdcTemperatureSensor.h +10 -0
  361. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/Executor.c +25 -0
  362. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/Executor.h +9 -0
  363. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/IntrinsicsWrapper.c +18 -0
  364. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/IntrinsicsWrapper.h +7 -0
  365. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/Main.c +46 -0
  366. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/Main.h +7 -0
  367. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/Model.c +10 -0
  368. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/Model.h +8 -0
  369. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/ModelConfig.h +7 -0
  370. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TaskScheduler.c +72 -0
  371. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TaskScheduler.h +11 -0
  372. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TemperatureCalculator.c +27 -0
  373. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TemperatureCalculator.h +6 -0
  374. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TemperatureFilter.c +39 -0
  375. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TemperatureFilter.h +10 -0
  376. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TimerConductor.c +15 -0
  377. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TimerConductor.h +9 -0
  378. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TimerConfigurator.c +51 -0
  379. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TimerConfigurator.h +15 -0
  380. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TimerHardware.c +15 -0
  381. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TimerHardware.h +8 -0
  382. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TimerInterruptConfigurator.c +55 -0
  383. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TimerInterruptConfigurator.h +13 -0
  384. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TimerInterruptHandler.c +25 -0
  385. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TimerInterruptHandler.h +10 -0
  386. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TimerModel.c +9 -0
  387. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/TimerModel.h +8 -0
  388. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/Types.h +103 -0
  389. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/UsartBaudRateRegisterCalculator.c +18 -0
  390. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/UsartBaudRateRegisterCalculator.h +6 -0
  391. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/UsartConductor.c +21 -0
  392. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/UsartConductor.h +7 -0
  393. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/UsartConfigurator.c +39 -0
  394. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/UsartConfigurator.h +13 -0
  395. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/UsartHardware.c +22 -0
  396. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/UsartHardware.h +9 -0
  397. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/UsartModel.c +34 -0
  398. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/UsartModel.h +10 -0
  399. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/UsartPutChar.c +16 -0
  400. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/UsartPutChar.h +8 -0
  401. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/UsartTransmitBufferStatus.c +7 -0
  402. data/new_project_template/vendor/ceedling/vendor/cmock/examples/src/UsartTransmitBufferStatus.h +8 -0
  403. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestAdcConductor.c +121 -0
  404. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestAdcHardware.c +44 -0
  405. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestAdcHardwareConfigurator.c +43 -0
  406. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestAdcModel.c +33 -0
  407. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestAdcTemperatureSensor.c +47 -0
  408. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestExecutor.c +36 -0
  409. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestMain.c +24 -0
  410. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestModel.c +20 -0
  411. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestTaskScheduler.c +104 -0
  412. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestTemperatureCalculator.c +33 -0
  413. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestTemperatureFilter.c +69 -0
  414. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestTimerConductor.c +32 -0
  415. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestTimerConfigurator.c +112 -0
  416. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestTimerHardware.c +26 -0
  417. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestTimerInterruptConfigurator.c +78 -0
  418. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestTimerInterruptHandler.c +66 -0
  419. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestTimerModel.c +18 -0
  420. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestUsartBaudRateRegisterCalculator.c +21 -0
  421. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestUsartConductor.c +40 -0
  422. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestUsartConfigurator.c +77 -0
  423. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestUsartHardware.c +37 -0
  424. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestUsartModel.c +40 -0
  425. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestUsartPutChar.c +43 -0
  426. data/new_project_template/vendor/ceedling/vendor/cmock/examples/test/TestUsartTransmitBufferStatus.c +22 -0
  427. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/Resource/SAM7_FLASH.mac +71 -0
  428. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/Resource/SAM7_RAM.mac +94 -0
  429. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/Resource/SAM7_SIM.mac +67 -0
  430. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/Resource/at91SAM7X256_FLASH.xcl +185 -0
  431. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/Resource/at91SAM7X256_RAM.xcl +185 -0
  432. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/Resource/ioat91sam7x256.ddf +2259 -0
  433. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/cmock_demo.dep +3691 -0
  434. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/cmock_demo.ewd +1696 -0
  435. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/cmock_demo.ewp +2581 -0
  436. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/cmock_demo.eww +10 -0
  437. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/incIAR/AT91SAM7X-EK.h +61 -0
  438. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/incIAR/AT91SAM7X256.inc +2314 -0
  439. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/incIAR/AT91SAM7X256.rdf +4704 -0
  440. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/incIAR/AT91SAM7X256.tcl +3407 -0
  441. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/incIAR/AT91SAM7X256_inc.h +2268 -0
  442. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/incIAR/ioat91sam7x256.h +4380 -0
  443. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/incIAR/lib_AT91SAM7X256.h +4211 -0
  444. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/settings/cmock_demo.cspy.bat +32 -0
  445. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/settings/cmock_demo.dbgdt +86 -0
  446. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/settings/cmock_demo.dni +42 -0
  447. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/settings/cmock_demo.wsdt +76 -0
  448. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/srcIAR/Cstartup.s79 +266 -0
  449. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v4/srcIAR/Cstartup_SAM7.c +98 -0
  450. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/Resource/SAM7_FLASH.mac +71 -0
  451. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/Resource/SAM7_RAM.mac +94 -0
  452. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/Resource/SAM7_SIM.mac +67 -0
  453. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/Resource/at91SAM7X256_FLASH.icf +43 -0
  454. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/Resource/at91SAM7X256_RAM.icf +42 -0
  455. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/cmock_demo.dep +4204 -0
  456. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/cmock_demo.ewd +1906 -0
  457. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/cmock_demo.ewp +2426 -0
  458. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/cmock_demo.eww +26 -0
  459. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/incIAR/AT91SAM7X-EK.h +61 -0
  460. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/incIAR/AT91SAM7X256_inc.h +2268 -0
  461. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/incIAR/lib_AT91SAM7X256.h +4211 -0
  462. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/incIAR/project.h +30 -0
  463. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/settings/BasicInterrupt_SAM7X.cspy.bat +33 -0
  464. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/settings/BasicInterrupt_SAM7X.dbgdt +5 -0
  465. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/settings/BasicInterrupt_SAM7X.dni +18 -0
  466. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/settings/BasicInterrupt_SAM7X.wsdt +74 -0
  467. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/settings/BasicInterrupt_SAM7X_FLASH_Debug.jlink +12 -0
  468. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/settings/cmock_demo.cspy.bat +33 -0
  469. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/settings/cmock_demo.dbgdt +85 -0
  470. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/settings/cmock_demo.dni +44 -0
  471. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/settings/cmock_demo.wsdt +73 -0
  472. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/settings/cmock_demo_Binary.jlink +12 -0
  473. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/settings/cmock_demo_FLASH_Debug.jlink +12 -0
  474. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/settings/cmock_demo_RAM_Debug.jlink +12 -0
  475. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/srcIAR/Cstartup.s +299 -0
  476. data/new_project_template/vendor/ceedling/vendor/cmock/iar/iar_v5/srcIAR/Cstartup_SAM7.c +98 -0
  477. data/new_project_template/vendor/ceedling/vendor/cmock/lib/cmock.rb +65 -0
  478. data/new_project_template/vendor/ceedling/vendor/cmock/lib/cmock_config.rb +123 -0
  479. data/new_project_template/vendor/ceedling/vendor/cmock/lib/cmock_file_writer.rb +33 -0
  480. data/new_project_template/vendor/ceedling/vendor/cmock/lib/cmock_generator.rb +196 -0
  481. data/new_project_template/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_array.rb +57 -0
  482. data/new_project_template/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_callback.rb +78 -0
  483. data/new_project_template/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_cexception.rb +51 -0
  484. data/new_project_template/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect.rb +86 -0
  485. data/new_project_template/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore.rb +85 -0
  486. data/new_project_template/vendor/ceedling/vendor/cmock/lib/cmock_generator_utils.rb +177 -0
  487. data/new_project_template/vendor/ceedling/vendor/cmock/lib/cmock_header_parser.rb +270 -0
  488. data/new_project_template/vendor/ceedling/vendor/cmock/lib/cmock_plugin_manager.rb +40 -0
  489. data/new_project_template/vendor/ceedling/vendor/cmock/lib/cmock_unityhelper_parser.rb +74 -0
  490. data/new_project_template/vendor/ceedling/vendor/cmock/rakefile.rb +89 -0
  491. data/new_project_template/vendor/ceedling/vendor/cmock/rakefile_helper.rb +383 -0
  492. data/new_project_template/vendor/ceedling/vendor/cmock/release/build.info +2 -0
  493. data/new_project_template/vendor/ceedling/vendor/cmock/release/version.info +2 -0
  494. data/new_project_template/vendor/ceedling/vendor/cmock/src/cmock.c +186 -0
  495. data/new_project_template/vendor/ceedling/vendor/cmock/src/cmock.h +30 -0
  496. data/new_project_template/vendor/ceedling/vendor/cmock/targets/gcc.yml +50 -0
  497. data/new_project_template/vendor/ceedling/vendor/cmock/targets/gcc_32_with_64_support.yml +52 -0
  498. data/new_project_template/vendor/ceedling/vendor/cmock/targets/gcc_64.yml +53 -0
  499. data/new_project_template/vendor/ceedling/vendor/cmock/targets/iar_arm_v4.yml +107 -0
  500. data/new_project_template/vendor/ceedling/vendor/cmock/targets/iar_arm_v5.yml +92 -0
  501. data/new_project_template/vendor/ceedling/vendor/cmock/test/c/TestCMockC.c +280 -0
  502. data/new_project_template/vendor/ceedling/vendor/cmock/test/c/TestCMockC.yml +12 -0
  503. data/new_project_template/vendor/ceedling/vendor/cmock/test/c/TestCMockCDynamic.c +186 -0
  504. data/new_project_template/vendor/ceedling/vendor/cmock/test/c/TestCMockCDynamic.yml +12 -0
  505. data/new_project_template/vendor/ceedling/vendor/cmock/test/c/TestCMockCDynamic_Runner.c +35 -0
  506. data/new_project_template/vendor/ceedling/vendor/cmock/test/c/TestCMockC_Runner.c +37 -0
  507. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/systest_generator.rb +178 -0
  508. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_compilation/config.yml +9 -0
  509. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_compilation/const.h +15 -0
  510. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_compilation/osek.h +275 -0
  511. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_compilation/parsing.h +47 -0
  512. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/all_plugins_but_other_limits.yml +340 -0
  513. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/all_plugins_coexist.yml +381 -0
  514. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/array_and_pointer_handling.yml +382 -0
  515. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/basic_expect_and_return.yml +123 -0
  516. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/const_primitives_handling.yml +87 -0
  517. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/enforce_strict_ordering.yml +247 -0
  518. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/expect_and_return_custom_types.yml +108 -0
  519. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/expect_and_return_treat_as.yml +173 -0
  520. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/expect_and_throw.yml +170 -0
  521. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/fancy_pointer_handling.yml +208 -0
  522. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/function_pointer_handling.yml +82 -0
  523. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/ignore_and_return.yml +153 -0
  524. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/newer_standards_stuff1.yml +52 -0
  525. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/nonstandard_parsed_stuff_1.yml +91 -0
  526. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/nonstandard_parsed_stuff_2.yml +59 -0
  527. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/parsing_challenges.yml +222 -0
  528. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/struct_union_enum_expect_and_return.yml +277 -0
  529. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/stubs_with_callbacks.yml +221 -0
  530. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/unity_64bit_support.yml +82 -0
  531. data/new_project_template/vendor/ceedling/vendor/cmock/test/system/test_interactions/unity_ignores.yml +139 -0
  532. data/new_project_template/vendor/ceedling/vendor/cmock/test/test_helper.rb +44 -0
  533. data/new_project_template/vendor/ceedling/vendor/cmock/test/unit/cmock_config_test.rb +45 -0
  534. data/new_project_template/vendor/ceedling/vendor/cmock/test/unit/cmock_config_test.yml +5 -0
  535. data/new_project_template/vendor/ceedling/vendor/cmock/test/unit/cmock_file_writer_test.rb +30 -0
  536. data/new_project_template/vendor/ceedling/vendor/cmock/test/unit/cmock_generator_main_test.rb +412 -0
  537. data/new_project_template/vendor/ceedling/vendor/cmock/test/unit/cmock_generator_plugin_array_test.rb +114 -0
  538. data/new_project_template/vendor/ceedling/vendor/cmock/test/unit/cmock_generator_plugin_callback_test.rb +190 -0
  539. data/new_project_template/vendor/ceedling/vendor/cmock/test/unit/cmock_generator_plugin_cexception_test.rb +94 -0
  540. data/new_project_template/vendor/ceedling/vendor/cmock/test/unit/cmock_generator_plugin_expect_test.rb +206 -0
  541. data/new_project_template/vendor/ceedling/vendor/cmock/test/unit/cmock_generator_plugin_ignore_test.rb +159 -0
  542. data/new_project_template/vendor/ceedling/vendor/cmock/test/unit/cmock_generator_utils_test.rb +291 -0
  543. data/new_project_template/vendor/ceedling/vendor/cmock/test/unit/cmock_header_parser_test.rb +1170 -0
  544. data/new_project_template/vendor/ceedling/vendor/cmock/test/unit/cmock_plugin_manager_test.rb +85 -0
  545. data/new_project_template/vendor/ceedling/vendor/cmock/test/unit/cmock_unityhelper_parser_test.rb +223 -0
  546. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/behaviors/Manifest.txt +9 -0
  547. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/behaviors/Rakefile +19 -0
  548. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/behaviors/lib/behaviors/reporttask.rb +158 -0
  549. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/behaviors/lib/behaviors.rb +76 -0
  550. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/behaviors/test/behaviors_tasks_test.rb +73 -0
  551. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/behaviors/test/behaviors_test.rb +50 -0
  552. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/behaviors/test/tasks_test/Rakefile +19 -0
  553. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/behaviors/test/tasks_test/lib/user.rb +2 -0
  554. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/behaviors/test/tasks_test/test/user_test.rb +17 -0
  555. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/docs/CExceptionSummary.odt +0 -0
  556. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/docs/CExceptionSummary.pdf +0 -0
  557. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/docs/license.txt +30 -0
  558. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/docs/readme.txt +236 -0
  559. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/lib/CException.c +39 -0
  560. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/lib/CException.h +70 -0
  561. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/makefile +24 -0
  562. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/rakefile.rb +41 -0
  563. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/release/build.info +2 -0
  564. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/release/version.info +2 -0
  565. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/test/CExceptionConfig.h +27 -0
  566. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/test/TestException.c +291 -0
  567. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/test/TestException_Runner.c +62 -0
  568. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/auto/colour_prompt.rb +94 -0
  569. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/auto/colour_reporter.rb +39 -0
  570. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/auto/generate_config.yml +36 -0
  571. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/auto/generate_module.rb +202 -0
  572. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/auto/generate_test_runner.rb +303 -0
  573. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/auto/test_file_filter.rb +23 -0
  574. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/auto/unity_test_summary.rb +126 -0
  575. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/docs/Unity Summary.odt +0 -0
  576. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/docs/Unity Summary.pdf +0 -0
  577. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/docs/Unity Summary.txt +217 -0
  578. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/docs/license.txt +31 -0
  579. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/examples/helper/UnityHelper.c +10 -0
  580. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/examples/helper/UnityHelper.h +12 -0
  581. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/examples/makefile +40 -0
  582. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/examples/rakefile.rb +32 -0
  583. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/examples/rakefile_helper.rb +260 -0
  584. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/examples/readme.txt +18 -0
  585. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/examples/src/ProductionCode.c +24 -0
  586. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/examples/src/ProductionCode.h +3 -0
  587. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/examples/src/ProductionCode2.c +9 -0
  588. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/examples/src/ProductionCode2.h +2 -0
  589. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/examples/test/TestProductionCode.c +62 -0
  590. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/examples/test/TestProductionCode2.c +26 -0
  591. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/examples/test/no_ruby/TestProductionCode2_Runner.c +46 -0
  592. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/examples/test/no_ruby/TestProductionCode_Runner.c +50 -0
  593. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/build/MakefileWorker.mk +331 -0
  594. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/build/filterGcov.sh +61 -0
  595. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/rakefile.rb +37 -0
  596. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/rakefile_helper.rb +178 -0
  597. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/readme.txt +9 -0
  598. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/src/unity_fixture.c +381 -0
  599. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/src/unity_fixture.h +81 -0
  600. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/src/unity_fixture_internals.h +44 -0
  601. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/src/unity_fixture_malloc_overrides.h +16 -0
  602. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/test/main/AllTests.c +21 -0
  603. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/test/testunity_fixture.c +39 -0
  604. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/test/unity_fixture_Test.c +321 -0
  605. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/test/unity_fixture_TestRunner.c +40 -0
  606. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/test/unity_output_Spy.c +56 -0
  607. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/extras/fixture/test/unity_output_Spy.h +17 -0
  608. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/makefile +35 -0
  609. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/rakefile.rb +48 -0
  610. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/rakefile_helper.rb +243 -0
  611. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/release/build.info +2 -0
  612. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/release/version.info +2 -0
  613. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/src/unity.c +856 -0
  614. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/src/unity.h +213 -0
  615. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/src/unity_internals.h +355 -0
  616. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/targets/gcc.yml +42 -0
  617. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/targets/gcc_64.yml +43 -0
  618. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/targets/hitech_picc18.yml +101 -0
  619. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/targets/iar_arm_v4.yml +89 -0
  620. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/targets/iar_arm_v5.yml +79 -0
  621. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/targets/iar_arm_v5_3.yml +79 -0
  622. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/targets/iar_armcortex_LM3S9B92_v5_4.yml +93 -0
  623. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/targets/iar_cortexm3_v5.yml +83 -0
  624. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/targets/iar_msp430.yml +94 -0
  625. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/targets/iar_sh2a_v6.yml +85 -0
  626. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_cmd.c +54 -0
  627. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_def.c +50 -0
  628. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_cmd.c +76 -0
  629. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_def.c +72 -0
  630. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_new1.c +85 -0
  631. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_new2.c +85 -0
  632. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_param.c +73 -0
  633. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_run1.c +85 -0
  634. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_run2.c +85 -0
  635. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_mock_yaml.c +86 -0
  636. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_new1.c +60 -0
  637. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_new2.c +63 -0
  638. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_param.c +51 -0
  639. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_run1.c +60 -0
  640. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_run2.c +63 -0
  641. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/expectdata/testsample_yaml.c +64 -0
  642. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/test_generate_test_runner.rb +94 -0
  643. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/testdata/mocksample.c +51 -0
  644. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/testdata/sample.yml +9 -0
  645. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/testdata/testsample.c +51 -0
  646. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/testparameterized.c +101 -0
  647. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/c_exception/vendor/unity/test/testunity.c +1510 -0
  648. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/CHANGES +78 -0
  649. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/LICENSE +7 -0
  650. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/README +70 -0
  651. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/Rakefile +8 -0
  652. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/config/environment.rb +12 -0
  653. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/lib/assert_error.rb +23 -0
  654. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/lib/extend_test_unit.rb +14 -0
  655. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/lib/hardmock/errors.rb +22 -0
  656. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/lib/hardmock/expectation.rb +229 -0
  657. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/lib/hardmock/expectation_builder.rb +9 -0
  658. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/lib/hardmock/expector.rb +26 -0
  659. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/lib/hardmock/method_cleanout.rb +33 -0
  660. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/lib/hardmock/mock.rb +180 -0
  661. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/lib/hardmock/mock_control.rb +53 -0
  662. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/lib/hardmock/stubbing.rb +210 -0
  663. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/lib/hardmock/trapper.rb +31 -0
  664. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/lib/hardmock/utils.rb +9 -0
  665. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/lib/hardmock.rb +86 -0
  666. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/lib/test_unit_before_after.rb +169 -0
  667. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/rake_tasks/rdoc.rake +19 -0
  668. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/rake_tasks/rdoc_options.rb +4 -0
  669. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/rake_tasks/test.rake +22 -0
  670. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/functional/assert_error_test.rb +52 -0
  671. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/functional/auto_verify_test.rb +178 -0
  672. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/functional/direct_mock_usage_test.rb +396 -0
  673. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/functional/hardmock_test.rb +434 -0
  674. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/functional/stubbing_test.rb +479 -0
  675. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/test_helper.rb +43 -0
  676. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/unit/expectation_builder_test.rb +19 -0
  677. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/unit/expectation_test.rb +372 -0
  678. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/unit/expector_test.rb +57 -0
  679. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/unit/method_cleanout_test.rb +36 -0
  680. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/unit/mock_control_test.rb +175 -0
  681. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/unit/mock_test.rb +279 -0
  682. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/unit/test_unit_before_after_test.rb +452 -0
  683. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/unit/trapper_test.rb +62 -0
  684. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/hardmock/test/unit/verify_error_test.rb +40 -0
  685. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/auto/colour_prompt.rb +94 -0
  686. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/auto/colour_reporter.rb +39 -0
  687. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/auto/generate_config.yml +36 -0
  688. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/auto/generate_module.rb +202 -0
  689. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/auto/generate_test_runner.rb +303 -0
  690. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/auto/test_file_filter.rb +23 -0
  691. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/auto/unity_test_summary.rb +126 -0
  692. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/docs/Unity Summary.odt +0 -0
  693. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/docs/Unity Summary.pdf +0 -0
  694. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/docs/Unity Summary.txt +217 -0
  695. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/docs/license.txt +31 -0
  696. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/examples/helper/UnityHelper.c +10 -0
  697. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/examples/helper/UnityHelper.h +12 -0
  698. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/examples/makefile +40 -0
  699. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/examples/rakefile.rb +32 -0
  700. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/examples/rakefile_helper.rb +260 -0
  701. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/examples/readme.txt +18 -0
  702. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/examples/src/ProductionCode.c +24 -0
  703. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/examples/src/ProductionCode.h +3 -0
  704. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/examples/src/ProductionCode2.c +9 -0
  705. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/examples/src/ProductionCode2.h +2 -0
  706. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/examples/test/TestProductionCode.c +62 -0
  707. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/examples/test/TestProductionCode2.c +26 -0
  708. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/examples/test/no_ruby/TestProductionCode2_Runner.c +46 -0
  709. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/examples/test/no_ruby/TestProductionCode_Runner.c +50 -0
  710. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/build/MakefileWorker.mk +331 -0
  711. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/build/filterGcov.sh +61 -0
  712. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/rakefile.rb +37 -0
  713. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/rakefile_helper.rb +178 -0
  714. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/readme.txt +9 -0
  715. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/src/unity_fixture.c +381 -0
  716. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/src/unity_fixture.h +81 -0
  717. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/src/unity_fixture_internals.h +44 -0
  718. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/src/unity_fixture_malloc_overrides.h +16 -0
  719. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/test/main/AllTests.c +21 -0
  720. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/test/testunity_fixture.c +39 -0
  721. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/test/unity_fixture_Test.c +321 -0
  722. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/test/unity_fixture_TestRunner.c +40 -0
  723. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/test/unity_output_Spy.c +56 -0
  724. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/extras/fixture/test/unity_output_Spy.h +17 -0
  725. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/makefile +35 -0
  726. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/rakefile.rb +48 -0
  727. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/rakefile_helper.rb +243 -0
  728. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/release/build.info +2 -0
  729. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/release/version.info +2 -0
  730. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/src/unity.c +856 -0
  731. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/src/unity.h +213 -0
  732. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/src/unity_internals.h +355 -0
  733. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/targets/gcc.yml +42 -0
  734. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/targets/gcc_64.yml +43 -0
  735. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/targets/hitech_picc18.yml +101 -0
  736. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/targets/iar_arm_v4.yml +89 -0
  737. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/targets/iar_arm_v5.yml +79 -0
  738. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/targets/iar_arm_v5_3.yml +79 -0
  739. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/targets/iar_armcortex_LM3S9B92_v5_4.yml +93 -0
  740. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/targets/iar_cortexm3_v5.yml +83 -0
  741. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/targets/iar_msp430.yml +94 -0
  742. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/targets/iar_sh2a_v6.yml +85 -0
  743. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_cmd.c +54 -0
  744. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_def.c +50 -0
  745. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_mock_cmd.c +76 -0
  746. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_mock_def.c +72 -0
  747. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_mock_new1.c +85 -0
  748. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_mock_new2.c +85 -0
  749. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_mock_param.c +73 -0
  750. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_mock_run1.c +85 -0
  751. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_mock_run2.c +85 -0
  752. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_mock_yaml.c +86 -0
  753. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_new1.c +60 -0
  754. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_new2.c +63 -0
  755. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_param.c +51 -0
  756. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_run1.c +60 -0
  757. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_run2.c +63 -0
  758. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/expectdata/testsample_yaml.c +64 -0
  759. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/test_generate_test_runner.rb +94 -0
  760. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/testdata/mocksample.c +51 -0
  761. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/testdata/sample.yml +9 -0
  762. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/testdata/testsample.c +51 -0
  763. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/testparameterized.c +101 -0
  764. data/new_project_template/vendor/ceedling/vendor/cmock/vendor/unity/test/testunity.c +1510 -0
  765. data/new_project_template/vendor/ceedling/vendor/constructor/History.rdoc +19 -0
  766. data/new_project_template/vendor/ceedling/vendor/constructor/README.rdoc +72 -0
  767. data/new_project_template/vendor/ceedling/vendor/constructor/Rakefile +33 -0
  768. data/new_project_template/vendor/ceedling/vendor/constructor/homepage/Notes.txt +27 -0
  769. data/new_project_template/vendor/ceedling/vendor/constructor/homepage/Rakefile +15 -0
  770. data/new_project_template/vendor/ceedling/vendor/constructor/homepage/index.erb +27 -0
  771. data/new_project_template/vendor/ceedling/vendor/constructor/homepage/index.html +36 -0
  772. data/new_project_template/vendor/ceedling/vendor/constructor/homepage/page_header.graffle +0 -0
  773. data/new_project_template/vendor/ceedling/vendor/constructor/homepage/page_header.html +9 -0
  774. data/new_project_template/vendor/ceedling/vendor/constructor/homepage/page_header.png +0 -0
  775. data/new_project_template/vendor/ceedling/vendor/constructor/homepage/sample_code.png +0 -0
  776. data/new_project_template/vendor/ceedling/vendor/constructor/homepage/sample_code.rb +12 -0
  777. data/new_project_template/vendor/ceedling/vendor/constructor/lib/constructor.rb +127 -0
  778. data/new_project_template/vendor/ceedling/vendor/constructor/lib/constructor_struct.rb +33 -0
  779. data/new_project_template/vendor/ceedling/vendor/constructor/specs/constructor_spec.rb +407 -0
  780. data/new_project_template/vendor/ceedling/vendor/constructor/specs/constructor_struct_spec.rb +84 -0
  781. data/new_project_template/vendor/ceedling/vendor/deep_merge/MIT-LICENSE +20 -0
  782. data/new_project_template/vendor/ceedling/vendor/deep_merge/README +94 -0
  783. data/new_project_template/vendor/ceedling/vendor/deep_merge/Rakefile +28 -0
  784. data/new_project_template/vendor/ceedling/vendor/deep_merge/lib/deep_merge.rb +211 -0
  785. data/new_project_template/vendor/ceedling/vendor/deep_merge/test/test_deep_merge.rb +553 -0
  786. data/new_project_template/vendor/ceedling/vendor/diy/History.txt +28 -0
  787. data/new_project_template/vendor/ceedling/vendor/diy/README.rdoc +233 -0
  788. data/new_project_template/vendor/ceedling/vendor/diy/Rakefile +33 -0
  789. data/new_project_template/vendor/ceedling/vendor/diy/TODO.txt +9 -0
  790. data/new_project_template/vendor/ceedling/vendor/diy/diy.gemspec +131 -0
  791. data/new_project_template/vendor/ceedling/vendor/diy/lib/diy/factory.rb +36 -0
  792. data/new_project_template/vendor/ceedling/vendor/diy/lib/diy.rb +403 -0
  793. data/new_project_template/vendor/ceedling/vendor/diy/sample_code/car.rb +7 -0
  794. data/new_project_template/vendor/ceedling/vendor/diy/sample_code/chassis.rb +5 -0
  795. data/new_project_template/vendor/ceedling/vendor/diy/sample_code/diy_example.rb +26 -0
  796. data/new_project_template/vendor/ceedling/vendor/diy/sample_code/engine.rb +5 -0
  797. data/new_project_template/vendor/ceedling/vendor/diy/sample_code/objects.yml +10 -0
  798. data/new_project_template/vendor/ceedling/vendor/diy/test/constructor.rb +119 -0
  799. data/new_project_template/vendor/ceedling/vendor/diy/test/diy_test.rb +608 -0
  800. data/new_project_template/vendor/ceedling/vendor/diy/test/factory_test.rb +79 -0
  801. data/new_project_template/vendor/ceedling/vendor/diy/test/files/broken_construction.yml +7 -0
  802. data/new_project_template/vendor/ceedling/vendor/diy/test/files/cat/cat.rb +3 -0
  803. data/new_project_template/vendor/ceedling/vendor/diy/test/files/cat/extra_conflict.yml +5 -0
  804. data/new_project_template/vendor/ceedling/vendor/diy/test/files/cat/heritage.rb +2 -0
  805. data/new_project_template/vendor/ceedling/vendor/diy/test/files/cat/needs_input.yml +3 -0
  806. data/new_project_template/vendor/ceedling/vendor/diy/test/files/cat/the_cat_lineage.rb +1 -0
  807. data/new_project_template/vendor/ceedling/vendor/diy/test/files/dog/dog_model.rb +3 -0
  808. data/new_project_template/vendor/ceedling/vendor/diy/test/files/dog/dog_presenter.rb +3 -0
  809. data/new_project_template/vendor/ceedling/vendor/diy/test/files/dog/dog_view.rb +2 -0
  810. data/new_project_template/vendor/ceedling/vendor/diy/test/files/dog/file_resolver.rb +2 -0
  811. data/new_project_template/vendor/ceedling/vendor/diy/test/files/dog/other_thing.rb +2 -0
  812. data/new_project_template/vendor/ceedling/vendor/diy/test/files/dog/simple.yml +11 -0
  813. data/new_project_template/vendor/ceedling/vendor/diy/test/files/donkey/foo/bar/qux.rb +7 -0
  814. data/new_project_template/vendor/ceedling/vendor/diy/test/files/donkey/foo.rb +8 -0
  815. data/new_project_template/vendor/ceedling/vendor/diy/test/files/factory/beef.rb +5 -0
  816. data/new_project_template/vendor/ceedling/vendor/diy/test/files/factory/dog.rb +6 -0
  817. data/new_project_template/vendor/ceedling/vendor/diy/test/files/factory/factory.yml +19 -0
  818. data/new_project_template/vendor/ceedling/vendor/diy/test/files/factory/farm/llama.rb +7 -0
  819. data/new_project_template/vendor/ceedling/vendor/diy/test/files/factory/farm/pork.rb +7 -0
  820. data/new_project_template/vendor/ceedling/vendor/diy/test/files/factory/kitten.rb +13 -0
  821. data/new_project_template/vendor/ceedling/vendor/diy/test/files/fud/objects.yml +13 -0
  822. data/new_project_template/vendor/ceedling/vendor/diy/test/files/fud/toy.rb +14 -0
  823. data/new_project_template/vendor/ceedling/vendor/diy/test/files/functions/attached_things_builder.rb +2 -0
  824. data/new_project_template/vendor/ceedling/vendor/diy/test/files/functions/invalid_method.yml +5 -0
  825. data/new_project_template/vendor/ceedling/vendor/diy/test/files/functions/method_extractor.rb +3 -0
  826. data/new_project_template/vendor/ceedling/vendor/diy/test/files/functions/nonsingleton_objects.yml +6 -0
  827. data/new_project_template/vendor/ceedling/vendor/diy/test/files/functions/objects.yml +22 -0
  828. data/new_project_template/vendor/ceedling/vendor/diy/test/files/functions/thing.rb +3 -0
  829. data/new_project_template/vendor/ceedling/vendor/diy/test/files/functions/thing_builder.rb +25 -0
  830. data/new_project_template/vendor/ceedling/vendor/diy/test/files/functions/things_builder.rb +3 -0
  831. data/new_project_template/vendor/ceedling/vendor/diy/test/files/gnu/objects.yml +14 -0
  832. data/new_project_template/vendor/ceedling/vendor/diy/test/files/gnu/thinger.rb +7 -0
  833. data/new_project_template/vendor/ceedling/vendor/diy/test/files/goat/base.rb +8 -0
  834. data/new_project_template/vendor/ceedling/vendor/diy/test/files/goat/can.rb +6 -0
  835. data/new_project_template/vendor/ceedling/vendor/diy/test/files/goat/goat.rb +6 -0
  836. data/new_project_template/vendor/ceedling/vendor/diy/test/files/goat/objects.yml +12 -0
  837. data/new_project_template/vendor/ceedling/vendor/diy/test/files/goat/paper.rb +6 -0
  838. data/new_project_template/vendor/ceedling/vendor/diy/test/files/goat/plane.rb +7 -0
  839. data/new_project_template/vendor/ceedling/vendor/diy/test/files/goat/shirt.rb +6 -0
  840. data/new_project_template/vendor/ceedling/vendor/diy/test/files/goat/wings.rb +8 -0
  841. data/new_project_template/vendor/ceedling/vendor/diy/test/files/horse/holder_thing.rb +3 -0
  842. data/new_project_template/vendor/ceedling/vendor/diy/test/files/horse/objects.yml +7 -0
  843. data/new_project_template/vendor/ceedling/vendor/diy/test/files/namespace/animal/bird.rb +5 -0
  844. data/new_project_template/vendor/ceedling/vendor/diy/test/files/namespace/animal/cat.rb +5 -0
  845. data/new_project_template/vendor/ceedling/vendor/diy/test/files/namespace/animal/reptile/hardshell/turtle.rb +8 -0
  846. data/new_project_template/vendor/ceedling/vendor/diy/test/files/namespace/animal/reptile/lizard.rb +7 -0
  847. data/new_project_template/vendor/ceedling/vendor/diy/test/files/namespace/bad_module_specified.yml +8 -0
  848. data/new_project_template/vendor/ceedling/vendor/diy/test/files/namespace/class_name_combine.yml +8 -0
  849. data/new_project_template/vendor/ceedling/vendor/diy/test/files/namespace/hello.txt +1 -0
  850. data/new_project_template/vendor/ceedling/vendor/diy/test/files/namespace/no_module_specified.yml +8 -0
  851. data/new_project_template/vendor/ceedling/vendor/diy/test/files/namespace/objects.yml +21 -0
  852. data/new_project_template/vendor/ceedling/vendor/diy/test/files/namespace/road.rb +2 -0
  853. data/new_project_template/vendor/ceedling/vendor/diy/test/files/namespace/sky.rb +2 -0
  854. data/new_project_template/vendor/ceedling/vendor/diy/test/files/namespace/subcontext.yml +22 -0
  855. data/new_project_template/vendor/ceedling/vendor/diy/test/files/non_singleton/air.rb +2 -0
  856. data/new_project_template/vendor/ceedling/vendor/diy/test/files/non_singleton/fat_cat.rb +3 -0
  857. data/new_project_template/vendor/ceedling/vendor/diy/test/files/non_singleton/objects.yml +19 -0
  858. data/new_project_template/vendor/ceedling/vendor/diy/test/files/non_singleton/pig.rb +3 -0
  859. data/new_project_template/vendor/ceedling/vendor/diy/test/files/non_singleton/thread_spinner.rb +3 -0
  860. data/new_project_template/vendor/ceedling/vendor/diy/test/files/non_singleton/tick.rb +3 -0
  861. data/new_project_template/vendor/ceedling/vendor/diy/test/files/non_singleton/yard.rb +2 -0
  862. data/new_project_template/vendor/ceedling/vendor/diy/test/files/yak/core_model.rb +3 -0
  863. data/new_project_template/vendor/ceedling/vendor/diy/test/files/yak/core_presenter.rb +3 -0
  864. data/new_project_template/vendor/ceedling/vendor/diy/test/files/yak/core_view.rb +1 -0
  865. data/new_project_template/vendor/ceedling/vendor/diy/test/files/yak/data_source.rb +1 -0
  866. data/new_project_template/vendor/ceedling/vendor/diy/test/files/yak/fringe_model.rb +3 -0
  867. data/new_project_template/vendor/ceedling/vendor/diy/test/files/yak/fringe_presenter.rb +3 -0
  868. data/new_project_template/vendor/ceedling/vendor/diy/test/files/yak/fringe_view.rb +1 -0
  869. data/new_project_template/vendor/ceedling/vendor/diy/test/files/yak/giant_squid.rb +3 -0
  870. data/new_project_template/vendor/ceedling/vendor/diy/test/files/yak/krill.rb +2 -0
  871. data/new_project_template/vendor/ceedling/vendor/diy/test/files/yak/my_objects.yml +21 -0
  872. data/new_project_template/vendor/ceedling/vendor/diy/test/files/yak/sub_sub_context_test.yml +27 -0
  873. data/new_project_template/vendor/ceedling/vendor/diy/test/test_helper.rb +55 -0
  874. data/new_project_template/vendor/ceedling/vendor/hardmock/CHANGES +78 -0
  875. data/new_project_template/vendor/ceedling/vendor/hardmock/LICENSE +7 -0
  876. data/new_project_template/vendor/ceedling/vendor/hardmock/README +70 -0
  877. data/new_project_template/vendor/ceedling/vendor/hardmock/Rakefile +8 -0
  878. data/new_project_template/vendor/ceedling/vendor/hardmock/config/environment.rb +12 -0
  879. data/new_project_template/vendor/ceedling/vendor/hardmock/lib/assert_error.rb +23 -0
  880. data/new_project_template/vendor/ceedling/vendor/hardmock/lib/extend_test_unit.rb +14 -0
  881. data/new_project_template/vendor/ceedling/vendor/hardmock/lib/hardmock/errors.rb +22 -0
  882. data/new_project_template/vendor/ceedling/vendor/hardmock/lib/hardmock/expectation.rb +229 -0
  883. data/new_project_template/vendor/ceedling/vendor/hardmock/lib/hardmock/expectation_builder.rb +9 -0
  884. data/new_project_template/vendor/ceedling/vendor/hardmock/lib/hardmock/expector.rb +26 -0
  885. data/new_project_template/vendor/ceedling/vendor/hardmock/lib/hardmock/method_cleanout.rb +33 -0
  886. data/new_project_template/vendor/ceedling/vendor/hardmock/lib/hardmock/mock.rb +180 -0
  887. data/new_project_template/vendor/ceedling/vendor/hardmock/lib/hardmock/mock_control.rb +53 -0
  888. data/new_project_template/vendor/ceedling/vendor/hardmock/lib/hardmock/stubbing.rb +210 -0
  889. data/new_project_template/vendor/ceedling/vendor/hardmock/lib/hardmock/trapper.rb +31 -0
  890. data/new_project_template/vendor/ceedling/vendor/hardmock/lib/hardmock/utils.rb +9 -0
  891. data/new_project_template/vendor/ceedling/vendor/hardmock/lib/hardmock.rb +86 -0
  892. data/new_project_template/vendor/ceedling/vendor/hardmock/lib/test_unit_before_after.rb +169 -0
  893. data/new_project_template/vendor/ceedling/vendor/hardmock/rake_tasks/rdoc.rake +19 -0
  894. data/new_project_template/vendor/ceedling/vendor/hardmock/rake_tasks/rdoc_options.rb +4 -0
  895. data/new_project_template/vendor/ceedling/vendor/hardmock/rake_tasks/test.rake +22 -0
  896. data/new_project_template/vendor/ceedling/vendor/hardmock/test/functional/assert_error_test.rb +52 -0
  897. data/new_project_template/vendor/ceedling/vendor/hardmock/test/functional/auto_verify_test.rb +178 -0
  898. data/new_project_template/vendor/ceedling/vendor/hardmock/test/functional/direct_mock_usage_test.rb +396 -0
  899. data/new_project_template/vendor/ceedling/vendor/hardmock/test/functional/hardmock_test.rb +434 -0
  900. data/new_project_template/vendor/ceedling/vendor/hardmock/test/functional/stubbing_test.rb +479 -0
  901. data/new_project_template/vendor/ceedling/vendor/hardmock/test/test_helper.rb +43 -0
  902. data/new_project_template/vendor/ceedling/vendor/hardmock/test/unit/expectation_builder_test.rb +19 -0
  903. data/new_project_template/vendor/ceedling/vendor/hardmock/test/unit/expectation_test.rb +372 -0
  904. data/new_project_template/vendor/ceedling/vendor/hardmock/test/unit/expector_test.rb +57 -0
  905. data/new_project_template/vendor/ceedling/vendor/hardmock/test/unit/method_cleanout_test.rb +36 -0
  906. data/new_project_template/vendor/ceedling/vendor/hardmock/test/unit/mock_control_test.rb +175 -0
  907. data/new_project_template/vendor/ceedling/vendor/hardmock/test/unit/mock_test.rb +279 -0
  908. data/new_project_template/vendor/ceedling/vendor/hardmock/test/unit/test_unit_before_after_test.rb +452 -0
  909. data/new_project_template/vendor/ceedling/vendor/hardmock/test/unit/trapper_test.rb +62 -0
  910. data/new_project_template/vendor/ceedling/vendor/hardmock/test/unit/verify_error_test.rb +40 -0
  911. data/new_project_template/vendor/ceedling/vendor/unity/auto/colour_prompt.rb +94 -0
  912. data/new_project_template/vendor/ceedling/vendor/unity/auto/colour_reporter.rb +39 -0
  913. data/new_project_template/vendor/ceedling/vendor/unity/auto/generate_config.yml +36 -0
  914. data/new_project_template/vendor/ceedling/vendor/unity/auto/generate_module.rb +202 -0
  915. data/new_project_template/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb +303 -0
  916. data/new_project_template/vendor/ceedling/vendor/unity/auto/test_file_filter.rb +23 -0
  917. data/new_project_template/vendor/ceedling/vendor/unity/auto/unity_test_summary.rb +126 -0
  918. data/new_project_template/vendor/ceedling/vendor/unity/docs/Unity Summary.odt +0 -0
  919. data/new_project_template/vendor/ceedling/vendor/unity/docs/Unity Summary.pdf +0 -0
  920. data/new_project_template/vendor/ceedling/vendor/unity/docs/Unity Summary.txt +217 -0
  921. data/new_project_template/vendor/ceedling/vendor/unity/docs/license.txt +31 -0
  922. data/new_project_template/vendor/ceedling/vendor/unity/examples/helper/UnityHelper.c +10 -0
  923. data/new_project_template/vendor/ceedling/vendor/unity/examples/helper/UnityHelper.h +12 -0
  924. data/new_project_template/vendor/ceedling/vendor/unity/examples/makefile +40 -0
  925. data/new_project_template/vendor/ceedling/vendor/unity/examples/rakefile.rb +32 -0
  926. data/new_project_template/vendor/ceedling/vendor/unity/examples/rakefile_helper.rb +260 -0
  927. data/new_project_template/vendor/ceedling/vendor/unity/examples/readme.txt +18 -0
  928. data/new_project_template/vendor/ceedling/vendor/unity/examples/src/ProductionCode.c +24 -0
  929. data/new_project_template/vendor/ceedling/vendor/unity/examples/src/ProductionCode.h +3 -0
  930. data/new_project_template/vendor/ceedling/vendor/unity/examples/src/ProductionCode2.c +9 -0
  931. data/new_project_template/vendor/ceedling/vendor/unity/examples/src/ProductionCode2.h +2 -0
  932. data/new_project_template/vendor/ceedling/vendor/unity/examples/test/TestProductionCode.c +62 -0
  933. data/new_project_template/vendor/ceedling/vendor/unity/examples/test/TestProductionCode2.c +26 -0
  934. data/new_project_template/vendor/ceedling/vendor/unity/examples/test/no_ruby/TestProductionCode2_Runner.c +46 -0
  935. data/new_project_template/vendor/ceedling/vendor/unity/examples/test/no_ruby/TestProductionCode_Runner.c +50 -0
  936. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/build/MakefileWorker.mk +331 -0
  937. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/build/filterGcov.sh +61 -0
  938. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/rakefile.rb +37 -0
  939. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/rakefile_helper.rb +178 -0
  940. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/readme.txt +9 -0
  941. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/src/unity_fixture.c +381 -0
  942. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/src/unity_fixture.h +81 -0
  943. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/src/unity_fixture_internals.h +44 -0
  944. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/src/unity_fixture_malloc_overrides.h +16 -0
  945. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/test/main/AllTests.c +21 -0
  946. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/test/testunity_fixture.c +39 -0
  947. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/test/unity_fixture_Test.c +321 -0
  948. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/test/unity_fixture_TestRunner.c +40 -0
  949. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/test/unity_output_Spy.c +56 -0
  950. data/new_project_template/vendor/ceedling/vendor/unity/extras/fixture/test/unity_output_Spy.h +17 -0
  951. data/new_project_template/vendor/ceedling/vendor/unity/makefile +35 -0
  952. data/new_project_template/vendor/ceedling/vendor/unity/rakefile.rb +48 -0
  953. data/new_project_template/vendor/ceedling/vendor/unity/rakefile_helper.rb +243 -0
  954. data/new_project_template/vendor/ceedling/vendor/unity/release/build.info +2 -0
  955. data/new_project_template/vendor/ceedling/vendor/unity/release/version.info +2 -0
  956. data/new_project_template/vendor/ceedling/vendor/unity/src/unity.c +856 -0
  957. data/new_project_template/vendor/ceedling/vendor/unity/src/unity.h +213 -0
  958. data/new_project_template/vendor/ceedling/vendor/unity/src/unity_internals.h +355 -0
  959. data/new_project_template/vendor/ceedling/vendor/unity/targets/gcc.yml +42 -0
  960. data/new_project_template/vendor/ceedling/vendor/unity/targets/gcc_64.yml +43 -0
  961. data/new_project_template/vendor/ceedling/vendor/unity/targets/hitech_picc18.yml +101 -0
  962. data/new_project_template/vendor/ceedling/vendor/unity/targets/iar_arm_v4.yml +89 -0
  963. data/new_project_template/vendor/ceedling/vendor/unity/targets/iar_arm_v5.yml +79 -0
  964. data/new_project_template/vendor/ceedling/vendor/unity/targets/iar_arm_v5_3.yml +79 -0
  965. data/new_project_template/vendor/ceedling/vendor/unity/targets/iar_armcortex_LM3S9B92_v5_4.yml +93 -0
  966. data/new_project_template/vendor/ceedling/vendor/unity/targets/iar_cortexm3_v5.yml +83 -0
  967. data/new_project_template/vendor/ceedling/vendor/unity/targets/iar_msp430.yml +94 -0
  968. data/new_project_template/vendor/ceedling/vendor/unity/targets/iar_sh2a_v6.yml +85 -0
  969. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_cmd.c +54 -0
  970. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_def.c +50 -0
  971. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_mock_cmd.c +76 -0
  972. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_mock_def.c +72 -0
  973. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_mock_new1.c +85 -0
  974. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_mock_new2.c +85 -0
  975. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_mock_param.c +73 -0
  976. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_mock_run1.c +85 -0
  977. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_mock_run2.c +85 -0
  978. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_mock_yaml.c +86 -0
  979. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_new1.c +60 -0
  980. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_new2.c +63 -0
  981. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_param.c +51 -0
  982. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_run1.c +60 -0
  983. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_run2.c +63 -0
  984. data/new_project_template/vendor/ceedling/vendor/unity/test/expectdata/testsample_yaml.c +64 -0
  985. data/new_project_template/vendor/ceedling/vendor/unity/test/test_generate_test_runner.rb +94 -0
  986. data/new_project_template/vendor/ceedling/vendor/unity/test/testdata/mocksample.c +51 -0
  987. data/new_project_template/vendor/ceedling/vendor/unity/test/testdata/sample.yml +9 -0
  988. data/new_project_template/vendor/ceedling/vendor/unity/test/testdata/testsample.c +51 -0
  989. data/new_project_template/vendor/ceedling/vendor/unity/test/testparameterized.c +101 -0
  990. data/new_project_template/vendor/ceedling/vendor/unity/test/testunity.c +1510 -0
  991. metadata +1058 -0
@@ -0,0 +1,4380 @@
1
+ // - ----------------------------------------------------------------------------
2
+ // - ATMEL Microcontroller Software Support - ROUSSET -
3
+ // - ----------------------------------------------------------------------------
4
+ // - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
5
+ // - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6
+ // - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
7
+ // - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
8
+ // - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
9
+ // - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
10
+ // - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
11
+ // - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
12
+ // - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
13
+ // - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
14
+ // - ----------------------------------------------------------------------------
15
+ // - File Name : AT91SAM7X256.h
16
+ // - Object : AT91SAM7X256 definitions
17
+ // - Generated : AT91 SW Application Group 11/02/2005 (15:17:24)
18
+ // -
19
+ // - CVS Reference : /AT91SAM7X256.pl/1.14/Tue Sep 13 15:06:52 2005//
20
+ // - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
21
+ // - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
22
+ // - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
23
+ // - CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 14:57:50 2005//
24
+ // - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
25
+ // - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
26
+ // - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
27
+ // - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
28
+ // - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
29
+ // - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
30
+ // - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
31
+ // - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
32
+ // - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
33
+ // - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
34
+ // - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
35
+ // - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
36
+ // - CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:19:19 2005//
37
+ // - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
38
+ // - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
39
+ // - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
40
+ // - CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:05:35 2005//
41
+ // - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
42
+ // - ----------------------------------------------------------------------------
43
+
44
+ #ifndef AT91SAM7X256_H
45
+ #define AT91SAM7X256_H
46
+
47
+ #ifdef __IAR_SYSTEMS_ICC__
48
+
49
+ typedef volatile unsigned int AT91_REG;// Hardware register definition
50
+
51
+ // *****************************************************************************
52
+ // SOFTWARE API DEFINITION FOR System Peripherals
53
+ // *****************************************************************************
54
+ typedef struct _AT91S_SYS {
55
+ AT91_REG AIC_SMR[32]; // Source Mode Register
56
+ AT91_REG AIC_SVR[32]; // Source Vector Register
57
+ AT91_REG AIC_IVR; // IRQ Vector Register
58
+ AT91_REG AIC_FVR; // FIQ Vector Register
59
+ AT91_REG AIC_ISR; // Interrupt Status Register
60
+ AT91_REG AIC_IPR; // Interrupt Pending Register
61
+ AT91_REG AIC_IMR; // Interrupt Mask Register
62
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
63
+ AT91_REG Reserved0[2]; //
64
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
65
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
66
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
67
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
68
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
69
+ AT91_REG AIC_SPU; // Spurious Vector Register
70
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
71
+ AT91_REG Reserved1[1]; //
72
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
73
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
74
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
75
+ AT91_REG Reserved2[45]; //
76
+ AT91_REG DBGU_CR; // Control Register
77
+ AT91_REG DBGU_MR; // Mode Register
78
+ AT91_REG DBGU_IER; // Interrupt Enable Register
79
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
80
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
81
+ AT91_REG DBGU_CSR; // Channel Status Register
82
+ AT91_REG DBGU_RHR; // Receiver Holding Register
83
+ AT91_REG DBGU_THR; // Transmitter Holding Register
84
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
85
+ AT91_REG Reserved3[7]; //
86
+ AT91_REG DBGU_CIDR; // Chip ID Register
87
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
88
+ AT91_REG DBGU_FNTR; // Force NTRST Register
89
+ AT91_REG Reserved4[45]; //
90
+ AT91_REG DBGU_RPR; // Receive Pointer Register
91
+ AT91_REG DBGU_RCR; // Receive Counter Register
92
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
93
+ AT91_REG DBGU_TCR; // Transmit Counter Register
94
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
95
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
96
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
97
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
98
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
99
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
100
+ AT91_REG Reserved5[54]; //
101
+ AT91_REG PIOA_PER; // PIO Enable Register
102
+ AT91_REG PIOA_PDR; // PIO Disable Register
103
+ AT91_REG PIOA_PSR; // PIO Status Register
104
+ AT91_REG Reserved6[1]; //
105
+ AT91_REG PIOA_OER; // Output Enable Register
106
+ AT91_REG PIOA_ODR; // Output Disable Registerr
107
+ AT91_REG PIOA_OSR; // Output Status Register
108
+ AT91_REG Reserved7[1]; //
109
+ AT91_REG PIOA_IFER; // Input Filter Enable Register
110
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register
111
+ AT91_REG PIOA_IFSR; // Input Filter Status Register
112
+ AT91_REG Reserved8[1]; //
113
+ AT91_REG PIOA_SODR; // Set Output Data Register
114
+ AT91_REG PIOA_CODR; // Clear Output Data Register
115
+ AT91_REG PIOA_ODSR; // Output Data Status Register
116
+ AT91_REG PIOA_PDSR; // Pin Data Status Register
117
+ AT91_REG PIOA_IER; // Interrupt Enable Register
118
+ AT91_REG PIOA_IDR; // Interrupt Disable Register
119
+ AT91_REG PIOA_IMR; // Interrupt Mask Register
120
+ AT91_REG PIOA_ISR; // Interrupt Status Register
121
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register
122
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register
123
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register
124
+ AT91_REG Reserved9[1]; //
125
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register
126
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register
127
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register
128
+ AT91_REG Reserved10[1]; //
129
+ AT91_REG PIOA_ASR; // Select A Register
130
+ AT91_REG PIOA_BSR; // Select B Register
131
+ AT91_REG PIOA_ABSR; // AB Select Status Register
132
+ AT91_REG Reserved11[9]; //
133
+ AT91_REG PIOA_OWER; // Output Write Enable Register
134
+ AT91_REG PIOA_OWDR; // Output Write Disable Register
135
+ AT91_REG PIOA_OWSR; // Output Write Status Register
136
+ AT91_REG Reserved12[85]; //
137
+ AT91_REG PIOB_PER; // PIO Enable Register
138
+ AT91_REG PIOB_PDR; // PIO Disable Register
139
+ AT91_REG PIOB_PSR; // PIO Status Register
140
+ AT91_REG Reserved13[1]; //
141
+ AT91_REG PIOB_OER; // Output Enable Register
142
+ AT91_REG PIOB_ODR; // Output Disable Registerr
143
+ AT91_REG PIOB_OSR; // Output Status Register
144
+ AT91_REG Reserved14[1]; //
145
+ AT91_REG PIOB_IFER; // Input Filter Enable Register
146
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register
147
+ AT91_REG PIOB_IFSR; // Input Filter Status Register
148
+ AT91_REG Reserved15[1]; //
149
+ AT91_REG PIOB_SODR; // Set Output Data Register
150
+ AT91_REG PIOB_CODR; // Clear Output Data Register
151
+ AT91_REG PIOB_ODSR; // Output Data Status Register
152
+ AT91_REG PIOB_PDSR; // Pin Data Status Register
153
+ AT91_REG PIOB_IER; // Interrupt Enable Register
154
+ AT91_REG PIOB_IDR; // Interrupt Disable Register
155
+ AT91_REG PIOB_IMR; // Interrupt Mask Register
156
+ AT91_REG PIOB_ISR; // Interrupt Status Register
157
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register
158
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register
159
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register
160
+ AT91_REG Reserved16[1]; //
161
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register
162
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register
163
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register
164
+ AT91_REG Reserved17[1]; //
165
+ AT91_REG PIOB_ASR; // Select A Register
166
+ AT91_REG PIOB_BSR; // Select B Register
167
+ AT91_REG PIOB_ABSR; // AB Select Status Register
168
+ AT91_REG Reserved18[9]; //
169
+ AT91_REG PIOB_OWER; // Output Write Enable Register
170
+ AT91_REG PIOB_OWDR; // Output Write Disable Register
171
+ AT91_REG PIOB_OWSR; // Output Write Status Register
172
+ AT91_REG Reserved19[341]; //
173
+ AT91_REG PMC_SCER; // System Clock Enable Register
174
+ AT91_REG PMC_SCDR; // System Clock Disable Register
175
+ AT91_REG PMC_SCSR; // System Clock Status Register
176
+ AT91_REG Reserved20[1]; //
177
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
178
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
179
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
180
+ AT91_REG Reserved21[1]; //
181
+ AT91_REG PMC_MOR; // Main Oscillator Register
182
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
183
+ AT91_REG Reserved22[1]; //
184
+ AT91_REG PMC_PLLR; // PLL Register
185
+ AT91_REG PMC_MCKR; // Master Clock Register
186
+ AT91_REG Reserved23[3]; //
187
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
188
+ AT91_REG Reserved24[4]; //
189
+ AT91_REG PMC_IER; // Interrupt Enable Register
190
+ AT91_REG PMC_IDR; // Interrupt Disable Register
191
+ AT91_REG PMC_SR; // Status Register
192
+ AT91_REG PMC_IMR; // Interrupt Mask Register
193
+ AT91_REG Reserved25[36]; //
194
+ AT91_REG RSTC_RCR; // Reset Control Register
195
+ AT91_REG RSTC_RSR; // Reset Status Register
196
+ AT91_REG RSTC_RMR; // Reset Mode Register
197
+ AT91_REG Reserved26[5]; //
198
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
199
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
200
+ AT91_REG RTTC_RTVR; // Real-time Value Register
201
+ AT91_REG RTTC_RTSR; // Real-time Status Register
202
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
203
+ AT91_REG PITC_PISR; // Period Interval Status Register
204
+ AT91_REG PITC_PIVR; // Period Interval Value Register
205
+ AT91_REG PITC_PIIR; // Period Interval Image Register
206
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
207
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
208
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
209
+ AT91_REG Reserved27[5]; //
210
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
211
+ } AT91S_SYS, *AT91PS_SYS;
212
+
213
+
214
+ // *****************************************************************************
215
+ // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
216
+ // *****************************************************************************
217
+ typedef struct _AT91S_AIC {
218
+ AT91_REG AIC_SMR[32]; // Source Mode Register
219
+ AT91_REG AIC_SVR[32]; // Source Vector Register
220
+ AT91_REG AIC_IVR; // IRQ Vector Register
221
+ AT91_REG AIC_FVR; // FIQ Vector Register
222
+ AT91_REG AIC_ISR; // Interrupt Status Register
223
+ AT91_REG AIC_IPR; // Interrupt Pending Register
224
+ AT91_REG AIC_IMR; // Interrupt Mask Register
225
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
226
+ AT91_REG Reserved0[2]; //
227
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
228
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
229
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
230
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
231
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
232
+ AT91_REG AIC_SPU; // Spurious Vector Register
233
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
234
+ AT91_REG Reserved1[1]; //
235
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
236
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
237
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
238
+ } AT91S_AIC, *AT91PS_AIC;
239
+
240
+ // -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
241
+ #define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
242
+ #define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
243
+ #define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
244
+ #define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
245
+ #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
246
+ #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
247
+ #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
248
+ #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
249
+ #define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
250
+ #define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
251
+ // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
252
+ #define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
253
+ #define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
254
+ // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
255
+ #define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
256
+ #define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
257
+
258
+ // *****************************************************************************
259
+ // SOFTWARE API DEFINITION FOR Peripheral DMA Controller
260
+ // *****************************************************************************
261
+ typedef struct _AT91S_PDC {
262
+ AT91_REG PDC_RPR; // Receive Pointer Register
263
+ AT91_REG PDC_RCR; // Receive Counter Register
264
+ AT91_REG PDC_TPR; // Transmit Pointer Register
265
+ AT91_REG PDC_TCR; // Transmit Counter Register
266
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register
267
+ AT91_REG PDC_RNCR; // Receive Next Counter Register
268
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register
269
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register
270
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register
271
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register
272
+ } AT91S_PDC, *AT91PS_PDC;
273
+
274
+ // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
275
+ #define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
276
+ #define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
277
+ #define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
278
+ #define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
279
+ // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
280
+
281
+ // *****************************************************************************
282
+ // SOFTWARE API DEFINITION FOR Debug Unit
283
+ // *****************************************************************************
284
+ typedef struct _AT91S_DBGU {
285
+ AT91_REG DBGU_CR; // Control Register
286
+ AT91_REG DBGU_MR; // Mode Register
287
+ AT91_REG DBGU_IER; // Interrupt Enable Register
288
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
289
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
290
+ AT91_REG DBGU_CSR; // Channel Status Register
291
+ AT91_REG DBGU_RHR; // Receiver Holding Register
292
+ AT91_REG DBGU_THR; // Transmitter Holding Register
293
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
294
+ AT91_REG Reserved0[7]; //
295
+ AT91_REG DBGU_CIDR; // Chip ID Register
296
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
297
+ AT91_REG DBGU_FNTR; // Force NTRST Register
298
+ AT91_REG Reserved1[45]; //
299
+ AT91_REG DBGU_RPR; // Receive Pointer Register
300
+ AT91_REG DBGU_RCR; // Receive Counter Register
301
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
302
+ AT91_REG DBGU_TCR; // Transmit Counter Register
303
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
304
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
305
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
306
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
307
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
308
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
309
+ } AT91S_DBGU, *AT91PS_DBGU;
310
+
311
+ // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
312
+ #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
313
+ #define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
314
+ #define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
315
+ #define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
316
+ #define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
317
+ #define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
318
+ #define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
319
+ // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
320
+ #define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
321
+ #define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
322
+ #define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
323
+ #define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
324
+ #define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
325
+ #define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
326
+ #define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
327
+ #define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
328
+ #define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
329
+ #define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
330
+ #define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
331
+ #define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
332
+ // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
333
+ #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
334
+ #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
335
+ #define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
336
+ #define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
337
+ #define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
338
+ #define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
339
+ #define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
340
+ #define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
341
+ #define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
342
+ #define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
343
+ #define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
344
+ #define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
345
+ // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
346
+ // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
347
+ // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
348
+ // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
349
+ #define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
350
+
351
+ // *****************************************************************************
352
+ // SOFTWARE API DEFINITION FOR Parallel Input Output Controler
353
+ // *****************************************************************************
354
+ typedef struct _AT91S_PIO {
355
+ AT91_REG PIO_PER; // PIO Enable Register
356
+ AT91_REG PIO_PDR; // PIO Disable Register
357
+ AT91_REG PIO_PSR; // PIO Status Register
358
+ AT91_REG Reserved0[1]; //
359
+ AT91_REG PIO_OER; // Output Enable Register
360
+ AT91_REG PIO_ODR; // Output Disable Registerr
361
+ AT91_REG PIO_OSR; // Output Status Register
362
+ AT91_REG Reserved1[1]; //
363
+ AT91_REG PIO_IFER; // Input Filter Enable Register
364
+ AT91_REG PIO_IFDR; // Input Filter Disable Register
365
+ AT91_REG PIO_IFSR; // Input Filter Status Register
366
+ AT91_REG Reserved2[1]; //
367
+ AT91_REG PIO_SODR; // Set Output Data Register
368
+ AT91_REG PIO_CODR; // Clear Output Data Register
369
+ AT91_REG PIO_ODSR; // Output Data Status Register
370
+ AT91_REG PIO_PDSR; // Pin Data Status Register
371
+ AT91_REG PIO_IER; // Interrupt Enable Register
372
+ AT91_REG PIO_IDR; // Interrupt Disable Register
373
+ AT91_REG PIO_IMR; // Interrupt Mask Register
374
+ AT91_REG PIO_ISR; // Interrupt Status Register
375
+ AT91_REG PIO_MDER; // Multi-driver Enable Register
376
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register
377
+ AT91_REG PIO_MDSR; // Multi-driver Status Register
378
+ AT91_REG Reserved3[1]; //
379
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register
380
+ AT91_REG PIO_PPUER; // Pull-up Enable Register
381
+ AT91_REG PIO_PPUSR; // Pull-up Status Register
382
+ AT91_REG Reserved4[1]; //
383
+ AT91_REG PIO_ASR; // Select A Register
384
+ AT91_REG PIO_BSR; // Select B Register
385
+ AT91_REG PIO_ABSR; // AB Select Status Register
386
+ AT91_REG Reserved5[9]; //
387
+ AT91_REG PIO_OWER; // Output Write Enable Register
388
+ AT91_REG PIO_OWDR; // Output Write Disable Register
389
+ AT91_REG PIO_OWSR; // Output Write Status Register
390
+ } AT91S_PIO, *AT91PS_PIO;
391
+
392
+
393
+ // *****************************************************************************
394
+ // SOFTWARE API DEFINITION FOR Clock Generator Controler
395
+ // *****************************************************************************
396
+ typedef struct _AT91S_CKGR {
397
+ AT91_REG CKGR_MOR; // Main Oscillator Register
398
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
399
+ AT91_REG Reserved0[1]; //
400
+ AT91_REG CKGR_PLLR; // PLL Register
401
+ } AT91S_CKGR, *AT91PS_CKGR;
402
+
403
+ // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
404
+ #define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
405
+ #define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
406
+ #define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
407
+ // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
408
+ #define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
409
+ #define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
410
+ // -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
411
+ #define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
412
+ #define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
413
+ #define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
414
+ #define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
415
+ #define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
416
+ #define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
417
+ #define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
418
+ #define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
419
+ #define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
420
+ #define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
421
+ #define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
422
+ #define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
423
+ #define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
424
+ #define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
425
+
426
+ // *****************************************************************************
427
+ // SOFTWARE API DEFINITION FOR Power Management Controler
428
+ // *****************************************************************************
429
+ typedef struct _AT91S_PMC {
430
+ AT91_REG PMC_SCER; // System Clock Enable Register
431
+ AT91_REG PMC_SCDR; // System Clock Disable Register
432
+ AT91_REG PMC_SCSR; // System Clock Status Register
433
+ AT91_REG Reserved0[1]; //
434
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
435
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
436
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
437
+ AT91_REG Reserved1[1]; //
438
+ AT91_REG PMC_MOR; // Main Oscillator Register
439
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
440
+ AT91_REG Reserved2[1]; //
441
+ AT91_REG PMC_PLLR; // PLL Register
442
+ AT91_REG PMC_MCKR; // Master Clock Register
443
+ AT91_REG Reserved3[3]; //
444
+ AT91_REG PMC_PCKR[4]; // Programmable Clock Register
445
+ AT91_REG Reserved4[4]; //
446
+ AT91_REG PMC_IER; // Interrupt Enable Register
447
+ AT91_REG PMC_IDR; // Interrupt Disable Register
448
+ AT91_REG PMC_SR; // Status Register
449
+ AT91_REG PMC_IMR; // Interrupt Mask Register
450
+ } AT91S_PMC, *AT91PS_PMC;
451
+
452
+ // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
453
+ #define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
454
+ #define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
455
+ #define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
456
+ #define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
457
+ #define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
458
+ #define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
459
+ // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
460
+ // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
461
+ // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
462
+ // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
463
+ // -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
464
+ // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
465
+ #define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
466
+ #define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
467
+ #define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
468
+ #define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
469
+ #define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
470
+ #define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
471
+ #define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
472
+ #define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
473
+ #define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
474
+ #define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
475
+ #define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
476
+ #define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
477
+ // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
478
+ // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
479
+ #define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
480
+ #define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
481
+ #define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
482
+ #define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
483
+ #define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
484
+ #define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
485
+ #define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
486
+ // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
487
+ // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
488
+ // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
489
+
490
+ // *****************************************************************************
491
+ // SOFTWARE API DEFINITION FOR Reset Controller Interface
492
+ // *****************************************************************************
493
+ typedef struct _AT91S_RSTC {
494
+ AT91_REG RSTC_RCR; // Reset Control Register
495
+ AT91_REG RSTC_RSR; // Reset Status Register
496
+ AT91_REG RSTC_RMR; // Reset Mode Register
497
+ } AT91S_RSTC, *AT91PS_RSTC;
498
+
499
+ // -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
500
+ #define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
501
+ #define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
502
+ #define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
503
+ #define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
504
+ // -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
505
+ #define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
506
+ #define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
507
+ #define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
508
+ #define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
509
+ #define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
510
+ #define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
511
+ #define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
512
+ #define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
513
+ #define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
514
+ #define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
515
+ #define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
516
+ // -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
517
+ #define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
518
+ #define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
519
+ #define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Length
520
+ #define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
521
+
522
+ // *****************************************************************************
523
+ // SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
524
+ // *****************************************************************************
525
+ typedef struct _AT91S_RTTC {
526
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
527
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
528
+ AT91_REG RTTC_RTVR; // Real-time Value Register
529
+ AT91_REG RTTC_RTSR; // Real-time Status Register
530
+ } AT91S_RTTC, *AT91PS_RTTC;
531
+
532
+ // -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
533
+ #define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
534
+ #define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
535
+ #define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
536
+ #define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
537
+ // -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
538
+ #define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
539
+ // -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
540
+ #define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
541
+ // -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
542
+ #define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
543
+ #define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
544
+
545
+ // *****************************************************************************
546
+ // SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
547
+ // *****************************************************************************
548
+ typedef struct _AT91S_PITC {
549
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
550
+ AT91_REG PITC_PISR; // Period Interval Status Register
551
+ AT91_REG PITC_PIVR; // Period Interval Value Register
552
+ AT91_REG PITC_PIIR; // Period Interval Image Register
553
+ } AT91S_PITC, *AT91PS_PITC;
554
+
555
+ // -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
556
+ #define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
557
+ #define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
558
+ #define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
559
+ // -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
560
+ #define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
561
+ // -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
562
+ #define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
563
+ #define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
564
+ // -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
565
+
566
+ // *****************************************************************************
567
+ // SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
568
+ // *****************************************************************************
569
+ typedef struct _AT91S_WDTC {
570
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
571
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
572
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
573
+ } AT91S_WDTC, *AT91PS_WDTC;
574
+
575
+ // -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
576
+ #define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
577
+ #define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
578
+ // -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
579
+ #define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
580
+ #define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
581
+ #define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
582
+ #define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
583
+ #define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
584
+ #define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
585
+ #define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
586
+ #define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
587
+ // -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
588
+ #define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
589
+ #define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
590
+
591
+ // *****************************************************************************
592
+ // SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
593
+ // *****************************************************************************
594
+ typedef struct _AT91S_VREG {
595
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
596
+ } AT91S_VREG, *AT91PS_VREG;
597
+
598
+ // -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
599
+ #define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
600
+
601
+ // *****************************************************************************
602
+ // SOFTWARE API DEFINITION FOR Memory Controller Interface
603
+ // *****************************************************************************
604
+ typedef struct _AT91S_MC {
605
+ AT91_REG MC_RCR; // MC Remap Control Register
606
+ AT91_REG MC_ASR; // MC Abort Status Register
607
+ AT91_REG MC_AASR; // MC Abort Address Status Register
608
+ AT91_REG Reserved0[21]; //
609
+ AT91_REG MC_FMR; // MC Flash Mode Register
610
+ AT91_REG MC_FCR; // MC Flash Command Register
611
+ AT91_REG MC_FSR; // MC Flash Status Register
612
+ } AT91S_MC, *AT91PS_MC;
613
+
614
+ // -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
615
+ #define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
616
+ // -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
617
+ #define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
618
+ #define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
619
+ #define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
620
+ #define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
621
+ #define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
622
+ #define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
623
+ #define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
624
+ #define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
625
+ #define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
626
+ #define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
627
+ #define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
628
+ #define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
629
+ #define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
630
+ #define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
631
+ // -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
632
+ #define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
633
+ #define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
634
+ #define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
635
+ #define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
636
+ #define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
637
+ #define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
638
+ #define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
639
+ #define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
640
+ #define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
641
+ #define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
642
+ // -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
643
+ #define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
644
+ #define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
645
+ #define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
646
+ #define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
647
+ #define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
648
+ #define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
649
+ #define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
650
+ #define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
651
+ #define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
652
+ #define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
653
+ #define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
654
+ // -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
655
+ #define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
656
+ #define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
657
+ #define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
658
+ #define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
659
+ #define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
660
+ #define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
661
+ #define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
662
+ #define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
663
+ #define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
664
+ #define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
665
+ #define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
666
+ #define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
667
+ #define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
668
+ #define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
669
+ #define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
670
+ #define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
671
+ #define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
672
+ #define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
673
+ #define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
674
+ #define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
675
+ #define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
676
+ #define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
677
+ #define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
678
+ #define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
679
+ #define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
680
+
681
+ // *****************************************************************************
682
+ // SOFTWARE API DEFINITION FOR Serial Parallel Interface
683
+ // *****************************************************************************
684
+ typedef struct _AT91S_SPI {
685
+ AT91_REG SPI_CR; // Control Register
686
+ AT91_REG SPI_MR; // Mode Register
687
+ AT91_REG SPI_RDR; // Receive Data Register
688
+ AT91_REG SPI_TDR; // Transmit Data Register
689
+ AT91_REG SPI_SR; // Status Register
690
+ AT91_REG SPI_IER; // Interrupt Enable Register
691
+ AT91_REG SPI_IDR; // Interrupt Disable Register
692
+ AT91_REG SPI_IMR; // Interrupt Mask Register
693
+ AT91_REG Reserved0[4]; //
694
+ AT91_REG SPI_CSR[4]; // Chip Select Register
695
+ AT91_REG Reserved1[48]; //
696
+ AT91_REG SPI_RPR; // Receive Pointer Register
697
+ AT91_REG SPI_RCR; // Receive Counter Register
698
+ AT91_REG SPI_TPR; // Transmit Pointer Register
699
+ AT91_REG SPI_TCR; // Transmit Counter Register
700
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register
701
+ AT91_REG SPI_RNCR; // Receive Next Counter Register
702
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register
703
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register
704
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register
705
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register
706
+ } AT91S_SPI, *AT91PS_SPI;
707
+
708
+ // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
709
+ #define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
710
+ #define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
711
+ #define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
712
+ #define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
713
+ // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
714
+ #define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
715
+ #define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
716
+ #define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
717
+ #define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
718
+ #define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
719
+ #define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
720
+ #define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
721
+ #define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
722
+ #define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
723
+ #define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
724
+ // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
725
+ #define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
726
+ #define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
727
+ // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
728
+ #define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
729
+ #define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
730
+ // -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
731
+ #define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
732
+ #define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
733
+ #define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
734
+ #define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
735
+ #define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
736
+ #define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
737
+ #define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
738
+ #define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
739
+ #define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
740
+ #define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
741
+ #define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
742
+ // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
743
+ // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
744
+ // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
745
+ // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
746
+ #define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
747
+ #define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
748
+ #define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
749
+ #define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
750
+ #define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
751
+ #define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
752
+ #define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
753
+ #define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
754
+ #define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
755
+ #define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
756
+ #define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
757
+ #define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
758
+ #define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
759
+ #define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
760
+ #define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
761
+ #define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
762
+
763
+ // *****************************************************************************
764
+ // SOFTWARE API DEFINITION FOR Usart
765
+ // *****************************************************************************
766
+ typedef struct _AT91S_USART {
767
+ AT91_REG US_CR; // Control Register
768
+ AT91_REG US_MR; // Mode Register
769
+ AT91_REG US_IER; // Interrupt Enable Register
770
+ AT91_REG US_IDR; // Interrupt Disable Register
771
+ AT91_REG US_IMR; // Interrupt Mask Register
772
+ AT91_REG US_CSR; // Channel Status Register
773
+ AT91_REG US_RHR; // Receiver Holding Register
774
+ AT91_REG US_THR; // Transmitter Holding Register
775
+ AT91_REG US_BRGR; // Baud Rate Generator Register
776
+ AT91_REG US_RTOR; // Receiver Time-out Register
777
+ AT91_REG US_TTGR; // Transmitter Time-guard Register
778
+ AT91_REG Reserved0[5]; //
779
+ AT91_REG US_FIDI; // FI_DI_Ratio Register
780
+ AT91_REG US_NER; // Nb Errors Register
781
+ AT91_REG Reserved1[1]; //
782
+ AT91_REG US_IF; // IRDA_FILTER Register
783
+ AT91_REG Reserved2[44]; //
784
+ AT91_REG US_RPR; // Receive Pointer Register
785
+ AT91_REG US_RCR; // Receive Counter Register
786
+ AT91_REG US_TPR; // Transmit Pointer Register
787
+ AT91_REG US_TCR; // Transmit Counter Register
788
+ AT91_REG US_RNPR; // Receive Next Pointer Register
789
+ AT91_REG US_RNCR; // Receive Next Counter Register
790
+ AT91_REG US_TNPR; // Transmit Next Pointer Register
791
+ AT91_REG US_TNCR; // Transmit Next Counter Register
792
+ AT91_REG US_PTCR; // PDC Transfer Control Register
793
+ AT91_REG US_PTSR; // PDC Transfer Status Register
794
+ } AT91S_USART, *AT91PS_USART;
795
+
796
+ // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
797
+ #define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
798
+ #define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
799
+ #define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
800
+ #define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
801
+ #define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
802
+ #define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
803
+ #define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
804
+ #define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
805
+ #define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
806
+ #define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
807
+ #define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
808
+ // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
809
+ #define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
810
+ #define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
811
+ #define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
812
+ #define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
813
+ #define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
814
+ #define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
815
+ #define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
816
+ #define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
817
+ #define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
818
+ #define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
819
+ #define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
820
+ #define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
821
+ #define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
822
+ #define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
823
+ #define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
824
+ #define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
825
+ #define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
826
+ #define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
827
+ #define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
828
+ #define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
829
+ #define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
830
+ #define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
831
+ #define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
832
+ #define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
833
+ #define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
834
+ #define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
835
+ #define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
836
+ #define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
837
+ #define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
838
+ #define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
839
+ #define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
840
+ #define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
841
+ // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
842
+ #define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
843
+ #define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
844
+ #define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
845
+ #define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
846
+ #define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
847
+ #define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
848
+ #define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
849
+ #define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
850
+ // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
851
+ // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
852
+ // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
853
+ #define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
854
+ #define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
855
+ #define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
856
+ #define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
857
+
858
+ // *****************************************************************************
859
+ // SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
860
+ // *****************************************************************************
861
+ typedef struct _AT91S_SSC {
862
+ AT91_REG SSC_CR; // Control Register
863
+ AT91_REG SSC_CMR; // Clock Mode Register
864
+ AT91_REG Reserved0[2]; //
865
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister
866
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register
867
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register
868
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register
869
+ AT91_REG SSC_RHR; // Receive Holding Register
870
+ AT91_REG SSC_THR; // Transmit Holding Register
871
+ AT91_REG Reserved1[2]; //
872
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register
873
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register
874
+ AT91_REG Reserved2[2]; //
875
+ AT91_REG SSC_SR; // Status Register
876
+ AT91_REG SSC_IER; // Interrupt Enable Register
877
+ AT91_REG SSC_IDR; // Interrupt Disable Register
878
+ AT91_REG SSC_IMR; // Interrupt Mask Register
879
+ AT91_REG Reserved3[44]; //
880
+ AT91_REG SSC_RPR; // Receive Pointer Register
881
+ AT91_REG SSC_RCR; // Receive Counter Register
882
+ AT91_REG SSC_TPR; // Transmit Pointer Register
883
+ AT91_REG SSC_TCR; // Transmit Counter Register
884
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register
885
+ AT91_REG SSC_RNCR; // Receive Next Counter Register
886
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register
887
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register
888
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register
889
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register
890
+ } AT91S_SSC, *AT91PS_SSC;
891
+
892
+ // -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
893
+ #define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
894
+ #define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
895
+ #define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
896
+ #define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
897
+ #define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
898
+ // -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
899
+ #define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
900
+ #define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
901
+ #define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
902
+ #define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
903
+ #define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
904
+ #define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
905
+ #define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
906
+ #define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
907
+ #define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
908
+ #define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
909
+ #define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
910
+ #define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
911
+ #define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
912
+ #define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
913
+ #define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
914
+ #define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
915
+ #define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
916
+ #define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
917
+ #define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
918
+ #define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
919
+ #define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
920
+ #define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
921
+ #define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
922
+ #define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection
923
+ #define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
924
+ #define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
925
+ // -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
926
+ #define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
927
+ #define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
928
+ #define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
929
+ #define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
930
+ #define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
931
+ #define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
932
+ #define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
933
+ #define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
934
+ #define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
935
+ #define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
936
+ #define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
937
+ #define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
938
+ #define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
939
+ // -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
940
+ // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
941
+ #define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
942
+ #define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
943
+ // -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
944
+ #define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
945
+ #define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
946
+ #define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
947
+ #define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
948
+ #define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
949
+ #define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
950
+ #define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
951
+ #define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
952
+ #define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0
953
+ #define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1
954
+ #define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
955
+ #define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
956
+ #define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
957
+ #define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
958
+ // -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
959
+ // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
960
+ // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
961
+
962
+ // *****************************************************************************
963
+ // SOFTWARE API DEFINITION FOR Two-wire Interface
964
+ // *****************************************************************************
965
+ typedef struct _AT91S_TWI {
966
+ AT91_REG TWI_CR; // Control Register
967
+ AT91_REG TWI_MMR; // Master Mode Register
968
+ AT91_REG Reserved0[1]; //
969
+ AT91_REG TWI_IADR; // Internal Address Register
970
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register
971
+ AT91_REG Reserved1[3]; //
972
+ AT91_REG TWI_SR; // Status Register
973
+ AT91_REG TWI_IER; // Interrupt Enable Register
974
+ AT91_REG TWI_IDR; // Interrupt Disable Register
975
+ AT91_REG TWI_IMR; // Interrupt Mask Register
976
+ AT91_REG TWI_RHR; // Receive Holding Register
977
+ AT91_REG TWI_THR; // Transmit Holding Register
978
+ } AT91S_TWI, *AT91PS_TWI;
979
+
980
+ // -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
981
+ #define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
982
+ #define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
983
+ #define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
984
+ #define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
985
+ #define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
986
+ // -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
987
+ #define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
988
+ #define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
989
+ #define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
990
+ #define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
991
+ #define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
992
+ #define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
993
+ #define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
994
+ // -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
995
+ #define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
996
+ #define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
997
+ #define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
998
+ // -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
999
+ #define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
1000
+ #define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
1001
+ #define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
1002
+ #define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
1003
+ #define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
1004
+ #define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
1005
+ // -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
1006
+ // -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
1007
+ // -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
1008
+
1009
+ // *****************************************************************************
1010
+ // SOFTWARE API DEFINITION FOR PWMC Channel Interface
1011
+ // *****************************************************************************
1012
+ typedef struct _AT91S_PWMC_CH {
1013
+ AT91_REG PWMC_CMR; // Channel Mode Register
1014
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
1015
+ AT91_REG PWMC_CPRDR; // Channel Period Register
1016
+ AT91_REG PWMC_CCNTR; // Channel Counter Register
1017
+ AT91_REG PWMC_CUPDR; // Channel Update Register
1018
+ AT91_REG PWMC_Reserved[3]; // Reserved
1019
+ } AT91S_PWMC_CH, *AT91PS_PWMC_CH;
1020
+
1021
+ // -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
1022
+ #define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
1023
+ #define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
1024
+ #define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
1025
+ #define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
1026
+ #define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
1027
+ #define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
1028
+ #define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
1029
+ // -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
1030
+ #define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
1031
+ // -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
1032
+ #define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
1033
+ // -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
1034
+ #define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
1035
+ // -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
1036
+ #define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
1037
+
1038
+ // *****************************************************************************
1039
+ // SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
1040
+ // *****************************************************************************
1041
+ typedef struct _AT91S_PWMC {
1042
+ AT91_REG PWMC_MR; // PWMC Mode Register
1043
+ AT91_REG PWMC_ENA; // PWMC Enable Register
1044
+ AT91_REG PWMC_DIS; // PWMC Disable Register
1045
+ AT91_REG PWMC_SR; // PWMC Status Register
1046
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
1047
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
1048
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
1049
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
1050
+ AT91_REG Reserved0[55]; //
1051
+ AT91_REG PWMC_VR; // PWMC Version Register
1052
+ AT91_REG Reserved1[64]; //
1053
+ AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
1054
+ } AT91S_PWMC, *AT91PS_PWMC;
1055
+
1056
+ // -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
1057
+ #define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
1058
+ #define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
1059
+ #define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
1060
+ #define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
1061
+ #define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
1062
+ #define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
1063
+ // -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
1064
+ #define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
1065
+ #define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
1066
+ #define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
1067
+ #define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
1068
+ // -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
1069
+ // -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
1070
+ // -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
1071
+ // -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
1072
+ // -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
1073
+ // -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
1074
+
1075
+ // *****************************************************************************
1076
+ // SOFTWARE API DEFINITION FOR USB Device Interface
1077
+ // *****************************************************************************
1078
+ typedef struct _AT91S_UDP {
1079
+ AT91_REG UDP_NUM; // Frame Number Register
1080
+ AT91_REG UDP_GLBSTATE; // Global State Register
1081
+ AT91_REG UDP_FADDR; // Function Address Register
1082
+ AT91_REG Reserved0[1]; //
1083
+ AT91_REG UDP_IER; // Interrupt Enable Register
1084
+ AT91_REG UDP_IDR; // Interrupt Disable Register
1085
+ AT91_REG UDP_IMR; // Interrupt Mask Register
1086
+ AT91_REG UDP_ISR; // Interrupt Status Register
1087
+ AT91_REG UDP_ICR; // Interrupt Clear Register
1088
+ AT91_REG Reserved1[1]; //
1089
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register
1090
+ AT91_REG Reserved2[1]; //
1091
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
1092
+ AT91_REG Reserved3[2]; //
1093
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
1094
+ AT91_REG Reserved4[3]; //
1095
+ AT91_REG UDP_TXVC; // Transceiver Control Register
1096
+ } AT91S_UDP, *AT91PS_UDP;
1097
+
1098
+ // -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
1099
+ #define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
1100
+ #define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
1101
+ #define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
1102
+ // -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
1103
+ #define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
1104
+ #define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
1105
+ #define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
1106
+ #define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
1107
+ #define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
1108
+ // -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
1109
+ #define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
1110
+ #define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
1111
+ // -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
1112
+ #define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
1113
+ #define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
1114
+ #define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
1115
+ #define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
1116
+ #define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
1117
+ #define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
1118
+ #define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
1119
+ #define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
1120
+ #define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
1121
+ #define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
1122
+ #define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
1123
+ // -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
1124
+ // -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
1125
+ // -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
1126
+ #define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
1127
+ // -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
1128
+ // -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
1129
+ #define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
1130
+ #define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
1131
+ #define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
1132
+ #define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
1133
+ #define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
1134
+ #define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
1135
+ // -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
1136
+ #define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
1137
+ #define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
1138
+ #define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
1139
+ #define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
1140
+ #define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
1141
+ #define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
1142
+ #define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
1143
+ #define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
1144
+ #define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
1145
+ #define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
1146
+ #define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
1147
+ #define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
1148
+ #define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
1149
+ #define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
1150
+ #define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
1151
+ #define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
1152
+ #define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
1153
+ #define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
1154
+ #define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
1155
+ // -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
1156
+ #define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
1157
+ #define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
1158
+
1159
+ // *****************************************************************************
1160
+ // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
1161
+ // *****************************************************************************
1162
+ typedef struct _AT91S_TC {
1163
+ AT91_REG TC_CCR; // Channel Control Register
1164
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
1165
+ AT91_REG Reserved0[2]; //
1166
+ AT91_REG TC_CV; // Counter Value
1167
+ AT91_REG TC_RA; // Register A
1168
+ AT91_REG TC_RB; // Register B
1169
+ AT91_REG TC_RC; // Register C
1170
+ AT91_REG TC_SR; // Status Register
1171
+ AT91_REG TC_IER; // Interrupt Enable Register
1172
+ AT91_REG TC_IDR; // Interrupt Disable Register
1173
+ AT91_REG TC_IMR; // Interrupt Mask Register
1174
+ } AT91S_TC, *AT91PS_TC;
1175
+
1176
+ // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
1177
+ #define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
1178
+ #define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
1179
+ #define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
1180
+ // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
1181
+ #define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
1182
+ #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
1183
+ #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
1184
+ #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
1185
+ #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
1186
+ #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
1187
+ #define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
1188
+ #define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
1189
+ #define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
1190
+ #define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
1191
+ #define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
1192
+ #define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
1193
+ #define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
1194
+ #define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
1195
+ #define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
1196
+ #define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
1197
+ #define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
1198
+ #define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
1199
+ #define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
1200
+ #define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
1201
+ #define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
1202
+ #define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
1203
+ #define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
1204
+ #define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
1205
+ #define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
1206
+ #define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
1207
+ #define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
1208
+ #define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
1209
+ #define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
1210
+ #define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
1211
+ #define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
1212
+ #define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
1213
+ #define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
1214
+ #define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
1215
+ #define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
1216
+ #define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
1217
+ #define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
1218
+ #define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
1219
+ #define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
1220
+ #define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
1221
+ #define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
1222
+ #define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
1223
+ #define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
1224
+ #define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
1225
+ #define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
1226
+ #define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
1227
+ #define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
1228
+ #define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
1229
+ #define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
1230
+ #define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
1231
+ #define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
1232
+ #define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
1233
+ #define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
1234
+ #define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
1235
+ #define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
1236
+ #define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
1237
+ #define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
1238
+ #define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
1239
+ #define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
1240
+ #define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
1241
+ #define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
1242
+ #define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
1243
+ #define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
1244
+ #define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
1245
+ #define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
1246
+ #define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
1247
+ #define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
1248
+ #define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
1249
+ #define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
1250
+ #define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
1251
+ #define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
1252
+ #define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
1253
+ #define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
1254
+ #define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
1255
+ #define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
1256
+ #define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
1257
+ #define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
1258
+ #define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
1259
+ #define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
1260
+ #define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
1261
+ #define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
1262
+ #define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
1263
+ #define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
1264
+ #define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
1265
+ #define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
1266
+ #define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
1267
+ #define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
1268
+ #define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
1269
+ #define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
1270
+ #define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
1271
+ #define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
1272
+ #define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
1273
+ #define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
1274
+ // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
1275
+ #define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
1276
+ #define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
1277
+ #define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
1278
+ #define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
1279
+ #define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
1280
+ #define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
1281
+ #define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
1282
+ #define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
1283
+ #define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
1284
+ #define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
1285
+ #define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
1286
+ // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
1287
+ // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
1288
+ // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
1289
+
1290
+ // *****************************************************************************
1291
+ // SOFTWARE API DEFINITION FOR Timer Counter Interface
1292
+ // *****************************************************************************
1293
+ typedef struct _AT91S_TCB {
1294
+ AT91S_TC TCB_TC0; // TC Channel 0
1295
+ AT91_REG Reserved0[4]; //
1296
+ AT91S_TC TCB_TC1; // TC Channel 1
1297
+ AT91_REG Reserved1[4]; //
1298
+ AT91S_TC TCB_TC2; // TC Channel 2
1299
+ AT91_REG Reserved2[4]; //
1300
+ AT91_REG TCB_BCR; // TC Block Control Register
1301
+ AT91_REG TCB_BMR; // TC Block Mode Register
1302
+ } AT91S_TCB, *AT91PS_TCB;
1303
+
1304
+ // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
1305
+ #define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
1306
+ // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
1307
+ #define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
1308
+ #define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
1309
+ #define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
1310
+ #define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
1311
+ #define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
1312
+ #define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
1313
+ #define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
1314
+ #define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
1315
+ #define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
1316
+ #define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
1317
+ #define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
1318
+ #define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
1319
+ #define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
1320
+ #define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
1321
+ #define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
1322
+
1323
+ // *****************************************************************************
1324
+ // SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
1325
+ // *****************************************************************************
1326
+ typedef struct _AT91S_CAN_MB {
1327
+ AT91_REG CAN_MB_MMR; // MailBox Mode Register
1328
+ AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
1329
+ AT91_REG CAN_MB_MID; // MailBox ID Register
1330
+ AT91_REG CAN_MB_MFID; // MailBox Family ID Register
1331
+ AT91_REG CAN_MB_MSR; // MailBox Status Register
1332
+ AT91_REG CAN_MB_MDL; // MailBox Data Low Register
1333
+ AT91_REG CAN_MB_MDH; // MailBox Data High Register
1334
+ AT91_REG CAN_MB_MCR; // MailBox Control Register
1335
+ } AT91S_CAN_MB, *AT91PS_CAN_MB;
1336
+
1337
+ // -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
1338
+ #define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
1339
+ #define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
1340
+ #define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
1341
+ #define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
1342
+ #define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
1343
+ #define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
1344
+ #define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB)
1345
+ #define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB)
1346
+ #define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB)
1347
+ // -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
1348
+ #define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
1349
+ #define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
1350
+ #define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
1351
+ // -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
1352
+ // -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
1353
+ // -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
1354
+ #define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value
1355
+ #define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
1356
+ #define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
1357
+ #define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
1358
+ #define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
1359
+ #define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
1360
+ // -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
1361
+ // -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
1362
+ // -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
1363
+ #define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
1364
+ #define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
1365
+
1366
+ // *****************************************************************************
1367
+ // SOFTWARE API DEFINITION FOR Control Area Network Interface
1368
+ // *****************************************************************************
1369
+ typedef struct _AT91S_CAN {
1370
+ AT91_REG CAN_MR; // Mode Register
1371
+ AT91_REG CAN_IER; // Interrupt Enable Register
1372
+ AT91_REG CAN_IDR; // Interrupt Disable Register
1373
+ AT91_REG CAN_IMR; // Interrupt Mask Register
1374
+ AT91_REG CAN_SR; // Status Register
1375
+ AT91_REG CAN_BR; // Baudrate Register
1376
+ AT91_REG CAN_TIM; // Timer Register
1377
+ AT91_REG CAN_TIMESTP; // Time Stamp Register
1378
+ AT91_REG CAN_ECR; // Error Counter Register
1379
+ AT91_REG CAN_TCR; // Transfer Command Register
1380
+ AT91_REG CAN_ACR; // Abort Command Register
1381
+ AT91_REG Reserved0[52]; //
1382
+ AT91_REG CAN_VR; // Version Register
1383
+ AT91_REG Reserved1[64]; //
1384
+ AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
1385
+ AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
1386
+ AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
1387
+ AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
1388
+ AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
1389
+ AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
1390
+ AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
1391
+ AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
1392
+ AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
1393
+ AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
1394
+ AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
1395
+ AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
1396
+ AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
1397
+ AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
1398
+ AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
1399
+ AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
1400
+ } AT91S_CAN, *AT91PS_CAN;
1401
+
1402
+ // -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
1403
+ #define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable
1404
+ #define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode
1405
+ #define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
1406
+ #define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame
1407
+ #define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
1408
+ #define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
1409
+ #define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze
1410
+ #define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat
1411
+ // -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
1412
+ #define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag
1413
+ #define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag
1414
+ #define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag
1415
+ #define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag
1416
+ #define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag
1417
+ #define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag
1418
+ #define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag
1419
+ #define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag
1420
+ #define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag
1421
+ #define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag
1422
+ #define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
1423
+ #define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
1424
+ #define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
1425
+ #define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
1426
+ #define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
1427
+ #define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
1428
+ #define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
1429
+ #define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
1430
+ #define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
1431
+ #define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
1432
+ #define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
1433
+ #define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
1434
+ #define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
1435
+ #define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
1436
+ #define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error
1437
+ #define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
1438
+ #define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
1439
+ #define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error
1440
+ #define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error
1441
+ // -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
1442
+ // -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
1443
+ // -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
1444
+ #define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
1445
+ #define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
1446
+ #define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
1447
+ // -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
1448
+ #define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment
1449
+ #define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment
1450
+ #define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment
1451
+ #define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
1452
+ #define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
1453
+ #define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
1454
+ // -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
1455
+ #define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field
1456
+ // -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
1457
+ // -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
1458
+ #define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter
1459
+ #define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
1460
+ // -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
1461
+ #define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
1462
+ // -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
1463
+
1464
+ // *****************************************************************************
1465
+ // SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
1466
+ // *****************************************************************************
1467
+ typedef struct _AT91S_EMAC {
1468
+ AT91_REG EMAC_NCR; // Network Control Register
1469
+ AT91_REG EMAC_NCFGR; // Network Configuration Register
1470
+ AT91_REG EMAC_NSR; // Network Status Register
1471
+ AT91_REG Reserved0[2]; //
1472
+ AT91_REG EMAC_TSR; // Transmit Status Register
1473
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
1474
+ AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
1475
+ AT91_REG EMAC_RSR; // Receive Status Register
1476
+ AT91_REG EMAC_ISR; // Interrupt Status Register
1477
+ AT91_REG EMAC_IER; // Interrupt Enable Register
1478
+ AT91_REG EMAC_IDR; // Interrupt Disable Register
1479
+ AT91_REG EMAC_IMR; // Interrupt Mask Register
1480
+ AT91_REG EMAC_MAN; // PHY Maintenance Register
1481
+ AT91_REG EMAC_PTR; // Pause Time Register
1482
+ AT91_REG EMAC_PFR; // Pause Frames received Register
1483
+ AT91_REG EMAC_FTO; // Frames Transmitted OK Register
1484
+ AT91_REG EMAC_SCF; // Single Collision Frame Register
1485
+ AT91_REG EMAC_MCF; // Multiple Collision Frame Register
1486
+ AT91_REG EMAC_FRO; // Frames Received OK Register
1487
+ AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
1488
+ AT91_REG EMAC_ALE; // Alignment Error Register
1489
+ AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
1490
+ AT91_REG EMAC_LCOL; // Late Collision Register
1491
+ AT91_REG EMAC_ECOL; // Excessive Collision Register
1492
+ AT91_REG EMAC_TUND; // Transmit Underrun Error Register
1493
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register
1494
+ AT91_REG EMAC_RRE; // Receive Ressource Error Register
1495
+ AT91_REG EMAC_ROV; // Receive Overrun Errors Register
1496
+ AT91_REG EMAC_RSE; // Receive Symbol Errors Register
1497
+ AT91_REG EMAC_ELE; // Excessive Length Errors Register
1498
+ AT91_REG EMAC_RJA; // Receive Jabbers Register
1499
+ AT91_REG EMAC_USF; // Undersize Frames Register
1500
+ AT91_REG EMAC_STE; // SQE Test Error Register
1501
+ AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
1502
+ AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
1503
+ AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
1504
+ AT91_REG EMAC_HRT; // Hash Address Top[63:32]
1505
+ AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
1506
+ AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
1507
+ AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
1508
+ AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
1509
+ AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
1510
+ AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
1511
+ AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
1512
+ AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
1513
+ AT91_REG EMAC_TID; // Type ID Checking Register
1514
+ AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
1515
+ AT91_REG EMAC_USRIO; // USER Input/Output Register
1516
+ AT91_REG EMAC_WOL; // Wake On LAN Register
1517
+ AT91_REG Reserved1[13]; //
1518
+ AT91_REG EMAC_REV; // Revision Register
1519
+ } AT91S_EMAC, *AT91PS_EMAC;
1520
+
1521
+ // -------- EMAC_NCR : (EMAC Offset: 0x0) --------
1522
+ #define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
1523
+ #define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
1524
+ #define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
1525
+ #define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
1526
+ #define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
1527
+ #define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
1528
+ #define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
1529
+ #define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
1530
+ #define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
1531
+ #define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission.
1532
+ #define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
1533
+ #define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
1534
+ #define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
1535
+ // -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
1536
+ #define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
1537
+ #define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
1538
+ #define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames.
1539
+ #define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
1540
+ #define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
1541
+ #define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable
1542
+ #define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
1543
+ #define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
1544
+ #define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
1545
+ #define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
1546
+ #define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
1547
+ #define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
1548
+ #define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
1549
+ #define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
1550
+ #define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
1551
+ #define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC)
1552
+ #define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC)
1553
+ #define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
1554
+ #define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
1555
+ #define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
1556
+ #define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
1557
+ #define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
1558
+ #define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
1559
+ #define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC)
1560
+ #define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
1561
+ // -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
1562
+ #define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC)
1563
+ #define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
1564
+ #define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
1565
+ // -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
1566
+ #define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC)
1567
+ #define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
1568
+ #define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC)
1569
+ #define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go
1570
+ #define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame
1571
+ #define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
1572
+ #define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
1573
+ // -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
1574
+ #define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
1575
+ #define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
1576
+ #define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC)
1577
+ // -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
1578
+ #define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC)
1579
+ #define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC)
1580
+ #define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC)
1581
+ #define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC)
1582
+ #define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC)
1583
+ #define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC)
1584
+ #define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC)
1585
+ #define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC)
1586
+ #define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
1587
+ #define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
1588
+ #define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
1589
+ #define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC)
1590
+ #define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC)
1591
+ // -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
1592
+ // -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
1593
+ // -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
1594
+ // -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
1595
+ #define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
1596
+ #define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
1597
+ #define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
1598
+ #define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
1599
+ #define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
1600
+ #define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC)
1601
+ // -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
1602
+ #define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII
1603
+ #define AT91C_EMAC_CLKEN ((unsigned int) 0x1 << 1) // (EMAC) Clock Enable
1604
+ // -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
1605
+ #define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address
1606
+ #define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
1607
+ #define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
1608
+ #define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
1609
+ // -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
1610
+ #define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC)
1611
+ #define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC)
1612
+
1613
+ // *****************************************************************************
1614
+ // SOFTWARE API DEFINITION FOR Analog to Digital Convertor
1615
+ // *****************************************************************************
1616
+ typedef struct _AT91S_ADC {
1617
+ AT91_REG ADC_CR; // ADC Control Register
1618
+ AT91_REG ADC_MR; // ADC Mode Register
1619
+ AT91_REG Reserved0[2]; //
1620
+ AT91_REG ADC_CHER; // ADC Channel Enable Register
1621
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register
1622
+ AT91_REG ADC_CHSR; // ADC Channel Status Register
1623
+ AT91_REG ADC_SR; // ADC Status Register
1624
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register
1625
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register
1626
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register
1627
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register
1628
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0
1629
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1
1630
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2
1631
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3
1632
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4
1633
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5
1634
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6
1635
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7
1636
+ AT91_REG Reserved1[44]; //
1637
+ AT91_REG ADC_RPR; // Receive Pointer Register
1638
+ AT91_REG ADC_RCR; // Receive Counter Register
1639
+ AT91_REG ADC_TPR; // Transmit Pointer Register
1640
+ AT91_REG ADC_TCR; // Transmit Counter Register
1641
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register
1642
+ AT91_REG ADC_RNCR; // Receive Next Counter Register
1643
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register
1644
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register
1645
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register
1646
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register
1647
+ } AT91S_ADC, *AT91PS_ADC;
1648
+
1649
+ // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
1650
+ #define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
1651
+ #define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
1652
+ // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
1653
+ #define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
1654
+ #define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
1655
+ #define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
1656
+ #define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
1657
+ #define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
1658
+ #define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
1659
+ #define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
1660
+ #define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
1661
+ #define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
1662
+ #define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
1663
+ #define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
1664
+ #define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
1665
+ #define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
1666
+ #define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
1667
+ #define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
1668
+ #define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
1669
+ #define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
1670
+ #define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
1671
+ #define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
1672
+ #define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
1673
+ // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
1674
+ #define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
1675
+ #define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
1676
+ #define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
1677
+ #define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
1678
+ #define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
1679
+ #define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
1680
+ #define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
1681
+ #define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
1682
+ // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
1683
+ // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
1684
+ // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
1685
+ #define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
1686
+ #define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
1687
+ #define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
1688
+ #define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
1689
+ #define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
1690
+ #define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
1691
+ #define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
1692
+ #define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
1693
+ #define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
1694
+ #define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
1695
+ #define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
1696
+ #define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
1697
+ #define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
1698
+ #define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
1699
+ #define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
1700
+ #define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
1701
+ #define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
1702
+ #define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
1703
+ #define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
1704
+ #define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
1705
+ // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
1706
+ #define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
1707
+ // -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
1708
+ // -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
1709
+ // -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
1710
+ // -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
1711
+ #define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
1712
+ // -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
1713
+ // -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
1714
+ // -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
1715
+ // -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
1716
+ // -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
1717
+ // -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
1718
+ // -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
1719
+
1720
+ // *****************************************************************************
1721
+ // REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
1722
+ // *****************************************************************************
1723
+ // ========== Register definition for SYS peripheral ==========
1724
+ // ========== Register definition for AIC peripheral ==========
1725
+ #define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
1726
+ #define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
1727
+ #define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
1728
+ #define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
1729
+ #define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
1730
+ #define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
1731
+ #define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
1732
+ #define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
1733
+ #define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
1734
+ #define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
1735
+ #define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
1736
+ #define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
1737
+ #define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
1738
+ #define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
1739
+ #define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
1740
+ #define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
1741
+ #define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
1742
+ #define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
1743
+ // ========== Register definition for PDC_DBGU peripheral ==========
1744
+ #define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
1745
+ #define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
1746
+ #define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
1747
+ #define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
1748
+ #define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
1749
+ #define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
1750
+ #define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
1751
+ #define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
1752
+ #define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
1753
+ #define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
1754
+ // ========== Register definition for DBGU peripheral ==========
1755
+ #define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
1756
+ #define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
1757
+ #define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
1758
+ #define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
1759
+ #define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
1760
+ #define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
1761
+ #define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
1762
+ #define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
1763
+ #define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
1764
+ #define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
1765
+ #define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
1766
+ #define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
1767
+ // ========== Register definition for PIOA peripheral ==========
1768
+ #define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
1769
+ #define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
1770
+ #define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
1771
+ #define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
1772
+ #define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
1773
+ #define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
1774
+ #define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
1775
+ #define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
1776
+ #define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
1777
+ #define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
1778
+ #define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
1779
+ #define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
1780
+ #define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
1781
+ #define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
1782
+ #define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
1783
+ #define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
1784
+ #define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
1785
+ #define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
1786
+ #define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
1787
+ #define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
1788
+ #define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
1789
+ #define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
1790
+ #define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
1791
+ #define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
1792
+ #define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
1793
+ #define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
1794
+ #define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
1795
+ #define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
1796
+ #define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
1797
+ // ========== Register definition for PIOB peripheral ==========
1798
+ #define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
1799
+ #define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
1800
+ #define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
1801
+ #define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
1802
+ #define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
1803
+ #define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
1804
+ #define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
1805
+ #define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
1806
+ #define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
1807
+ #define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
1808
+ #define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
1809
+ #define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
1810
+ #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
1811
+ #define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
1812
+ #define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
1813
+ #define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
1814
+ #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
1815
+ #define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
1816
+ #define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
1817
+ #define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
1818
+ #define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
1819
+ #define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
1820
+ #define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
1821
+ #define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
1822
+ #define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
1823
+ #define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
1824
+ #define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
1825
+ #define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
1826
+ #define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
1827
+ // ========== Register definition for CKGR peripheral ==========
1828
+ #define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
1829
+ #define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
1830
+ #define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
1831
+ // ========== Register definition for PMC peripheral ==========
1832
+ #define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
1833
+ #define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
1834
+ #define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
1835
+ #define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
1836
+ #define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
1837
+ #define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
1838
+ #define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
1839
+ #define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
1840
+ #define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
1841
+ #define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
1842
+ #define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
1843
+ #define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
1844
+ #define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
1845
+ #define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
1846
+ #define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
1847
+ // ========== Register definition for RSTC peripheral ==========
1848
+ #define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
1849
+ #define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
1850
+ #define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
1851
+ // ========== Register definition for RTTC peripheral ==========
1852
+ #define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
1853
+ #define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
1854
+ #define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
1855
+ #define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
1856
+ // ========== Register definition for PITC peripheral ==========
1857
+ #define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
1858
+ #define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
1859
+ #define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
1860
+ #define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
1861
+ // ========== Register definition for WDTC peripheral ==========
1862
+ #define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
1863
+ #define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
1864
+ #define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
1865
+ // ========== Register definition for VREG peripheral ==========
1866
+ #define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
1867
+ // ========== Register definition for MC peripheral ==========
1868
+ #define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
1869
+ #define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
1870
+ #define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
1871
+ #define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
1872
+ #define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
1873
+ #define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
1874
+ // ========== Register definition for PDC_SPI1 peripheral ==========
1875
+ #define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
1876
+ #define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
1877
+ #define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
1878
+ #define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
1879
+ #define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
1880
+ #define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
1881
+ #define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
1882
+ #define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
1883
+ #define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
1884
+ #define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
1885
+ // ========== Register definition for SPI1 peripheral ==========
1886
+ #define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
1887
+ #define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
1888
+ #define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
1889
+ #define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
1890
+ #define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
1891
+ #define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
1892
+ #define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
1893
+ #define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
1894
+ #define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
1895
+ // ========== Register definition for PDC_SPI0 peripheral ==========
1896
+ #define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
1897
+ #define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
1898
+ #define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
1899
+ #define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
1900
+ #define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
1901
+ #define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
1902
+ #define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
1903
+ #define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
1904
+ #define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
1905
+ #define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
1906
+ // ========== Register definition for SPI0 peripheral ==========
1907
+ #define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
1908
+ #define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
1909
+ #define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
1910
+ #define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
1911
+ #define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
1912
+ #define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
1913
+ #define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
1914
+ #define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
1915
+ #define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
1916
+ // ========== Register definition for PDC_US1 peripheral ==========
1917
+ #define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
1918
+ #define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
1919
+ #define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
1920
+ #define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
1921
+ #define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
1922
+ #define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
1923
+ #define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
1924
+ #define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
1925
+ #define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
1926
+ #define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
1927
+ // ========== Register definition for US1 peripheral ==========
1928
+ #define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
1929
+ #define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
1930
+ #define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
1931
+ #define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
1932
+ #define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
1933
+ #define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
1934
+ #define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
1935
+ #define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
1936
+ #define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
1937
+ #define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
1938
+ #define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
1939
+ #define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
1940
+ #define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
1941
+ #define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
1942
+ // ========== Register definition for PDC_US0 peripheral ==========
1943
+ #define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
1944
+ #define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
1945
+ #define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
1946
+ #define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
1947
+ #define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
1948
+ #define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
1949
+ #define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
1950
+ #define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
1951
+ #define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
1952
+ #define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
1953
+ // ========== Register definition for US0 peripheral ==========
1954
+ #define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
1955
+ #define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
1956
+ #define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
1957
+ #define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
1958
+ #define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
1959
+ #define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
1960
+ #define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
1961
+ #define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
1962
+ #define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
1963
+ #define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
1964
+ #define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
1965
+ #define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
1966
+ #define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
1967
+ #define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
1968
+ // ========== Register definition for PDC_SSC peripheral ==========
1969
+ #define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
1970
+ #define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
1971
+ #define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
1972
+ #define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
1973
+ #define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
1974
+ #define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
1975
+ #define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
1976
+ #define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
1977
+ #define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
1978
+ #define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
1979
+ // ========== Register definition for SSC peripheral ==========
1980
+ #define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
1981
+ #define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
1982
+ #define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
1983
+ #define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
1984
+ #define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
1985
+ #define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
1986
+ #define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
1987
+ #define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
1988
+ #define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
1989
+ #define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
1990
+ #define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
1991
+ #define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
1992
+ #define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
1993
+ #define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
1994
+ // ========== Register definition for TWI peripheral ==========
1995
+ #define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
1996
+ #define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
1997
+ #define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
1998
+ #define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
1999
+ #define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
2000
+ #define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
2001
+ #define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
2002
+ #define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
2003
+ #define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
2004
+ #define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
2005
+ // ========== Register definition for PWMC_CH3 peripheral ==========
2006
+ #define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
2007
+ #define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
2008
+ #define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
2009
+ #define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
2010
+ #define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
2011
+ #define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
2012
+ // ========== Register definition for PWMC_CH2 peripheral ==========
2013
+ #define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
2014
+ #define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
2015
+ #define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
2016
+ #define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
2017
+ #define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
2018
+ #define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
2019
+ // ========== Register definition for PWMC_CH1 peripheral ==========
2020
+ #define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
2021
+ #define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
2022
+ #define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
2023
+ #define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
2024
+ #define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
2025
+ #define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
2026
+ // ========== Register definition for PWMC_CH0 peripheral ==========
2027
+ #define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
2028
+ #define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
2029
+ #define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
2030
+ #define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
2031
+ #define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
2032
+ #define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
2033
+ // ========== Register definition for PWMC peripheral ==========
2034
+ #define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
2035
+ #define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
2036
+ #define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
2037
+ #define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
2038
+ #define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
2039
+ #define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
2040
+ #define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
2041
+ #define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
2042
+ #define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
2043
+ // ========== Register definition for UDP peripheral ==========
2044
+ #define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
2045
+ #define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
2046
+ #define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
2047
+ #define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
2048
+ #define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
2049
+ #define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
2050
+ #define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
2051
+ #define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
2052
+ #define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
2053
+ #define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
2054
+ #define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
2055
+ #define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
2056
+ // ========== Register definition for TC0 peripheral ==========
2057
+ #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
2058
+ #define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
2059
+ #define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
2060
+ #define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
2061
+ #define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
2062
+ #define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
2063
+ #define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
2064
+ #define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
2065
+ #define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
2066
+ #define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
2067
+ // ========== Register definition for TC1 peripheral ==========
2068
+ #define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
2069
+ #define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
2070
+ #define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
2071
+ #define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
2072
+ #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
2073
+ #define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
2074
+ #define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
2075
+ #define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
2076
+ #define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
2077
+ #define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
2078
+ // ========== Register definition for TC2 peripheral ==========
2079
+ #define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
2080
+ #define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
2081
+ #define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
2082
+ #define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
2083
+ #define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
2084
+ #define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
2085
+ #define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
2086
+ #define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
2087
+ #define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
2088
+ #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
2089
+ // ========== Register definition for TCB peripheral ==========
2090
+ #define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
2091
+ #define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
2092
+ // ========== Register definition for CAN_MB0 peripheral ==========
2093
+ #define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
2094
+ #define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
2095
+ #define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
2096
+ #define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
2097
+ #define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
2098
+ #define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
2099
+ #define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
2100
+ #define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
2101
+ // ========== Register definition for CAN_MB1 peripheral ==========
2102
+ #define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
2103
+ #define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
2104
+ #define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
2105
+ #define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
2106
+ #define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
2107
+ #define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
2108
+ #define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
2109
+ #define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
2110
+ // ========== Register definition for CAN_MB2 peripheral ==========
2111
+ #define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
2112
+ #define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
2113
+ #define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
2114
+ #define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
2115
+ #define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
2116
+ #define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
2117
+ #define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
2118
+ #define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
2119
+ // ========== Register definition for CAN_MB3 peripheral ==========
2120
+ #define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
2121
+ #define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
2122
+ #define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
2123
+ #define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
2124
+ #define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
2125
+ #define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
2126
+ #define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
2127
+ #define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
2128
+ // ========== Register definition for CAN_MB4 peripheral ==========
2129
+ #define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
2130
+ #define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
2131
+ #define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
2132
+ #define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
2133
+ #define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
2134
+ #define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
2135
+ #define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
2136
+ #define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
2137
+ // ========== Register definition for CAN_MB5 peripheral ==========
2138
+ #define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
2139
+ #define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
2140
+ #define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
2141
+ #define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
2142
+ #define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
2143
+ #define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
2144
+ #define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
2145
+ #define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
2146
+ // ========== Register definition for CAN_MB6 peripheral ==========
2147
+ #define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
2148
+ #define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
2149
+ #define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
2150
+ #define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
2151
+ #define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
2152
+ #define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
2153
+ #define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
2154
+ #define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
2155
+ // ========== Register definition for CAN_MB7 peripheral ==========
2156
+ #define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
2157
+ #define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
2158
+ #define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
2159
+ #define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
2160
+ #define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
2161
+ #define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
2162
+ #define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
2163
+ #define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
2164
+ // ========== Register definition for CAN peripheral ==========
2165
+ #define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
2166
+ #define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
2167
+ #define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
2168
+ #define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
2169
+ #define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
2170
+ #define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
2171
+ #define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
2172
+ #define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
2173
+ #define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
2174
+ #define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
2175
+ #define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
2176
+ #define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
2177
+ // ========== Register definition for EMAC peripheral ==========
2178
+ #define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
2179
+ #define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
2180
+ #define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
2181
+ #define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
2182
+ #define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
2183
+ #define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
2184
+ #define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
2185
+ #define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
2186
+ #define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
2187
+ #define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
2188
+ #define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
2189
+ #define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
2190
+ #define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
2191
+ #define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
2192
+ #define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
2193
+ #define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
2194
+ #define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
2195
+ #define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
2196
+ #define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
2197
+ #define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
2198
+ #define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
2199
+ #define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
2200
+ #define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
2201
+ #define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
2202
+ #define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
2203
+ #define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
2204
+ #define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
2205
+ #define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
2206
+ #define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
2207
+ #define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
2208
+ #define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
2209
+ #define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
2210
+ #define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
2211
+ #define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
2212
+ #define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
2213
+ #define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
2214
+ #define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
2215
+ #define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
2216
+ #define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
2217
+ #define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
2218
+ #define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
2219
+ #define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
2220
+ #define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
2221
+ #define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
2222
+ #define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
2223
+ #define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
2224
+ #define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
2225
+ #define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
2226
+ #define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
2227
+ // ========== Register definition for PDC_ADC peripheral ==========
2228
+ #define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
2229
+ #define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
2230
+ #define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
2231
+ #define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
2232
+ #define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
2233
+ #define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
2234
+ #define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
2235
+ #define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
2236
+ #define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
2237
+ #define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
2238
+ // ========== Register definition for ADC peripheral ==========
2239
+ #define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
2240
+ #define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
2241
+ #define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
2242
+ #define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
2243
+ #define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
2244
+ #define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
2245
+ #define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
2246
+ #define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
2247
+ #define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
2248
+ #define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
2249
+ #define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
2250
+ #define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
2251
+ #define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
2252
+ #define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
2253
+ #define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
2254
+ #define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
2255
+ #define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
2256
+ #define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
2257
+
2258
+ // *****************************************************************************
2259
+ // PIO DEFINITIONS FOR AT91SAM7X256
2260
+ // *****************************************************************************
2261
+ #define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
2262
+ #define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
2263
+ #define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
2264
+ #define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
2265
+ #define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
2266
+ #define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
2267
+ #define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
2268
+ #define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
2269
+ #define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
2270
+ #define AT91C_PA12_SPI0_NPCS0 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
2271
+ #define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
2272
+ #define AT91C_PA13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
2273
+ #define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
2274
+ #define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
2275
+ #define AT91C_PA14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
2276
+ #define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
2277
+ #define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
2278
+ #define AT91C_PA15_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
2279
+ #define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
2280
+ #define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
2281
+ #define AT91C_PA16_SPI0_MISO ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
2282
+ #define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
2283
+ #define AT91C_PA17_SPI0_MOSI ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
2284
+ #define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
2285
+ #define AT91C_PA18_SPI0_SPCK ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
2286
+ #define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
2287
+ #define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
2288
+ #define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
2289
+ #define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
2290
+ #define AT91C_PA2_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
2291
+ #define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
2292
+ #define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
2293
+ #define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
2294
+ #define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
2295
+ #define AT91C_PA21_SPI1_NPCS0 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
2296
+ #define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
2297
+ #define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
2298
+ #define AT91C_PA22_SPI1_SPCK ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
2299
+ #define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
2300
+ #define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
2301
+ #define AT91C_PA23_SPI1_MOSI ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
2302
+ #define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
2303
+ #define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
2304
+ #define AT91C_PA24_SPI1_MISO ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
2305
+ #define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
2306
+ #define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
2307
+ #define AT91C_PA25_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
2308
+ #define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
2309
+ #define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
2310
+ #define AT91C_PA26_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
2311
+ #define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
2312
+ #define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
2313
+ #define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
2314
+ #define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
2315
+ #define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
2316
+ #define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
2317
+ #define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
2318
+ #define AT91C_PA29_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
2319
+ #define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
2320
+ #define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
2321
+ #define AT91C_PA3_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
2322
+ #define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
2323
+ #define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
2324
+ #define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
2325
+ #define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
2326
+ #define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
2327
+ #define AT91C_PA4_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
2328
+ #define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
2329
+ #define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
2330
+ #define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
2331
+ #define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
2332
+ #define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
2333
+ #define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
2334
+ #define AT91C_PA7_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
2335
+ #define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
2336
+ #define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
2337
+ #define AT91C_PA8_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
2338
+ #define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
2339
+ #define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
2340
+ #define AT91C_PA9_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
2341
+ #define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
2342
+ #define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
2343
+ #define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
2344
+ #define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
2345
+ #define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
2346
+ #define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
2347
+ #define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
2348
+ #define AT91C_PB10_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
2349
+ #define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
2350
+ #define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
2351
+ #define AT91C_PB11_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
2352
+ #define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
2353
+ #define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
2354
+ #define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
2355
+ #define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
2356
+ #define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
2357
+ #define AT91C_PB13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
2358
+ #define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
2359
+ #define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
2360
+ #define AT91C_PB14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
2361
+ #define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
2362
+ #define AT91C_PB15_ERXDV_ECRSDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
2363
+ #define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
2364
+ #define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
2365
+ #define AT91C_PB16_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
2366
+ #define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
2367
+ #define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
2368
+ #define AT91C_PB17_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
2369
+ #define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
2370
+ #define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
2371
+ #define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
2372
+ #define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
2373
+ #define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
2374
+ #define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
2375
+ #define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
2376
+ #define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
2377
+ #define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
2378
+ #define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
2379
+ #define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
2380
+ #define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
2381
+ #define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
2382
+ #define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
2383
+ #define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
2384
+ #define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
2385
+ #define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
2386
+ #define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
2387
+ #define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
2388
+ #define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
2389
+ #define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
2390
+ #define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
2391
+ #define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
2392
+ #define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
2393
+ #define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
2394
+ #define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
2395
+ #define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
2396
+ #define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
2397
+ #define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
2398
+ #define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
2399
+ #define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
2400
+ #define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
2401
+ #define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
2402
+ #define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
2403
+ #define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
2404
+ #define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
2405
+ #define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
2406
+ #define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
2407
+ #define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
2408
+ #define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
2409
+ #define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
2410
+ #define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
2411
+ #define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
2412
+ #define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
2413
+ #define AT91C_PB4_ECRS ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
2414
+ #define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
2415
+ #define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
2416
+ #define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
2417
+ #define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
2418
+ #define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
2419
+ #define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
2420
+ #define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
2421
+ #define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
2422
+ #define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
2423
+ #define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
2424
+
2425
+ // *****************************************************************************
2426
+ // PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
2427
+ // *****************************************************************************
2428
+ #define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
2429
+ #define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
2430
+ #define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
2431
+ #define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
2432
+ #define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0
2433
+ #define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1
2434
+ #define AT91C_ID_US0 ((unsigned int) 6) // USART 0
2435
+ #define AT91C_ID_US1 ((unsigned int) 7) // USART 1
2436
+ #define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
2437
+ #define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
2438
+ #define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
2439
+ #define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
2440
+ #define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
2441
+ #define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
2442
+ #define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
2443
+ #define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller
2444
+ #define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC
2445
+ #define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter
2446
+ #define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved
2447
+ #define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved
2448
+ #define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
2449
+ #define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
2450
+ #define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
2451
+ #define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
2452
+ #define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
2453
+ #define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
2454
+ #define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
2455
+ #define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
2456
+ #define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
2457
+ #define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
2458
+ #define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
2459
+ #define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
2460
+ #define AT91C_ALL_INT ((unsigned int) 0xC003FFFF) // ALL VALID INTERRUPTS
2461
+
2462
+ // *****************************************************************************
2463
+ // BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
2464
+ // *****************************************************************************
2465
+ #define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
2466
+ #define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
2467
+ #define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
2468
+ #define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
2469
+ #define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
2470
+ #define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
2471
+ #define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
2472
+ #define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
2473
+ #define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
2474
+ #define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
2475
+ #define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
2476
+ #define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
2477
+ #define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
2478
+ #define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
2479
+ #define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
2480
+ #define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
2481
+ #define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
2482
+ #define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
2483
+ #define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
2484
+ #define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
2485
+ #define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
2486
+ #define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
2487
+ #define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
2488
+ #define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
2489
+ #define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
2490
+ #define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
2491
+ #define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
2492
+ #define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
2493
+ #define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
2494
+ #define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
2495
+ #define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
2496
+ #define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
2497
+ #define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
2498
+ #define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
2499
+ #define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
2500
+ #define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
2501
+ #define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
2502
+ #define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
2503
+ #define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
2504
+ #define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
2505
+ #define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
2506
+ #define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
2507
+ #define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
2508
+ #define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
2509
+ #define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
2510
+ #define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
2511
+ #define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
2512
+
2513
+ // *****************************************************************************
2514
+ // MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
2515
+ // *****************************************************************************
2516
+ // ISRAM
2517
+ #define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
2518
+ #define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbytes)
2519
+ // IFLASH
2520
+ #define AT91C_IFLASH ((char *) 0x00100000) // Internal FLASH base address
2521
+ #define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal FLASH size in byte (256 Kbytes)
2522
+ #define AT91C_IFLASH_PAGE_SIZE ((unsigned int) 256) // Internal FLASH Page Size: 256 bytes
2523
+ #define AT91C_IFLASH_LOCK_REGION_SIZE ((unsigned int) 16384) // Internal FLASH Lock Region Size: 16 Kbytes
2524
+ #define AT91C_IFLASH_NB_OF_PAGES ((unsigned int) 1024) // Internal FLASH Number of Pages: 1024 bytes
2525
+ #define AT91C_IFLASH_NB_OF_LOCK_BITS ((unsigned int) 16) // Internal FLASH Number of Lock Bits: 16 bytes
2526
+ #endif /* __IAR_SYSTEMS_ICC__ */
2527
+
2528
+ #ifdef __IAR_SYSTEMS_ASM__
2529
+
2530
+ // - Hardware register definition
2531
+
2532
+ // - *****************************************************************************
2533
+ // - SOFTWARE API DEFINITION FOR System Peripherals
2534
+ // - *****************************************************************************
2535
+
2536
+ // - *****************************************************************************
2537
+ // - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
2538
+ // - *****************************************************************************
2539
+ // - -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
2540
+ AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level
2541
+ AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level
2542
+ AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level
2543
+ AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type
2544
+ AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive
2545
+ AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive
2546
+ AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
2547
+ AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered
2548
+ AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
2549
+ AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
2550
+ // - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
2551
+ AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status
2552
+ AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status
2553
+ // - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
2554
+ AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode
2555
+ AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask
2556
+
2557
+ // - *****************************************************************************
2558
+ // - SOFTWARE API DEFINITION FOR Peripheral DMA Controller
2559
+ // - *****************************************************************************
2560
+ // - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
2561
+ AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable
2562
+ AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable
2563
+ AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable
2564
+ AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable
2565
+ // - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
2566
+
2567
+ // - *****************************************************************************
2568
+ // - SOFTWARE API DEFINITION FOR Debug Unit
2569
+ // - *****************************************************************************
2570
+ // - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
2571
+ AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver
2572
+ AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter
2573
+ AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable
2574
+ AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable
2575
+ AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable
2576
+ AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable
2577
+ AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits
2578
+ // - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
2579
+ AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type
2580
+ AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity
2581
+ AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity
2582
+ AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space)
2583
+ AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark)
2584
+ AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity
2585
+ AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode
2586
+ AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode
2587
+ AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
2588
+ AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
2589
+ AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
2590
+ AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
2591
+ // - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
2592
+ AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt
2593
+ AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt
2594
+ AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt
2595
+ AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt
2596
+ AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt
2597
+ AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt
2598
+ AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt
2599
+ AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt
2600
+ AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
2601
+ AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
2602
+ AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
2603
+ AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
2604
+ // - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
2605
+ // - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
2606
+ // - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
2607
+ // - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
2608
+ AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG
2609
+
2610
+ // - *****************************************************************************
2611
+ // - SOFTWARE API DEFINITION FOR Parallel Input Output Controler
2612
+ // - *****************************************************************************
2613
+
2614
+ // - *****************************************************************************
2615
+ // - SOFTWARE API DEFINITION FOR Clock Generator Controler
2616
+ // - *****************************************************************************
2617
+ // - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
2618
+ AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable
2619
+ AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass
2620
+ AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time
2621
+ // - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
2622
+ AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency
2623
+ AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
2624
+ // - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
2625
+ AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected
2626
+ AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0
2627
+ AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed
2628
+ AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter
2629
+ AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
2630
+ AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
2631
+ AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
2632
+ AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
2633
+ AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
2634
+ AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
2635
+ AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
2636
+ AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
2637
+ AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
2638
+ AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
2639
+
2640
+ // - *****************************************************************************
2641
+ // - SOFTWARE API DEFINITION FOR Power Management Controler
2642
+ // - *****************************************************************************
2643
+ // - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
2644
+ AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock
2645
+ AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock
2646
+ AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output
2647
+ AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output
2648
+ AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
2649
+ AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output
2650
+ // - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
2651
+ // - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
2652
+ // - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
2653
+ // - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
2654
+ // - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
2655
+ // - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
2656
+ AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection
2657
+ AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected
2658
+ AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected
2659
+ AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected
2660
+ AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler
2661
+ AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock
2662
+ AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2
2663
+ AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4
2664
+ AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8
2665
+ AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16
2666
+ AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32
2667
+ AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64
2668
+ // - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
2669
+ // - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
2670
+ AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask
2671
+ AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask
2672
+ AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
2673
+ AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
2674
+ AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
2675
+ AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
2676
+ AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
2677
+ // - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
2678
+ // - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
2679
+ // - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
2680
+
2681
+ // - *****************************************************************************
2682
+ // - SOFTWARE API DEFINITION FOR Reset Controller Interface
2683
+ // - *****************************************************************************
2684
+ // - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
2685
+ AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset
2686
+ AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset
2687
+ AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset
2688
+ AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password
2689
+ // - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
2690
+ AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status
2691
+ AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status
2692
+ AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type
2693
+ AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising.
2694
+ AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
2695
+ AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
2696
+ AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software.
2697
+ AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low.
2698
+ AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured.
2699
+ AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level
2700
+ AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
2701
+ // - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
2702
+ AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable
2703
+ AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable
2704
+ AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Length
2705
+ AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
2706
+
2707
+ // - *****************************************************************************
2708
+ // - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
2709
+ // - *****************************************************************************
2710
+ // - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
2711
+ AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value
2712
+ AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
2713
+ AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
2714
+ AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
2715
+ // - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
2716
+ AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value
2717
+ // - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
2718
+ AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value
2719
+ // - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
2720
+ AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status
2721
+ AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment
2722
+
2723
+ // - *****************************************************************************
2724
+ // - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
2725
+ // - *****************************************************************************
2726
+ // - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
2727
+ AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value
2728
+ AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
2729
+ AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
2730
+ // - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
2731
+ AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status
2732
+ // - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
2733
+ AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value
2734
+ AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
2735
+ // - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
2736
+
2737
+ // - *****************************************************************************
2738
+ // - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
2739
+ // - *****************************************************************************
2740
+ // - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
2741
+ AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart
2742
+ AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
2743
+ // - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
2744
+ AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart
2745
+ AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
2746
+ AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
2747
+ AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
2748
+ AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
2749
+ AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
2750
+ AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
2751
+ AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
2752
+ // - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
2753
+ AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow
2754
+ AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error
2755
+
2756
+ // - *****************************************************************************
2757
+ // - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
2758
+ // - *****************************************************************************
2759
+ // - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
2760
+ AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode
2761
+
2762
+ // - *****************************************************************************
2763
+ // - SOFTWARE API DEFINITION FOR Memory Controller Interface
2764
+ // - *****************************************************************************
2765
+ // - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
2766
+ AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit
2767
+ // - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
2768
+ AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status
2769
+ AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status
2770
+ AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status
2771
+ AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte
2772
+ AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word
2773
+ AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word
2774
+ AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status
2775
+ AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read
2776
+ AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write
2777
+ AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch
2778
+ AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
2779
+ AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
2780
+ AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
2781
+ AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
2782
+ // - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
2783
+ AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready
2784
+ AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error
2785
+ AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error
2786
+ AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming
2787
+ AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State
2788
+ AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations
2789
+ AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations
2790
+ AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations
2791
+ AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations
2792
+ AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
2793
+ // - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
2794
+ AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command
2795
+ AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
2796
+ AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
2797
+ AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
2798
+ AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
2799
+ AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
2800
+ AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits.
2801
+ AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
2802
+ AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
2803
+ AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number
2804
+ AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key
2805
+ // - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
2806
+ AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status
2807
+ AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status
2808
+ AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status
2809
+ AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
2810
+ AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
2811
+ AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
2812
+ AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
2813
+ AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
2814
+ AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
2815
+ AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
2816
+ AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
2817
+ AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
2818
+ AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
2819
+ AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
2820
+ AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
2821
+ AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
2822
+ AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
2823
+ AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
2824
+ AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
2825
+ AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
2826
+ AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
2827
+ AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
2828
+ AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
2829
+ AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
2830
+ AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
2831
+
2832
+ // - *****************************************************************************
2833
+ // - SOFTWARE API DEFINITION FOR Serial Parallel Interface
2834
+ // - *****************************************************************************
2835
+ // - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
2836
+ AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable
2837
+ AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable
2838
+ AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset
2839
+ AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
2840
+ // - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
2841
+ AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode
2842
+ AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select
2843
+ AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select
2844
+ AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select
2845
+ AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode
2846
+ AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection
2847
+ AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection
2848
+ AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection
2849
+ AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
2850
+ AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
2851
+ // - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
2852
+ AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data
2853
+ AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
2854
+ // - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
2855
+ AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data
2856
+ AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
2857
+ // - -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
2858
+ AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full
2859
+ AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty
2860
+ AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error
2861
+ AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status
2862
+ AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer
2863
+ AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer
2864
+ AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt
2865
+ AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt
2866
+ AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt
2867
+ AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt
2868
+ AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status
2869
+ // - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
2870
+ // - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
2871
+ // - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
2872
+ // - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
2873
+ AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity
2874
+ AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase
2875
+ AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer
2876
+ AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer
2877
+ AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer
2878
+ AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer
2879
+ AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer
2880
+ AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer
2881
+ AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer
2882
+ AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer
2883
+ AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer
2884
+ AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer
2885
+ AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer
2886
+ AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate
2887
+ AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK
2888
+ AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
2889
+
2890
+ // - *****************************************************************************
2891
+ // - SOFTWARE API DEFINITION FOR Usart
2892
+ // - *****************************************************************************
2893
+ // - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
2894
+ AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break
2895
+ AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break
2896
+ AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out
2897
+ AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address
2898
+ AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations
2899
+ AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
2900
+ AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out
2901
+ AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
2902
+ AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
2903
+ AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable
2904
+ AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable
2905
+ // - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
2906
+ AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode
2907
+ AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal
2908
+ AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485
2909
+ AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking
2910
+ AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem
2911
+ AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
2912
+ AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
2913
+ AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA
2914
+ AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking
2915
+ AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
2916
+ AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock
2917
+ AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1
2918
+ AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM)
2919
+ AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK)
2920
+ AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
2921
+ AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits
2922
+ AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits
2923
+ AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits
2924
+ AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits
2925
+ AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select
2926
+ AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits
2927
+ AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit
2928
+ AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
2929
+ AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits
2930
+ AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order
2931
+ AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length
2932
+ AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select
2933
+ AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode
2934
+ AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
2935
+ AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK
2936
+ AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions
2937
+ AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter
2938
+ // - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
2939
+ AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break
2940
+ AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out
2941
+ AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
2942
+ AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge
2943
+ AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
2944
+ AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
2945
+ AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag
2946
+ AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
2947
+ // - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
2948
+ // - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
2949
+ // - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
2950
+ AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input
2951
+ AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input
2952
+ AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input
2953
+ AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input
2954
+
2955
+ // - *****************************************************************************
2956
+ // - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
2957
+ // - *****************************************************************************
2958
+ // - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
2959
+ AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable
2960
+ AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable
2961
+ AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable
2962
+ AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable
2963
+ AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset
2964
+ // - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
2965
+ AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection
2966
+ AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock
2967
+ AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal
2968
+ AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin
2969
+ AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
2970
+ AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
2971
+ AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
2972
+ AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
2973
+ AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion
2974
+ AT91C_SSC_CKG EQU (0x3 << 6) ;- (SSC) Receive/Transmit Clock Gating Selection
2975
+ AT91C_SSC_CKG_NONE EQU (0x0 << 6) ;- (SSC) Receive/Transmit Clock Gating: None, continuous clock
2976
+ AT91C_SSC_CKG_LOW EQU (0x1 << 6) ;- (SSC) Receive/Transmit Clock enabled only if RF Low
2977
+ AT91C_SSC_CKG_HIGH EQU (0x2 << 6) ;- (SSC) Receive/Transmit Clock enabled only if RF High
2978
+ AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection
2979
+ AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
2980
+ AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start
2981
+ AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input
2982
+ AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input
2983
+ AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input
2984
+ AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input
2985
+ AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input
2986
+ AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input
2987
+ AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0
2988
+ AT91C_SSC_STOP EQU (0x1 << 12) ;- (SSC) Receive Stop Selection
2989
+ AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
2990
+ AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
2991
+ // - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
2992
+ AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length
2993
+ AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode
2994
+ AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First
2995
+ AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame
2996
+ AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
2997
+ AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
2998
+ AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
2999
+ AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
3000
+ AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
3001
+ AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
3002
+ AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
3003
+ AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
3004
+ AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
3005
+ // - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
3006
+ // - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
3007
+ AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value
3008
+ AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
3009
+ // - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
3010
+ AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready
3011
+ AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty
3012
+ AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission
3013
+ AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty
3014
+ AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready
3015
+ AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun
3016
+ AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception
3017
+ AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full
3018
+ AT91C_SSC_CP0 EQU (0x1 << 8) ;- (SSC) Compare 0
3019
+ AT91C_SSC_CP1 EQU (0x1 << 9) ;- (SSC) Compare 1
3020
+ AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync
3021
+ AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync
3022
+ AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable
3023
+ AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable
3024
+ // - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
3025
+ // - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
3026
+ // - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
3027
+
3028
+ // - *****************************************************************************
3029
+ // - SOFTWARE API DEFINITION FOR Two-wire Interface
3030
+ // - *****************************************************************************
3031
+ // - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
3032
+ AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition
3033
+ AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition
3034
+ AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled
3035
+ AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled
3036
+ AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset
3037
+ // - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
3038
+ AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size
3039
+ AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address
3040
+ AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address
3041
+ AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address
3042
+ AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address
3043
+ AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction
3044
+ AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address
3045
+ // - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
3046
+ AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider
3047
+ AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider
3048
+ AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider
3049
+ // - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
3050
+ AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed
3051
+ AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY
3052
+ AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY
3053
+ AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error
3054
+ AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error
3055
+ AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged
3056
+ // - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
3057
+ // - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
3058
+ // - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
3059
+
3060
+ // - *****************************************************************************
3061
+ // - SOFTWARE API DEFINITION FOR PWMC Channel Interface
3062
+ // - *****************************************************************************
3063
+ // - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
3064
+ AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
3065
+ AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH)
3066
+ AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH)
3067
+ AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH)
3068
+ AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment
3069
+ AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity
3070
+ AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
3071
+ // - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
3072
+ AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle
3073
+ // - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
3074
+ AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period
3075
+ // - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
3076
+ AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter
3077
+ // - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
3078
+ AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update
3079
+
3080
+ // - *****************************************************************************
3081
+ // - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
3082
+ // - *****************************************************************************
3083
+ // - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
3084
+ AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor.
3085
+ AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A
3086
+ AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC)
3087
+ AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
3088
+ AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
3089
+ AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC)
3090
+ // - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
3091
+ AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0
3092
+ AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1
3093
+ AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2
3094
+ AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3
3095
+ // - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
3096
+ // - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
3097
+ // - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
3098
+ // - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
3099
+ // - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
3100
+ // - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
3101
+
3102
+ // - *****************************************************************************
3103
+ // - SOFTWARE API DEFINITION FOR USB Device Interface
3104
+ // - *****************************************************************************
3105
+ // - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
3106
+ AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
3107
+ AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error
3108
+ AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK
3109
+ // - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
3110
+ AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable
3111
+ AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured
3112
+ AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume
3113
+ AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host
3114
+ AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable
3115
+ // - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
3116
+ AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value
3117
+ AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable
3118
+ // - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
3119
+ AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt
3120
+ AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt
3121
+ AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt
3122
+ AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt
3123
+ AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt
3124
+ AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt
3125
+ AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt
3126
+ AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt
3127
+ AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
3128
+ AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
3129
+ AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
3130
+ // - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
3131
+ // - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
3132
+ // - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
3133
+ AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
3134
+ // - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
3135
+ // - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
3136
+ AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0
3137
+ AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1
3138
+ AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2
3139
+ AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3
3140
+ AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4
3141
+ AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5
3142
+ // - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
3143
+ AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR
3144
+ AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0
3145
+ AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints)
3146
+ AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints)
3147
+ AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready
3148
+ AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
3149
+ AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
3150
+ AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction
3151
+ AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type
3152
+ AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control
3153
+ AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT
3154
+ AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT
3155
+ AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT
3156
+ AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN
3157
+ AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN
3158
+ AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN
3159
+ AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle
3160
+ AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
3161
+ AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
3162
+ // - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
3163
+ AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP)
3164
+ AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON
3165
+
3166
+ // - *****************************************************************************
3167
+ // - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
3168
+ // - *****************************************************************************
3169
+ // - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
3170
+ AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command
3171
+ AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command
3172
+ AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command
3173
+ // - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
3174
+ AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection
3175
+ AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
3176
+ AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
3177
+ AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
3178
+ AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
3179
+ AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
3180
+ AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0
3181
+ AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1
3182
+ AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2
3183
+ AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert
3184
+ AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection
3185
+ AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal
3186
+ AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock
3187
+ AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock
3188
+ AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock
3189
+ AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare
3190
+ AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading
3191
+ AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare
3192
+ AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading
3193
+ AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection
3194
+ AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None
3195
+ AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge
3196
+ AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge
3197
+ AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge
3198
+ AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection
3199
+ AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None
3200
+ AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge
3201
+ AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge
3202
+ AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge
3203
+ AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection
3204
+ AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
3205
+ AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
3206
+ AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
3207
+ AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
3208
+ AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
3209
+ AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable
3210
+ AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection
3211
+ AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
3212
+ AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
3213
+ AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
3214
+ AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
3215
+ AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
3216
+ AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC)
3217
+ AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
3218
+ AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none
3219
+ AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set
3220
+ AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear
3221
+ AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle
3222
+ AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection
3223
+ AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None
3224
+ AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
3225
+ AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
3226
+ AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
3227
+ AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
3228
+ AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none
3229
+ AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set
3230
+ AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear
3231
+ AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle
3232
+ AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection
3233
+ AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None
3234
+ AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
3235
+ AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
3236
+ AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
3237
+ AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
3238
+ AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none
3239
+ AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set
3240
+ AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear
3241
+ AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle
3242
+ AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
3243
+ AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none
3244
+ AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set
3245
+ AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear
3246
+ AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle
3247
+ AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
3248
+ AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none
3249
+ AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set
3250
+ AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear
3251
+ AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle
3252
+ AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
3253
+ AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none
3254
+ AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set
3255
+ AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear
3256
+ AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle
3257
+ AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
3258
+ AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none
3259
+ AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set
3260
+ AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear
3261
+ AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle
3262
+ AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
3263
+ AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none
3264
+ AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set
3265
+ AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear
3266
+ AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle
3267
+ // - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
3268
+ AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow
3269
+ AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun
3270
+ AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare
3271
+ AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare
3272
+ AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare
3273
+ AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading
3274
+ AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading
3275
+ AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger
3276
+ AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling
3277
+ AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror
3278
+ AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror
3279
+ // - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
3280
+ // - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
3281
+ // - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
3282
+
3283
+ // - *****************************************************************************
3284
+ // - SOFTWARE API DEFINITION FOR Timer Counter Interface
3285
+ // - *****************************************************************************
3286
+ // - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
3287
+ AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command
3288
+ // - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
3289
+ AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection
3290
+ AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0
3291
+ AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0
3292
+ AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0
3293
+ AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0
3294
+ AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection
3295
+ AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1
3296
+ AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1
3297
+ AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1
3298
+ AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1
3299
+ AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection
3300
+ AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2
3301
+ AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2
3302
+ AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2
3303
+ AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2
3304
+
3305
+ // - *****************************************************************************
3306
+ // - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
3307
+ // - *****************************************************************************
3308
+ // - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
3309
+ AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark
3310
+ AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority
3311
+ AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type
3312
+ AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB)
3313
+ AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB)
3314
+ AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB)
3315
+ AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB)
3316
+ AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB)
3317
+ AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB)
3318
+ // - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
3319
+ AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode
3320
+ AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode
3321
+ AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version
3322
+ // - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
3323
+ // - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
3324
+ // - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
3325
+ AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value
3326
+ AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code
3327
+ AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request
3328
+ AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort
3329
+ AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready
3330
+ AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored
3331
+ // - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
3332
+ // - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
3333
+ // - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
3334
+ AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox
3335
+ AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command
3336
+
3337
+ // - *****************************************************************************
3338
+ // - SOFTWARE API DEFINITION FOR Control Area Network Interface
3339
+ // - *****************************************************************************
3340
+ // - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
3341
+ AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable
3342
+ AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode
3343
+ AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
3344
+ AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame
3345
+ AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame
3346
+ AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode
3347
+ AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze
3348
+ AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat
3349
+ // - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
3350
+ AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag
3351
+ AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag
3352
+ AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag
3353
+ AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag
3354
+ AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag
3355
+ AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag
3356
+ AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag
3357
+ AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag
3358
+ AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag
3359
+ AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag
3360
+ AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag
3361
+ AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag
3362
+ AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag
3363
+ AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag
3364
+ AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag
3365
+ AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag
3366
+ AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag
3367
+ AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag
3368
+ AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag
3369
+ AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag
3370
+ AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag
3371
+ AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag
3372
+ AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag
3373
+ AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag
3374
+ AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error
3375
+ AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error
3376
+ AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error
3377
+ AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error
3378
+ AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error
3379
+ // - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
3380
+ // - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
3381
+ // - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
3382
+ AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy
3383
+ AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy
3384
+ AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy
3385
+ // - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
3386
+ AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment
3387
+ AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment
3388
+ AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment
3389
+ AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment
3390
+ AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler
3391
+ AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode
3392
+ // - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
3393
+ AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field
3394
+ // - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
3395
+ // - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
3396
+ AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter
3397
+ AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter
3398
+ // - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
3399
+ AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field
3400
+ // - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
3401
+
3402
+ // - *****************************************************************************
3403
+ // - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
3404
+ // - *****************************************************************************
3405
+ // - -------- EMAC_NCR : (EMAC Offset: 0x0) --------
3406
+ AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
3407
+ AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local.
3408
+ AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable.
3409
+ AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable.
3410
+ AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable.
3411
+ AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers.
3412
+ AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers.
3413
+ AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers.
3414
+ AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure.
3415
+ AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission.
3416
+ AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt.
3417
+ AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame
3418
+ AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame
3419
+ // - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
3420
+ AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed.
3421
+ AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex.
3422
+ AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames.
3423
+ AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames.
3424
+ AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast.
3425
+ AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable
3426
+ AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable.
3427
+ AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes.
3428
+ AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable.
3429
+ AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC)
3430
+ AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8
3431
+ AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16
3432
+ AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32
3433
+ AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64
3434
+ AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC)
3435
+ AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC)
3436
+ AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC)
3437
+ AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer
3438
+ AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer
3439
+ AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer
3440
+ AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer
3441
+ AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable
3442
+ AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS
3443
+ AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC)
3444
+ AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS
3445
+ // - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
3446
+ AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC)
3447
+ AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC)
3448
+ AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC)
3449
+ // - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
3450
+ AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC)
3451
+ AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC)
3452
+ AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC)
3453
+ AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go
3454
+ AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame
3455
+ AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC)
3456
+ AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC)
3457
+ // - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
3458
+ AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC)
3459
+ AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC)
3460
+ AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC)
3461
+ // - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
3462
+ AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC)
3463
+ AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC)
3464
+ AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC)
3465
+ AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC)
3466
+ AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC)
3467
+ AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC)
3468
+ AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC)
3469
+ AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC)
3470
+ AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC)
3471
+ AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC)
3472
+ AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC)
3473
+ AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC)
3474
+ AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC)
3475
+ // - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
3476
+ // - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
3477
+ // - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
3478
+ // - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
3479
+ AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC)
3480
+ AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC)
3481
+ AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC)
3482
+ AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC)
3483
+ AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC)
3484
+ AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC)
3485
+ // - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
3486
+ AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII
3487
+ AT91C_EMAC_CLKEN EQU (0x1 << 1) ;- (EMAC) Clock Enable
3488
+ // - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
3489
+ AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address
3490
+ AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable
3491
+ AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable
3492
+ AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable
3493
+ // - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
3494
+ AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC)
3495
+ AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC)
3496
+
3497
+ // - *****************************************************************************
3498
+ // - SOFTWARE API DEFINITION FOR Analog to Digital Convertor
3499
+ // - *****************************************************************************
3500
+ // - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
3501
+ AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset
3502
+ AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion
3503
+ // - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
3504
+ AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable
3505
+ AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
3506
+ AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
3507
+ AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection
3508
+ AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0
3509
+ AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1
3510
+ AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2
3511
+ AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3
3512
+ AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4
3513
+ AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5
3514
+ AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger
3515
+ AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution.
3516
+ AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution
3517
+ AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution
3518
+ AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode
3519
+ AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode
3520
+ AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode
3521
+ AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection
3522
+ AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time
3523
+ AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time
3524
+ // - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
3525
+ AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0
3526
+ AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1
3527
+ AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2
3528
+ AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3
3529
+ AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4
3530
+ AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5
3531
+ AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6
3532
+ AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7
3533
+ // - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
3534
+ // - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
3535
+ // - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
3536
+ AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion
3537
+ AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion
3538
+ AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion
3539
+ AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion
3540
+ AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion
3541
+ AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion
3542
+ AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion
3543
+ AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion
3544
+ AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error
3545
+ AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error
3546
+ AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error
3547
+ AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error
3548
+ AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error
3549
+ AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error
3550
+ AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error
3551
+ AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error
3552
+ AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready
3553
+ AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun
3554
+ AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
3555
+ AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
3556
+ // - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
3557
+ AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted
3558
+ // - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
3559
+ // - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
3560
+ // - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
3561
+ // - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
3562
+ AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data
3563
+ // - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
3564
+ // - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
3565
+ // - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
3566
+ // - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
3567
+ // - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
3568
+ // - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
3569
+ // - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
3570
+
3571
+ // - *****************************************************************************
3572
+ // - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
3573
+ // - *****************************************************************************
3574
+ // - ========== Register definition for SYS peripheral ==========
3575
+ // - ========== Register definition for AIC peripheral ==========
3576
+ AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
3577
+ AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register
3578
+ AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
3579
+ AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
3580
+ AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
3581
+ AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register
3582
+ AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
3583
+ AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
3584
+ AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
3585
+ AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
3586
+ AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
3587
+ AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
3588
+ AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
3589
+ AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
3590
+ AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
3591
+ AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
3592
+ AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
3593
+ AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
3594
+ // - ========== Register definition for PDC_DBGU peripheral ==========
3595
+ AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
3596
+ AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
3597
+ AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
3598
+ AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
3599
+ AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
3600
+ AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
3601
+ AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
3602
+ AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
3603
+ AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
3604
+ AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
3605
+ // - ========== Register definition for DBGU peripheral ==========
3606
+ AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
3607
+ AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
3608
+ AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
3609
+ AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
3610
+ AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
3611
+ AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register
3612
+ AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
3613
+ AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register
3614
+ AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
3615
+ AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
3616
+ AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
3617
+ AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
3618
+ // - ========== Register definition for PIOA peripheral ==========
3619
+ AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
3620
+ AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
3621
+ AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
3622
+ AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
3623
+ AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
3624
+ AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
3625
+ AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
3626
+ AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
3627
+ AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
3628
+ AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
3629
+ AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
3630
+ AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
3631
+ AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
3632
+ AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
3633
+ AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
3634
+ AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register
3635
+ AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
3636
+ AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
3637
+ AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
3638
+ AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
3639
+ AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register
3640
+ AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register
3641
+ AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
3642
+ AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
3643
+ AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
3644
+ AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
3645
+ AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
3646
+ AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
3647
+ AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
3648
+ // - ========== Register definition for PIOB peripheral ==========
3649
+ AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
3650
+ AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
3651
+ AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
3652
+ AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
3653
+ AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register
3654
+ AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
3655
+ AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
3656
+ AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
3657
+ AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
3658
+ AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
3659
+ AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
3660
+ AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
3661
+ AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
3662
+ AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
3663
+ AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
3664
+ AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
3665
+ AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
3666
+ AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
3667
+ AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
3668
+ AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
3669
+ AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
3670
+ AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
3671
+ AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register
3672
+ AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
3673
+ AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
3674
+ AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register
3675
+ AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
3676
+ AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
3677
+ AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
3678
+ // - ========== Register definition for CKGR peripheral ==========
3679
+ AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
3680
+ AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
3681
+ AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register
3682
+ // - ========== Register definition for PMC peripheral ==========
3683
+ AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
3684
+ AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
3685
+ AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register
3686
+ AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
3687
+ AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
3688
+ AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
3689
+ AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
3690
+ AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
3691
+ AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
3692
+ AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
3693
+ AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register
3694
+ AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
3695
+ AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
3696
+ AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
3697
+ AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register
3698
+ // - ========== Register definition for RSTC peripheral ==========
3699
+ AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
3700
+ AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
3701
+ AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
3702
+ // - ========== Register definition for RTTC peripheral ==========
3703
+ AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
3704
+ AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
3705
+ AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
3706
+ AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
3707
+ // - ========== Register definition for PITC peripheral ==========
3708
+ AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
3709
+ AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
3710
+ AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
3711
+ AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
3712
+ // - ========== Register definition for WDTC peripheral ==========
3713
+ AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
3714
+ AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
3715
+ AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
3716
+ // - ========== Register definition for VREG peripheral ==========
3717
+ AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
3718
+ // - ========== Register definition for MC peripheral ==========
3719
+ AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
3720
+ AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
3721
+ AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
3722
+ AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
3723
+ AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
3724
+ AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
3725
+ // - ========== Register definition for PDC_SPI1 peripheral ==========
3726
+ AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
3727
+ AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
3728
+ AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
3729
+ AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
3730
+ AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
3731
+ AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
3732
+ AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
3733
+ AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
3734
+ AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
3735
+ AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
3736
+ // - ========== Register definition for SPI1 peripheral ==========
3737
+ AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
3738
+ AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
3739
+ AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register
3740
+ AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
3741
+ AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
3742
+ AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register
3743
+ AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
3744
+ AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register
3745
+ AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
3746
+ // - ========== Register definition for PDC_SPI0 peripheral ==========
3747
+ AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
3748
+ AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
3749
+ AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
3750
+ AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
3751
+ AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
3752
+ AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
3753
+ AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
3754
+ AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
3755
+ AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
3756
+ AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
3757
+ // - ========== Register definition for SPI0 peripheral ==========
3758
+ AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
3759
+ AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register
3760
+ AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
3761
+ AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register
3762
+ AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register
3763
+ AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
3764
+ AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
3765
+ AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
3766
+ AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
3767
+ // - ========== Register definition for PDC_US1 peripheral ==========
3768
+ AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
3769
+ AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
3770
+ AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
3771
+ AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
3772
+ AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
3773
+ AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
3774
+ AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
3775
+ AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
3776
+ AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
3777
+ AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
3778
+ // - ========== Register definition for US1 peripheral ==========
3779
+ AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
3780
+ AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register
3781
+ AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
3782
+ AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register
3783
+ AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
3784
+ AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
3785
+ AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
3786
+ AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
3787
+ AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
3788
+ AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
3789
+ AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
3790
+ AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
3791
+ AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register
3792
+ AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register
3793
+ // - ========== Register definition for PDC_US0 peripheral ==========
3794
+ AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
3795
+ AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
3796
+ AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
3797
+ AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
3798
+ AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
3799
+ AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
3800
+ AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
3801
+ AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
3802
+ AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
3803
+ AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
3804
+ // - ========== Register definition for US0 peripheral ==========
3805
+ AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
3806
+ AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register
3807
+ AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register
3808
+ AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
3809
+ AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
3810
+ AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
3811
+ AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register
3812
+ AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
3813
+ AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register
3814
+ AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
3815
+ AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
3816
+ AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
3817
+ AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
3818
+ AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
3819
+ // - ========== Register definition for PDC_SSC peripheral ==========
3820
+ AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
3821
+ AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
3822
+ AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
3823
+ AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
3824
+ AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
3825
+ AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
3826
+ AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
3827
+ AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
3828
+ AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
3829
+ AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
3830
+ // - ========== Register definition for SSC peripheral ==========
3831
+ AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
3832
+ AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
3833
+ AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
3834
+ AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
3835
+ AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
3836
+ AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
3837
+ AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
3838
+ AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
3839
+ AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register
3840
+ AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
3841
+ AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
3842
+ AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register
3843
+ AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
3844
+ AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
3845
+ // - ========== Register definition for TWI peripheral ==========
3846
+ AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
3847
+ AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register
3848
+ AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register
3849
+ AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
3850
+ AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
3851
+ AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
3852
+ AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register
3853
+ AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register
3854
+ AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
3855
+ AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
3856
+ // - ========== Register definition for PWMC_CH3 peripheral ==========
3857
+ AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
3858
+ AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
3859
+ AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
3860
+ AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
3861
+ AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
3862
+ AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
3863
+ // - ========== Register definition for PWMC_CH2 peripheral ==========
3864
+ AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
3865
+ AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
3866
+ AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
3867
+ AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
3868
+ AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
3869
+ AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
3870
+ // - ========== Register definition for PWMC_CH1 peripheral ==========
3871
+ AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
3872
+ AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
3873
+ AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
3874
+ AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
3875
+ AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
3876
+ AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
3877
+ // - ========== Register definition for PWMC_CH0 peripheral ==========
3878
+ AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
3879
+ AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
3880
+ AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
3881
+ AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
3882
+ AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
3883
+ AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
3884
+ // - ========== Register definition for PWMC peripheral ==========
3885
+ AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
3886
+ AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
3887
+ AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
3888
+ AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
3889
+ AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
3890
+ AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
3891
+ AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
3892
+ AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
3893
+ AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
3894
+ // - ========== Register definition for UDP peripheral ==========
3895
+ AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
3896
+ AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register
3897
+ AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register
3898
+ AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
3899
+ AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
3900
+ AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
3901
+ AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
3902
+ AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
3903
+ AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
3904
+ AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
3905
+ AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register
3906
+ AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
3907
+ // - ========== Register definition for TC0 peripheral ==========
3908
+ AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register
3909
+ AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C
3910
+ AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B
3911
+ AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register
3912
+ AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
3913
+ AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
3914
+ AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A
3915
+ AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
3916
+ AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value
3917
+ AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
3918
+ // - ========== Register definition for TC1 peripheral ==========
3919
+ AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B
3920
+ AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register
3921
+ AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
3922
+ AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
3923
+ AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register
3924
+ AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
3925
+ AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A
3926
+ AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C
3927
+ AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
3928
+ AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value
3929
+ // - ========== Register definition for TC2 peripheral ==========
3930
+ AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
3931
+ AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register
3932
+ AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value
3933
+ AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A
3934
+ AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B
3935
+ AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
3936
+ AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
3937
+ AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C
3938
+ AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
3939
+ AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register
3940
+ // - ========== Register definition for TCB peripheral ==========
3941
+ AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
3942
+ AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
3943
+ // - ========== Register definition for CAN_MB0 peripheral ==========
3944
+ AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
3945
+ AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
3946
+ AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
3947
+ AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
3948
+ AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
3949
+ AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
3950
+ AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
3951
+ AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
3952
+ // - ========== Register definition for CAN_MB1 peripheral ==========
3953
+ AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
3954
+ AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
3955
+ AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
3956
+ AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
3957
+ AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
3958
+ AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
3959
+ AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
3960
+ AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
3961
+ // - ========== Register definition for CAN_MB2 peripheral ==========
3962
+ AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
3963
+ AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
3964
+ AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
3965
+ AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
3966
+ AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
3967
+ AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
3968
+ AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
3969
+ AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
3970
+ // - ========== Register definition for CAN_MB3 peripheral ==========
3971
+ AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
3972
+ AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
3973
+ AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
3974
+ AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
3975
+ AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
3976
+ AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
3977
+ AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
3978
+ AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
3979
+ // - ========== Register definition for CAN_MB4 peripheral ==========
3980
+ AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
3981
+ AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
3982
+ AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
3983
+ AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
3984
+ AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
3985
+ AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
3986
+ AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
3987
+ AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
3988
+ // - ========== Register definition for CAN_MB5 peripheral ==========
3989
+ AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
3990
+ AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
3991
+ AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
3992
+ AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
3993
+ AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
3994
+ AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
3995
+ AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
3996
+ AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
3997
+ // - ========== Register definition for CAN_MB6 peripheral ==========
3998
+ AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
3999
+ AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
4000
+ AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
4001
+ AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
4002
+ AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
4003
+ AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
4004
+ AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
4005
+ AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
4006
+ // - ========== Register definition for CAN_MB7 peripheral ==========
4007
+ AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
4008
+ AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
4009
+ AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
4010
+ AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
4011
+ AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
4012
+ AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
4013
+ AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
4014
+ AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
4015
+ // - ========== Register definition for CAN peripheral ==========
4016
+ AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
4017
+ AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
4018
+ AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
4019
+ AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register
4020
+ AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
4021
+ AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register
4022
+ AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
4023
+ AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register
4024
+ AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register
4025
+ AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register
4026
+ AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register
4027
+ AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register
4028
+ // - ========== Register definition for EMAC peripheral ==========
4029
+ AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
4030
+ AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
4031
+ AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
4032
+ AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
4033
+ AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
4034
+ AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
4035
+ AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
4036
+ AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
4037
+ AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
4038
+ AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register
4039
+ AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
4040
+ AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
4041
+ AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
4042
+ AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
4043
+ AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
4044
+ AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
4045
+ AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
4046
+ AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
4047
+ AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
4048
+ AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
4049
+ AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
4050
+ AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
4051
+ AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
4052
+ AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
4053
+ AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
4054
+ AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
4055
+ AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
4056
+ AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
4057
+ AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
4058
+ AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
4059
+ AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
4060
+ AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
4061
+ AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
4062
+ AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
4063
+ AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
4064
+ AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
4065
+ AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
4066
+ AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
4067
+ AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
4068
+ AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
4069
+ AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register
4070
+ AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
4071
+ AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
4072
+ AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
4073
+ AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
4074
+ AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
4075
+ AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
4076
+ AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
4077
+ AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
4078
+ // - ========== Register definition for PDC_ADC peripheral ==========
4079
+ AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
4080
+ AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
4081
+ AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
4082
+ AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
4083
+ AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
4084
+ AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
4085
+ AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
4086
+ AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
4087
+ AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
4088
+ AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
4089
+ // - ========== Register definition for ADC peripheral ==========
4090
+ AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
4091
+ AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
4092
+ AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
4093
+ AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
4094
+ AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
4095
+ AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register
4096
+ AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
4097
+ AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
4098
+ AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
4099
+ AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
4100
+ AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register
4101
+ AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
4102
+ AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
4103
+ AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
4104
+ AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
4105
+ AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
4106
+ AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
4107
+ AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
4108
+
4109
+ // - *****************************************************************************
4110
+ // - PIO DEFINITIONS FOR AT91SAM7X256
4111
+ // - *****************************************************************************
4112
+ AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0
4113
+ AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data
4114
+ AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1
4115
+ AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data
4116
+ AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10
4117
+ AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data
4118
+ AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11
4119
+ AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock
4120
+ AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12
4121
+ AT91C_PA12_SPI0_NPCS0 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0
4122
+ AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13
4123
+ AT91C_PA13_SPI0_NPCS1 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1
4124
+ AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1
4125
+ AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14
4126
+ AT91C_PA14_SPI0_NPCS2 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2
4127
+ AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1
4128
+ AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15
4129
+ AT91C_PA15_SPI0_NPCS3 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3
4130
+ AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input
4131
+ AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16
4132
+ AT91C_PA16_SPI0_MISO EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave
4133
+ AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17
4134
+ AT91C_PA17_SPI0_MOSI EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave
4135
+ AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18
4136
+ AT91C_PA18_SPI0_SPCK EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock
4137
+ AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19
4138
+ AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive
4139
+ AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2
4140
+ AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock
4141
+ AT91C_PA2_SPI1_NPCS1 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1
4142
+ AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20
4143
+ AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit
4144
+ AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21
4145
+ AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync
4146
+ AT91C_PA21_SPI1_NPCS0 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0
4147
+ AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22
4148
+ AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock
4149
+ AT91C_PA22_SPI1_SPCK EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock
4150
+ AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23
4151
+ AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data
4152
+ AT91C_PA23_SPI1_MOSI EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave
4153
+ AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24
4154
+ AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data
4155
+ AT91C_PA24_SPI1_MISO EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave
4156
+ AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25
4157
+ AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock
4158
+ AT91C_PA25_SPI1_NPCS1 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1
4159
+ AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26
4160
+ AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync
4161
+ AT91C_PA26_SPI1_NPCS2 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2
4162
+ AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27
4163
+ AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data
4164
+ AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3
4165
+ AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28
4166
+ AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data
4167
+ AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29
4168
+ AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input
4169
+ AT91C_PA29_SPI1_NPCS3 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3
4170
+ AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3
4171
+ AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send
4172
+ AT91C_PA3_SPI1_NPCS2 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2
4173
+ AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30
4174
+ AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0
4175
+ AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2
4176
+ AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4
4177
+ AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send
4178
+ AT91C_PA4_SPI1_NPCS3 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3
4179
+ AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5
4180
+ AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data
4181
+ AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6
4182
+ AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data
4183
+ AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7
4184
+ AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock
4185
+ AT91C_PA7_SPI0_NPCS1 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1
4186
+ AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8
4187
+ AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send
4188
+ AT91C_PA8_SPI0_NPCS2 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2
4189
+ AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9
4190
+ AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send
4191
+ AT91C_PA9_SPI0_NPCS3 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3
4192
+ AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0
4193
+ AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock
4194
+ AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0
4195
+ AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1
4196
+ AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable
4197
+ AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10
4198
+ AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2
4199
+ AT91C_PB10_SPI1_NPCS1 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1
4200
+ AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11
4201
+ AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3
4202
+ AT91C_PB11_SPI1_NPCS2 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2
4203
+ AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12
4204
+ AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error
4205
+ AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input
4206
+ AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13
4207
+ AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2
4208
+ AT91C_PB13_SPI0_NPCS1 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1
4209
+ AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14
4210
+ AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3
4211
+ AT91C_PB14_SPI0_NPCS2 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2
4212
+ AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15
4213
+ AT91C_PB15_ERXDV_ECRSDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid
4214
+ AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16
4215
+ AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected
4216
+ AT91C_PB16_SPI1_NPCS3 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3
4217
+ AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17
4218
+ AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock
4219
+ AT91C_PB17_SPI0_NPCS3 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3
4220
+ AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18
4221
+ AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec
4222
+ AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger
4223
+ AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19
4224
+ AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0
4225
+ AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input
4226
+ AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2
4227
+ AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0
4228
+ AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20
4229
+ AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1
4230
+ AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0
4231
+ AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21
4232
+ AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2
4233
+ AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1
4234
+ AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22
4235
+ AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3
4236
+ AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2
4237
+ AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23
4238
+ AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A
4239
+ AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect
4240
+ AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24
4241
+ AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B
4242
+ AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready
4243
+ AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25
4244
+ AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A
4245
+ AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready
4246
+ AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26
4247
+ AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B
4248
+ AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator
4249
+ AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27
4250
+ AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A
4251
+ AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0
4252
+ AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28
4253
+ AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B
4254
+ AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1
4255
+ AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29
4256
+ AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1
4257
+ AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2
4258
+ AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3
4259
+ AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1
4260
+ AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30
4261
+ AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2
4262
+ AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3
4263
+ AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4
4264
+ AT91C_PB4_ECRS EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
4265
+ AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5
4266
+ AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0
4267
+ AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6
4268
+ AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1
4269
+ AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7
4270
+ AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error
4271
+ AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8
4272
+ AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock
4273
+ AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9
4274
+ AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output
4275
+
4276
+ // - *****************************************************************************
4277
+ // - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
4278
+ // - *****************************************************************************
4279
+ AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
4280
+ AT91C_ID_SYS EQU ( 1) ;- System Peripheral
4281
+ AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A
4282
+ AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B
4283
+ AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0
4284
+ AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1
4285
+ AT91C_ID_US0 EQU ( 6) ;- USART 0
4286
+ AT91C_ID_US1 EQU ( 7) ;- USART 1
4287
+ AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller
4288
+ AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface
4289
+ AT91C_ID_PWMC EQU (10) ;- PWM Controller
4290
+ AT91C_ID_UDP EQU (11) ;- USB Device Port
4291
+ AT91C_ID_TC0 EQU (12) ;- Timer Counter 0
4292
+ AT91C_ID_TC1 EQU (13) ;- Timer Counter 1
4293
+ AT91C_ID_TC2 EQU (14) ;- Timer Counter 2
4294
+ AT91C_ID_CAN EQU (15) ;- Control Area Network Controller
4295
+ AT91C_ID_EMAC EQU (16) ;- Ethernet MAC
4296
+ AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter
4297
+ AT91C_ID_18_Reserved EQU (18) ;- Reserved
4298
+ AT91C_ID_19_Reserved EQU (19) ;- Reserved
4299
+ AT91C_ID_20_Reserved EQU (20) ;- Reserved
4300
+ AT91C_ID_21_Reserved EQU (21) ;- Reserved
4301
+ AT91C_ID_22_Reserved EQU (22) ;- Reserved
4302
+ AT91C_ID_23_Reserved EQU (23) ;- Reserved
4303
+ AT91C_ID_24_Reserved EQU (24) ;- Reserved
4304
+ AT91C_ID_25_Reserved EQU (25) ;- Reserved
4305
+ AT91C_ID_26_Reserved EQU (26) ;- Reserved
4306
+ AT91C_ID_27_Reserved EQU (27) ;- Reserved
4307
+ AT91C_ID_28_Reserved EQU (28) ;- Reserved
4308
+ AT91C_ID_29_Reserved EQU (29) ;- Reserved
4309
+ AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0)
4310
+ AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1)
4311
+ AT91C_ALL_INT EQU (0xC003FFFF) ;- ALL VALID INTERRUPTS
4312
+
4313
+ // - *****************************************************************************
4314
+ // - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
4315
+ // - *****************************************************************************
4316
+ AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address
4317
+ AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address
4318
+ AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
4319
+ AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address
4320
+ AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address
4321
+ AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address
4322
+ AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address
4323
+ AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address
4324
+ AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address
4325
+ AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address
4326
+ AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address
4327
+ AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address
4328
+ AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address
4329
+ AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address
4330
+ AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
4331
+ AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address
4332
+ AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
4333
+ AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address
4334
+ AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address
4335
+ AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address
4336
+ AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address
4337
+ AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address
4338
+ AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
4339
+ AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address
4340
+ AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address
4341
+ AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
4342
+ AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
4343
+ AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
4344
+ AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
4345
+ AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address
4346
+ AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address
4347
+ AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address
4348
+ AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address
4349
+ AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address
4350
+ AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address
4351
+ AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
4352
+ AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
4353
+ AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
4354
+ AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
4355
+ AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
4356
+ AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
4357
+ AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
4358
+ AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
4359
+ AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address
4360
+ AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address
4361
+ AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
4362
+ AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address
4363
+
4364
+ // - *****************************************************************************
4365
+ // - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
4366
+ // - *****************************************************************************
4367
+ // - ISRAM
4368
+ AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address
4369
+ AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbytes)
4370
+ // - IFLASH
4371
+ AT91C_IFLASH EQU (0x00100000) ;- Internal FLASH base address
4372
+ AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal FLASH size in byte (256 Kbytes)
4373
+ AT91C_IFLASH_PAGE_SIZE EQU (256) ;- Internal FLASH Page Size: 256 bytes
4374
+ AT91C_IFLASH_LOCK_REGION_SIZE EQU (16384) ;- Internal FLASH Lock Region Size: 16 Kbytes
4375
+ AT91C_IFLASH_NB_OF_PAGES EQU (1024) ;- Internal FLASH Number of Pages: 1024 bytes
4376
+ AT91C_IFLASH_NB_OF_LOCK_BITS EQU (16) ;- Internal FLASH Number of Lock Bits: 16 bytes
4377
+ #endif /* __IAR_SYSTEMS_ASM__ */
4378
+
4379
+
4380
+ #endif /* AT91SAM7X256_H */