ceedling 0.0.1

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Files changed (991) hide show
  1. data/.gitignore +4 -0
  2. data/.vim +1 -0
  3. data/Gemfile +3 -0
  4. data/LICENSE +19 -0
  5. data/Rakefile +18 -0
  6. data/bin/ceedling +39 -0
  7. data/ceedling.gemspec +23 -0
  8. data/lib/ceedling/version.rb +10 -0
  9. data/lib/ceedling/version.rb.erb +10 -0
  10. data/lib/ceedling.rb +5 -0
  11. data/new_project_template/build/.gitkeep +0 -0
  12. data/new_project_template/project.yml +65 -0
  13. data/new_project_template/rakefile.rb +4 -0
  14. data/new_project_template/src/.gitkeep +0 -0
  15. data/new_project_template/test/.gitkeep +0 -0
  16. data/new_project_template/test/support/.gitkeep +0 -0
  17. data/new_project_template/vendor/ceedling/config/test_environment.rb +12 -0
  18. data/new_project_template/vendor/ceedling/docs/Ceedling Packet.odt +0 -0
  19. data/new_project_template/vendor/ceedling/docs/Ceedling Packet.pdf +0 -0
  20. data/new_project_template/vendor/ceedling/docs/CeedlingLogo.png +0 -0
  21. data/new_project_template/vendor/ceedling/examples/temp_sensor/gcc.yml +42 -0
  22. data/new_project_template/vendor/ceedling/examples/temp_sensor/iar_v4.yml +91 -0
  23. data/new_project_template/vendor/ceedling/examples/temp_sensor/iar_v5.yml +80 -0
  24. data/new_project_template/vendor/ceedling/examples/temp_sensor/project.yml +65 -0
  25. data/new_project_template/vendor/ceedling/examples/temp_sensor/rakefile.rb +5 -0
  26. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcConductor.c +42 -0
  27. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcConductor.h +13 -0
  28. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardware.c +27 -0
  29. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardware.h +11 -0
  30. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardwareConfigurator.c +18 -0
  31. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcHardwareConfigurator.h +10 -0
  32. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcModel.c +33 -0
  33. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcModel.h +13 -0
  34. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcTemperatureSensor.c +51 -0
  35. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/AdcTemperatureSensor.h +10 -0
  36. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Executor.c +25 -0
  37. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Executor.h +9 -0
  38. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/IntrinsicsWrapper.c +18 -0
  39. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/IntrinsicsWrapper.h +7 -0
  40. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Main.c +46 -0
  41. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Main.h +7 -0
  42. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Model.c +10 -0
  43. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Model.h +8 -0
  44. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/ModelConfig.h +7 -0
  45. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TaskScheduler.c +72 -0
  46. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TaskScheduler.h +11 -0
  47. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureCalculator.c +27 -0
  48. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureCalculator.h +8 -0
  49. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureFilter.c +39 -0
  50. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TemperatureFilter.h +10 -0
  51. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConductor.c +15 -0
  52. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConductor.h +9 -0
  53. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConfigurator.c +51 -0
  54. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerConfigurator.h +15 -0
  55. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerHardware.c +15 -0
  56. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerHardware.h +8 -0
  57. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptConfigurator.c +55 -0
  58. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptConfigurator.h +13 -0
  59. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptHandler.c +25 -0
  60. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerInterruptHandler.h +10 -0
  61. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerModel.c +9 -0
  62. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/TimerModel.h +8 -0
  63. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/Types.h +90 -0
  64. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartBaudRateRegisterCalculator.c +18 -0
  65. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartBaudRateRegisterCalculator.h +8 -0
  66. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConductor.c +21 -0
  67. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConductor.h +7 -0
  68. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConfigurator.c +39 -0
  69. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartConfigurator.h +13 -0
  70. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartHardware.c +22 -0
  71. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartHardware.h +9 -0
  72. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartModel.c +34 -0
  73. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartModel.h +10 -0
  74. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartPutChar.c +16 -0
  75. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartPutChar.h +8 -0
  76. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartTransmitBufferStatus.c +7 -0
  77. data/new_project_template/vendor/ceedling/examples/temp_sensor/src/UsartTransmitBufferStatus.h +8 -0
  78. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcConductor.c +121 -0
  79. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcHardware.c +44 -0
  80. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestAdcModel.c +33 -0
  81. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestExecutor.c +36 -0
  82. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestMain.c +24 -0
  83. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestModel.c +20 -0
  84. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTaskScheduler.c +104 -0
  85. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTemperatureCalculator.c +33 -0
  86. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTemperatureFilter.c +69 -0
  87. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerConductor.c +32 -0
  88. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerHardware.c +26 -0
  89. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestTimerModel.c +18 -0
  90. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartBaudRateRegisterCalculator.c +21 -0
  91. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartConductor.c +40 -0
  92. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartHardware.c +36 -0
  93. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/TestUsartModel.c +40 -0
  94. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/support/UnityHelper.c +12 -0
  95. data/new_project_template/vendor/ceedling/examples/temp_sensor/test/support/UnityHelper.h +8 -0
  96. data/new_project_template/vendor/ceedling/lib/cacheinator.rb +42 -0
  97. data/new_project_template/vendor/ceedling/lib/cacheinator_helper.rb +12 -0
  98. data/new_project_template/vendor/ceedling/lib/cmock_builder.rb +15 -0
  99. data/new_project_template/vendor/ceedling/lib/configurator.rb +254 -0
  100. data/new_project_template/vendor/ceedling/lib/configurator_builder.rb +408 -0
  101. data/new_project_template/vendor/ceedling/lib/configurator_plugins.rb +96 -0
  102. data/new_project_template/vendor/ceedling/lib/configurator_setup.rb +114 -0
  103. data/new_project_template/vendor/ceedling/lib/configurator_validator.rb +154 -0
  104. data/new_project_template/vendor/ceedling/lib/constants.rb +66 -0
  105. data/new_project_template/vendor/ceedling/lib/defaults.rb +349 -0
  106. data/new_project_template/vendor/ceedling/lib/dependinator.rb +92 -0
  107. data/new_project_template/vendor/ceedling/lib/file_finder.rb +132 -0
  108. data/new_project_template/vendor/ceedling/lib/file_finder_helper.rb +54 -0
  109. data/new_project_template/vendor/ceedling/lib/file_path_utils.rb +177 -0
  110. data/new_project_template/vendor/ceedling/lib/file_system_utils.rb +59 -0
  111. data/new_project_template/vendor/ceedling/lib/file_wrapper.rb +74 -0
  112. data/new_project_template/vendor/ceedling/lib/generator.rb +131 -0
  113. data/new_project_template/vendor/ceedling/lib/generator_test_results.rb +90 -0
  114. data/new_project_template/vendor/ceedling/lib/generator_test_results_sanity_checker.rb +62 -0
  115. data/new_project_template/vendor/ceedling/lib/generator_test_runner.rb +206 -0
  116. data/new_project_template/vendor/ceedling/lib/loginator.rb +31 -0
  117. data/new_project_template/vendor/ceedling/lib/makefile.rb +46 -0
  118. data/new_project_template/vendor/ceedling/lib/objects.yml +278 -0
  119. data/new_project_template/vendor/ceedling/lib/plugin.rb +63 -0
  120. data/new_project_template/vendor/ceedling/lib/plugin_manager.rb +85 -0
  121. data/new_project_template/vendor/ceedling/lib/plugin_manager_helper.rb +19 -0
  122. data/new_project_template/vendor/ceedling/lib/plugin_reportinator.rb +75 -0
  123. data/new_project_template/vendor/ceedling/lib/plugin_reportinator_helper.rb +52 -0
  124. data/new_project_template/vendor/ceedling/lib/preprocessinator.rb +43 -0
  125. data/new_project_template/vendor/ceedling/lib/preprocessinator_extractor.rb +27 -0
  126. data/new_project_template/vendor/ceedling/lib/preprocessinator_file_handler.rb +21 -0
  127. data/new_project_template/vendor/ceedling/lib/preprocessinator_helper.rb +46 -0
  128. data/new_project_template/vendor/ceedling/lib/preprocessinator_includes_handler.rb +55 -0
  129. data/new_project_template/vendor/ceedling/lib/project_config_manager.rb +38 -0
  130. data/new_project_template/vendor/ceedling/lib/project_file_loader.rb +64 -0
  131. data/new_project_template/vendor/ceedling/lib/rake_utils.rb +17 -0
  132. data/new_project_template/vendor/ceedling/lib/rake_wrapper.rb +31 -0
  133. data/new_project_template/vendor/ceedling/lib/rakefile.rb +60 -0
  134. data/new_project_template/vendor/ceedling/lib/release_invoker.rb +29 -0
  135. data/new_project_template/vendor/ceedling/lib/release_invoker_helper.rb +16 -0
  136. data/new_project_template/vendor/ceedling/lib/reportinator.rb +9 -0
  137. data/new_project_template/vendor/ceedling/lib/rules_cmock.rake +9 -0
  138. data/new_project_template/vendor/ceedling/lib/rules_preprocess.rake +26 -0
  139. data/new_project_template/vendor/ceedling/lib/rules_release.rake +63 -0
  140. data/new_project_template/vendor/ceedling/lib/rules_release_aux_dependencies.rake +15 -0
  141. data/new_project_template/vendor/ceedling/lib/rules_tests.rake +49 -0
  142. data/new_project_template/vendor/ceedling/lib/rules_tests_aux_dependencies.rake +15 -0
  143. data/new_project_template/vendor/ceedling/lib/setupinator.rb +45 -0
  144. data/new_project_template/vendor/ceedling/lib/stream_wrapper.rb +20 -0
  145. data/new_project_template/vendor/ceedling/lib/streaminator.rb +41 -0
  146. data/new_project_template/vendor/ceedling/lib/streaminator_helper.rb +15 -0
  147. data/new_project_template/vendor/ceedling/lib/system_wrapper.rb +67 -0
  148. data/new_project_template/vendor/ceedling/lib/task_invoker.rb +85 -0
  149. data/new_project_template/vendor/ceedling/lib/tasks_base.rake +104 -0
  150. data/new_project_template/vendor/ceedling/lib/tasks_filesystem.rake +89 -0
  151. data/new_project_template/vendor/ceedling/lib/tasks_release.rake +22 -0
  152. data/new_project_template/vendor/ceedling/lib/tasks_tests.rake +49 -0
  153. data/new_project_template/vendor/ceedling/lib/tasks_vendor.rake +36 -0
  154. data/new_project_template/vendor/ceedling/lib/test_includes_extractor.rb +81 -0
  155. data/new_project_template/vendor/ceedling/lib/test_invoker.rb +72 -0
  156. data/new_project_template/vendor/ceedling/lib/test_invoker_helper.rb +41 -0
  157. data/new_project_template/vendor/ceedling/lib/tool_executor.rb +178 -0
  158. data/new_project_template/vendor/ceedling/lib/tool_executor_helper.rb +57 -0
  159. data/new_project_template/vendor/ceedling/lib/verbosinator.rb +10 -0
  160. data/new_project_template/vendor/ceedling/lib/yaml_wrapper.rb +16 -0
  161. data/new_project_template/vendor/ceedling/plugins/stdout_ide_tests_report/stdout_ide_tests_report.rb +44 -0
  162. data/new_project_template/vendor/ceedling/plugins/stdout_ide_tests_report/stdout_ide_tests_report.yml +4 -0
  163. data/new_project_template/vendor/ceedling/plugins/stdout_pretty_tests_report/stdout_pretty_tests_report.rb +108 -0
  164. data/new_project_template/vendor/ceedling/plugins/stdout_pretty_tests_report/stdout_pretty_tests_report.yml +4 -0
  165. data/new_project_template/vendor/ceedling/plugins/xml_tests_report/xml_tests_report.rb +106 -0
  166. data/new_project_template/vendor/ceedling/rakefile.rb +59 -0
  167. data/new_project_template/vendor/ceedling/rakefile_helper.rb +23 -0
  168. data/new_project_template/vendor/ceedling/release/build.info +1 -0
  169. data/new_project_template/vendor/ceedling/release/version.info +1 -0
  170. data/new_project_template/vendor/ceedling/test/integration/paths.yml +17 -0
  171. data/new_project_template/vendor/ceedling/test/integration/paths_test.rb +80 -0
  172. data/new_project_template/vendor/ceedling/test/integration/rake_rules_aux_dependencies_test.rb +75 -0
  173. data/new_project_template/vendor/ceedling/test/integration/rake_rules_cmock_test.rb +74 -0
  174. data/new_project_template/vendor/ceedling/test/integration/rake_rules_preprocess_test.rb +178 -0
  175. data/new_project_template/vendor/ceedling/test/integration/rake_rules_test.rb +268 -0
  176. data/new_project_template/vendor/ceedling/test/integration/rake_tasks_test.rb +103 -0
  177. data/new_project_template/vendor/ceedling/test/integration_test_helper.rb +34 -0
  178. data/new_project_template/vendor/ceedling/test/rakefile_rules.rb +10 -0
  179. data/new_project_template/vendor/ceedling/test/rakefile_rules_aux_dependencies.rb +10 -0
  180. data/new_project_template/vendor/ceedling/test/rakefile_rules_cmock.rb +10 -0
  181. data/new_project_template/vendor/ceedling/test/rakefile_rules_preprocess.rb +10 -0
  182. data/new_project_template/vendor/ceedling/test/rakefile_tasks.rb +10 -0
  183. data/new_project_template/vendor/ceedling/test/system/file_system_dependencies.yml +20 -0
  184. data/new_project_template/vendor/ceedling/test/system/file_system_kitchen_sink.yml +20 -0
  185. data/new_project_template/vendor/ceedling/test/system/file_system_mocks.yml +20 -0
  186. data/new_project_template/vendor/ceedling/test/system/file_system_preprocess.yml +20 -0
  187. data/new_project_template/vendor/ceedling/test/system/file_system_simple.yml +20 -0
  188. data/new_project_template/vendor/ceedling/test/system/file_system_test.rb +78 -0
  189. data/new_project_template/vendor/ceedling/test/system/mocks/include/a_file.h +2 -0
  190. data/new_project_template/vendor/ceedling/test/system/mocks/include/other_stuff.h +2 -0
  191. data/new_project_template/vendor/ceedling/test/system/mocks/include/stuff.h +3 -0
  192. data/new_project_template/vendor/ceedling/test/system/mocks/source/a_file.c +9 -0
  193. data/new_project_template/vendor/ceedling/test/system/mocks/test/test_a_file.c +41 -0
  194. data/new_project_template/vendor/ceedling/test/system/mocks/test/test_no_file.c +14 -0
  195. data/new_project_template/vendor/ceedling/test/system/project_mocks.yml +43 -0
  196. data/new_project_template/vendor/ceedling/test/system/project_mocks_test.rb +38 -0
  197. data/new_project_template/vendor/ceedling/test/system/project_simple.yml +36 -0
  198. data/new_project_template/vendor/ceedling/test/system/project_simple_test.rb +39 -0
  199. data/new_project_template/vendor/ceedling/test/system/rule_mocks_test.rb +44 -0
  200. data/new_project_template/vendor/ceedling/test/system/rule_runners_test.rb +44 -0
  201. data/new_project_template/vendor/ceedling/test/system/simple/include/other_stuff.h +2 -0
  202. data/new_project_template/vendor/ceedling/test/system/simple/include/stuff.h +3 -0
  203. data/new_project_template/vendor/ceedling/test/system/simple/source/other_stuff.c +6 -0
  204. data/new_project_template/vendor/ceedling/test/system/simple/source/stuff.c +7 -0
  205. data/new_project_template/vendor/ceedling/test/system/simple/test/test_other_stuff.c +30 -0
  206. data/new_project_template/vendor/ceedling/test/system/simple/test/test_stuff.c +51 -0
  207. data/new_project_template/vendor/ceedling/test/system_test_helper.rb +73 -0
  208. data/new_project_template/vendor/ceedling/test/test_helper.rb +93 -0
  209. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_builder_test.rb +571 -0
  210. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_helper_test.rb +234 -0
  211. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_test.rb +232 -0
  212. data/new_project_template/vendor/ceedling/test/unit/busted/configurator_validator_test.rb +169 -0
  213. data/new_project_template/vendor/ceedling/test/unit/busted/deep_merge_fix_test.rb +55 -0
  214. data/new_project_template/vendor/ceedling/test/unit/busted/dependinator_test.rb +129 -0
  215. data/new_project_template/vendor/ceedling/test/unit/busted/file_finder_helper_test.rb +45 -0
  216. data/new_project_template/vendor/ceedling/test/unit/busted/file_finder_test.rb +114 -0
  217. data/new_project_template/vendor/ceedling/test/unit/busted/file_path_utils_test.rb +97 -0
  218. data/new_project_template/vendor/ceedling/test/unit/busted/file_system_utils_test.rb +21 -0
  219. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test.rb +187 -0
  220. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test_results_test.rb +129 -0
  221. data/new_project_template/vendor/ceedling/test/unit/busted/generator_test_runner_test.rb +478 -0
  222. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_extractor_test.rb +729 -0
  223. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_file_handler_test.rb +38 -0
  224. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_helper_test.rb +156 -0
  225. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_includes_handler_test.rb +93 -0
  226. data/new_project_template/vendor/ceedling/test/unit/busted/preprocessinator_test.rb +57 -0
  227. data/new_project_template/vendor/ceedling/test/unit/busted/project_file_loader_test.rb +142 -0
  228. data/new_project_template/vendor/ceedling/test/unit/busted/setupinator_test.rb +45 -0
  229. data/new_project_template/vendor/ceedling/test/unit/busted/streaminator_test.rb +49 -0
  230. data/new_project_template/vendor/ceedling/test/unit/busted/task_invoker_test.rb +69 -0
  231. data/new_project_template/vendor/ceedling/test/unit/busted/test_includes_extractor_test.rb +111 -0
  232. data/new_project_template/vendor/ceedling/test/unit/busted/test_invoker_helper_test.rb +62 -0
  233. data/new_project_template/vendor/ceedling/test/unit/busted/test_invoker_test.rb +47 -0
  234. data/new_project_template/vendor/ceedling/test/unit/busted/tool_executor_helper_test.rb +100 -0
  235. data/new_project_template/vendor/ceedling/test/unit/busted/tool_executor_test.rb +351 -0
  236. data/new_project_template/vendor/ceedling/test/unit/busted/verbosinator_test.rb +65 -0
  237. data/new_project_template/vendor/ceedling/test/unit_test_helper.rb +16 -0
  238. data/new_project_template/vendor/ceedling/vendor/behaviors/Manifest.txt +9 -0
  239. data/new_project_template/vendor/ceedling/vendor/behaviors/Rakefile +19 -0
  240. data/new_project_template/vendor/ceedling/vendor/behaviors/lib/behaviors/reporttask.rb +158 -0
  241. data/new_project_template/vendor/ceedling/vendor/behaviors/lib/behaviors.rb +76 -0
  242. data/new_project_template/vendor/ceedling/vendor/behaviors/test/behaviors_tasks_test.rb +73 -0
  243. data/new_project_template/vendor/ceedling/vendor/behaviors/test/behaviors_test.rb +50 -0
  244. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/Rakefile +19 -0
  245. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/lib/user.rb +2 -0
  246. data/new_project_template/vendor/ceedling/vendor/behaviors/test/tasks_test/test/user_test.rb +17 -0
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@@ -0,0 +1,4704 @@
1
+ # ----------------------------------------------------------------------------
2
+ # ATMEL Microcontroller Software Support - ROUSSET -
3
+ # ----------------------------------------------------------------------------
4
+ # DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
5
+ # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6
+ # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
7
+ # DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
8
+ # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
9
+ # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
10
+ # OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
11
+ # LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
12
+ # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
13
+ # EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
14
+ # ----------------------------------------------------------------------------
15
+ # File Name : AT91SAM7X256.h
16
+ # Object : AT91SAM7X256 definitions
17
+ # Generated : AT91 SW Application Group 11/02/2005 (15:17:24)
18
+ #
19
+ # CVS Reference : /AT91SAM7X256.pl/1.14/Tue Sep 13 15:06:52 2005//
20
+ # CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
21
+ # CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
22
+ # CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
23
+ # CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 14:57:50 2005//
24
+ # CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
25
+ # CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
26
+ # CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
27
+ # CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
28
+ # CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
29
+ # CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
30
+ # CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
31
+ # CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
32
+ # CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
33
+ # CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
34
+ # CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
35
+ # CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
36
+ # CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:19:19 2005//
37
+ # CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
38
+ # CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
39
+ # CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
40
+ # CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:05:35 2005//
41
+ # CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
42
+ # ----------------------------------------------------------------------------
43
+
44
+ rdf.version=1
45
+
46
+ ~sysinclude=arm_default.rdf
47
+ ~sysinclude=arm_status.rdf
48
+ # ========== Register definition for SYS peripheral ==========
49
+ # ========== Register definition for AIC peripheral ==========
50
+ AT91C_AIC_IVR.name="AT91C_AIC_IVR"
51
+ AT91C_AIC_IVR.description="IRQ Vector Register"
52
+ AT91C_AIC_IVR.helpkey="IRQ Vector Register"
53
+ AT91C_AIC_IVR.access=memorymapped
54
+ AT91C_AIC_IVR.address=0xFFFFF100
55
+ AT91C_AIC_IVR.width=32
56
+ AT91C_AIC_IVR.byteEndian=little
57
+ AT91C_AIC_IVR.permission.write=none
58
+ AT91C_AIC_SMR.name="AT91C_AIC_SMR"
59
+ AT91C_AIC_SMR.description="Source Mode Register"
60
+ AT91C_AIC_SMR.helpkey="Source Mode Register"
61
+ AT91C_AIC_SMR.access=memorymapped
62
+ AT91C_AIC_SMR.address=0xFFFFF000
63
+ AT91C_AIC_SMR.width=32
64
+ AT91C_AIC_SMR.byteEndian=little
65
+ AT91C_AIC_FVR.name="AT91C_AIC_FVR"
66
+ AT91C_AIC_FVR.description="FIQ Vector Register"
67
+ AT91C_AIC_FVR.helpkey="FIQ Vector Register"
68
+ AT91C_AIC_FVR.access=memorymapped
69
+ AT91C_AIC_FVR.address=0xFFFFF104
70
+ AT91C_AIC_FVR.width=32
71
+ AT91C_AIC_FVR.byteEndian=little
72
+ AT91C_AIC_FVR.permission.write=none
73
+ AT91C_AIC_DCR.name="AT91C_AIC_DCR"
74
+ AT91C_AIC_DCR.description="Debug Control Register (Protect)"
75
+ AT91C_AIC_DCR.helpkey="Debug Control Register (Protect)"
76
+ AT91C_AIC_DCR.access=memorymapped
77
+ AT91C_AIC_DCR.address=0xFFFFF138
78
+ AT91C_AIC_DCR.width=32
79
+ AT91C_AIC_DCR.byteEndian=little
80
+ AT91C_AIC_EOICR.name="AT91C_AIC_EOICR"
81
+ AT91C_AIC_EOICR.description="End of Interrupt Command Register"
82
+ AT91C_AIC_EOICR.helpkey="End of Interrupt Command Register"
83
+ AT91C_AIC_EOICR.access=memorymapped
84
+ AT91C_AIC_EOICR.address=0xFFFFF130
85
+ AT91C_AIC_EOICR.width=32
86
+ AT91C_AIC_EOICR.byteEndian=little
87
+ AT91C_AIC_EOICR.type=enum
88
+ AT91C_AIC_EOICR.enum.0.name=*** Write only ***
89
+ AT91C_AIC_EOICR.enum.1.name=Error
90
+ AT91C_AIC_SVR.name="AT91C_AIC_SVR"
91
+ AT91C_AIC_SVR.description="Source Vector Register"
92
+ AT91C_AIC_SVR.helpkey="Source Vector Register"
93
+ AT91C_AIC_SVR.access=memorymapped
94
+ AT91C_AIC_SVR.address=0xFFFFF080
95
+ AT91C_AIC_SVR.width=32
96
+ AT91C_AIC_SVR.byteEndian=little
97
+ AT91C_AIC_FFSR.name="AT91C_AIC_FFSR"
98
+ AT91C_AIC_FFSR.description="Fast Forcing Status Register"
99
+ AT91C_AIC_FFSR.helpkey="Fast Forcing Status Register"
100
+ AT91C_AIC_FFSR.access=memorymapped
101
+ AT91C_AIC_FFSR.address=0xFFFFF148
102
+ AT91C_AIC_FFSR.width=32
103
+ AT91C_AIC_FFSR.byteEndian=little
104
+ AT91C_AIC_FFSR.permission.write=none
105
+ AT91C_AIC_ICCR.name="AT91C_AIC_ICCR"
106
+ AT91C_AIC_ICCR.description="Interrupt Clear Command Register"
107
+ AT91C_AIC_ICCR.helpkey="Interrupt Clear Command Register"
108
+ AT91C_AIC_ICCR.access=memorymapped
109
+ AT91C_AIC_ICCR.address=0xFFFFF128
110
+ AT91C_AIC_ICCR.width=32
111
+ AT91C_AIC_ICCR.byteEndian=little
112
+ AT91C_AIC_ICCR.type=enum
113
+ AT91C_AIC_ICCR.enum.0.name=*** Write only ***
114
+ AT91C_AIC_ICCR.enum.1.name=Error
115
+ AT91C_AIC_ISR.name="AT91C_AIC_ISR"
116
+ AT91C_AIC_ISR.description="Interrupt Status Register"
117
+ AT91C_AIC_ISR.helpkey="Interrupt Status Register"
118
+ AT91C_AIC_ISR.access=memorymapped
119
+ AT91C_AIC_ISR.address=0xFFFFF108
120
+ AT91C_AIC_ISR.width=32
121
+ AT91C_AIC_ISR.byteEndian=little
122
+ AT91C_AIC_ISR.permission.write=none
123
+ AT91C_AIC_IMR.name="AT91C_AIC_IMR"
124
+ AT91C_AIC_IMR.description="Interrupt Mask Register"
125
+ AT91C_AIC_IMR.helpkey="Interrupt Mask Register"
126
+ AT91C_AIC_IMR.access=memorymapped
127
+ AT91C_AIC_IMR.address=0xFFFFF110
128
+ AT91C_AIC_IMR.width=32
129
+ AT91C_AIC_IMR.byteEndian=little
130
+ AT91C_AIC_IMR.permission.write=none
131
+ AT91C_AIC_IPR.name="AT91C_AIC_IPR"
132
+ AT91C_AIC_IPR.description="Interrupt Pending Register"
133
+ AT91C_AIC_IPR.helpkey="Interrupt Pending Register"
134
+ AT91C_AIC_IPR.access=memorymapped
135
+ AT91C_AIC_IPR.address=0xFFFFF10C
136
+ AT91C_AIC_IPR.width=32
137
+ AT91C_AIC_IPR.byteEndian=little
138
+ AT91C_AIC_IPR.permission.write=none
139
+ AT91C_AIC_FFER.name="AT91C_AIC_FFER"
140
+ AT91C_AIC_FFER.description="Fast Forcing Enable Register"
141
+ AT91C_AIC_FFER.helpkey="Fast Forcing Enable Register"
142
+ AT91C_AIC_FFER.access=memorymapped
143
+ AT91C_AIC_FFER.address=0xFFFFF140
144
+ AT91C_AIC_FFER.width=32
145
+ AT91C_AIC_FFER.byteEndian=little
146
+ AT91C_AIC_FFER.type=enum
147
+ AT91C_AIC_FFER.enum.0.name=*** Write only ***
148
+ AT91C_AIC_FFER.enum.1.name=Error
149
+ AT91C_AIC_IECR.name="AT91C_AIC_IECR"
150
+ AT91C_AIC_IECR.description="Interrupt Enable Command Register"
151
+ AT91C_AIC_IECR.helpkey="Interrupt Enable Command Register"
152
+ AT91C_AIC_IECR.access=memorymapped
153
+ AT91C_AIC_IECR.address=0xFFFFF120
154
+ AT91C_AIC_IECR.width=32
155
+ AT91C_AIC_IECR.byteEndian=little
156
+ AT91C_AIC_IECR.type=enum
157
+ AT91C_AIC_IECR.enum.0.name=*** Write only ***
158
+ AT91C_AIC_IECR.enum.1.name=Error
159
+ AT91C_AIC_ISCR.name="AT91C_AIC_ISCR"
160
+ AT91C_AIC_ISCR.description="Interrupt Set Command Register"
161
+ AT91C_AIC_ISCR.helpkey="Interrupt Set Command Register"
162
+ AT91C_AIC_ISCR.access=memorymapped
163
+ AT91C_AIC_ISCR.address=0xFFFFF12C
164
+ AT91C_AIC_ISCR.width=32
165
+ AT91C_AIC_ISCR.byteEndian=little
166
+ AT91C_AIC_ISCR.type=enum
167
+ AT91C_AIC_ISCR.enum.0.name=*** Write only ***
168
+ AT91C_AIC_ISCR.enum.1.name=Error
169
+ AT91C_AIC_FFDR.name="AT91C_AIC_FFDR"
170
+ AT91C_AIC_FFDR.description="Fast Forcing Disable Register"
171
+ AT91C_AIC_FFDR.helpkey="Fast Forcing Disable Register"
172
+ AT91C_AIC_FFDR.access=memorymapped
173
+ AT91C_AIC_FFDR.address=0xFFFFF144
174
+ AT91C_AIC_FFDR.width=32
175
+ AT91C_AIC_FFDR.byteEndian=little
176
+ AT91C_AIC_FFDR.type=enum
177
+ AT91C_AIC_FFDR.enum.0.name=*** Write only ***
178
+ AT91C_AIC_FFDR.enum.1.name=Error
179
+ AT91C_AIC_CISR.name="AT91C_AIC_CISR"
180
+ AT91C_AIC_CISR.description="Core Interrupt Status Register"
181
+ AT91C_AIC_CISR.helpkey="Core Interrupt Status Register"
182
+ AT91C_AIC_CISR.access=memorymapped
183
+ AT91C_AIC_CISR.address=0xFFFFF114
184
+ AT91C_AIC_CISR.width=32
185
+ AT91C_AIC_CISR.byteEndian=little
186
+ AT91C_AIC_CISR.permission.write=none
187
+ AT91C_AIC_IDCR.name="AT91C_AIC_IDCR"
188
+ AT91C_AIC_IDCR.description="Interrupt Disable Command Register"
189
+ AT91C_AIC_IDCR.helpkey="Interrupt Disable Command Register"
190
+ AT91C_AIC_IDCR.access=memorymapped
191
+ AT91C_AIC_IDCR.address=0xFFFFF124
192
+ AT91C_AIC_IDCR.width=32
193
+ AT91C_AIC_IDCR.byteEndian=little
194
+ AT91C_AIC_IDCR.type=enum
195
+ AT91C_AIC_IDCR.enum.0.name=*** Write only ***
196
+ AT91C_AIC_IDCR.enum.1.name=Error
197
+ AT91C_AIC_SPU.name="AT91C_AIC_SPU"
198
+ AT91C_AIC_SPU.description="Spurious Vector Register"
199
+ AT91C_AIC_SPU.helpkey="Spurious Vector Register"
200
+ AT91C_AIC_SPU.access=memorymapped
201
+ AT91C_AIC_SPU.address=0xFFFFF134
202
+ AT91C_AIC_SPU.width=32
203
+ AT91C_AIC_SPU.byteEndian=little
204
+ # ========== Register definition for PDC_DBGU peripheral ==========
205
+ AT91C_DBGU_TCR.name="AT91C_DBGU_TCR"
206
+ AT91C_DBGU_TCR.description="Transmit Counter Register"
207
+ AT91C_DBGU_TCR.helpkey="Transmit Counter Register"
208
+ AT91C_DBGU_TCR.access=memorymapped
209
+ AT91C_DBGU_TCR.address=0xFFFFF30C
210
+ AT91C_DBGU_TCR.width=32
211
+ AT91C_DBGU_TCR.byteEndian=little
212
+ AT91C_DBGU_RNPR.name="AT91C_DBGU_RNPR"
213
+ AT91C_DBGU_RNPR.description="Receive Next Pointer Register"
214
+ AT91C_DBGU_RNPR.helpkey="Receive Next Pointer Register"
215
+ AT91C_DBGU_RNPR.access=memorymapped
216
+ AT91C_DBGU_RNPR.address=0xFFFFF310
217
+ AT91C_DBGU_RNPR.width=32
218
+ AT91C_DBGU_RNPR.byteEndian=little
219
+ AT91C_DBGU_TNPR.name="AT91C_DBGU_TNPR"
220
+ AT91C_DBGU_TNPR.description="Transmit Next Pointer Register"
221
+ AT91C_DBGU_TNPR.helpkey="Transmit Next Pointer Register"
222
+ AT91C_DBGU_TNPR.access=memorymapped
223
+ AT91C_DBGU_TNPR.address=0xFFFFF318
224
+ AT91C_DBGU_TNPR.width=32
225
+ AT91C_DBGU_TNPR.byteEndian=little
226
+ AT91C_DBGU_TPR.name="AT91C_DBGU_TPR"
227
+ AT91C_DBGU_TPR.description="Transmit Pointer Register"
228
+ AT91C_DBGU_TPR.helpkey="Transmit Pointer Register"
229
+ AT91C_DBGU_TPR.access=memorymapped
230
+ AT91C_DBGU_TPR.address=0xFFFFF308
231
+ AT91C_DBGU_TPR.width=32
232
+ AT91C_DBGU_TPR.byteEndian=little
233
+ AT91C_DBGU_RPR.name="AT91C_DBGU_RPR"
234
+ AT91C_DBGU_RPR.description="Receive Pointer Register"
235
+ AT91C_DBGU_RPR.helpkey="Receive Pointer Register"
236
+ AT91C_DBGU_RPR.access=memorymapped
237
+ AT91C_DBGU_RPR.address=0xFFFFF300
238
+ AT91C_DBGU_RPR.width=32
239
+ AT91C_DBGU_RPR.byteEndian=little
240
+ AT91C_DBGU_RCR.name="AT91C_DBGU_RCR"
241
+ AT91C_DBGU_RCR.description="Receive Counter Register"
242
+ AT91C_DBGU_RCR.helpkey="Receive Counter Register"
243
+ AT91C_DBGU_RCR.access=memorymapped
244
+ AT91C_DBGU_RCR.address=0xFFFFF304
245
+ AT91C_DBGU_RCR.width=32
246
+ AT91C_DBGU_RCR.byteEndian=little
247
+ AT91C_DBGU_RNCR.name="AT91C_DBGU_RNCR"
248
+ AT91C_DBGU_RNCR.description="Receive Next Counter Register"
249
+ AT91C_DBGU_RNCR.helpkey="Receive Next Counter Register"
250
+ AT91C_DBGU_RNCR.access=memorymapped
251
+ AT91C_DBGU_RNCR.address=0xFFFFF314
252
+ AT91C_DBGU_RNCR.width=32
253
+ AT91C_DBGU_RNCR.byteEndian=little
254
+ AT91C_DBGU_PTCR.name="AT91C_DBGU_PTCR"
255
+ AT91C_DBGU_PTCR.description="PDC Transfer Control Register"
256
+ AT91C_DBGU_PTCR.helpkey="PDC Transfer Control Register"
257
+ AT91C_DBGU_PTCR.access=memorymapped
258
+ AT91C_DBGU_PTCR.address=0xFFFFF320
259
+ AT91C_DBGU_PTCR.width=32
260
+ AT91C_DBGU_PTCR.byteEndian=little
261
+ AT91C_DBGU_PTCR.type=enum
262
+ AT91C_DBGU_PTCR.enum.0.name=*** Write only ***
263
+ AT91C_DBGU_PTCR.enum.1.name=Error
264
+ AT91C_DBGU_PTSR.name="AT91C_DBGU_PTSR"
265
+ AT91C_DBGU_PTSR.description="PDC Transfer Status Register"
266
+ AT91C_DBGU_PTSR.helpkey="PDC Transfer Status Register"
267
+ AT91C_DBGU_PTSR.access=memorymapped
268
+ AT91C_DBGU_PTSR.address=0xFFFFF324
269
+ AT91C_DBGU_PTSR.width=32
270
+ AT91C_DBGU_PTSR.byteEndian=little
271
+ AT91C_DBGU_PTSR.permission.write=none
272
+ AT91C_DBGU_TNCR.name="AT91C_DBGU_TNCR"
273
+ AT91C_DBGU_TNCR.description="Transmit Next Counter Register"
274
+ AT91C_DBGU_TNCR.helpkey="Transmit Next Counter Register"
275
+ AT91C_DBGU_TNCR.access=memorymapped
276
+ AT91C_DBGU_TNCR.address=0xFFFFF31C
277
+ AT91C_DBGU_TNCR.width=32
278
+ AT91C_DBGU_TNCR.byteEndian=little
279
+ # ========== Register definition for DBGU peripheral ==========
280
+ AT91C_DBGU_EXID.name="AT91C_DBGU_EXID"
281
+ AT91C_DBGU_EXID.description="Chip ID Extension Register"
282
+ AT91C_DBGU_EXID.helpkey="Chip ID Extension Register"
283
+ AT91C_DBGU_EXID.access=memorymapped
284
+ AT91C_DBGU_EXID.address=0xFFFFF244
285
+ AT91C_DBGU_EXID.width=32
286
+ AT91C_DBGU_EXID.byteEndian=little
287
+ AT91C_DBGU_EXID.permission.write=none
288
+ AT91C_DBGU_BRGR.name="AT91C_DBGU_BRGR"
289
+ AT91C_DBGU_BRGR.description="Baud Rate Generator Register"
290
+ AT91C_DBGU_BRGR.helpkey="Baud Rate Generator Register"
291
+ AT91C_DBGU_BRGR.access=memorymapped
292
+ AT91C_DBGU_BRGR.address=0xFFFFF220
293
+ AT91C_DBGU_BRGR.width=32
294
+ AT91C_DBGU_BRGR.byteEndian=little
295
+ AT91C_DBGU_IDR.name="AT91C_DBGU_IDR"
296
+ AT91C_DBGU_IDR.description="Interrupt Disable Register"
297
+ AT91C_DBGU_IDR.helpkey="Interrupt Disable Register"
298
+ AT91C_DBGU_IDR.access=memorymapped
299
+ AT91C_DBGU_IDR.address=0xFFFFF20C
300
+ AT91C_DBGU_IDR.width=32
301
+ AT91C_DBGU_IDR.byteEndian=little
302
+ AT91C_DBGU_IDR.type=enum
303
+ AT91C_DBGU_IDR.enum.0.name=*** Write only ***
304
+ AT91C_DBGU_IDR.enum.1.name=Error
305
+ AT91C_DBGU_CSR.name="AT91C_DBGU_CSR"
306
+ AT91C_DBGU_CSR.description="Channel Status Register"
307
+ AT91C_DBGU_CSR.helpkey="Channel Status Register"
308
+ AT91C_DBGU_CSR.access=memorymapped
309
+ AT91C_DBGU_CSR.address=0xFFFFF214
310
+ AT91C_DBGU_CSR.width=32
311
+ AT91C_DBGU_CSR.byteEndian=little
312
+ AT91C_DBGU_CSR.permission.write=none
313
+ AT91C_DBGU_CIDR.name="AT91C_DBGU_CIDR"
314
+ AT91C_DBGU_CIDR.description="Chip ID Register"
315
+ AT91C_DBGU_CIDR.helpkey="Chip ID Register"
316
+ AT91C_DBGU_CIDR.access=memorymapped
317
+ AT91C_DBGU_CIDR.address=0xFFFFF240
318
+ AT91C_DBGU_CIDR.width=32
319
+ AT91C_DBGU_CIDR.byteEndian=little
320
+ AT91C_DBGU_CIDR.permission.write=none
321
+ AT91C_DBGU_MR.name="AT91C_DBGU_MR"
322
+ AT91C_DBGU_MR.description="Mode Register"
323
+ AT91C_DBGU_MR.helpkey="Mode Register"
324
+ AT91C_DBGU_MR.access=memorymapped
325
+ AT91C_DBGU_MR.address=0xFFFFF204
326
+ AT91C_DBGU_MR.width=32
327
+ AT91C_DBGU_MR.byteEndian=little
328
+ AT91C_DBGU_IMR.name="AT91C_DBGU_IMR"
329
+ AT91C_DBGU_IMR.description="Interrupt Mask Register"
330
+ AT91C_DBGU_IMR.helpkey="Interrupt Mask Register"
331
+ AT91C_DBGU_IMR.access=memorymapped
332
+ AT91C_DBGU_IMR.address=0xFFFFF210
333
+ AT91C_DBGU_IMR.width=32
334
+ AT91C_DBGU_IMR.byteEndian=little
335
+ AT91C_DBGU_IMR.permission.write=none
336
+ AT91C_DBGU_CR.name="AT91C_DBGU_CR"
337
+ AT91C_DBGU_CR.description="Control Register"
338
+ AT91C_DBGU_CR.helpkey="Control Register"
339
+ AT91C_DBGU_CR.access=memorymapped
340
+ AT91C_DBGU_CR.address=0xFFFFF200
341
+ AT91C_DBGU_CR.width=32
342
+ AT91C_DBGU_CR.byteEndian=little
343
+ AT91C_DBGU_CR.type=enum
344
+ AT91C_DBGU_CR.enum.0.name=*** Write only ***
345
+ AT91C_DBGU_CR.enum.1.name=Error
346
+ AT91C_DBGU_FNTR.name="AT91C_DBGU_FNTR"
347
+ AT91C_DBGU_FNTR.description="Force NTRST Register"
348
+ AT91C_DBGU_FNTR.helpkey="Force NTRST Register"
349
+ AT91C_DBGU_FNTR.access=memorymapped
350
+ AT91C_DBGU_FNTR.address=0xFFFFF248
351
+ AT91C_DBGU_FNTR.width=32
352
+ AT91C_DBGU_FNTR.byteEndian=little
353
+ AT91C_DBGU_THR.name="AT91C_DBGU_THR"
354
+ AT91C_DBGU_THR.description="Transmitter Holding Register"
355
+ AT91C_DBGU_THR.helpkey="Transmitter Holding Register"
356
+ AT91C_DBGU_THR.access=memorymapped
357
+ AT91C_DBGU_THR.address=0xFFFFF21C
358
+ AT91C_DBGU_THR.width=32
359
+ AT91C_DBGU_THR.byteEndian=little
360
+ AT91C_DBGU_THR.type=enum
361
+ AT91C_DBGU_THR.enum.0.name=*** Write only ***
362
+ AT91C_DBGU_THR.enum.1.name=Error
363
+ AT91C_DBGU_RHR.name="AT91C_DBGU_RHR"
364
+ AT91C_DBGU_RHR.description="Receiver Holding Register"
365
+ AT91C_DBGU_RHR.helpkey="Receiver Holding Register"
366
+ AT91C_DBGU_RHR.access=memorymapped
367
+ AT91C_DBGU_RHR.address=0xFFFFF218
368
+ AT91C_DBGU_RHR.width=32
369
+ AT91C_DBGU_RHR.byteEndian=little
370
+ AT91C_DBGU_RHR.permission.write=none
371
+ AT91C_DBGU_IER.name="AT91C_DBGU_IER"
372
+ AT91C_DBGU_IER.description="Interrupt Enable Register"
373
+ AT91C_DBGU_IER.helpkey="Interrupt Enable Register"
374
+ AT91C_DBGU_IER.access=memorymapped
375
+ AT91C_DBGU_IER.address=0xFFFFF208
376
+ AT91C_DBGU_IER.width=32
377
+ AT91C_DBGU_IER.byteEndian=little
378
+ AT91C_DBGU_IER.type=enum
379
+ AT91C_DBGU_IER.enum.0.name=*** Write only ***
380
+ AT91C_DBGU_IER.enum.1.name=Error
381
+ # ========== Register definition for PIOA peripheral ==========
382
+ AT91C_PIOA_ODR.name="AT91C_PIOA_ODR"
383
+ AT91C_PIOA_ODR.description="Output Disable Registerr"
384
+ AT91C_PIOA_ODR.helpkey="Output Disable Registerr"
385
+ AT91C_PIOA_ODR.access=memorymapped
386
+ AT91C_PIOA_ODR.address=0xFFFFF414
387
+ AT91C_PIOA_ODR.width=32
388
+ AT91C_PIOA_ODR.byteEndian=little
389
+ AT91C_PIOA_ODR.type=enum
390
+ AT91C_PIOA_ODR.enum.0.name=*** Write only ***
391
+ AT91C_PIOA_ODR.enum.1.name=Error
392
+ AT91C_PIOA_SODR.name="AT91C_PIOA_SODR"
393
+ AT91C_PIOA_SODR.description="Set Output Data Register"
394
+ AT91C_PIOA_SODR.helpkey="Set Output Data Register"
395
+ AT91C_PIOA_SODR.access=memorymapped
396
+ AT91C_PIOA_SODR.address=0xFFFFF430
397
+ AT91C_PIOA_SODR.width=32
398
+ AT91C_PIOA_SODR.byteEndian=little
399
+ AT91C_PIOA_SODR.type=enum
400
+ AT91C_PIOA_SODR.enum.0.name=*** Write only ***
401
+ AT91C_PIOA_SODR.enum.1.name=Error
402
+ AT91C_PIOA_ISR.name="AT91C_PIOA_ISR"
403
+ AT91C_PIOA_ISR.description="Interrupt Status Register"
404
+ AT91C_PIOA_ISR.helpkey="Interrupt Status Register"
405
+ AT91C_PIOA_ISR.access=memorymapped
406
+ AT91C_PIOA_ISR.address=0xFFFFF44C
407
+ AT91C_PIOA_ISR.width=32
408
+ AT91C_PIOA_ISR.byteEndian=little
409
+ AT91C_PIOA_ISR.permission.write=none
410
+ AT91C_PIOA_ABSR.name="AT91C_PIOA_ABSR"
411
+ AT91C_PIOA_ABSR.description="AB Select Status Register"
412
+ AT91C_PIOA_ABSR.helpkey="AB Select Status Register"
413
+ AT91C_PIOA_ABSR.access=memorymapped
414
+ AT91C_PIOA_ABSR.address=0xFFFFF478
415
+ AT91C_PIOA_ABSR.width=32
416
+ AT91C_PIOA_ABSR.byteEndian=little
417
+ AT91C_PIOA_ABSR.permission.write=none
418
+ AT91C_PIOA_IER.name="AT91C_PIOA_IER"
419
+ AT91C_PIOA_IER.description="Interrupt Enable Register"
420
+ AT91C_PIOA_IER.helpkey="Interrupt Enable Register"
421
+ AT91C_PIOA_IER.access=memorymapped
422
+ AT91C_PIOA_IER.address=0xFFFFF440
423
+ AT91C_PIOA_IER.width=32
424
+ AT91C_PIOA_IER.byteEndian=little
425
+ AT91C_PIOA_IER.type=enum
426
+ AT91C_PIOA_IER.enum.0.name=*** Write only ***
427
+ AT91C_PIOA_IER.enum.1.name=Error
428
+ AT91C_PIOA_PPUDR.name="AT91C_PIOA_PPUDR"
429
+ AT91C_PIOA_PPUDR.description="Pull-up Disable Register"
430
+ AT91C_PIOA_PPUDR.helpkey="Pull-up Disable Register"
431
+ AT91C_PIOA_PPUDR.access=memorymapped
432
+ AT91C_PIOA_PPUDR.address=0xFFFFF460
433
+ AT91C_PIOA_PPUDR.width=32
434
+ AT91C_PIOA_PPUDR.byteEndian=little
435
+ AT91C_PIOA_PPUDR.type=enum
436
+ AT91C_PIOA_PPUDR.enum.0.name=*** Write only ***
437
+ AT91C_PIOA_PPUDR.enum.1.name=Error
438
+ AT91C_PIOA_IMR.name="AT91C_PIOA_IMR"
439
+ AT91C_PIOA_IMR.description="Interrupt Mask Register"
440
+ AT91C_PIOA_IMR.helpkey="Interrupt Mask Register"
441
+ AT91C_PIOA_IMR.access=memorymapped
442
+ AT91C_PIOA_IMR.address=0xFFFFF448
443
+ AT91C_PIOA_IMR.width=32
444
+ AT91C_PIOA_IMR.byteEndian=little
445
+ AT91C_PIOA_IMR.permission.write=none
446
+ AT91C_PIOA_PER.name="AT91C_PIOA_PER"
447
+ AT91C_PIOA_PER.description="PIO Enable Register"
448
+ AT91C_PIOA_PER.helpkey="PIO Enable Register"
449
+ AT91C_PIOA_PER.access=memorymapped
450
+ AT91C_PIOA_PER.address=0xFFFFF400
451
+ AT91C_PIOA_PER.width=32
452
+ AT91C_PIOA_PER.byteEndian=little
453
+ AT91C_PIOA_PER.type=enum
454
+ AT91C_PIOA_PER.enum.0.name=*** Write only ***
455
+ AT91C_PIOA_PER.enum.1.name=Error
456
+ AT91C_PIOA_IFDR.name="AT91C_PIOA_IFDR"
457
+ AT91C_PIOA_IFDR.description="Input Filter Disable Register"
458
+ AT91C_PIOA_IFDR.helpkey="Input Filter Disable Register"
459
+ AT91C_PIOA_IFDR.access=memorymapped
460
+ AT91C_PIOA_IFDR.address=0xFFFFF424
461
+ AT91C_PIOA_IFDR.width=32
462
+ AT91C_PIOA_IFDR.byteEndian=little
463
+ AT91C_PIOA_IFDR.type=enum
464
+ AT91C_PIOA_IFDR.enum.0.name=*** Write only ***
465
+ AT91C_PIOA_IFDR.enum.1.name=Error
466
+ AT91C_PIOA_OWDR.name="AT91C_PIOA_OWDR"
467
+ AT91C_PIOA_OWDR.description="Output Write Disable Register"
468
+ AT91C_PIOA_OWDR.helpkey="Output Write Disable Register"
469
+ AT91C_PIOA_OWDR.access=memorymapped
470
+ AT91C_PIOA_OWDR.address=0xFFFFF4A4
471
+ AT91C_PIOA_OWDR.width=32
472
+ AT91C_PIOA_OWDR.byteEndian=little
473
+ AT91C_PIOA_OWDR.type=enum
474
+ AT91C_PIOA_OWDR.enum.0.name=*** Write only ***
475
+ AT91C_PIOA_OWDR.enum.1.name=Error
476
+ AT91C_PIOA_MDSR.name="AT91C_PIOA_MDSR"
477
+ AT91C_PIOA_MDSR.description="Multi-driver Status Register"
478
+ AT91C_PIOA_MDSR.helpkey="Multi-driver Status Register"
479
+ AT91C_PIOA_MDSR.access=memorymapped
480
+ AT91C_PIOA_MDSR.address=0xFFFFF458
481
+ AT91C_PIOA_MDSR.width=32
482
+ AT91C_PIOA_MDSR.byteEndian=little
483
+ AT91C_PIOA_MDSR.permission.write=none
484
+ AT91C_PIOA_IDR.name="AT91C_PIOA_IDR"
485
+ AT91C_PIOA_IDR.description="Interrupt Disable Register"
486
+ AT91C_PIOA_IDR.helpkey="Interrupt Disable Register"
487
+ AT91C_PIOA_IDR.access=memorymapped
488
+ AT91C_PIOA_IDR.address=0xFFFFF444
489
+ AT91C_PIOA_IDR.width=32
490
+ AT91C_PIOA_IDR.byteEndian=little
491
+ AT91C_PIOA_IDR.type=enum
492
+ AT91C_PIOA_IDR.enum.0.name=*** Write only ***
493
+ AT91C_PIOA_IDR.enum.1.name=Error
494
+ AT91C_PIOA_ODSR.name="AT91C_PIOA_ODSR"
495
+ AT91C_PIOA_ODSR.description="Output Data Status Register"
496
+ AT91C_PIOA_ODSR.helpkey="Output Data Status Register"
497
+ AT91C_PIOA_ODSR.access=memorymapped
498
+ AT91C_PIOA_ODSR.address=0xFFFFF438
499
+ AT91C_PIOA_ODSR.width=32
500
+ AT91C_PIOA_ODSR.byteEndian=little
501
+ AT91C_PIOA_ODSR.permission.write=none
502
+ AT91C_PIOA_PPUSR.name="AT91C_PIOA_PPUSR"
503
+ AT91C_PIOA_PPUSR.description="Pull-up Status Register"
504
+ AT91C_PIOA_PPUSR.helpkey="Pull-up Status Register"
505
+ AT91C_PIOA_PPUSR.access=memorymapped
506
+ AT91C_PIOA_PPUSR.address=0xFFFFF468
507
+ AT91C_PIOA_PPUSR.width=32
508
+ AT91C_PIOA_PPUSR.byteEndian=little
509
+ AT91C_PIOA_PPUSR.permission.write=none
510
+ AT91C_PIOA_OWSR.name="AT91C_PIOA_OWSR"
511
+ AT91C_PIOA_OWSR.description="Output Write Status Register"
512
+ AT91C_PIOA_OWSR.helpkey="Output Write Status Register"
513
+ AT91C_PIOA_OWSR.access=memorymapped
514
+ AT91C_PIOA_OWSR.address=0xFFFFF4A8
515
+ AT91C_PIOA_OWSR.width=32
516
+ AT91C_PIOA_OWSR.byteEndian=little
517
+ AT91C_PIOA_OWSR.permission.write=none
518
+ AT91C_PIOA_BSR.name="AT91C_PIOA_BSR"
519
+ AT91C_PIOA_BSR.description="Select B Register"
520
+ AT91C_PIOA_BSR.helpkey="Select B Register"
521
+ AT91C_PIOA_BSR.access=memorymapped
522
+ AT91C_PIOA_BSR.address=0xFFFFF474
523
+ AT91C_PIOA_BSR.width=32
524
+ AT91C_PIOA_BSR.byteEndian=little
525
+ AT91C_PIOA_BSR.type=enum
526
+ AT91C_PIOA_BSR.enum.0.name=*** Write only ***
527
+ AT91C_PIOA_BSR.enum.1.name=Error
528
+ AT91C_PIOA_OWER.name="AT91C_PIOA_OWER"
529
+ AT91C_PIOA_OWER.description="Output Write Enable Register"
530
+ AT91C_PIOA_OWER.helpkey="Output Write Enable Register"
531
+ AT91C_PIOA_OWER.access=memorymapped
532
+ AT91C_PIOA_OWER.address=0xFFFFF4A0
533
+ AT91C_PIOA_OWER.width=32
534
+ AT91C_PIOA_OWER.byteEndian=little
535
+ AT91C_PIOA_OWER.type=enum
536
+ AT91C_PIOA_OWER.enum.0.name=*** Write only ***
537
+ AT91C_PIOA_OWER.enum.1.name=Error
538
+ AT91C_PIOA_IFER.name="AT91C_PIOA_IFER"
539
+ AT91C_PIOA_IFER.description="Input Filter Enable Register"
540
+ AT91C_PIOA_IFER.helpkey="Input Filter Enable Register"
541
+ AT91C_PIOA_IFER.access=memorymapped
542
+ AT91C_PIOA_IFER.address=0xFFFFF420
543
+ AT91C_PIOA_IFER.width=32
544
+ AT91C_PIOA_IFER.byteEndian=little
545
+ AT91C_PIOA_IFER.type=enum
546
+ AT91C_PIOA_IFER.enum.0.name=*** Write only ***
547
+ AT91C_PIOA_IFER.enum.1.name=Error
548
+ AT91C_PIOA_PDSR.name="AT91C_PIOA_PDSR"
549
+ AT91C_PIOA_PDSR.description="Pin Data Status Register"
550
+ AT91C_PIOA_PDSR.helpkey="Pin Data Status Register"
551
+ AT91C_PIOA_PDSR.access=memorymapped
552
+ AT91C_PIOA_PDSR.address=0xFFFFF43C
553
+ AT91C_PIOA_PDSR.width=32
554
+ AT91C_PIOA_PDSR.byteEndian=little
555
+ AT91C_PIOA_PDSR.permission.write=none
556
+ AT91C_PIOA_PPUER.name="AT91C_PIOA_PPUER"
557
+ AT91C_PIOA_PPUER.description="Pull-up Enable Register"
558
+ AT91C_PIOA_PPUER.helpkey="Pull-up Enable Register"
559
+ AT91C_PIOA_PPUER.access=memorymapped
560
+ AT91C_PIOA_PPUER.address=0xFFFFF464
561
+ AT91C_PIOA_PPUER.width=32
562
+ AT91C_PIOA_PPUER.byteEndian=little
563
+ AT91C_PIOA_PPUER.type=enum
564
+ AT91C_PIOA_PPUER.enum.0.name=*** Write only ***
565
+ AT91C_PIOA_PPUER.enum.1.name=Error
566
+ AT91C_PIOA_OSR.name="AT91C_PIOA_OSR"
567
+ AT91C_PIOA_OSR.description="Output Status Register"
568
+ AT91C_PIOA_OSR.helpkey="Output Status Register"
569
+ AT91C_PIOA_OSR.access=memorymapped
570
+ AT91C_PIOA_OSR.address=0xFFFFF418
571
+ AT91C_PIOA_OSR.width=32
572
+ AT91C_PIOA_OSR.byteEndian=little
573
+ AT91C_PIOA_OSR.permission.write=none
574
+ AT91C_PIOA_ASR.name="AT91C_PIOA_ASR"
575
+ AT91C_PIOA_ASR.description="Select A Register"
576
+ AT91C_PIOA_ASR.helpkey="Select A Register"
577
+ AT91C_PIOA_ASR.access=memorymapped
578
+ AT91C_PIOA_ASR.address=0xFFFFF470
579
+ AT91C_PIOA_ASR.width=32
580
+ AT91C_PIOA_ASR.byteEndian=little
581
+ AT91C_PIOA_ASR.type=enum
582
+ AT91C_PIOA_ASR.enum.0.name=*** Write only ***
583
+ AT91C_PIOA_ASR.enum.1.name=Error
584
+ AT91C_PIOA_MDDR.name="AT91C_PIOA_MDDR"
585
+ AT91C_PIOA_MDDR.description="Multi-driver Disable Register"
586
+ AT91C_PIOA_MDDR.helpkey="Multi-driver Disable Register"
587
+ AT91C_PIOA_MDDR.access=memorymapped
588
+ AT91C_PIOA_MDDR.address=0xFFFFF454
589
+ AT91C_PIOA_MDDR.width=32
590
+ AT91C_PIOA_MDDR.byteEndian=little
591
+ AT91C_PIOA_MDDR.type=enum
592
+ AT91C_PIOA_MDDR.enum.0.name=*** Write only ***
593
+ AT91C_PIOA_MDDR.enum.1.name=Error
594
+ AT91C_PIOA_CODR.name="AT91C_PIOA_CODR"
595
+ AT91C_PIOA_CODR.description="Clear Output Data Register"
596
+ AT91C_PIOA_CODR.helpkey="Clear Output Data Register"
597
+ AT91C_PIOA_CODR.access=memorymapped
598
+ AT91C_PIOA_CODR.address=0xFFFFF434
599
+ AT91C_PIOA_CODR.width=32
600
+ AT91C_PIOA_CODR.byteEndian=little
601
+ AT91C_PIOA_CODR.type=enum
602
+ AT91C_PIOA_CODR.enum.0.name=*** Write only ***
603
+ AT91C_PIOA_CODR.enum.1.name=Error
604
+ AT91C_PIOA_MDER.name="AT91C_PIOA_MDER"
605
+ AT91C_PIOA_MDER.description="Multi-driver Enable Register"
606
+ AT91C_PIOA_MDER.helpkey="Multi-driver Enable Register"
607
+ AT91C_PIOA_MDER.access=memorymapped
608
+ AT91C_PIOA_MDER.address=0xFFFFF450
609
+ AT91C_PIOA_MDER.width=32
610
+ AT91C_PIOA_MDER.byteEndian=little
611
+ AT91C_PIOA_MDER.type=enum
612
+ AT91C_PIOA_MDER.enum.0.name=*** Write only ***
613
+ AT91C_PIOA_MDER.enum.1.name=Error
614
+ AT91C_PIOA_PDR.name="AT91C_PIOA_PDR"
615
+ AT91C_PIOA_PDR.description="PIO Disable Register"
616
+ AT91C_PIOA_PDR.helpkey="PIO Disable Register"
617
+ AT91C_PIOA_PDR.access=memorymapped
618
+ AT91C_PIOA_PDR.address=0xFFFFF404
619
+ AT91C_PIOA_PDR.width=32
620
+ AT91C_PIOA_PDR.byteEndian=little
621
+ AT91C_PIOA_PDR.type=enum
622
+ AT91C_PIOA_PDR.enum.0.name=*** Write only ***
623
+ AT91C_PIOA_PDR.enum.1.name=Error
624
+ AT91C_PIOA_IFSR.name="AT91C_PIOA_IFSR"
625
+ AT91C_PIOA_IFSR.description="Input Filter Status Register"
626
+ AT91C_PIOA_IFSR.helpkey="Input Filter Status Register"
627
+ AT91C_PIOA_IFSR.access=memorymapped
628
+ AT91C_PIOA_IFSR.address=0xFFFFF428
629
+ AT91C_PIOA_IFSR.width=32
630
+ AT91C_PIOA_IFSR.byteEndian=little
631
+ AT91C_PIOA_IFSR.permission.write=none
632
+ AT91C_PIOA_OER.name="AT91C_PIOA_OER"
633
+ AT91C_PIOA_OER.description="Output Enable Register"
634
+ AT91C_PIOA_OER.helpkey="Output Enable Register"
635
+ AT91C_PIOA_OER.access=memorymapped
636
+ AT91C_PIOA_OER.address=0xFFFFF410
637
+ AT91C_PIOA_OER.width=32
638
+ AT91C_PIOA_OER.byteEndian=little
639
+ AT91C_PIOA_OER.type=enum
640
+ AT91C_PIOA_OER.enum.0.name=*** Write only ***
641
+ AT91C_PIOA_OER.enum.1.name=Error
642
+ AT91C_PIOA_PSR.name="AT91C_PIOA_PSR"
643
+ AT91C_PIOA_PSR.description="PIO Status Register"
644
+ AT91C_PIOA_PSR.helpkey="PIO Status Register"
645
+ AT91C_PIOA_PSR.access=memorymapped
646
+ AT91C_PIOA_PSR.address=0xFFFFF408
647
+ AT91C_PIOA_PSR.width=32
648
+ AT91C_PIOA_PSR.byteEndian=little
649
+ AT91C_PIOA_PSR.permission.write=none
650
+ # ========== Register definition for PIOB peripheral ==========
651
+ AT91C_PIOB_OWDR.name="AT91C_PIOB_OWDR"
652
+ AT91C_PIOB_OWDR.description="Output Write Disable Register"
653
+ AT91C_PIOB_OWDR.helpkey="Output Write Disable Register"
654
+ AT91C_PIOB_OWDR.access=memorymapped
655
+ AT91C_PIOB_OWDR.address=0xFFFFF6A4
656
+ AT91C_PIOB_OWDR.width=32
657
+ AT91C_PIOB_OWDR.byteEndian=little
658
+ AT91C_PIOB_OWDR.type=enum
659
+ AT91C_PIOB_OWDR.enum.0.name=*** Write only ***
660
+ AT91C_PIOB_OWDR.enum.1.name=Error
661
+ AT91C_PIOB_MDER.name="AT91C_PIOB_MDER"
662
+ AT91C_PIOB_MDER.description="Multi-driver Enable Register"
663
+ AT91C_PIOB_MDER.helpkey="Multi-driver Enable Register"
664
+ AT91C_PIOB_MDER.access=memorymapped
665
+ AT91C_PIOB_MDER.address=0xFFFFF650
666
+ AT91C_PIOB_MDER.width=32
667
+ AT91C_PIOB_MDER.byteEndian=little
668
+ AT91C_PIOB_MDER.type=enum
669
+ AT91C_PIOB_MDER.enum.0.name=*** Write only ***
670
+ AT91C_PIOB_MDER.enum.1.name=Error
671
+ AT91C_PIOB_PPUSR.name="AT91C_PIOB_PPUSR"
672
+ AT91C_PIOB_PPUSR.description="Pull-up Status Register"
673
+ AT91C_PIOB_PPUSR.helpkey="Pull-up Status Register"
674
+ AT91C_PIOB_PPUSR.access=memorymapped
675
+ AT91C_PIOB_PPUSR.address=0xFFFFF668
676
+ AT91C_PIOB_PPUSR.width=32
677
+ AT91C_PIOB_PPUSR.byteEndian=little
678
+ AT91C_PIOB_PPUSR.permission.write=none
679
+ AT91C_PIOB_IMR.name="AT91C_PIOB_IMR"
680
+ AT91C_PIOB_IMR.description="Interrupt Mask Register"
681
+ AT91C_PIOB_IMR.helpkey="Interrupt Mask Register"
682
+ AT91C_PIOB_IMR.access=memorymapped
683
+ AT91C_PIOB_IMR.address=0xFFFFF648
684
+ AT91C_PIOB_IMR.width=32
685
+ AT91C_PIOB_IMR.byteEndian=little
686
+ AT91C_PIOB_IMR.permission.write=none
687
+ AT91C_PIOB_ASR.name="AT91C_PIOB_ASR"
688
+ AT91C_PIOB_ASR.description="Select A Register"
689
+ AT91C_PIOB_ASR.helpkey="Select A Register"
690
+ AT91C_PIOB_ASR.access=memorymapped
691
+ AT91C_PIOB_ASR.address=0xFFFFF670
692
+ AT91C_PIOB_ASR.width=32
693
+ AT91C_PIOB_ASR.byteEndian=little
694
+ AT91C_PIOB_ASR.type=enum
695
+ AT91C_PIOB_ASR.enum.0.name=*** Write only ***
696
+ AT91C_PIOB_ASR.enum.1.name=Error
697
+ AT91C_PIOB_PPUDR.name="AT91C_PIOB_PPUDR"
698
+ AT91C_PIOB_PPUDR.description="Pull-up Disable Register"
699
+ AT91C_PIOB_PPUDR.helpkey="Pull-up Disable Register"
700
+ AT91C_PIOB_PPUDR.access=memorymapped
701
+ AT91C_PIOB_PPUDR.address=0xFFFFF660
702
+ AT91C_PIOB_PPUDR.width=32
703
+ AT91C_PIOB_PPUDR.byteEndian=little
704
+ AT91C_PIOB_PPUDR.type=enum
705
+ AT91C_PIOB_PPUDR.enum.0.name=*** Write only ***
706
+ AT91C_PIOB_PPUDR.enum.1.name=Error
707
+ AT91C_PIOB_PSR.name="AT91C_PIOB_PSR"
708
+ AT91C_PIOB_PSR.description="PIO Status Register"
709
+ AT91C_PIOB_PSR.helpkey="PIO Status Register"
710
+ AT91C_PIOB_PSR.access=memorymapped
711
+ AT91C_PIOB_PSR.address=0xFFFFF608
712
+ AT91C_PIOB_PSR.width=32
713
+ AT91C_PIOB_PSR.byteEndian=little
714
+ AT91C_PIOB_PSR.permission.write=none
715
+ AT91C_PIOB_IER.name="AT91C_PIOB_IER"
716
+ AT91C_PIOB_IER.description="Interrupt Enable Register"
717
+ AT91C_PIOB_IER.helpkey="Interrupt Enable Register"
718
+ AT91C_PIOB_IER.access=memorymapped
719
+ AT91C_PIOB_IER.address=0xFFFFF640
720
+ AT91C_PIOB_IER.width=32
721
+ AT91C_PIOB_IER.byteEndian=little
722
+ AT91C_PIOB_IER.type=enum
723
+ AT91C_PIOB_IER.enum.0.name=*** Write only ***
724
+ AT91C_PIOB_IER.enum.1.name=Error
725
+ AT91C_PIOB_CODR.name="AT91C_PIOB_CODR"
726
+ AT91C_PIOB_CODR.description="Clear Output Data Register"
727
+ AT91C_PIOB_CODR.helpkey="Clear Output Data Register"
728
+ AT91C_PIOB_CODR.access=memorymapped
729
+ AT91C_PIOB_CODR.address=0xFFFFF634
730
+ AT91C_PIOB_CODR.width=32
731
+ AT91C_PIOB_CODR.byteEndian=little
732
+ AT91C_PIOB_CODR.type=enum
733
+ AT91C_PIOB_CODR.enum.0.name=*** Write only ***
734
+ AT91C_PIOB_CODR.enum.1.name=Error
735
+ AT91C_PIOB_OWER.name="AT91C_PIOB_OWER"
736
+ AT91C_PIOB_OWER.description="Output Write Enable Register"
737
+ AT91C_PIOB_OWER.helpkey="Output Write Enable Register"
738
+ AT91C_PIOB_OWER.access=memorymapped
739
+ AT91C_PIOB_OWER.address=0xFFFFF6A0
740
+ AT91C_PIOB_OWER.width=32
741
+ AT91C_PIOB_OWER.byteEndian=little
742
+ AT91C_PIOB_OWER.type=enum
743
+ AT91C_PIOB_OWER.enum.0.name=*** Write only ***
744
+ AT91C_PIOB_OWER.enum.1.name=Error
745
+ AT91C_PIOB_ABSR.name="AT91C_PIOB_ABSR"
746
+ AT91C_PIOB_ABSR.description="AB Select Status Register"
747
+ AT91C_PIOB_ABSR.helpkey="AB Select Status Register"
748
+ AT91C_PIOB_ABSR.access=memorymapped
749
+ AT91C_PIOB_ABSR.address=0xFFFFF678
750
+ AT91C_PIOB_ABSR.width=32
751
+ AT91C_PIOB_ABSR.byteEndian=little
752
+ AT91C_PIOB_ABSR.permission.write=none
753
+ AT91C_PIOB_IFDR.name="AT91C_PIOB_IFDR"
754
+ AT91C_PIOB_IFDR.description="Input Filter Disable Register"
755
+ AT91C_PIOB_IFDR.helpkey="Input Filter Disable Register"
756
+ AT91C_PIOB_IFDR.access=memorymapped
757
+ AT91C_PIOB_IFDR.address=0xFFFFF624
758
+ AT91C_PIOB_IFDR.width=32
759
+ AT91C_PIOB_IFDR.byteEndian=little
760
+ AT91C_PIOB_IFDR.type=enum
761
+ AT91C_PIOB_IFDR.enum.0.name=*** Write only ***
762
+ AT91C_PIOB_IFDR.enum.1.name=Error
763
+ AT91C_PIOB_PDSR.name="AT91C_PIOB_PDSR"
764
+ AT91C_PIOB_PDSR.description="Pin Data Status Register"
765
+ AT91C_PIOB_PDSR.helpkey="Pin Data Status Register"
766
+ AT91C_PIOB_PDSR.access=memorymapped
767
+ AT91C_PIOB_PDSR.address=0xFFFFF63C
768
+ AT91C_PIOB_PDSR.width=32
769
+ AT91C_PIOB_PDSR.byteEndian=little
770
+ AT91C_PIOB_PDSR.permission.write=none
771
+ AT91C_PIOB_IDR.name="AT91C_PIOB_IDR"
772
+ AT91C_PIOB_IDR.description="Interrupt Disable Register"
773
+ AT91C_PIOB_IDR.helpkey="Interrupt Disable Register"
774
+ AT91C_PIOB_IDR.access=memorymapped
775
+ AT91C_PIOB_IDR.address=0xFFFFF644
776
+ AT91C_PIOB_IDR.width=32
777
+ AT91C_PIOB_IDR.byteEndian=little
778
+ AT91C_PIOB_IDR.type=enum
779
+ AT91C_PIOB_IDR.enum.0.name=*** Write only ***
780
+ AT91C_PIOB_IDR.enum.1.name=Error
781
+ AT91C_PIOB_OWSR.name="AT91C_PIOB_OWSR"
782
+ AT91C_PIOB_OWSR.description="Output Write Status Register"
783
+ AT91C_PIOB_OWSR.helpkey="Output Write Status Register"
784
+ AT91C_PIOB_OWSR.access=memorymapped
785
+ AT91C_PIOB_OWSR.address=0xFFFFF6A8
786
+ AT91C_PIOB_OWSR.width=32
787
+ AT91C_PIOB_OWSR.byteEndian=little
788
+ AT91C_PIOB_OWSR.permission.write=none
789
+ AT91C_PIOB_PDR.name="AT91C_PIOB_PDR"
790
+ AT91C_PIOB_PDR.description="PIO Disable Register"
791
+ AT91C_PIOB_PDR.helpkey="PIO Disable Register"
792
+ AT91C_PIOB_PDR.access=memorymapped
793
+ AT91C_PIOB_PDR.address=0xFFFFF604
794
+ AT91C_PIOB_PDR.width=32
795
+ AT91C_PIOB_PDR.byteEndian=little
796
+ AT91C_PIOB_PDR.type=enum
797
+ AT91C_PIOB_PDR.enum.0.name=*** Write only ***
798
+ AT91C_PIOB_PDR.enum.1.name=Error
799
+ AT91C_PIOB_ODR.name="AT91C_PIOB_ODR"
800
+ AT91C_PIOB_ODR.description="Output Disable Registerr"
801
+ AT91C_PIOB_ODR.helpkey="Output Disable Registerr"
802
+ AT91C_PIOB_ODR.access=memorymapped
803
+ AT91C_PIOB_ODR.address=0xFFFFF614
804
+ AT91C_PIOB_ODR.width=32
805
+ AT91C_PIOB_ODR.byteEndian=little
806
+ AT91C_PIOB_ODR.type=enum
807
+ AT91C_PIOB_ODR.enum.0.name=*** Write only ***
808
+ AT91C_PIOB_ODR.enum.1.name=Error
809
+ AT91C_PIOB_IFSR.name="AT91C_PIOB_IFSR"
810
+ AT91C_PIOB_IFSR.description="Input Filter Status Register"
811
+ AT91C_PIOB_IFSR.helpkey="Input Filter Status Register"
812
+ AT91C_PIOB_IFSR.access=memorymapped
813
+ AT91C_PIOB_IFSR.address=0xFFFFF628
814
+ AT91C_PIOB_IFSR.width=32
815
+ AT91C_PIOB_IFSR.byteEndian=little
816
+ AT91C_PIOB_IFSR.permission.write=none
817
+ AT91C_PIOB_PPUER.name="AT91C_PIOB_PPUER"
818
+ AT91C_PIOB_PPUER.description="Pull-up Enable Register"
819
+ AT91C_PIOB_PPUER.helpkey="Pull-up Enable Register"
820
+ AT91C_PIOB_PPUER.access=memorymapped
821
+ AT91C_PIOB_PPUER.address=0xFFFFF664
822
+ AT91C_PIOB_PPUER.width=32
823
+ AT91C_PIOB_PPUER.byteEndian=little
824
+ AT91C_PIOB_PPUER.type=enum
825
+ AT91C_PIOB_PPUER.enum.0.name=*** Write only ***
826
+ AT91C_PIOB_PPUER.enum.1.name=Error
827
+ AT91C_PIOB_SODR.name="AT91C_PIOB_SODR"
828
+ AT91C_PIOB_SODR.description="Set Output Data Register"
829
+ AT91C_PIOB_SODR.helpkey="Set Output Data Register"
830
+ AT91C_PIOB_SODR.access=memorymapped
831
+ AT91C_PIOB_SODR.address=0xFFFFF630
832
+ AT91C_PIOB_SODR.width=32
833
+ AT91C_PIOB_SODR.byteEndian=little
834
+ AT91C_PIOB_SODR.type=enum
835
+ AT91C_PIOB_SODR.enum.0.name=*** Write only ***
836
+ AT91C_PIOB_SODR.enum.1.name=Error
837
+ AT91C_PIOB_ISR.name="AT91C_PIOB_ISR"
838
+ AT91C_PIOB_ISR.description="Interrupt Status Register"
839
+ AT91C_PIOB_ISR.helpkey="Interrupt Status Register"
840
+ AT91C_PIOB_ISR.access=memorymapped
841
+ AT91C_PIOB_ISR.address=0xFFFFF64C
842
+ AT91C_PIOB_ISR.width=32
843
+ AT91C_PIOB_ISR.byteEndian=little
844
+ AT91C_PIOB_ISR.permission.write=none
845
+ AT91C_PIOB_ODSR.name="AT91C_PIOB_ODSR"
846
+ AT91C_PIOB_ODSR.description="Output Data Status Register"
847
+ AT91C_PIOB_ODSR.helpkey="Output Data Status Register"
848
+ AT91C_PIOB_ODSR.access=memorymapped
849
+ AT91C_PIOB_ODSR.address=0xFFFFF638
850
+ AT91C_PIOB_ODSR.width=32
851
+ AT91C_PIOB_ODSR.byteEndian=little
852
+ AT91C_PIOB_ODSR.permission.write=none
853
+ AT91C_PIOB_OSR.name="AT91C_PIOB_OSR"
854
+ AT91C_PIOB_OSR.description="Output Status Register"
855
+ AT91C_PIOB_OSR.helpkey="Output Status Register"
856
+ AT91C_PIOB_OSR.access=memorymapped
857
+ AT91C_PIOB_OSR.address=0xFFFFF618
858
+ AT91C_PIOB_OSR.width=32
859
+ AT91C_PIOB_OSR.byteEndian=little
860
+ AT91C_PIOB_OSR.permission.write=none
861
+ AT91C_PIOB_MDSR.name="AT91C_PIOB_MDSR"
862
+ AT91C_PIOB_MDSR.description="Multi-driver Status Register"
863
+ AT91C_PIOB_MDSR.helpkey="Multi-driver Status Register"
864
+ AT91C_PIOB_MDSR.access=memorymapped
865
+ AT91C_PIOB_MDSR.address=0xFFFFF658
866
+ AT91C_PIOB_MDSR.width=32
867
+ AT91C_PIOB_MDSR.byteEndian=little
868
+ AT91C_PIOB_MDSR.permission.write=none
869
+ AT91C_PIOB_IFER.name="AT91C_PIOB_IFER"
870
+ AT91C_PIOB_IFER.description="Input Filter Enable Register"
871
+ AT91C_PIOB_IFER.helpkey="Input Filter Enable Register"
872
+ AT91C_PIOB_IFER.access=memorymapped
873
+ AT91C_PIOB_IFER.address=0xFFFFF620
874
+ AT91C_PIOB_IFER.width=32
875
+ AT91C_PIOB_IFER.byteEndian=little
876
+ AT91C_PIOB_IFER.type=enum
877
+ AT91C_PIOB_IFER.enum.0.name=*** Write only ***
878
+ AT91C_PIOB_IFER.enum.1.name=Error
879
+ AT91C_PIOB_BSR.name="AT91C_PIOB_BSR"
880
+ AT91C_PIOB_BSR.description="Select B Register"
881
+ AT91C_PIOB_BSR.helpkey="Select B Register"
882
+ AT91C_PIOB_BSR.access=memorymapped
883
+ AT91C_PIOB_BSR.address=0xFFFFF674
884
+ AT91C_PIOB_BSR.width=32
885
+ AT91C_PIOB_BSR.byteEndian=little
886
+ AT91C_PIOB_BSR.type=enum
887
+ AT91C_PIOB_BSR.enum.0.name=*** Write only ***
888
+ AT91C_PIOB_BSR.enum.1.name=Error
889
+ AT91C_PIOB_MDDR.name="AT91C_PIOB_MDDR"
890
+ AT91C_PIOB_MDDR.description="Multi-driver Disable Register"
891
+ AT91C_PIOB_MDDR.helpkey="Multi-driver Disable Register"
892
+ AT91C_PIOB_MDDR.access=memorymapped
893
+ AT91C_PIOB_MDDR.address=0xFFFFF654
894
+ AT91C_PIOB_MDDR.width=32
895
+ AT91C_PIOB_MDDR.byteEndian=little
896
+ AT91C_PIOB_MDDR.type=enum
897
+ AT91C_PIOB_MDDR.enum.0.name=*** Write only ***
898
+ AT91C_PIOB_MDDR.enum.1.name=Error
899
+ AT91C_PIOB_OER.name="AT91C_PIOB_OER"
900
+ AT91C_PIOB_OER.description="Output Enable Register"
901
+ AT91C_PIOB_OER.helpkey="Output Enable Register"
902
+ AT91C_PIOB_OER.access=memorymapped
903
+ AT91C_PIOB_OER.address=0xFFFFF610
904
+ AT91C_PIOB_OER.width=32
905
+ AT91C_PIOB_OER.byteEndian=little
906
+ AT91C_PIOB_OER.type=enum
907
+ AT91C_PIOB_OER.enum.0.name=*** Write only ***
908
+ AT91C_PIOB_OER.enum.1.name=Error
909
+ AT91C_PIOB_PER.name="AT91C_PIOB_PER"
910
+ AT91C_PIOB_PER.description="PIO Enable Register"
911
+ AT91C_PIOB_PER.helpkey="PIO Enable Register"
912
+ AT91C_PIOB_PER.access=memorymapped
913
+ AT91C_PIOB_PER.address=0xFFFFF600
914
+ AT91C_PIOB_PER.width=32
915
+ AT91C_PIOB_PER.byteEndian=little
916
+ AT91C_PIOB_PER.type=enum
917
+ AT91C_PIOB_PER.enum.0.name=*** Write only ***
918
+ AT91C_PIOB_PER.enum.1.name=Error
919
+ # ========== Register definition for CKGR peripheral ==========
920
+ AT91C_CKGR_MOR.name="AT91C_CKGR_MOR"
921
+ AT91C_CKGR_MOR.description="Main Oscillator Register"
922
+ AT91C_CKGR_MOR.helpkey="Main Oscillator Register"
923
+ AT91C_CKGR_MOR.access=memorymapped
924
+ AT91C_CKGR_MOR.address=0xFFFFFC20
925
+ AT91C_CKGR_MOR.width=32
926
+ AT91C_CKGR_MOR.byteEndian=little
927
+ AT91C_CKGR_PLLR.name="AT91C_CKGR_PLLR"
928
+ AT91C_CKGR_PLLR.description="PLL Register"
929
+ AT91C_CKGR_PLLR.helpkey="PLL Register"
930
+ AT91C_CKGR_PLLR.access=memorymapped
931
+ AT91C_CKGR_PLLR.address=0xFFFFFC2C
932
+ AT91C_CKGR_PLLR.width=32
933
+ AT91C_CKGR_PLLR.byteEndian=little
934
+ AT91C_CKGR_MCFR.name="AT91C_CKGR_MCFR"
935
+ AT91C_CKGR_MCFR.description="Main Clock Frequency Register"
936
+ AT91C_CKGR_MCFR.helpkey="Main Clock Frequency Register"
937
+ AT91C_CKGR_MCFR.access=memorymapped
938
+ AT91C_CKGR_MCFR.address=0xFFFFFC24
939
+ AT91C_CKGR_MCFR.width=32
940
+ AT91C_CKGR_MCFR.byteEndian=little
941
+ AT91C_CKGR_MCFR.permission.write=none
942
+ # ========== Register definition for PMC peripheral ==========
943
+ AT91C_PMC_IDR.name="AT91C_PMC_IDR"
944
+ AT91C_PMC_IDR.description="Interrupt Disable Register"
945
+ AT91C_PMC_IDR.helpkey="Interrupt Disable Register"
946
+ AT91C_PMC_IDR.access=memorymapped
947
+ AT91C_PMC_IDR.address=0xFFFFFC64
948
+ AT91C_PMC_IDR.width=32
949
+ AT91C_PMC_IDR.byteEndian=little
950
+ AT91C_PMC_IDR.type=enum
951
+ AT91C_PMC_IDR.enum.0.name=*** Write only ***
952
+ AT91C_PMC_IDR.enum.1.name=Error
953
+ AT91C_PMC_MOR.name="AT91C_PMC_MOR"
954
+ AT91C_PMC_MOR.description="Main Oscillator Register"
955
+ AT91C_PMC_MOR.helpkey="Main Oscillator Register"
956
+ AT91C_PMC_MOR.access=memorymapped
957
+ AT91C_PMC_MOR.address=0xFFFFFC20
958
+ AT91C_PMC_MOR.width=32
959
+ AT91C_PMC_MOR.byteEndian=little
960
+ AT91C_PMC_PLLR.name="AT91C_PMC_PLLR"
961
+ AT91C_PMC_PLLR.description="PLL Register"
962
+ AT91C_PMC_PLLR.helpkey="PLL Register"
963
+ AT91C_PMC_PLLR.access=memorymapped
964
+ AT91C_PMC_PLLR.address=0xFFFFFC2C
965
+ AT91C_PMC_PLLR.width=32
966
+ AT91C_PMC_PLLR.byteEndian=little
967
+ AT91C_PMC_PCER.name="AT91C_PMC_PCER"
968
+ AT91C_PMC_PCER.description="Peripheral Clock Enable Register"
969
+ AT91C_PMC_PCER.helpkey="Peripheral Clock Enable Register"
970
+ AT91C_PMC_PCER.access=memorymapped
971
+ AT91C_PMC_PCER.address=0xFFFFFC10
972
+ AT91C_PMC_PCER.width=32
973
+ AT91C_PMC_PCER.byteEndian=little
974
+ AT91C_PMC_PCER.type=enum
975
+ AT91C_PMC_PCER.enum.0.name=*** Write only ***
976
+ AT91C_PMC_PCER.enum.1.name=Error
977
+ AT91C_PMC_PCKR.name="AT91C_PMC_PCKR"
978
+ AT91C_PMC_PCKR.description="Programmable Clock Register"
979
+ AT91C_PMC_PCKR.helpkey="Programmable Clock Register"
980
+ AT91C_PMC_PCKR.access=memorymapped
981
+ AT91C_PMC_PCKR.address=0xFFFFFC40
982
+ AT91C_PMC_PCKR.width=32
983
+ AT91C_PMC_PCKR.byteEndian=little
984
+ AT91C_PMC_MCKR.name="AT91C_PMC_MCKR"
985
+ AT91C_PMC_MCKR.description="Master Clock Register"
986
+ AT91C_PMC_MCKR.helpkey="Master Clock Register"
987
+ AT91C_PMC_MCKR.access=memorymapped
988
+ AT91C_PMC_MCKR.address=0xFFFFFC30
989
+ AT91C_PMC_MCKR.width=32
990
+ AT91C_PMC_MCKR.byteEndian=little
991
+ AT91C_PMC_SCDR.name="AT91C_PMC_SCDR"
992
+ AT91C_PMC_SCDR.description="System Clock Disable Register"
993
+ AT91C_PMC_SCDR.helpkey="System Clock Disable Register"
994
+ AT91C_PMC_SCDR.access=memorymapped
995
+ AT91C_PMC_SCDR.address=0xFFFFFC04
996
+ AT91C_PMC_SCDR.width=32
997
+ AT91C_PMC_SCDR.byteEndian=little
998
+ AT91C_PMC_SCDR.type=enum
999
+ AT91C_PMC_SCDR.enum.0.name=*** Write only ***
1000
+ AT91C_PMC_SCDR.enum.1.name=Error
1001
+ AT91C_PMC_PCDR.name="AT91C_PMC_PCDR"
1002
+ AT91C_PMC_PCDR.description="Peripheral Clock Disable Register"
1003
+ AT91C_PMC_PCDR.helpkey="Peripheral Clock Disable Register"
1004
+ AT91C_PMC_PCDR.access=memorymapped
1005
+ AT91C_PMC_PCDR.address=0xFFFFFC14
1006
+ AT91C_PMC_PCDR.width=32
1007
+ AT91C_PMC_PCDR.byteEndian=little
1008
+ AT91C_PMC_PCDR.type=enum
1009
+ AT91C_PMC_PCDR.enum.0.name=*** Write only ***
1010
+ AT91C_PMC_PCDR.enum.1.name=Error
1011
+ AT91C_PMC_SCSR.name="AT91C_PMC_SCSR"
1012
+ AT91C_PMC_SCSR.description="System Clock Status Register"
1013
+ AT91C_PMC_SCSR.helpkey="System Clock Status Register"
1014
+ AT91C_PMC_SCSR.access=memorymapped
1015
+ AT91C_PMC_SCSR.address=0xFFFFFC08
1016
+ AT91C_PMC_SCSR.width=32
1017
+ AT91C_PMC_SCSR.byteEndian=little
1018
+ AT91C_PMC_SCSR.permission.write=none
1019
+ AT91C_PMC_PCSR.name="AT91C_PMC_PCSR"
1020
+ AT91C_PMC_PCSR.description="Peripheral Clock Status Register"
1021
+ AT91C_PMC_PCSR.helpkey="Peripheral Clock Status Register"
1022
+ AT91C_PMC_PCSR.access=memorymapped
1023
+ AT91C_PMC_PCSR.address=0xFFFFFC18
1024
+ AT91C_PMC_PCSR.width=32
1025
+ AT91C_PMC_PCSR.byteEndian=little
1026
+ AT91C_PMC_PCSR.permission.write=none
1027
+ AT91C_PMC_MCFR.name="AT91C_PMC_MCFR"
1028
+ AT91C_PMC_MCFR.description="Main Clock Frequency Register"
1029
+ AT91C_PMC_MCFR.helpkey="Main Clock Frequency Register"
1030
+ AT91C_PMC_MCFR.access=memorymapped
1031
+ AT91C_PMC_MCFR.address=0xFFFFFC24
1032
+ AT91C_PMC_MCFR.width=32
1033
+ AT91C_PMC_MCFR.byteEndian=little
1034
+ AT91C_PMC_MCFR.permission.write=none
1035
+ AT91C_PMC_SCER.name="AT91C_PMC_SCER"
1036
+ AT91C_PMC_SCER.description="System Clock Enable Register"
1037
+ AT91C_PMC_SCER.helpkey="System Clock Enable Register"
1038
+ AT91C_PMC_SCER.access=memorymapped
1039
+ AT91C_PMC_SCER.address=0xFFFFFC00
1040
+ AT91C_PMC_SCER.width=32
1041
+ AT91C_PMC_SCER.byteEndian=little
1042
+ AT91C_PMC_SCER.type=enum
1043
+ AT91C_PMC_SCER.enum.0.name=*** Write only ***
1044
+ AT91C_PMC_SCER.enum.1.name=Error
1045
+ AT91C_PMC_IMR.name="AT91C_PMC_IMR"
1046
+ AT91C_PMC_IMR.description="Interrupt Mask Register"
1047
+ AT91C_PMC_IMR.helpkey="Interrupt Mask Register"
1048
+ AT91C_PMC_IMR.access=memorymapped
1049
+ AT91C_PMC_IMR.address=0xFFFFFC6C
1050
+ AT91C_PMC_IMR.width=32
1051
+ AT91C_PMC_IMR.byteEndian=little
1052
+ AT91C_PMC_IMR.permission.write=none
1053
+ AT91C_PMC_IER.name="AT91C_PMC_IER"
1054
+ AT91C_PMC_IER.description="Interrupt Enable Register"
1055
+ AT91C_PMC_IER.helpkey="Interrupt Enable Register"
1056
+ AT91C_PMC_IER.access=memorymapped
1057
+ AT91C_PMC_IER.address=0xFFFFFC60
1058
+ AT91C_PMC_IER.width=32
1059
+ AT91C_PMC_IER.byteEndian=little
1060
+ AT91C_PMC_IER.type=enum
1061
+ AT91C_PMC_IER.enum.0.name=*** Write only ***
1062
+ AT91C_PMC_IER.enum.1.name=Error
1063
+ AT91C_PMC_SR.name="AT91C_PMC_SR"
1064
+ AT91C_PMC_SR.description="Status Register"
1065
+ AT91C_PMC_SR.helpkey="Status Register"
1066
+ AT91C_PMC_SR.access=memorymapped
1067
+ AT91C_PMC_SR.address=0xFFFFFC68
1068
+ AT91C_PMC_SR.width=32
1069
+ AT91C_PMC_SR.byteEndian=little
1070
+ AT91C_PMC_SR.permission.write=none
1071
+ # ========== Register definition for RSTC peripheral ==========
1072
+ AT91C_RSTC_RCR.name="AT91C_RSTC_RCR"
1073
+ AT91C_RSTC_RCR.description="Reset Control Register"
1074
+ AT91C_RSTC_RCR.helpkey="Reset Control Register"
1075
+ AT91C_RSTC_RCR.access=memorymapped
1076
+ AT91C_RSTC_RCR.address=0xFFFFFD00
1077
+ AT91C_RSTC_RCR.width=32
1078
+ AT91C_RSTC_RCR.byteEndian=little
1079
+ AT91C_RSTC_RCR.type=enum
1080
+ AT91C_RSTC_RCR.enum.0.name=*** Write only ***
1081
+ AT91C_RSTC_RCR.enum.1.name=Error
1082
+ AT91C_RSTC_RMR.name="AT91C_RSTC_RMR"
1083
+ AT91C_RSTC_RMR.description="Reset Mode Register"
1084
+ AT91C_RSTC_RMR.helpkey="Reset Mode Register"
1085
+ AT91C_RSTC_RMR.access=memorymapped
1086
+ AT91C_RSTC_RMR.address=0xFFFFFD08
1087
+ AT91C_RSTC_RMR.width=32
1088
+ AT91C_RSTC_RMR.byteEndian=little
1089
+ AT91C_RSTC_RSR.name="AT91C_RSTC_RSR"
1090
+ AT91C_RSTC_RSR.description="Reset Status Register"
1091
+ AT91C_RSTC_RSR.helpkey="Reset Status Register"
1092
+ AT91C_RSTC_RSR.access=memorymapped
1093
+ AT91C_RSTC_RSR.address=0xFFFFFD04
1094
+ AT91C_RSTC_RSR.width=32
1095
+ AT91C_RSTC_RSR.byteEndian=little
1096
+ AT91C_RSTC_RSR.permission.write=none
1097
+ # ========== Register definition for RTTC peripheral ==========
1098
+ AT91C_RTTC_RTSR.name="AT91C_RTTC_RTSR"
1099
+ AT91C_RTTC_RTSR.description="Real-time Status Register"
1100
+ AT91C_RTTC_RTSR.helpkey="Real-time Status Register"
1101
+ AT91C_RTTC_RTSR.access=memorymapped
1102
+ AT91C_RTTC_RTSR.address=0xFFFFFD2C
1103
+ AT91C_RTTC_RTSR.width=32
1104
+ AT91C_RTTC_RTSR.byteEndian=little
1105
+ AT91C_RTTC_RTSR.permission.write=none
1106
+ AT91C_RTTC_RTMR.name="AT91C_RTTC_RTMR"
1107
+ AT91C_RTTC_RTMR.description="Real-time Mode Register"
1108
+ AT91C_RTTC_RTMR.helpkey="Real-time Mode Register"
1109
+ AT91C_RTTC_RTMR.access=memorymapped
1110
+ AT91C_RTTC_RTMR.address=0xFFFFFD20
1111
+ AT91C_RTTC_RTMR.width=32
1112
+ AT91C_RTTC_RTMR.byteEndian=little
1113
+ AT91C_RTTC_RTVR.name="AT91C_RTTC_RTVR"
1114
+ AT91C_RTTC_RTVR.description="Real-time Value Register"
1115
+ AT91C_RTTC_RTVR.helpkey="Real-time Value Register"
1116
+ AT91C_RTTC_RTVR.access=memorymapped
1117
+ AT91C_RTTC_RTVR.address=0xFFFFFD28
1118
+ AT91C_RTTC_RTVR.width=32
1119
+ AT91C_RTTC_RTVR.byteEndian=little
1120
+ AT91C_RTTC_RTVR.permission.write=none
1121
+ AT91C_RTTC_RTAR.name="AT91C_RTTC_RTAR"
1122
+ AT91C_RTTC_RTAR.description="Real-time Alarm Register"
1123
+ AT91C_RTTC_RTAR.helpkey="Real-time Alarm Register"
1124
+ AT91C_RTTC_RTAR.access=memorymapped
1125
+ AT91C_RTTC_RTAR.address=0xFFFFFD24
1126
+ AT91C_RTTC_RTAR.width=32
1127
+ AT91C_RTTC_RTAR.byteEndian=little
1128
+ # ========== Register definition for PITC peripheral ==========
1129
+ AT91C_PITC_PIVR.name="AT91C_PITC_PIVR"
1130
+ AT91C_PITC_PIVR.description="Period Interval Value Register"
1131
+ AT91C_PITC_PIVR.helpkey="Period Interval Value Register"
1132
+ AT91C_PITC_PIVR.access=memorymapped
1133
+ AT91C_PITC_PIVR.address=0xFFFFFD38
1134
+ AT91C_PITC_PIVR.width=32
1135
+ AT91C_PITC_PIVR.byteEndian=little
1136
+ AT91C_PITC_PIVR.permission.write=none
1137
+ AT91C_PITC_PISR.name="AT91C_PITC_PISR"
1138
+ AT91C_PITC_PISR.description="Period Interval Status Register"
1139
+ AT91C_PITC_PISR.helpkey="Period Interval Status Register"
1140
+ AT91C_PITC_PISR.access=memorymapped
1141
+ AT91C_PITC_PISR.address=0xFFFFFD34
1142
+ AT91C_PITC_PISR.width=32
1143
+ AT91C_PITC_PISR.byteEndian=little
1144
+ AT91C_PITC_PISR.permission.write=none
1145
+ AT91C_PITC_PIIR.name="AT91C_PITC_PIIR"
1146
+ AT91C_PITC_PIIR.description="Period Interval Image Register"
1147
+ AT91C_PITC_PIIR.helpkey="Period Interval Image Register"
1148
+ AT91C_PITC_PIIR.access=memorymapped
1149
+ AT91C_PITC_PIIR.address=0xFFFFFD3C
1150
+ AT91C_PITC_PIIR.width=32
1151
+ AT91C_PITC_PIIR.byteEndian=little
1152
+ AT91C_PITC_PIIR.permission.write=none
1153
+ AT91C_PITC_PIMR.name="AT91C_PITC_PIMR"
1154
+ AT91C_PITC_PIMR.description="Period Interval Mode Register"
1155
+ AT91C_PITC_PIMR.helpkey="Period Interval Mode Register"
1156
+ AT91C_PITC_PIMR.access=memorymapped
1157
+ AT91C_PITC_PIMR.address=0xFFFFFD30
1158
+ AT91C_PITC_PIMR.width=32
1159
+ AT91C_PITC_PIMR.byteEndian=little
1160
+ # ========== Register definition for WDTC peripheral ==========
1161
+ AT91C_WDTC_WDCR.name="AT91C_WDTC_WDCR"
1162
+ AT91C_WDTC_WDCR.description="Watchdog Control Register"
1163
+ AT91C_WDTC_WDCR.helpkey="Watchdog Control Register"
1164
+ AT91C_WDTC_WDCR.access=memorymapped
1165
+ AT91C_WDTC_WDCR.address=0xFFFFFD40
1166
+ AT91C_WDTC_WDCR.width=32
1167
+ AT91C_WDTC_WDCR.byteEndian=little
1168
+ AT91C_WDTC_WDCR.type=enum
1169
+ AT91C_WDTC_WDCR.enum.0.name=*** Write only ***
1170
+ AT91C_WDTC_WDCR.enum.1.name=Error
1171
+ AT91C_WDTC_WDSR.name="AT91C_WDTC_WDSR"
1172
+ AT91C_WDTC_WDSR.description="Watchdog Status Register"
1173
+ AT91C_WDTC_WDSR.helpkey="Watchdog Status Register"
1174
+ AT91C_WDTC_WDSR.access=memorymapped
1175
+ AT91C_WDTC_WDSR.address=0xFFFFFD48
1176
+ AT91C_WDTC_WDSR.width=32
1177
+ AT91C_WDTC_WDSR.byteEndian=little
1178
+ AT91C_WDTC_WDSR.permission.write=none
1179
+ AT91C_WDTC_WDMR.name="AT91C_WDTC_WDMR"
1180
+ AT91C_WDTC_WDMR.description="Watchdog Mode Register"
1181
+ AT91C_WDTC_WDMR.helpkey="Watchdog Mode Register"
1182
+ AT91C_WDTC_WDMR.access=memorymapped
1183
+ AT91C_WDTC_WDMR.address=0xFFFFFD44
1184
+ AT91C_WDTC_WDMR.width=32
1185
+ AT91C_WDTC_WDMR.byteEndian=little
1186
+ # ========== Register definition for VREG peripheral ==========
1187
+ AT91C_VREG_MR.name="AT91C_VREG_MR"
1188
+ AT91C_VREG_MR.description="Voltage Regulator Mode Register"
1189
+ AT91C_VREG_MR.helpkey="Voltage Regulator Mode Register"
1190
+ AT91C_VREG_MR.access=memorymapped
1191
+ AT91C_VREG_MR.address=0xFFFFFD60
1192
+ AT91C_VREG_MR.width=32
1193
+ AT91C_VREG_MR.byteEndian=little
1194
+ # ========== Register definition for MC peripheral ==========
1195
+ AT91C_MC_ASR.name="AT91C_MC_ASR"
1196
+ AT91C_MC_ASR.description="MC Abort Status Register"
1197
+ AT91C_MC_ASR.helpkey="MC Abort Status Register"
1198
+ AT91C_MC_ASR.access=memorymapped
1199
+ AT91C_MC_ASR.address=0xFFFFFF04
1200
+ AT91C_MC_ASR.width=32
1201
+ AT91C_MC_ASR.byteEndian=little
1202
+ AT91C_MC_ASR.permission.write=none
1203
+ AT91C_MC_RCR.name="AT91C_MC_RCR"
1204
+ AT91C_MC_RCR.description="MC Remap Control Register"
1205
+ AT91C_MC_RCR.helpkey="MC Remap Control Register"
1206
+ AT91C_MC_RCR.access=memorymapped
1207
+ AT91C_MC_RCR.address=0xFFFFFF00
1208
+ AT91C_MC_RCR.width=32
1209
+ AT91C_MC_RCR.byteEndian=little
1210
+ AT91C_MC_RCR.type=enum
1211
+ AT91C_MC_RCR.enum.0.name=*** Write only ***
1212
+ AT91C_MC_RCR.enum.1.name=Error
1213
+ AT91C_MC_FCR.name="AT91C_MC_FCR"
1214
+ AT91C_MC_FCR.description="MC Flash Command Register"
1215
+ AT91C_MC_FCR.helpkey="MC Flash Command Register"
1216
+ AT91C_MC_FCR.access=memorymapped
1217
+ AT91C_MC_FCR.address=0xFFFFFF64
1218
+ AT91C_MC_FCR.width=32
1219
+ AT91C_MC_FCR.byteEndian=little
1220
+ AT91C_MC_FCR.type=enum
1221
+ AT91C_MC_FCR.enum.0.name=*** Write only ***
1222
+ AT91C_MC_FCR.enum.1.name=Error
1223
+ AT91C_MC_AASR.name="AT91C_MC_AASR"
1224
+ AT91C_MC_AASR.description="MC Abort Address Status Register"
1225
+ AT91C_MC_AASR.helpkey="MC Abort Address Status Register"
1226
+ AT91C_MC_AASR.access=memorymapped
1227
+ AT91C_MC_AASR.address=0xFFFFFF08
1228
+ AT91C_MC_AASR.width=32
1229
+ AT91C_MC_AASR.byteEndian=little
1230
+ AT91C_MC_AASR.permission.write=none
1231
+ AT91C_MC_FSR.name="AT91C_MC_FSR"
1232
+ AT91C_MC_FSR.description="MC Flash Status Register"
1233
+ AT91C_MC_FSR.helpkey="MC Flash Status Register"
1234
+ AT91C_MC_FSR.access=memorymapped
1235
+ AT91C_MC_FSR.address=0xFFFFFF68
1236
+ AT91C_MC_FSR.width=32
1237
+ AT91C_MC_FSR.byteEndian=little
1238
+ AT91C_MC_FSR.permission.write=none
1239
+ AT91C_MC_FMR.name="AT91C_MC_FMR"
1240
+ AT91C_MC_FMR.description="MC Flash Mode Register"
1241
+ AT91C_MC_FMR.helpkey="MC Flash Mode Register"
1242
+ AT91C_MC_FMR.access=memorymapped
1243
+ AT91C_MC_FMR.address=0xFFFFFF60
1244
+ AT91C_MC_FMR.width=32
1245
+ AT91C_MC_FMR.byteEndian=little
1246
+ # ========== Register definition for PDC_SPI1 peripheral ==========
1247
+ AT91C_SPI1_PTCR.name="AT91C_SPI1_PTCR"
1248
+ AT91C_SPI1_PTCR.description="PDC Transfer Control Register"
1249
+ AT91C_SPI1_PTCR.helpkey="PDC Transfer Control Register"
1250
+ AT91C_SPI1_PTCR.access=memorymapped
1251
+ AT91C_SPI1_PTCR.address=0xFFFE4120
1252
+ AT91C_SPI1_PTCR.width=32
1253
+ AT91C_SPI1_PTCR.byteEndian=little
1254
+ AT91C_SPI1_PTCR.type=enum
1255
+ AT91C_SPI1_PTCR.enum.0.name=*** Write only ***
1256
+ AT91C_SPI1_PTCR.enum.1.name=Error
1257
+ AT91C_SPI1_RPR.name="AT91C_SPI1_RPR"
1258
+ AT91C_SPI1_RPR.description="Receive Pointer Register"
1259
+ AT91C_SPI1_RPR.helpkey="Receive Pointer Register"
1260
+ AT91C_SPI1_RPR.access=memorymapped
1261
+ AT91C_SPI1_RPR.address=0xFFFE4100
1262
+ AT91C_SPI1_RPR.width=32
1263
+ AT91C_SPI1_RPR.byteEndian=little
1264
+ AT91C_SPI1_TNCR.name="AT91C_SPI1_TNCR"
1265
+ AT91C_SPI1_TNCR.description="Transmit Next Counter Register"
1266
+ AT91C_SPI1_TNCR.helpkey="Transmit Next Counter Register"
1267
+ AT91C_SPI1_TNCR.access=memorymapped
1268
+ AT91C_SPI1_TNCR.address=0xFFFE411C
1269
+ AT91C_SPI1_TNCR.width=32
1270
+ AT91C_SPI1_TNCR.byteEndian=little
1271
+ AT91C_SPI1_TPR.name="AT91C_SPI1_TPR"
1272
+ AT91C_SPI1_TPR.description="Transmit Pointer Register"
1273
+ AT91C_SPI1_TPR.helpkey="Transmit Pointer Register"
1274
+ AT91C_SPI1_TPR.access=memorymapped
1275
+ AT91C_SPI1_TPR.address=0xFFFE4108
1276
+ AT91C_SPI1_TPR.width=32
1277
+ AT91C_SPI1_TPR.byteEndian=little
1278
+ AT91C_SPI1_TNPR.name="AT91C_SPI1_TNPR"
1279
+ AT91C_SPI1_TNPR.description="Transmit Next Pointer Register"
1280
+ AT91C_SPI1_TNPR.helpkey="Transmit Next Pointer Register"
1281
+ AT91C_SPI1_TNPR.access=memorymapped
1282
+ AT91C_SPI1_TNPR.address=0xFFFE4118
1283
+ AT91C_SPI1_TNPR.width=32
1284
+ AT91C_SPI1_TNPR.byteEndian=little
1285
+ AT91C_SPI1_TCR.name="AT91C_SPI1_TCR"
1286
+ AT91C_SPI1_TCR.description="Transmit Counter Register"
1287
+ AT91C_SPI1_TCR.helpkey="Transmit Counter Register"
1288
+ AT91C_SPI1_TCR.access=memorymapped
1289
+ AT91C_SPI1_TCR.address=0xFFFE410C
1290
+ AT91C_SPI1_TCR.width=32
1291
+ AT91C_SPI1_TCR.byteEndian=little
1292
+ AT91C_SPI1_RCR.name="AT91C_SPI1_RCR"
1293
+ AT91C_SPI1_RCR.description="Receive Counter Register"
1294
+ AT91C_SPI1_RCR.helpkey="Receive Counter Register"
1295
+ AT91C_SPI1_RCR.access=memorymapped
1296
+ AT91C_SPI1_RCR.address=0xFFFE4104
1297
+ AT91C_SPI1_RCR.width=32
1298
+ AT91C_SPI1_RCR.byteEndian=little
1299
+ AT91C_SPI1_RNPR.name="AT91C_SPI1_RNPR"
1300
+ AT91C_SPI1_RNPR.description="Receive Next Pointer Register"
1301
+ AT91C_SPI1_RNPR.helpkey="Receive Next Pointer Register"
1302
+ AT91C_SPI1_RNPR.access=memorymapped
1303
+ AT91C_SPI1_RNPR.address=0xFFFE4110
1304
+ AT91C_SPI1_RNPR.width=32
1305
+ AT91C_SPI1_RNPR.byteEndian=little
1306
+ AT91C_SPI1_RNCR.name="AT91C_SPI1_RNCR"
1307
+ AT91C_SPI1_RNCR.description="Receive Next Counter Register"
1308
+ AT91C_SPI1_RNCR.helpkey="Receive Next Counter Register"
1309
+ AT91C_SPI1_RNCR.access=memorymapped
1310
+ AT91C_SPI1_RNCR.address=0xFFFE4114
1311
+ AT91C_SPI1_RNCR.width=32
1312
+ AT91C_SPI1_RNCR.byteEndian=little
1313
+ AT91C_SPI1_PTSR.name="AT91C_SPI1_PTSR"
1314
+ AT91C_SPI1_PTSR.description="PDC Transfer Status Register"
1315
+ AT91C_SPI1_PTSR.helpkey="PDC Transfer Status Register"
1316
+ AT91C_SPI1_PTSR.access=memorymapped
1317
+ AT91C_SPI1_PTSR.address=0xFFFE4124
1318
+ AT91C_SPI1_PTSR.width=32
1319
+ AT91C_SPI1_PTSR.byteEndian=little
1320
+ AT91C_SPI1_PTSR.permission.write=none
1321
+ # ========== Register definition for SPI1 peripheral ==========
1322
+ AT91C_SPI1_IMR.name="AT91C_SPI1_IMR"
1323
+ AT91C_SPI1_IMR.description="Interrupt Mask Register"
1324
+ AT91C_SPI1_IMR.helpkey="Interrupt Mask Register"
1325
+ AT91C_SPI1_IMR.access=memorymapped
1326
+ AT91C_SPI1_IMR.address=0xFFFE401C
1327
+ AT91C_SPI1_IMR.width=32
1328
+ AT91C_SPI1_IMR.byteEndian=little
1329
+ AT91C_SPI1_IMR.permission.write=none
1330
+ AT91C_SPI1_IER.name="AT91C_SPI1_IER"
1331
+ AT91C_SPI1_IER.description="Interrupt Enable Register"
1332
+ AT91C_SPI1_IER.helpkey="Interrupt Enable Register"
1333
+ AT91C_SPI1_IER.access=memorymapped
1334
+ AT91C_SPI1_IER.address=0xFFFE4014
1335
+ AT91C_SPI1_IER.width=32
1336
+ AT91C_SPI1_IER.byteEndian=little
1337
+ AT91C_SPI1_IER.type=enum
1338
+ AT91C_SPI1_IER.enum.0.name=*** Write only ***
1339
+ AT91C_SPI1_IER.enum.1.name=Error
1340
+ AT91C_SPI1_MR.name="AT91C_SPI1_MR"
1341
+ AT91C_SPI1_MR.description="Mode Register"
1342
+ AT91C_SPI1_MR.helpkey="Mode Register"
1343
+ AT91C_SPI1_MR.access=memorymapped
1344
+ AT91C_SPI1_MR.address=0xFFFE4004
1345
+ AT91C_SPI1_MR.width=32
1346
+ AT91C_SPI1_MR.byteEndian=little
1347
+ AT91C_SPI1_RDR.name="AT91C_SPI1_RDR"
1348
+ AT91C_SPI1_RDR.description="Receive Data Register"
1349
+ AT91C_SPI1_RDR.helpkey="Receive Data Register"
1350
+ AT91C_SPI1_RDR.access=memorymapped
1351
+ AT91C_SPI1_RDR.address=0xFFFE4008
1352
+ AT91C_SPI1_RDR.width=32
1353
+ AT91C_SPI1_RDR.byteEndian=little
1354
+ AT91C_SPI1_RDR.permission.write=none
1355
+ AT91C_SPI1_IDR.name="AT91C_SPI1_IDR"
1356
+ AT91C_SPI1_IDR.description="Interrupt Disable Register"
1357
+ AT91C_SPI1_IDR.helpkey="Interrupt Disable Register"
1358
+ AT91C_SPI1_IDR.access=memorymapped
1359
+ AT91C_SPI1_IDR.address=0xFFFE4018
1360
+ AT91C_SPI1_IDR.width=32
1361
+ AT91C_SPI1_IDR.byteEndian=little
1362
+ AT91C_SPI1_IDR.type=enum
1363
+ AT91C_SPI1_IDR.enum.0.name=*** Write only ***
1364
+ AT91C_SPI1_IDR.enum.1.name=Error
1365
+ AT91C_SPI1_SR.name="AT91C_SPI1_SR"
1366
+ AT91C_SPI1_SR.description="Status Register"
1367
+ AT91C_SPI1_SR.helpkey="Status Register"
1368
+ AT91C_SPI1_SR.access=memorymapped
1369
+ AT91C_SPI1_SR.address=0xFFFE4010
1370
+ AT91C_SPI1_SR.width=32
1371
+ AT91C_SPI1_SR.byteEndian=little
1372
+ AT91C_SPI1_SR.permission.write=none
1373
+ AT91C_SPI1_TDR.name="AT91C_SPI1_TDR"
1374
+ AT91C_SPI1_TDR.description="Transmit Data Register"
1375
+ AT91C_SPI1_TDR.helpkey="Transmit Data Register"
1376
+ AT91C_SPI1_TDR.access=memorymapped
1377
+ AT91C_SPI1_TDR.address=0xFFFE400C
1378
+ AT91C_SPI1_TDR.width=32
1379
+ AT91C_SPI1_TDR.byteEndian=little
1380
+ AT91C_SPI1_TDR.type=enum
1381
+ AT91C_SPI1_TDR.enum.0.name=*** Write only ***
1382
+ AT91C_SPI1_TDR.enum.1.name=Error
1383
+ AT91C_SPI1_CR.name="AT91C_SPI1_CR"
1384
+ AT91C_SPI1_CR.description="Control Register"
1385
+ AT91C_SPI1_CR.helpkey="Control Register"
1386
+ AT91C_SPI1_CR.access=memorymapped
1387
+ AT91C_SPI1_CR.address=0xFFFE4000
1388
+ AT91C_SPI1_CR.width=32
1389
+ AT91C_SPI1_CR.byteEndian=little
1390
+ AT91C_SPI1_CR.permission.write=none
1391
+ AT91C_SPI1_CSR.name="AT91C_SPI1_CSR"
1392
+ AT91C_SPI1_CSR.description="Chip Select Register"
1393
+ AT91C_SPI1_CSR.helpkey="Chip Select Register"
1394
+ AT91C_SPI1_CSR.access=memorymapped
1395
+ AT91C_SPI1_CSR.address=0xFFFE4030
1396
+ AT91C_SPI1_CSR.width=32
1397
+ AT91C_SPI1_CSR.byteEndian=little
1398
+ # ========== Register definition for PDC_SPI0 peripheral ==========
1399
+ AT91C_SPI0_PTCR.name="AT91C_SPI0_PTCR"
1400
+ AT91C_SPI0_PTCR.description="PDC Transfer Control Register"
1401
+ AT91C_SPI0_PTCR.helpkey="PDC Transfer Control Register"
1402
+ AT91C_SPI0_PTCR.access=memorymapped
1403
+ AT91C_SPI0_PTCR.address=0xFFFE0120
1404
+ AT91C_SPI0_PTCR.width=32
1405
+ AT91C_SPI0_PTCR.byteEndian=little
1406
+ AT91C_SPI0_PTCR.type=enum
1407
+ AT91C_SPI0_PTCR.enum.0.name=*** Write only ***
1408
+ AT91C_SPI0_PTCR.enum.1.name=Error
1409
+ AT91C_SPI0_TPR.name="AT91C_SPI0_TPR"
1410
+ AT91C_SPI0_TPR.description="Transmit Pointer Register"
1411
+ AT91C_SPI0_TPR.helpkey="Transmit Pointer Register"
1412
+ AT91C_SPI0_TPR.access=memorymapped
1413
+ AT91C_SPI0_TPR.address=0xFFFE0108
1414
+ AT91C_SPI0_TPR.width=32
1415
+ AT91C_SPI0_TPR.byteEndian=little
1416
+ AT91C_SPI0_TCR.name="AT91C_SPI0_TCR"
1417
+ AT91C_SPI0_TCR.description="Transmit Counter Register"
1418
+ AT91C_SPI0_TCR.helpkey="Transmit Counter Register"
1419
+ AT91C_SPI0_TCR.access=memorymapped
1420
+ AT91C_SPI0_TCR.address=0xFFFE010C
1421
+ AT91C_SPI0_TCR.width=32
1422
+ AT91C_SPI0_TCR.byteEndian=little
1423
+ AT91C_SPI0_RCR.name="AT91C_SPI0_RCR"
1424
+ AT91C_SPI0_RCR.description="Receive Counter Register"
1425
+ AT91C_SPI0_RCR.helpkey="Receive Counter Register"
1426
+ AT91C_SPI0_RCR.access=memorymapped
1427
+ AT91C_SPI0_RCR.address=0xFFFE0104
1428
+ AT91C_SPI0_RCR.width=32
1429
+ AT91C_SPI0_RCR.byteEndian=little
1430
+ AT91C_SPI0_PTSR.name="AT91C_SPI0_PTSR"
1431
+ AT91C_SPI0_PTSR.description="PDC Transfer Status Register"
1432
+ AT91C_SPI0_PTSR.helpkey="PDC Transfer Status Register"
1433
+ AT91C_SPI0_PTSR.access=memorymapped
1434
+ AT91C_SPI0_PTSR.address=0xFFFE0124
1435
+ AT91C_SPI0_PTSR.width=32
1436
+ AT91C_SPI0_PTSR.byteEndian=little
1437
+ AT91C_SPI0_PTSR.permission.write=none
1438
+ AT91C_SPI0_RNPR.name="AT91C_SPI0_RNPR"
1439
+ AT91C_SPI0_RNPR.description="Receive Next Pointer Register"
1440
+ AT91C_SPI0_RNPR.helpkey="Receive Next Pointer Register"
1441
+ AT91C_SPI0_RNPR.access=memorymapped
1442
+ AT91C_SPI0_RNPR.address=0xFFFE0110
1443
+ AT91C_SPI0_RNPR.width=32
1444
+ AT91C_SPI0_RNPR.byteEndian=little
1445
+ AT91C_SPI0_RPR.name="AT91C_SPI0_RPR"
1446
+ AT91C_SPI0_RPR.description="Receive Pointer Register"
1447
+ AT91C_SPI0_RPR.helpkey="Receive Pointer Register"
1448
+ AT91C_SPI0_RPR.access=memorymapped
1449
+ AT91C_SPI0_RPR.address=0xFFFE0100
1450
+ AT91C_SPI0_RPR.width=32
1451
+ AT91C_SPI0_RPR.byteEndian=little
1452
+ AT91C_SPI0_TNCR.name="AT91C_SPI0_TNCR"
1453
+ AT91C_SPI0_TNCR.description="Transmit Next Counter Register"
1454
+ AT91C_SPI0_TNCR.helpkey="Transmit Next Counter Register"
1455
+ AT91C_SPI0_TNCR.access=memorymapped
1456
+ AT91C_SPI0_TNCR.address=0xFFFE011C
1457
+ AT91C_SPI0_TNCR.width=32
1458
+ AT91C_SPI0_TNCR.byteEndian=little
1459
+ AT91C_SPI0_RNCR.name="AT91C_SPI0_RNCR"
1460
+ AT91C_SPI0_RNCR.description="Receive Next Counter Register"
1461
+ AT91C_SPI0_RNCR.helpkey="Receive Next Counter Register"
1462
+ AT91C_SPI0_RNCR.access=memorymapped
1463
+ AT91C_SPI0_RNCR.address=0xFFFE0114
1464
+ AT91C_SPI0_RNCR.width=32
1465
+ AT91C_SPI0_RNCR.byteEndian=little
1466
+ AT91C_SPI0_TNPR.name="AT91C_SPI0_TNPR"
1467
+ AT91C_SPI0_TNPR.description="Transmit Next Pointer Register"
1468
+ AT91C_SPI0_TNPR.helpkey="Transmit Next Pointer Register"
1469
+ AT91C_SPI0_TNPR.access=memorymapped
1470
+ AT91C_SPI0_TNPR.address=0xFFFE0118
1471
+ AT91C_SPI0_TNPR.width=32
1472
+ AT91C_SPI0_TNPR.byteEndian=little
1473
+ # ========== Register definition for SPI0 peripheral ==========
1474
+ AT91C_SPI0_IER.name="AT91C_SPI0_IER"
1475
+ AT91C_SPI0_IER.description="Interrupt Enable Register"
1476
+ AT91C_SPI0_IER.helpkey="Interrupt Enable Register"
1477
+ AT91C_SPI0_IER.access=memorymapped
1478
+ AT91C_SPI0_IER.address=0xFFFE0014
1479
+ AT91C_SPI0_IER.width=32
1480
+ AT91C_SPI0_IER.byteEndian=little
1481
+ AT91C_SPI0_IER.type=enum
1482
+ AT91C_SPI0_IER.enum.0.name=*** Write only ***
1483
+ AT91C_SPI0_IER.enum.1.name=Error
1484
+ AT91C_SPI0_SR.name="AT91C_SPI0_SR"
1485
+ AT91C_SPI0_SR.description="Status Register"
1486
+ AT91C_SPI0_SR.helpkey="Status Register"
1487
+ AT91C_SPI0_SR.access=memorymapped
1488
+ AT91C_SPI0_SR.address=0xFFFE0010
1489
+ AT91C_SPI0_SR.width=32
1490
+ AT91C_SPI0_SR.byteEndian=little
1491
+ AT91C_SPI0_SR.permission.write=none
1492
+ AT91C_SPI0_IDR.name="AT91C_SPI0_IDR"
1493
+ AT91C_SPI0_IDR.description="Interrupt Disable Register"
1494
+ AT91C_SPI0_IDR.helpkey="Interrupt Disable Register"
1495
+ AT91C_SPI0_IDR.access=memorymapped
1496
+ AT91C_SPI0_IDR.address=0xFFFE0018
1497
+ AT91C_SPI0_IDR.width=32
1498
+ AT91C_SPI0_IDR.byteEndian=little
1499
+ AT91C_SPI0_IDR.type=enum
1500
+ AT91C_SPI0_IDR.enum.0.name=*** Write only ***
1501
+ AT91C_SPI0_IDR.enum.1.name=Error
1502
+ AT91C_SPI0_CR.name="AT91C_SPI0_CR"
1503
+ AT91C_SPI0_CR.description="Control Register"
1504
+ AT91C_SPI0_CR.helpkey="Control Register"
1505
+ AT91C_SPI0_CR.access=memorymapped
1506
+ AT91C_SPI0_CR.address=0xFFFE0000
1507
+ AT91C_SPI0_CR.width=32
1508
+ AT91C_SPI0_CR.byteEndian=little
1509
+ AT91C_SPI0_CR.permission.write=none
1510
+ AT91C_SPI0_MR.name="AT91C_SPI0_MR"
1511
+ AT91C_SPI0_MR.description="Mode Register"
1512
+ AT91C_SPI0_MR.helpkey="Mode Register"
1513
+ AT91C_SPI0_MR.access=memorymapped
1514
+ AT91C_SPI0_MR.address=0xFFFE0004
1515
+ AT91C_SPI0_MR.width=32
1516
+ AT91C_SPI0_MR.byteEndian=little
1517
+ AT91C_SPI0_IMR.name="AT91C_SPI0_IMR"
1518
+ AT91C_SPI0_IMR.description="Interrupt Mask Register"
1519
+ AT91C_SPI0_IMR.helpkey="Interrupt Mask Register"
1520
+ AT91C_SPI0_IMR.access=memorymapped
1521
+ AT91C_SPI0_IMR.address=0xFFFE001C
1522
+ AT91C_SPI0_IMR.width=32
1523
+ AT91C_SPI0_IMR.byteEndian=little
1524
+ AT91C_SPI0_IMR.permission.write=none
1525
+ AT91C_SPI0_TDR.name="AT91C_SPI0_TDR"
1526
+ AT91C_SPI0_TDR.description="Transmit Data Register"
1527
+ AT91C_SPI0_TDR.helpkey="Transmit Data Register"
1528
+ AT91C_SPI0_TDR.access=memorymapped
1529
+ AT91C_SPI0_TDR.address=0xFFFE000C
1530
+ AT91C_SPI0_TDR.width=32
1531
+ AT91C_SPI0_TDR.byteEndian=little
1532
+ AT91C_SPI0_TDR.type=enum
1533
+ AT91C_SPI0_TDR.enum.0.name=*** Write only ***
1534
+ AT91C_SPI0_TDR.enum.1.name=Error
1535
+ AT91C_SPI0_RDR.name="AT91C_SPI0_RDR"
1536
+ AT91C_SPI0_RDR.description="Receive Data Register"
1537
+ AT91C_SPI0_RDR.helpkey="Receive Data Register"
1538
+ AT91C_SPI0_RDR.access=memorymapped
1539
+ AT91C_SPI0_RDR.address=0xFFFE0008
1540
+ AT91C_SPI0_RDR.width=32
1541
+ AT91C_SPI0_RDR.byteEndian=little
1542
+ AT91C_SPI0_RDR.permission.write=none
1543
+ AT91C_SPI0_CSR.name="AT91C_SPI0_CSR"
1544
+ AT91C_SPI0_CSR.description="Chip Select Register"
1545
+ AT91C_SPI0_CSR.helpkey="Chip Select Register"
1546
+ AT91C_SPI0_CSR.access=memorymapped
1547
+ AT91C_SPI0_CSR.address=0xFFFE0030
1548
+ AT91C_SPI0_CSR.width=32
1549
+ AT91C_SPI0_CSR.byteEndian=little
1550
+ # ========== Register definition for PDC_US1 peripheral ==========
1551
+ AT91C_US1_RNCR.name="AT91C_US1_RNCR"
1552
+ AT91C_US1_RNCR.description="Receive Next Counter Register"
1553
+ AT91C_US1_RNCR.helpkey="Receive Next Counter Register"
1554
+ AT91C_US1_RNCR.access=memorymapped
1555
+ AT91C_US1_RNCR.address=0xFFFC4114
1556
+ AT91C_US1_RNCR.width=32
1557
+ AT91C_US1_RNCR.byteEndian=little
1558
+ AT91C_US1_PTCR.name="AT91C_US1_PTCR"
1559
+ AT91C_US1_PTCR.description="PDC Transfer Control Register"
1560
+ AT91C_US1_PTCR.helpkey="PDC Transfer Control Register"
1561
+ AT91C_US1_PTCR.access=memorymapped
1562
+ AT91C_US1_PTCR.address=0xFFFC4120
1563
+ AT91C_US1_PTCR.width=32
1564
+ AT91C_US1_PTCR.byteEndian=little
1565
+ AT91C_US1_PTCR.type=enum
1566
+ AT91C_US1_PTCR.enum.0.name=*** Write only ***
1567
+ AT91C_US1_PTCR.enum.1.name=Error
1568
+ AT91C_US1_TCR.name="AT91C_US1_TCR"
1569
+ AT91C_US1_TCR.description="Transmit Counter Register"
1570
+ AT91C_US1_TCR.helpkey="Transmit Counter Register"
1571
+ AT91C_US1_TCR.access=memorymapped
1572
+ AT91C_US1_TCR.address=0xFFFC410C
1573
+ AT91C_US1_TCR.width=32
1574
+ AT91C_US1_TCR.byteEndian=little
1575
+ AT91C_US1_PTSR.name="AT91C_US1_PTSR"
1576
+ AT91C_US1_PTSR.description="PDC Transfer Status Register"
1577
+ AT91C_US1_PTSR.helpkey="PDC Transfer Status Register"
1578
+ AT91C_US1_PTSR.access=memorymapped
1579
+ AT91C_US1_PTSR.address=0xFFFC4124
1580
+ AT91C_US1_PTSR.width=32
1581
+ AT91C_US1_PTSR.byteEndian=little
1582
+ AT91C_US1_PTSR.permission.write=none
1583
+ AT91C_US1_TNPR.name="AT91C_US1_TNPR"
1584
+ AT91C_US1_TNPR.description="Transmit Next Pointer Register"
1585
+ AT91C_US1_TNPR.helpkey="Transmit Next Pointer Register"
1586
+ AT91C_US1_TNPR.access=memorymapped
1587
+ AT91C_US1_TNPR.address=0xFFFC4118
1588
+ AT91C_US1_TNPR.width=32
1589
+ AT91C_US1_TNPR.byteEndian=little
1590
+ AT91C_US1_RCR.name="AT91C_US1_RCR"
1591
+ AT91C_US1_RCR.description="Receive Counter Register"
1592
+ AT91C_US1_RCR.helpkey="Receive Counter Register"
1593
+ AT91C_US1_RCR.access=memorymapped
1594
+ AT91C_US1_RCR.address=0xFFFC4104
1595
+ AT91C_US1_RCR.width=32
1596
+ AT91C_US1_RCR.byteEndian=little
1597
+ AT91C_US1_RNPR.name="AT91C_US1_RNPR"
1598
+ AT91C_US1_RNPR.description="Receive Next Pointer Register"
1599
+ AT91C_US1_RNPR.helpkey="Receive Next Pointer Register"
1600
+ AT91C_US1_RNPR.access=memorymapped
1601
+ AT91C_US1_RNPR.address=0xFFFC4110
1602
+ AT91C_US1_RNPR.width=32
1603
+ AT91C_US1_RNPR.byteEndian=little
1604
+ AT91C_US1_RPR.name="AT91C_US1_RPR"
1605
+ AT91C_US1_RPR.description="Receive Pointer Register"
1606
+ AT91C_US1_RPR.helpkey="Receive Pointer Register"
1607
+ AT91C_US1_RPR.access=memorymapped
1608
+ AT91C_US1_RPR.address=0xFFFC4100
1609
+ AT91C_US1_RPR.width=32
1610
+ AT91C_US1_RPR.byteEndian=little
1611
+ AT91C_US1_TNCR.name="AT91C_US1_TNCR"
1612
+ AT91C_US1_TNCR.description="Transmit Next Counter Register"
1613
+ AT91C_US1_TNCR.helpkey="Transmit Next Counter Register"
1614
+ AT91C_US1_TNCR.access=memorymapped
1615
+ AT91C_US1_TNCR.address=0xFFFC411C
1616
+ AT91C_US1_TNCR.width=32
1617
+ AT91C_US1_TNCR.byteEndian=little
1618
+ AT91C_US1_TPR.name="AT91C_US1_TPR"
1619
+ AT91C_US1_TPR.description="Transmit Pointer Register"
1620
+ AT91C_US1_TPR.helpkey="Transmit Pointer Register"
1621
+ AT91C_US1_TPR.access=memorymapped
1622
+ AT91C_US1_TPR.address=0xFFFC4108
1623
+ AT91C_US1_TPR.width=32
1624
+ AT91C_US1_TPR.byteEndian=little
1625
+ # ========== Register definition for US1 peripheral ==========
1626
+ AT91C_US1_IF.name="AT91C_US1_IF"
1627
+ AT91C_US1_IF.description="IRDA_FILTER Register"
1628
+ AT91C_US1_IF.helpkey="IRDA_FILTER Register"
1629
+ AT91C_US1_IF.access=memorymapped
1630
+ AT91C_US1_IF.address=0xFFFC404C
1631
+ AT91C_US1_IF.width=32
1632
+ AT91C_US1_IF.byteEndian=little
1633
+ AT91C_US1_NER.name="AT91C_US1_NER"
1634
+ AT91C_US1_NER.description="Nb Errors Register"
1635
+ AT91C_US1_NER.helpkey="Nb Errors Register"
1636
+ AT91C_US1_NER.access=memorymapped
1637
+ AT91C_US1_NER.address=0xFFFC4044
1638
+ AT91C_US1_NER.width=32
1639
+ AT91C_US1_NER.byteEndian=little
1640
+ AT91C_US1_NER.permission.write=none
1641
+ AT91C_US1_RTOR.name="AT91C_US1_RTOR"
1642
+ AT91C_US1_RTOR.description="Receiver Time-out Register"
1643
+ AT91C_US1_RTOR.helpkey="Receiver Time-out Register"
1644
+ AT91C_US1_RTOR.access=memorymapped
1645
+ AT91C_US1_RTOR.address=0xFFFC4024
1646
+ AT91C_US1_RTOR.width=32
1647
+ AT91C_US1_RTOR.byteEndian=little
1648
+ AT91C_US1_CSR.name="AT91C_US1_CSR"
1649
+ AT91C_US1_CSR.description="Channel Status Register"
1650
+ AT91C_US1_CSR.helpkey="Channel Status Register"
1651
+ AT91C_US1_CSR.access=memorymapped
1652
+ AT91C_US1_CSR.address=0xFFFC4014
1653
+ AT91C_US1_CSR.width=32
1654
+ AT91C_US1_CSR.byteEndian=little
1655
+ AT91C_US1_CSR.permission.write=none
1656
+ AT91C_US1_IDR.name="AT91C_US1_IDR"
1657
+ AT91C_US1_IDR.description="Interrupt Disable Register"
1658
+ AT91C_US1_IDR.helpkey="Interrupt Disable Register"
1659
+ AT91C_US1_IDR.access=memorymapped
1660
+ AT91C_US1_IDR.address=0xFFFC400C
1661
+ AT91C_US1_IDR.width=32
1662
+ AT91C_US1_IDR.byteEndian=little
1663
+ AT91C_US1_IDR.type=enum
1664
+ AT91C_US1_IDR.enum.0.name=*** Write only ***
1665
+ AT91C_US1_IDR.enum.1.name=Error
1666
+ AT91C_US1_IER.name="AT91C_US1_IER"
1667
+ AT91C_US1_IER.description="Interrupt Enable Register"
1668
+ AT91C_US1_IER.helpkey="Interrupt Enable Register"
1669
+ AT91C_US1_IER.access=memorymapped
1670
+ AT91C_US1_IER.address=0xFFFC4008
1671
+ AT91C_US1_IER.width=32
1672
+ AT91C_US1_IER.byteEndian=little
1673
+ AT91C_US1_IER.type=enum
1674
+ AT91C_US1_IER.enum.0.name=*** Write only ***
1675
+ AT91C_US1_IER.enum.1.name=Error
1676
+ AT91C_US1_THR.name="AT91C_US1_THR"
1677
+ AT91C_US1_THR.description="Transmitter Holding Register"
1678
+ AT91C_US1_THR.helpkey="Transmitter Holding Register"
1679
+ AT91C_US1_THR.access=memorymapped
1680
+ AT91C_US1_THR.address=0xFFFC401C
1681
+ AT91C_US1_THR.width=32
1682
+ AT91C_US1_THR.byteEndian=little
1683
+ AT91C_US1_THR.type=enum
1684
+ AT91C_US1_THR.enum.0.name=*** Write only ***
1685
+ AT91C_US1_THR.enum.1.name=Error
1686
+ AT91C_US1_TTGR.name="AT91C_US1_TTGR"
1687
+ AT91C_US1_TTGR.description="Transmitter Time-guard Register"
1688
+ AT91C_US1_TTGR.helpkey="Transmitter Time-guard Register"
1689
+ AT91C_US1_TTGR.access=memorymapped
1690
+ AT91C_US1_TTGR.address=0xFFFC4028
1691
+ AT91C_US1_TTGR.width=32
1692
+ AT91C_US1_TTGR.byteEndian=little
1693
+ AT91C_US1_RHR.name="AT91C_US1_RHR"
1694
+ AT91C_US1_RHR.description="Receiver Holding Register"
1695
+ AT91C_US1_RHR.helpkey="Receiver Holding Register"
1696
+ AT91C_US1_RHR.access=memorymapped
1697
+ AT91C_US1_RHR.address=0xFFFC4018
1698
+ AT91C_US1_RHR.width=32
1699
+ AT91C_US1_RHR.byteEndian=little
1700
+ AT91C_US1_RHR.permission.write=none
1701
+ AT91C_US1_BRGR.name="AT91C_US1_BRGR"
1702
+ AT91C_US1_BRGR.description="Baud Rate Generator Register"
1703
+ AT91C_US1_BRGR.helpkey="Baud Rate Generator Register"
1704
+ AT91C_US1_BRGR.access=memorymapped
1705
+ AT91C_US1_BRGR.address=0xFFFC4020
1706
+ AT91C_US1_BRGR.width=32
1707
+ AT91C_US1_BRGR.byteEndian=little
1708
+ AT91C_US1_IMR.name="AT91C_US1_IMR"
1709
+ AT91C_US1_IMR.description="Interrupt Mask Register"
1710
+ AT91C_US1_IMR.helpkey="Interrupt Mask Register"
1711
+ AT91C_US1_IMR.access=memorymapped
1712
+ AT91C_US1_IMR.address=0xFFFC4010
1713
+ AT91C_US1_IMR.width=32
1714
+ AT91C_US1_IMR.byteEndian=little
1715
+ AT91C_US1_IMR.permission.write=none
1716
+ AT91C_US1_FIDI.name="AT91C_US1_FIDI"
1717
+ AT91C_US1_FIDI.description="FI_DI_Ratio Register"
1718
+ AT91C_US1_FIDI.helpkey="FI_DI_Ratio Register"
1719
+ AT91C_US1_FIDI.access=memorymapped
1720
+ AT91C_US1_FIDI.address=0xFFFC4040
1721
+ AT91C_US1_FIDI.width=32
1722
+ AT91C_US1_FIDI.byteEndian=little
1723
+ AT91C_US1_CR.name="AT91C_US1_CR"
1724
+ AT91C_US1_CR.description="Control Register"
1725
+ AT91C_US1_CR.helpkey="Control Register"
1726
+ AT91C_US1_CR.access=memorymapped
1727
+ AT91C_US1_CR.address=0xFFFC4000
1728
+ AT91C_US1_CR.width=32
1729
+ AT91C_US1_CR.byteEndian=little
1730
+ AT91C_US1_CR.type=enum
1731
+ AT91C_US1_CR.enum.0.name=*** Write only ***
1732
+ AT91C_US1_CR.enum.1.name=Error
1733
+ AT91C_US1_MR.name="AT91C_US1_MR"
1734
+ AT91C_US1_MR.description="Mode Register"
1735
+ AT91C_US1_MR.helpkey="Mode Register"
1736
+ AT91C_US1_MR.access=memorymapped
1737
+ AT91C_US1_MR.address=0xFFFC4004
1738
+ AT91C_US1_MR.width=32
1739
+ AT91C_US1_MR.byteEndian=little
1740
+ # ========== Register definition for PDC_US0 peripheral ==========
1741
+ AT91C_US0_TNPR.name="AT91C_US0_TNPR"
1742
+ AT91C_US0_TNPR.description="Transmit Next Pointer Register"
1743
+ AT91C_US0_TNPR.helpkey="Transmit Next Pointer Register"
1744
+ AT91C_US0_TNPR.access=memorymapped
1745
+ AT91C_US0_TNPR.address=0xFFFC0118
1746
+ AT91C_US0_TNPR.width=32
1747
+ AT91C_US0_TNPR.byteEndian=little
1748
+ AT91C_US0_RNPR.name="AT91C_US0_RNPR"
1749
+ AT91C_US0_RNPR.description="Receive Next Pointer Register"
1750
+ AT91C_US0_RNPR.helpkey="Receive Next Pointer Register"
1751
+ AT91C_US0_RNPR.access=memorymapped
1752
+ AT91C_US0_RNPR.address=0xFFFC0110
1753
+ AT91C_US0_RNPR.width=32
1754
+ AT91C_US0_RNPR.byteEndian=little
1755
+ AT91C_US0_TCR.name="AT91C_US0_TCR"
1756
+ AT91C_US0_TCR.description="Transmit Counter Register"
1757
+ AT91C_US0_TCR.helpkey="Transmit Counter Register"
1758
+ AT91C_US0_TCR.access=memorymapped
1759
+ AT91C_US0_TCR.address=0xFFFC010C
1760
+ AT91C_US0_TCR.width=32
1761
+ AT91C_US0_TCR.byteEndian=little
1762
+ AT91C_US0_PTCR.name="AT91C_US0_PTCR"
1763
+ AT91C_US0_PTCR.description="PDC Transfer Control Register"
1764
+ AT91C_US0_PTCR.helpkey="PDC Transfer Control Register"
1765
+ AT91C_US0_PTCR.access=memorymapped
1766
+ AT91C_US0_PTCR.address=0xFFFC0120
1767
+ AT91C_US0_PTCR.width=32
1768
+ AT91C_US0_PTCR.byteEndian=little
1769
+ AT91C_US0_PTCR.type=enum
1770
+ AT91C_US0_PTCR.enum.0.name=*** Write only ***
1771
+ AT91C_US0_PTCR.enum.1.name=Error
1772
+ AT91C_US0_PTSR.name="AT91C_US0_PTSR"
1773
+ AT91C_US0_PTSR.description="PDC Transfer Status Register"
1774
+ AT91C_US0_PTSR.helpkey="PDC Transfer Status Register"
1775
+ AT91C_US0_PTSR.access=memorymapped
1776
+ AT91C_US0_PTSR.address=0xFFFC0124
1777
+ AT91C_US0_PTSR.width=32
1778
+ AT91C_US0_PTSR.byteEndian=little
1779
+ AT91C_US0_PTSR.permission.write=none
1780
+ AT91C_US0_TNCR.name="AT91C_US0_TNCR"
1781
+ AT91C_US0_TNCR.description="Transmit Next Counter Register"
1782
+ AT91C_US0_TNCR.helpkey="Transmit Next Counter Register"
1783
+ AT91C_US0_TNCR.access=memorymapped
1784
+ AT91C_US0_TNCR.address=0xFFFC011C
1785
+ AT91C_US0_TNCR.width=32
1786
+ AT91C_US0_TNCR.byteEndian=little
1787
+ AT91C_US0_TPR.name="AT91C_US0_TPR"
1788
+ AT91C_US0_TPR.description="Transmit Pointer Register"
1789
+ AT91C_US0_TPR.helpkey="Transmit Pointer Register"
1790
+ AT91C_US0_TPR.access=memorymapped
1791
+ AT91C_US0_TPR.address=0xFFFC0108
1792
+ AT91C_US0_TPR.width=32
1793
+ AT91C_US0_TPR.byteEndian=little
1794
+ AT91C_US0_RCR.name="AT91C_US0_RCR"
1795
+ AT91C_US0_RCR.description="Receive Counter Register"
1796
+ AT91C_US0_RCR.helpkey="Receive Counter Register"
1797
+ AT91C_US0_RCR.access=memorymapped
1798
+ AT91C_US0_RCR.address=0xFFFC0104
1799
+ AT91C_US0_RCR.width=32
1800
+ AT91C_US0_RCR.byteEndian=little
1801
+ AT91C_US0_RPR.name="AT91C_US0_RPR"
1802
+ AT91C_US0_RPR.description="Receive Pointer Register"
1803
+ AT91C_US0_RPR.helpkey="Receive Pointer Register"
1804
+ AT91C_US0_RPR.access=memorymapped
1805
+ AT91C_US0_RPR.address=0xFFFC0100
1806
+ AT91C_US0_RPR.width=32
1807
+ AT91C_US0_RPR.byteEndian=little
1808
+ AT91C_US0_RNCR.name="AT91C_US0_RNCR"
1809
+ AT91C_US0_RNCR.description="Receive Next Counter Register"
1810
+ AT91C_US0_RNCR.helpkey="Receive Next Counter Register"
1811
+ AT91C_US0_RNCR.access=memorymapped
1812
+ AT91C_US0_RNCR.address=0xFFFC0114
1813
+ AT91C_US0_RNCR.width=32
1814
+ AT91C_US0_RNCR.byteEndian=little
1815
+ # ========== Register definition for US0 peripheral ==========
1816
+ AT91C_US0_BRGR.name="AT91C_US0_BRGR"
1817
+ AT91C_US0_BRGR.description="Baud Rate Generator Register"
1818
+ AT91C_US0_BRGR.helpkey="Baud Rate Generator Register"
1819
+ AT91C_US0_BRGR.access=memorymapped
1820
+ AT91C_US0_BRGR.address=0xFFFC0020
1821
+ AT91C_US0_BRGR.width=32
1822
+ AT91C_US0_BRGR.byteEndian=little
1823
+ AT91C_US0_NER.name="AT91C_US0_NER"
1824
+ AT91C_US0_NER.description="Nb Errors Register"
1825
+ AT91C_US0_NER.helpkey="Nb Errors Register"
1826
+ AT91C_US0_NER.access=memorymapped
1827
+ AT91C_US0_NER.address=0xFFFC0044
1828
+ AT91C_US0_NER.width=32
1829
+ AT91C_US0_NER.byteEndian=little
1830
+ AT91C_US0_NER.permission.write=none
1831
+ AT91C_US0_CR.name="AT91C_US0_CR"
1832
+ AT91C_US0_CR.description="Control Register"
1833
+ AT91C_US0_CR.helpkey="Control Register"
1834
+ AT91C_US0_CR.access=memorymapped
1835
+ AT91C_US0_CR.address=0xFFFC0000
1836
+ AT91C_US0_CR.width=32
1837
+ AT91C_US0_CR.byteEndian=little
1838
+ AT91C_US0_CR.type=enum
1839
+ AT91C_US0_CR.enum.0.name=*** Write only ***
1840
+ AT91C_US0_CR.enum.1.name=Error
1841
+ AT91C_US0_IMR.name="AT91C_US0_IMR"
1842
+ AT91C_US0_IMR.description="Interrupt Mask Register"
1843
+ AT91C_US0_IMR.helpkey="Interrupt Mask Register"
1844
+ AT91C_US0_IMR.access=memorymapped
1845
+ AT91C_US0_IMR.address=0xFFFC0010
1846
+ AT91C_US0_IMR.width=32
1847
+ AT91C_US0_IMR.byteEndian=little
1848
+ AT91C_US0_IMR.permission.write=none
1849
+ AT91C_US0_FIDI.name="AT91C_US0_FIDI"
1850
+ AT91C_US0_FIDI.description="FI_DI_Ratio Register"
1851
+ AT91C_US0_FIDI.helpkey="FI_DI_Ratio Register"
1852
+ AT91C_US0_FIDI.access=memorymapped
1853
+ AT91C_US0_FIDI.address=0xFFFC0040
1854
+ AT91C_US0_FIDI.width=32
1855
+ AT91C_US0_FIDI.byteEndian=little
1856
+ AT91C_US0_TTGR.name="AT91C_US0_TTGR"
1857
+ AT91C_US0_TTGR.description="Transmitter Time-guard Register"
1858
+ AT91C_US0_TTGR.helpkey="Transmitter Time-guard Register"
1859
+ AT91C_US0_TTGR.access=memorymapped
1860
+ AT91C_US0_TTGR.address=0xFFFC0028
1861
+ AT91C_US0_TTGR.width=32
1862
+ AT91C_US0_TTGR.byteEndian=little
1863
+ AT91C_US0_MR.name="AT91C_US0_MR"
1864
+ AT91C_US0_MR.description="Mode Register"
1865
+ AT91C_US0_MR.helpkey="Mode Register"
1866
+ AT91C_US0_MR.access=memorymapped
1867
+ AT91C_US0_MR.address=0xFFFC0004
1868
+ AT91C_US0_MR.width=32
1869
+ AT91C_US0_MR.byteEndian=little
1870
+ AT91C_US0_RTOR.name="AT91C_US0_RTOR"
1871
+ AT91C_US0_RTOR.description="Receiver Time-out Register"
1872
+ AT91C_US0_RTOR.helpkey="Receiver Time-out Register"
1873
+ AT91C_US0_RTOR.access=memorymapped
1874
+ AT91C_US0_RTOR.address=0xFFFC0024
1875
+ AT91C_US0_RTOR.width=32
1876
+ AT91C_US0_RTOR.byteEndian=little
1877
+ AT91C_US0_CSR.name="AT91C_US0_CSR"
1878
+ AT91C_US0_CSR.description="Channel Status Register"
1879
+ AT91C_US0_CSR.helpkey="Channel Status Register"
1880
+ AT91C_US0_CSR.access=memorymapped
1881
+ AT91C_US0_CSR.address=0xFFFC0014
1882
+ AT91C_US0_CSR.width=32
1883
+ AT91C_US0_CSR.byteEndian=little
1884
+ AT91C_US0_CSR.permission.write=none
1885
+ AT91C_US0_RHR.name="AT91C_US0_RHR"
1886
+ AT91C_US0_RHR.description="Receiver Holding Register"
1887
+ AT91C_US0_RHR.helpkey="Receiver Holding Register"
1888
+ AT91C_US0_RHR.access=memorymapped
1889
+ AT91C_US0_RHR.address=0xFFFC0018
1890
+ AT91C_US0_RHR.width=32
1891
+ AT91C_US0_RHR.byteEndian=little
1892
+ AT91C_US0_RHR.permission.write=none
1893
+ AT91C_US0_IDR.name="AT91C_US0_IDR"
1894
+ AT91C_US0_IDR.description="Interrupt Disable Register"
1895
+ AT91C_US0_IDR.helpkey="Interrupt Disable Register"
1896
+ AT91C_US0_IDR.access=memorymapped
1897
+ AT91C_US0_IDR.address=0xFFFC000C
1898
+ AT91C_US0_IDR.width=32
1899
+ AT91C_US0_IDR.byteEndian=little
1900
+ AT91C_US0_IDR.type=enum
1901
+ AT91C_US0_IDR.enum.0.name=*** Write only ***
1902
+ AT91C_US0_IDR.enum.1.name=Error
1903
+ AT91C_US0_THR.name="AT91C_US0_THR"
1904
+ AT91C_US0_THR.description="Transmitter Holding Register"
1905
+ AT91C_US0_THR.helpkey="Transmitter Holding Register"
1906
+ AT91C_US0_THR.access=memorymapped
1907
+ AT91C_US0_THR.address=0xFFFC001C
1908
+ AT91C_US0_THR.width=32
1909
+ AT91C_US0_THR.byteEndian=little
1910
+ AT91C_US0_THR.type=enum
1911
+ AT91C_US0_THR.enum.0.name=*** Write only ***
1912
+ AT91C_US0_THR.enum.1.name=Error
1913
+ AT91C_US0_IF.name="AT91C_US0_IF"
1914
+ AT91C_US0_IF.description="IRDA_FILTER Register"
1915
+ AT91C_US0_IF.helpkey="IRDA_FILTER Register"
1916
+ AT91C_US0_IF.access=memorymapped
1917
+ AT91C_US0_IF.address=0xFFFC004C
1918
+ AT91C_US0_IF.width=32
1919
+ AT91C_US0_IF.byteEndian=little
1920
+ AT91C_US0_IER.name="AT91C_US0_IER"
1921
+ AT91C_US0_IER.description="Interrupt Enable Register"
1922
+ AT91C_US0_IER.helpkey="Interrupt Enable Register"
1923
+ AT91C_US0_IER.access=memorymapped
1924
+ AT91C_US0_IER.address=0xFFFC0008
1925
+ AT91C_US0_IER.width=32
1926
+ AT91C_US0_IER.byteEndian=little
1927
+ AT91C_US0_IER.type=enum
1928
+ AT91C_US0_IER.enum.0.name=*** Write only ***
1929
+ AT91C_US0_IER.enum.1.name=Error
1930
+ # ========== Register definition for PDC_SSC peripheral ==========
1931
+ AT91C_SSC_TNCR.name="AT91C_SSC_TNCR"
1932
+ AT91C_SSC_TNCR.description="Transmit Next Counter Register"
1933
+ AT91C_SSC_TNCR.helpkey="Transmit Next Counter Register"
1934
+ AT91C_SSC_TNCR.access=memorymapped
1935
+ AT91C_SSC_TNCR.address=0xFFFD411C
1936
+ AT91C_SSC_TNCR.width=32
1937
+ AT91C_SSC_TNCR.byteEndian=little
1938
+ AT91C_SSC_RPR.name="AT91C_SSC_RPR"
1939
+ AT91C_SSC_RPR.description="Receive Pointer Register"
1940
+ AT91C_SSC_RPR.helpkey="Receive Pointer Register"
1941
+ AT91C_SSC_RPR.access=memorymapped
1942
+ AT91C_SSC_RPR.address=0xFFFD4100
1943
+ AT91C_SSC_RPR.width=32
1944
+ AT91C_SSC_RPR.byteEndian=little
1945
+ AT91C_SSC_RNCR.name="AT91C_SSC_RNCR"
1946
+ AT91C_SSC_RNCR.description="Receive Next Counter Register"
1947
+ AT91C_SSC_RNCR.helpkey="Receive Next Counter Register"
1948
+ AT91C_SSC_RNCR.access=memorymapped
1949
+ AT91C_SSC_RNCR.address=0xFFFD4114
1950
+ AT91C_SSC_RNCR.width=32
1951
+ AT91C_SSC_RNCR.byteEndian=little
1952
+ AT91C_SSC_TPR.name="AT91C_SSC_TPR"
1953
+ AT91C_SSC_TPR.description="Transmit Pointer Register"
1954
+ AT91C_SSC_TPR.helpkey="Transmit Pointer Register"
1955
+ AT91C_SSC_TPR.access=memorymapped
1956
+ AT91C_SSC_TPR.address=0xFFFD4108
1957
+ AT91C_SSC_TPR.width=32
1958
+ AT91C_SSC_TPR.byteEndian=little
1959
+ AT91C_SSC_PTCR.name="AT91C_SSC_PTCR"
1960
+ AT91C_SSC_PTCR.description="PDC Transfer Control Register"
1961
+ AT91C_SSC_PTCR.helpkey="PDC Transfer Control Register"
1962
+ AT91C_SSC_PTCR.access=memorymapped
1963
+ AT91C_SSC_PTCR.address=0xFFFD4120
1964
+ AT91C_SSC_PTCR.width=32
1965
+ AT91C_SSC_PTCR.byteEndian=little
1966
+ AT91C_SSC_PTCR.type=enum
1967
+ AT91C_SSC_PTCR.enum.0.name=*** Write only ***
1968
+ AT91C_SSC_PTCR.enum.1.name=Error
1969
+ AT91C_SSC_TCR.name="AT91C_SSC_TCR"
1970
+ AT91C_SSC_TCR.description="Transmit Counter Register"
1971
+ AT91C_SSC_TCR.helpkey="Transmit Counter Register"
1972
+ AT91C_SSC_TCR.access=memorymapped
1973
+ AT91C_SSC_TCR.address=0xFFFD410C
1974
+ AT91C_SSC_TCR.width=32
1975
+ AT91C_SSC_TCR.byteEndian=little
1976
+ AT91C_SSC_RCR.name="AT91C_SSC_RCR"
1977
+ AT91C_SSC_RCR.description="Receive Counter Register"
1978
+ AT91C_SSC_RCR.helpkey="Receive Counter Register"
1979
+ AT91C_SSC_RCR.access=memorymapped
1980
+ AT91C_SSC_RCR.address=0xFFFD4104
1981
+ AT91C_SSC_RCR.width=32
1982
+ AT91C_SSC_RCR.byteEndian=little
1983
+ AT91C_SSC_RNPR.name="AT91C_SSC_RNPR"
1984
+ AT91C_SSC_RNPR.description="Receive Next Pointer Register"
1985
+ AT91C_SSC_RNPR.helpkey="Receive Next Pointer Register"
1986
+ AT91C_SSC_RNPR.access=memorymapped
1987
+ AT91C_SSC_RNPR.address=0xFFFD4110
1988
+ AT91C_SSC_RNPR.width=32
1989
+ AT91C_SSC_RNPR.byteEndian=little
1990
+ AT91C_SSC_TNPR.name="AT91C_SSC_TNPR"
1991
+ AT91C_SSC_TNPR.description="Transmit Next Pointer Register"
1992
+ AT91C_SSC_TNPR.helpkey="Transmit Next Pointer Register"
1993
+ AT91C_SSC_TNPR.access=memorymapped
1994
+ AT91C_SSC_TNPR.address=0xFFFD4118
1995
+ AT91C_SSC_TNPR.width=32
1996
+ AT91C_SSC_TNPR.byteEndian=little
1997
+ AT91C_SSC_PTSR.name="AT91C_SSC_PTSR"
1998
+ AT91C_SSC_PTSR.description="PDC Transfer Status Register"
1999
+ AT91C_SSC_PTSR.helpkey="PDC Transfer Status Register"
2000
+ AT91C_SSC_PTSR.access=memorymapped
2001
+ AT91C_SSC_PTSR.address=0xFFFD4124
2002
+ AT91C_SSC_PTSR.width=32
2003
+ AT91C_SSC_PTSR.byteEndian=little
2004
+ AT91C_SSC_PTSR.permission.write=none
2005
+ # ========== Register definition for SSC peripheral ==========
2006
+ AT91C_SSC_RHR.name="AT91C_SSC_RHR"
2007
+ AT91C_SSC_RHR.description="Receive Holding Register"
2008
+ AT91C_SSC_RHR.helpkey="Receive Holding Register"
2009
+ AT91C_SSC_RHR.access=memorymapped
2010
+ AT91C_SSC_RHR.address=0xFFFD4020
2011
+ AT91C_SSC_RHR.width=32
2012
+ AT91C_SSC_RHR.byteEndian=little
2013
+ AT91C_SSC_RHR.permission.write=none
2014
+ AT91C_SSC_RSHR.name="AT91C_SSC_RSHR"
2015
+ AT91C_SSC_RSHR.description="Receive Sync Holding Register"
2016
+ AT91C_SSC_RSHR.helpkey="Receive Sync Holding Register"
2017
+ AT91C_SSC_RSHR.access=memorymapped
2018
+ AT91C_SSC_RSHR.address=0xFFFD4030
2019
+ AT91C_SSC_RSHR.width=32
2020
+ AT91C_SSC_RSHR.byteEndian=little
2021
+ AT91C_SSC_RSHR.permission.write=none
2022
+ AT91C_SSC_TFMR.name="AT91C_SSC_TFMR"
2023
+ AT91C_SSC_TFMR.description="Transmit Frame Mode Register"
2024
+ AT91C_SSC_TFMR.helpkey="Transmit Frame Mode Register"
2025
+ AT91C_SSC_TFMR.access=memorymapped
2026
+ AT91C_SSC_TFMR.address=0xFFFD401C
2027
+ AT91C_SSC_TFMR.width=32
2028
+ AT91C_SSC_TFMR.byteEndian=little
2029
+ AT91C_SSC_IDR.name="AT91C_SSC_IDR"
2030
+ AT91C_SSC_IDR.description="Interrupt Disable Register"
2031
+ AT91C_SSC_IDR.helpkey="Interrupt Disable Register"
2032
+ AT91C_SSC_IDR.access=memorymapped
2033
+ AT91C_SSC_IDR.address=0xFFFD4048
2034
+ AT91C_SSC_IDR.width=32
2035
+ AT91C_SSC_IDR.byteEndian=little
2036
+ AT91C_SSC_IDR.type=enum
2037
+ AT91C_SSC_IDR.enum.0.name=*** Write only ***
2038
+ AT91C_SSC_IDR.enum.1.name=Error
2039
+ AT91C_SSC_THR.name="AT91C_SSC_THR"
2040
+ AT91C_SSC_THR.description="Transmit Holding Register"
2041
+ AT91C_SSC_THR.helpkey="Transmit Holding Register"
2042
+ AT91C_SSC_THR.access=memorymapped
2043
+ AT91C_SSC_THR.address=0xFFFD4024
2044
+ AT91C_SSC_THR.width=32
2045
+ AT91C_SSC_THR.byteEndian=little
2046
+ AT91C_SSC_THR.type=enum
2047
+ AT91C_SSC_THR.enum.0.name=*** Write only ***
2048
+ AT91C_SSC_THR.enum.1.name=Error
2049
+ AT91C_SSC_RCMR.name="AT91C_SSC_RCMR"
2050
+ AT91C_SSC_RCMR.description="Receive Clock ModeRegister"
2051
+ AT91C_SSC_RCMR.helpkey="Receive Clock ModeRegister"
2052
+ AT91C_SSC_RCMR.access=memorymapped
2053
+ AT91C_SSC_RCMR.address=0xFFFD4010
2054
+ AT91C_SSC_RCMR.width=32
2055
+ AT91C_SSC_RCMR.byteEndian=little
2056
+ AT91C_SSC_IER.name="AT91C_SSC_IER"
2057
+ AT91C_SSC_IER.description="Interrupt Enable Register"
2058
+ AT91C_SSC_IER.helpkey="Interrupt Enable Register"
2059
+ AT91C_SSC_IER.access=memorymapped
2060
+ AT91C_SSC_IER.address=0xFFFD4044
2061
+ AT91C_SSC_IER.width=32
2062
+ AT91C_SSC_IER.byteEndian=little
2063
+ AT91C_SSC_IER.type=enum
2064
+ AT91C_SSC_IER.enum.0.name=*** Write only ***
2065
+ AT91C_SSC_IER.enum.1.name=Error
2066
+ AT91C_SSC_TSHR.name="AT91C_SSC_TSHR"
2067
+ AT91C_SSC_TSHR.description="Transmit Sync Holding Register"
2068
+ AT91C_SSC_TSHR.helpkey="Transmit Sync Holding Register"
2069
+ AT91C_SSC_TSHR.access=memorymapped
2070
+ AT91C_SSC_TSHR.address=0xFFFD4034
2071
+ AT91C_SSC_TSHR.width=32
2072
+ AT91C_SSC_TSHR.byteEndian=little
2073
+ AT91C_SSC_SR.name="AT91C_SSC_SR"
2074
+ AT91C_SSC_SR.description="Status Register"
2075
+ AT91C_SSC_SR.helpkey="Status Register"
2076
+ AT91C_SSC_SR.access=memorymapped
2077
+ AT91C_SSC_SR.address=0xFFFD4040
2078
+ AT91C_SSC_SR.width=32
2079
+ AT91C_SSC_SR.byteEndian=little
2080
+ AT91C_SSC_SR.permission.write=none
2081
+ AT91C_SSC_CMR.name="AT91C_SSC_CMR"
2082
+ AT91C_SSC_CMR.description="Clock Mode Register"
2083
+ AT91C_SSC_CMR.helpkey="Clock Mode Register"
2084
+ AT91C_SSC_CMR.access=memorymapped
2085
+ AT91C_SSC_CMR.address=0xFFFD4004
2086
+ AT91C_SSC_CMR.width=32
2087
+ AT91C_SSC_CMR.byteEndian=little
2088
+ AT91C_SSC_TCMR.name="AT91C_SSC_TCMR"
2089
+ AT91C_SSC_TCMR.description="Transmit Clock Mode Register"
2090
+ AT91C_SSC_TCMR.helpkey="Transmit Clock Mode Register"
2091
+ AT91C_SSC_TCMR.access=memorymapped
2092
+ AT91C_SSC_TCMR.address=0xFFFD4018
2093
+ AT91C_SSC_TCMR.width=32
2094
+ AT91C_SSC_TCMR.byteEndian=little
2095
+ AT91C_SSC_CR.name="AT91C_SSC_CR"
2096
+ AT91C_SSC_CR.description="Control Register"
2097
+ AT91C_SSC_CR.helpkey="Control Register"
2098
+ AT91C_SSC_CR.access=memorymapped
2099
+ AT91C_SSC_CR.address=0xFFFD4000
2100
+ AT91C_SSC_CR.width=32
2101
+ AT91C_SSC_CR.byteEndian=little
2102
+ AT91C_SSC_CR.type=enum
2103
+ AT91C_SSC_CR.enum.0.name=*** Write only ***
2104
+ AT91C_SSC_CR.enum.1.name=Error
2105
+ AT91C_SSC_IMR.name="AT91C_SSC_IMR"
2106
+ AT91C_SSC_IMR.description="Interrupt Mask Register"
2107
+ AT91C_SSC_IMR.helpkey="Interrupt Mask Register"
2108
+ AT91C_SSC_IMR.access=memorymapped
2109
+ AT91C_SSC_IMR.address=0xFFFD404C
2110
+ AT91C_SSC_IMR.width=32
2111
+ AT91C_SSC_IMR.byteEndian=little
2112
+ AT91C_SSC_IMR.permission.write=none
2113
+ AT91C_SSC_RFMR.name="AT91C_SSC_RFMR"
2114
+ AT91C_SSC_RFMR.description="Receive Frame Mode Register"
2115
+ AT91C_SSC_RFMR.helpkey="Receive Frame Mode Register"
2116
+ AT91C_SSC_RFMR.access=memorymapped
2117
+ AT91C_SSC_RFMR.address=0xFFFD4014
2118
+ AT91C_SSC_RFMR.width=32
2119
+ AT91C_SSC_RFMR.byteEndian=little
2120
+ # ========== Register definition for TWI peripheral ==========
2121
+ AT91C_TWI_IER.name="AT91C_TWI_IER"
2122
+ AT91C_TWI_IER.description="Interrupt Enable Register"
2123
+ AT91C_TWI_IER.helpkey="Interrupt Enable Register"
2124
+ AT91C_TWI_IER.access=memorymapped
2125
+ AT91C_TWI_IER.address=0xFFFB8024
2126
+ AT91C_TWI_IER.width=32
2127
+ AT91C_TWI_IER.byteEndian=little
2128
+ AT91C_TWI_IER.type=enum
2129
+ AT91C_TWI_IER.enum.0.name=*** Write only ***
2130
+ AT91C_TWI_IER.enum.1.name=Error
2131
+ AT91C_TWI_CR.name="AT91C_TWI_CR"
2132
+ AT91C_TWI_CR.description="Control Register"
2133
+ AT91C_TWI_CR.helpkey="Control Register"
2134
+ AT91C_TWI_CR.access=memorymapped
2135
+ AT91C_TWI_CR.address=0xFFFB8000
2136
+ AT91C_TWI_CR.width=32
2137
+ AT91C_TWI_CR.byteEndian=little
2138
+ AT91C_TWI_CR.type=enum
2139
+ AT91C_TWI_CR.enum.0.name=*** Write only ***
2140
+ AT91C_TWI_CR.enum.1.name=Error
2141
+ AT91C_TWI_SR.name="AT91C_TWI_SR"
2142
+ AT91C_TWI_SR.description="Status Register"
2143
+ AT91C_TWI_SR.helpkey="Status Register"
2144
+ AT91C_TWI_SR.access=memorymapped
2145
+ AT91C_TWI_SR.address=0xFFFB8020
2146
+ AT91C_TWI_SR.width=32
2147
+ AT91C_TWI_SR.byteEndian=little
2148
+ AT91C_TWI_SR.permission.write=none
2149
+ AT91C_TWI_IMR.name="AT91C_TWI_IMR"
2150
+ AT91C_TWI_IMR.description="Interrupt Mask Register"
2151
+ AT91C_TWI_IMR.helpkey="Interrupt Mask Register"
2152
+ AT91C_TWI_IMR.access=memorymapped
2153
+ AT91C_TWI_IMR.address=0xFFFB802C
2154
+ AT91C_TWI_IMR.width=32
2155
+ AT91C_TWI_IMR.byteEndian=little
2156
+ AT91C_TWI_IMR.permission.write=none
2157
+ AT91C_TWI_THR.name="AT91C_TWI_THR"
2158
+ AT91C_TWI_THR.description="Transmit Holding Register"
2159
+ AT91C_TWI_THR.helpkey="Transmit Holding Register"
2160
+ AT91C_TWI_THR.access=memorymapped
2161
+ AT91C_TWI_THR.address=0xFFFB8034
2162
+ AT91C_TWI_THR.width=32
2163
+ AT91C_TWI_THR.byteEndian=little
2164
+ AT91C_TWI_THR.type=enum
2165
+ AT91C_TWI_THR.enum.0.name=*** Write only ***
2166
+ AT91C_TWI_THR.enum.1.name=Error
2167
+ AT91C_TWI_IDR.name="AT91C_TWI_IDR"
2168
+ AT91C_TWI_IDR.description="Interrupt Disable Register"
2169
+ AT91C_TWI_IDR.helpkey="Interrupt Disable Register"
2170
+ AT91C_TWI_IDR.access=memorymapped
2171
+ AT91C_TWI_IDR.address=0xFFFB8028
2172
+ AT91C_TWI_IDR.width=32
2173
+ AT91C_TWI_IDR.byteEndian=little
2174
+ AT91C_TWI_IDR.type=enum
2175
+ AT91C_TWI_IDR.enum.0.name=*** Write only ***
2176
+ AT91C_TWI_IDR.enum.1.name=Error
2177
+ AT91C_TWI_IADR.name="AT91C_TWI_IADR"
2178
+ AT91C_TWI_IADR.description="Internal Address Register"
2179
+ AT91C_TWI_IADR.helpkey="Internal Address Register"
2180
+ AT91C_TWI_IADR.access=memorymapped
2181
+ AT91C_TWI_IADR.address=0xFFFB800C
2182
+ AT91C_TWI_IADR.width=32
2183
+ AT91C_TWI_IADR.byteEndian=little
2184
+ AT91C_TWI_MMR.name="AT91C_TWI_MMR"
2185
+ AT91C_TWI_MMR.description="Master Mode Register"
2186
+ AT91C_TWI_MMR.helpkey="Master Mode Register"
2187
+ AT91C_TWI_MMR.access=memorymapped
2188
+ AT91C_TWI_MMR.address=0xFFFB8004
2189
+ AT91C_TWI_MMR.width=32
2190
+ AT91C_TWI_MMR.byteEndian=little
2191
+ AT91C_TWI_CWGR.name="AT91C_TWI_CWGR"
2192
+ AT91C_TWI_CWGR.description="Clock Waveform Generator Register"
2193
+ AT91C_TWI_CWGR.helpkey="Clock Waveform Generator Register"
2194
+ AT91C_TWI_CWGR.access=memorymapped
2195
+ AT91C_TWI_CWGR.address=0xFFFB8010
2196
+ AT91C_TWI_CWGR.width=32
2197
+ AT91C_TWI_CWGR.byteEndian=little
2198
+ AT91C_TWI_RHR.name="AT91C_TWI_RHR"
2199
+ AT91C_TWI_RHR.description="Receive Holding Register"
2200
+ AT91C_TWI_RHR.helpkey="Receive Holding Register"
2201
+ AT91C_TWI_RHR.access=memorymapped
2202
+ AT91C_TWI_RHR.address=0xFFFB8030
2203
+ AT91C_TWI_RHR.width=32
2204
+ AT91C_TWI_RHR.byteEndian=little
2205
+ AT91C_TWI_RHR.permission.write=none
2206
+ # ========== Register definition for PWMC_CH3 peripheral ==========
2207
+ AT91C_PWMC_CH3_CUPDR.name="AT91C_PWMC_CH3_CUPDR"
2208
+ AT91C_PWMC_CH3_CUPDR.description="Channel Update Register"
2209
+ AT91C_PWMC_CH3_CUPDR.helpkey="Channel Update Register"
2210
+ AT91C_PWMC_CH3_CUPDR.access=memorymapped
2211
+ AT91C_PWMC_CH3_CUPDR.address=0xFFFCC270
2212
+ AT91C_PWMC_CH3_CUPDR.width=32
2213
+ AT91C_PWMC_CH3_CUPDR.byteEndian=little
2214
+ AT91C_PWMC_CH3_CUPDR.type=enum
2215
+ AT91C_PWMC_CH3_CUPDR.enum.0.name=*** Write only ***
2216
+ AT91C_PWMC_CH3_CUPDR.enum.1.name=Error
2217
+ AT91C_PWMC_CH3_Reserved.name="AT91C_PWMC_CH3_Reserved"
2218
+ AT91C_PWMC_CH3_Reserved.description="Reserved"
2219
+ AT91C_PWMC_CH3_Reserved.helpkey="Reserved"
2220
+ AT91C_PWMC_CH3_Reserved.access=memorymapped
2221
+ AT91C_PWMC_CH3_Reserved.address=0xFFFCC274
2222
+ AT91C_PWMC_CH3_Reserved.width=32
2223
+ AT91C_PWMC_CH3_Reserved.byteEndian=little
2224
+ AT91C_PWMC_CH3_Reserved.type=enum
2225
+ AT91C_PWMC_CH3_Reserved.enum.0.name=*** Write only ***
2226
+ AT91C_PWMC_CH3_Reserved.enum.1.name=Error
2227
+ AT91C_PWMC_CH3_CPRDR.name="AT91C_PWMC_CH3_CPRDR"
2228
+ AT91C_PWMC_CH3_CPRDR.description="Channel Period Register"
2229
+ AT91C_PWMC_CH3_CPRDR.helpkey="Channel Period Register"
2230
+ AT91C_PWMC_CH3_CPRDR.access=memorymapped
2231
+ AT91C_PWMC_CH3_CPRDR.address=0xFFFCC268
2232
+ AT91C_PWMC_CH3_CPRDR.width=32
2233
+ AT91C_PWMC_CH3_CPRDR.byteEndian=little
2234
+ AT91C_PWMC_CH3_CDTYR.name="AT91C_PWMC_CH3_CDTYR"
2235
+ AT91C_PWMC_CH3_CDTYR.description="Channel Duty Cycle Register"
2236
+ AT91C_PWMC_CH3_CDTYR.helpkey="Channel Duty Cycle Register"
2237
+ AT91C_PWMC_CH3_CDTYR.access=memorymapped
2238
+ AT91C_PWMC_CH3_CDTYR.address=0xFFFCC264
2239
+ AT91C_PWMC_CH3_CDTYR.width=32
2240
+ AT91C_PWMC_CH3_CDTYR.byteEndian=little
2241
+ AT91C_PWMC_CH3_CCNTR.name="AT91C_PWMC_CH3_CCNTR"
2242
+ AT91C_PWMC_CH3_CCNTR.description="Channel Counter Register"
2243
+ AT91C_PWMC_CH3_CCNTR.helpkey="Channel Counter Register"
2244
+ AT91C_PWMC_CH3_CCNTR.access=memorymapped
2245
+ AT91C_PWMC_CH3_CCNTR.address=0xFFFCC26C
2246
+ AT91C_PWMC_CH3_CCNTR.width=32
2247
+ AT91C_PWMC_CH3_CCNTR.byteEndian=little
2248
+ AT91C_PWMC_CH3_CCNTR.permission.write=none
2249
+ AT91C_PWMC_CH3_CMR.name="AT91C_PWMC_CH3_CMR"
2250
+ AT91C_PWMC_CH3_CMR.description="Channel Mode Register"
2251
+ AT91C_PWMC_CH3_CMR.helpkey="Channel Mode Register"
2252
+ AT91C_PWMC_CH3_CMR.access=memorymapped
2253
+ AT91C_PWMC_CH3_CMR.address=0xFFFCC260
2254
+ AT91C_PWMC_CH3_CMR.width=32
2255
+ AT91C_PWMC_CH3_CMR.byteEndian=little
2256
+ # ========== Register definition for PWMC_CH2 peripheral ==========
2257
+ AT91C_PWMC_CH2_Reserved.name="AT91C_PWMC_CH2_Reserved"
2258
+ AT91C_PWMC_CH2_Reserved.description="Reserved"
2259
+ AT91C_PWMC_CH2_Reserved.helpkey="Reserved"
2260
+ AT91C_PWMC_CH2_Reserved.access=memorymapped
2261
+ AT91C_PWMC_CH2_Reserved.address=0xFFFCC254
2262
+ AT91C_PWMC_CH2_Reserved.width=32
2263
+ AT91C_PWMC_CH2_Reserved.byteEndian=little
2264
+ AT91C_PWMC_CH2_Reserved.type=enum
2265
+ AT91C_PWMC_CH2_Reserved.enum.0.name=*** Write only ***
2266
+ AT91C_PWMC_CH2_Reserved.enum.1.name=Error
2267
+ AT91C_PWMC_CH2_CMR.name="AT91C_PWMC_CH2_CMR"
2268
+ AT91C_PWMC_CH2_CMR.description="Channel Mode Register"
2269
+ AT91C_PWMC_CH2_CMR.helpkey="Channel Mode Register"
2270
+ AT91C_PWMC_CH2_CMR.access=memorymapped
2271
+ AT91C_PWMC_CH2_CMR.address=0xFFFCC240
2272
+ AT91C_PWMC_CH2_CMR.width=32
2273
+ AT91C_PWMC_CH2_CMR.byteEndian=little
2274
+ AT91C_PWMC_CH2_CCNTR.name="AT91C_PWMC_CH2_CCNTR"
2275
+ AT91C_PWMC_CH2_CCNTR.description="Channel Counter Register"
2276
+ AT91C_PWMC_CH2_CCNTR.helpkey="Channel Counter Register"
2277
+ AT91C_PWMC_CH2_CCNTR.access=memorymapped
2278
+ AT91C_PWMC_CH2_CCNTR.address=0xFFFCC24C
2279
+ AT91C_PWMC_CH2_CCNTR.width=32
2280
+ AT91C_PWMC_CH2_CCNTR.byteEndian=little
2281
+ AT91C_PWMC_CH2_CCNTR.permission.write=none
2282
+ AT91C_PWMC_CH2_CPRDR.name="AT91C_PWMC_CH2_CPRDR"
2283
+ AT91C_PWMC_CH2_CPRDR.description="Channel Period Register"
2284
+ AT91C_PWMC_CH2_CPRDR.helpkey="Channel Period Register"
2285
+ AT91C_PWMC_CH2_CPRDR.access=memorymapped
2286
+ AT91C_PWMC_CH2_CPRDR.address=0xFFFCC248
2287
+ AT91C_PWMC_CH2_CPRDR.width=32
2288
+ AT91C_PWMC_CH2_CPRDR.byteEndian=little
2289
+ AT91C_PWMC_CH2_CUPDR.name="AT91C_PWMC_CH2_CUPDR"
2290
+ AT91C_PWMC_CH2_CUPDR.description="Channel Update Register"
2291
+ AT91C_PWMC_CH2_CUPDR.helpkey="Channel Update Register"
2292
+ AT91C_PWMC_CH2_CUPDR.access=memorymapped
2293
+ AT91C_PWMC_CH2_CUPDR.address=0xFFFCC250
2294
+ AT91C_PWMC_CH2_CUPDR.width=32
2295
+ AT91C_PWMC_CH2_CUPDR.byteEndian=little
2296
+ AT91C_PWMC_CH2_CUPDR.type=enum
2297
+ AT91C_PWMC_CH2_CUPDR.enum.0.name=*** Write only ***
2298
+ AT91C_PWMC_CH2_CUPDR.enum.1.name=Error
2299
+ AT91C_PWMC_CH2_CDTYR.name="AT91C_PWMC_CH2_CDTYR"
2300
+ AT91C_PWMC_CH2_CDTYR.description="Channel Duty Cycle Register"
2301
+ AT91C_PWMC_CH2_CDTYR.helpkey="Channel Duty Cycle Register"
2302
+ AT91C_PWMC_CH2_CDTYR.access=memorymapped
2303
+ AT91C_PWMC_CH2_CDTYR.address=0xFFFCC244
2304
+ AT91C_PWMC_CH2_CDTYR.width=32
2305
+ AT91C_PWMC_CH2_CDTYR.byteEndian=little
2306
+ # ========== Register definition for PWMC_CH1 peripheral ==========
2307
+ AT91C_PWMC_CH1_Reserved.name="AT91C_PWMC_CH1_Reserved"
2308
+ AT91C_PWMC_CH1_Reserved.description="Reserved"
2309
+ AT91C_PWMC_CH1_Reserved.helpkey="Reserved"
2310
+ AT91C_PWMC_CH1_Reserved.access=memorymapped
2311
+ AT91C_PWMC_CH1_Reserved.address=0xFFFCC234
2312
+ AT91C_PWMC_CH1_Reserved.width=32
2313
+ AT91C_PWMC_CH1_Reserved.byteEndian=little
2314
+ AT91C_PWMC_CH1_Reserved.type=enum
2315
+ AT91C_PWMC_CH1_Reserved.enum.0.name=*** Write only ***
2316
+ AT91C_PWMC_CH1_Reserved.enum.1.name=Error
2317
+ AT91C_PWMC_CH1_CUPDR.name="AT91C_PWMC_CH1_CUPDR"
2318
+ AT91C_PWMC_CH1_CUPDR.description="Channel Update Register"
2319
+ AT91C_PWMC_CH1_CUPDR.helpkey="Channel Update Register"
2320
+ AT91C_PWMC_CH1_CUPDR.access=memorymapped
2321
+ AT91C_PWMC_CH1_CUPDR.address=0xFFFCC230
2322
+ AT91C_PWMC_CH1_CUPDR.width=32
2323
+ AT91C_PWMC_CH1_CUPDR.byteEndian=little
2324
+ AT91C_PWMC_CH1_CUPDR.type=enum
2325
+ AT91C_PWMC_CH1_CUPDR.enum.0.name=*** Write only ***
2326
+ AT91C_PWMC_CH1_CUPDR.enum.1.name=Error
2327
+ AT91C_PWMC_CH1_CPRDR.name="AT91C_PWMC_CH1_CPRDR"
2328
+ AT91C_PWMC_CH1_CPRDR.description="Channel Period Register"
2329
+ AT91C_PWMC_CH1_CPRDR.helpkey="Channel Period Register"
2330
+ AT91C_PWMC_CH1_CPRDR.access=memorymapped
2331
+ AT91C_PWMC_CH1_CPRDR.address=0xFFFCC228
2332
+ AT91C_PWMC_CH1_CPRDR.width=32
2333
+ AT91C_PWMC_CH1_CPRDR.byteEndian=little
2334
+ AT91C_PWMC_CH1_CCNTR.name="AT91C_PWMC_CH1_CCNTR"
2335
+ AT91C_PWMC_CH1_CCNTR.description="Channel Counter Register"
2336
+ AT91C_PWMC_CH1_CCNTR.helpkey="Channel Counter Register"
2337
+ AT91C_PWMC_CH1_CCNTR.access=memorymapped
2338
+ AT91C_PWMC_CH1_CCNTR.address=0xFFFCC22C
2339
+ AT91C_PWMC_CH1_CCNTR.width=32
2340
+ AT91C_PWMC_CH1_CCNTR.byteEndian=little
2341
+ AT91C_PWMC_CH1_CCNTR.permission.write=none
2342
+ AT91C_PWMC_CH1_CDTYR.name="AT91C_PWMC_CH1_CDTYR"
2343
+ AT91C_PWMC_CH1_CDTYR.description="Channel Duty Cycle Register"
2344
+ AT91C_PWMC_CH1_CDTYR.helpkey="Channel Duty Cycle Register"
2345
+ AT91C_PWMC_CH1_CDTYR.access=memorymapped
2346
+ AT91C_PWMC_CH1_CDTYR.address=0xFFFCC224
2347
+ AT91C_PWMC_CH1_CDTYR.width=32
2348
+ AT91C_PWMC_CH1_CDTYR.byteEndian=little
2349
+ AT91C_PWMC_CH1_CMR.name="AT91C_PWMC_CH1_CMR"
2350
+ AT91C_PWMC_CH1_CMR.description="Channel Mode Register"
2351
+ AT91C_PWMC_CH1_CMR.helpkey="Channel Mode Register"
2352
+ AT91C_PWMC_CH1_CMR.access=memorymapped
2353
+ AT91C_PWMC_CH1_CMR.address=0xFFFCC220
2354
+ AT91C_PWMC_CH1_CMR.width=32
2355
+ AT91C_PWMC_CH1_CMR.byteEndian=little
2356
+ # ========== Register definition for PWMC_CH0 peripheral ==========
2357
+ AT91C_PWMC_CH0_Reserved.name="AT91C_PWMC_CH0_Reserved"
2358
+ AT91C_PWMC_CH0_Reserved.description="Reserved"
2359
+ AT91C_PWMC_CH0_Reserved.helpkey="Reserved"
2360
+ AT91C_PWMC_CH0_Reserved.access=memorymapped
2361
+ AT91C_PWMC_CH0_Reserved.address=0xFFFCC214
2362
+ AT91C_PWMC_CH0_Reserved.width=32
2363
+ AT91C_PWMC_CH0_Reserved.byteEndian=little
2364
+ AT91C_PWMC_CH0_Reserved.type=enum
2365
+ AT91C_PWMC_CH0_Reserved.enum.0.name=*** Write only ***
2366
+ AT91C_PWMC_CH0_Reserved.enum.1.name=Error
2367
+ AT91C_PWMC_CH0_CPRDR.name="AT91C_PWMC_CH0_CPRDR"
2368
+ AT91C_PWMC_CH0_CPRDR.description="Channel Period Register"
2369
+ AT91C_PWMC_CH0_CPRDR.helpkey="Channel Period Register"
2370
+ AT91C_PWMC_CH0_CPRDR.access=memorymapped
2371
+ AT91C_PWMC_CH0_CPRDR.address=0xFFFCC208
2372
+ AT91C_PWMC_CH0_CPRDR.width=32
2373
+ AT91C_PWMC_CH0_CPRDR.byteEndian=little
2374
+ AT91C_PWMC_CH0_CDTYR.name="AT91C_PWMC_CH0_CDTYR"
2375
+ AT91C_PWMC_CH0_CDTYR.description="Channel Duty Cycle Register"
2376
+ AT91C_PWMC_CH0_CDTYR.helpkey="Channel Duty Cycle Register"
2377
+ AT91C_PWMC_CH0_CDTYR.access=memorymapped
2378
+ AT91C_PWMC_CH0_CDTYR.address=0xFFFCC204
2379
+ AT91C_PWMC_CH0_CDTYR.width=32
2380
+ AT91C_PWMC_CH0_CDTYR.byteEndian=little
2381
+ AT91C_PWMC_CH0_CMR.name="AT91C_PWMC_CH0_CMR"
2382
+ AT91C_PWMC_CH0_CMR.description="Channel Mode Register"
2383
+ AT91C_PWMC_CH0_CMR.helpkey="Channel Mode Register"
2384
+ AT91C_PWMC_CH0_CMR.access=memorymapped
2385
+ AT91C_PWMC_CH0_CMR.address=0xFFFCC200
2386
+ AT91C_PWMC_CH0_CMR.width=32
2387
+ AT91C_PWMC_CH0_CMR.byteEndian=little
2388
+ AT91C_PWMC_CH0_CUPDR.name="AT91C_PWMC_CH0_CUPDR"
2389
+ AT91C_PWMC_CH0_CUPDR.description="Channel Update Register"
2390
+ AT91C_PWMC_CH0_CUPDR.helpkey="Channel Update Register"
2391
+ AT91C_PWMC_CH0_CUPDR.access=memorymapped
2392
+ AT91C_PWMC_CH0_CUPDR.address=0xFFFCC210
2393
+ AT91C_PWMC_CH0_CUPDR.width=32
2394
+ AT91C_PWMC_CH0_CUPDR.byteEndian=little
2395
+ AT91C_PWMC_CH0_CUPDR.type=enum
2396
+ AT91C_PWMC_CH0_CUPDR.enum.0.name=*** Write only ***
2397
+ AT91C_PWMC_CH0_CUPDR.enum.1.name=Error
2398
+ AT91C_PWMC_CH0_CCNTR.name="AT91C_PWMC_CH0_CCNTR"
2399
+ AT91C_PWMC_CH0_CCNTR.description="Channel Counter Register"
2400
+ AT91C_PWMC_CH0_CCNTR.helpkey="Channel Counter Register"
2401
+ AT91C_PWMC_CH0_CCNTR.access=memorymapped
2402
+ AT91C_PWMC_CH0_CCNTR.address=0xFFFCC20C
2403
+ AT91C_PWMC_CH0_CCNTR.width=32
2404
+ AT91C_PWMC_CH0_CCNTR.byteEndian=little
2405
+ AT91C_PWMC_CH0_CCNTR.permission.write=none
2406
+ # ========== Register definition for PWMC peripheral ==========
2407
+ AT91C_PWMC_IDR.name="AT91C_PWMC_IDR"
2408
+ AT91C_PWMC_IDR.description="PWMC Interrupt Disable Register"
2409
+ AT91C_PWMC_IDR.helpkey="PWMC Interrupt Disable Register"
2410
+ AT91C_PWMC_IDR.access=memorymapped
2411
+ AT91C_PWMC_IDR.address=0xFFFCC014
2412
+ AT91C_PWMC_IDR.width=32
2413
+ AT91C_PWMC_IDR.byteEndian=little
2414
+ AT91C_PWMC_IDR.type=enum
2415
+ AT91C_PWMC_IDR.enum.0.name=*** Write only ***
2416
+ AT91C_PWMC_IDR.enum.1.name=Error
2417
+ AT91C_PWMC_DIS.name="AT91C_PWMC_DIS"
2418
+ AT91C_PWMC_DIS.description="PWMC Disable Register"
2419
+ AT91C_PWMC_DIS.helpkey="PWMC Disable Register"
2420
+ AT91C_PWMC_DIS.access=memorymapped
2421
+ AT91C_PWMC_DIS.address=0xFFFCC008
2422
+ AT91C_PWMC_DIS.width=32
2423
+ AT91C_PWMC_DIS.byteEndian=little
2424
+ AT91C_PWMC_DIS.type=enum
2425
+ AT91C_PWMC_DIS.enum.0.name=*** Write only ***
2426
+ AT91C_PWMC_DIS.enum.1.name=Error
2427
+ AT91C_PWMC_IER.name="AT91C_PWMC_IER"
2428
+ AT91C_PWMC_IER.description="PWMC Interrupt Enable Register"
2429
+ AT91C_PWMC_IER.helpkey="PWMC Interrupt Enable Register"
2430
+ AT91C_PWMC_IER.access=memorymapped
2431
+ AT91C_PWMC_IER.address=0xFFFCC010
2432
+ AT91C_PWMC_IER.width=32
2433
+ AT91C_PWMC_IER.byteEndian=little
2434
+ AT91C_PWMC_IER.type=enum
2435
+ AT91C_PWMC_IER.enum.0.name=*** Write only ***
2436
+ AT91C_PWMC_IER.enum.1.name=Error
2437
+ AT91C_PWMC_VR.name="AT91C_PWMC_VR"
2438
+ AT91C_PWMC_VR.description="PWMC Version Register"
2439
+ AT91C_PWMC_VR.helpkey="PWMC Version Register"
2440
+ AT91C_PWMC_VR.access=memorymapped
2441
+ AT91C_PWMC_VR.address=0xFFFCC0FC
2442
+ AT91C_PWMC_VR.width=32
2443
+ AT91C_PWMC_VR.byteEndian=little
2444
+ AT91C_PWMC_VR.permission.write=none
2445
+ AT91C_PWMC_ISR.name="AT91C_PWMC_ISR"
2446
+ AT91C_PWMC_ISR.description="PWMC Interrupt Status Register"
2447
+ AT91C_PWMC_ISR.helpkey="PWMC Interrupt Status Register"
2448
+ AT91C_PWMC_ISR.access=memorymapped
2449
+ AT91C_PWMC_ISR.address=0xFFFCC01C
2450
+ AT91C_PWMC_ISR.width=32
2451
+ AT91C_PWMC_ISR.byteEndian=little
2452
+ AT91C_PWMC_ISR.permission.write=none
2453
+ AT91C_PWMC_SR.name="AT91C_PWMC_SR"
2454
+ AT91C_PWMC_SR.description="PWMC Status Register"
2455
+ AT91C_PWMC_SR.helpkey="PWMC Status Register"
2456
+ AT91C_PWMC_SR.access=memorymapped
2457
+ AT91C_PWMC_SR.address=0xFFFCC00C
2458
+ AT91C_PWMC_SR.width=32
2459
+ AT91C_PWMC_SR.byteEndian=little
2460
+ AT91C_PWMC_SR.permission.write=none
2461
+ AT91C_PWMC_IMR.name="AT91C_PWMC_IMR"
2462
+ AT91C_PWMC_IMR.description="PWMC Interrupt Mask Register"
2463
+ AT91C_PWMC_IMR.helpkey="PWMC Interrupt Mask Register"
2464
+ AT91C_PWMC_IMR.access=memorymapped
2465
+ AT91C_PWMC_IMR.address=0xFFFCC018
2466
+ AT91C_PWMC_IMR.width=32
2467
+ AT91C_PWMC_IMR.byteEndian=little
2468
+ AT91C_PWMC_IMR.permission.write=none
2469
+ AT91C_PWMC_MR.name="AT91C_PWMC_MR"
2470
+ AT91C_PWMC_MR.description="PWMC Mode Register"
2471
+ AT91C_PWMC_MR.helpkey="PWMC Mode Register"
2472
+ AT91C_PWMC_MR.access=memorymapped
2473
+ AT91C_PWMC_MR.address=0xFFFCC000
2474
+ AT91C_PWMC_MR.width=32
2475
+ AT91C_PWMC_MR.byteEndian=little
2476
+ AT91C_PWMC_ENA.name="AT91C_PWMC_ENA"
2477
+ AT91C_PWMC_ENA.description="PWMC Enable Register"
2478
+ AT91C_PWMC_ENA.helpkey="PWMC Enable Register"
2479
+ AT91C_PWMC_ENA.access=memorymapped
2480
+ AT91C_PWMC_ENA.address=0xFFFCC004
2481
+ AT91C_PWMC_ENA.width=32
2482
+ AT91C_PWMC_ENA.byteEndian=little
2483
+ AT91C_PWMC_ENA.type=enum
2484
+ AT91C_PWMC_ENA.enum.0.name=*** Write only ***
2485
+ AT91C_PWMC_ENA.enum.1.name=Error
2486
+ # ========== Register definition for UDP peripheral ==========
2487
+ AT91C_UDP_IMR.name="AT91C_UDP_IMR"
2488
+ AT91C_UDP_IMR.description="Interrupt Mask Register"
2489
+ AT91C_UDP_IMR.helpkey="Interrupt Mask Register"
2490
+ AT91C_UDP_IMR.access=memorymapped
2491
+ AT91C_UDP_IMR.address=0xFFFB0018
2492
+ AT91C_UDP_IMR.width=32
2493
+ AT91C_UDP_IMR.byteEndian=little
2494
+ AT91C_UDP_IMR.permission.write=none
2495
+ AT91C_UDP_FADDR.name="AT91C_UDP_FADDR"
2496
+ AT91C_UDP_FADDR.description="Function Address Register"
2497
+ AT91C_UDP_FADDR.helpkey="Function Address Register"
2498
+ AT91C_UDP_FADDR.access=memorymapped
2499
+ AT91C_UDP_FADDR.address=0xFFFB0008
2500
+ AT91C_UDP_FADDR.width=32
2501
+ AT91C_UDP_FADDR.byteEndian=little
2502
+ AT91C_UDP_NUM.name="AT91C_UDP_NUM"
2503
+ AT91C_UDP_NUM.description="Frame Number Register"
2504
+ AT91C_UDP_NUM.helpkey="Frame Number Register"
2505
+ AT91C_UDP_NUM.access=memorymapped
2506
+ AT91C_UDP_NUM.address=0xFFFB0000
2507
+ AT91C_UDP_NUM.width=32
2508
+ AT91C_UDP_NUM.byteEndian=little
2509
+ AT91C_UDP_NUM.permission.write=none
2510
+ AT91C_UDP_FDR.name="AT91C_UDP_FDR"
2511
+ AT91C_UDP_FDR.description="Endpoint FIFO Data Register"
2512
+ AT91C_UDP_FDR.helpkey="Endpoint FIFO Data Register"
2513
+ AT91C_UDP_FDR.access=memorymapped
2514
+ AT91C_UDP_FDR.address=0xFFFB0050
2515
+ AT91C_UDP_FDR.width=32
2516
+ AT91C_UDP_FDR.byteEndian=little
2517
+ AT91C_UDP_ISR.name="AT91C_UDP_ISR"
2518
+ AT91C_UDP_ISR.description="Interrupt Status Register"
2519
+ AT91C_UDP_ISR.helpkey="Interrupt Status Register"
2520
+ AT91C_UDP_ISR.access=memorymapped
2521
+ AT91C_UDP_ISR.address=0xFFFB001C
2522
+ AT91C_UDP_ISR.width=32
2523
+ AT91C_UDP_ISR.byteEndian=little
2524
+ AT91C_UDP_ISR.permission.write=none
2525
+ AT91C_UDP_CSR.name="AT91C_UDP_CSR"
2526
+ AT91C_UDP_CSR.description="Endpoint Control and Status Register"
2527
+ AT91C_UDP_CSR.helpkey="Endpoint Control and Status Register"
2528
+ AT91C_UDP_CSR.access=memorymapped
2529
+ AT91C_UDP_CSR.address=0xFFFB0030
2530
+ AT91C_UDP_CSR.width=32
2531
+ AT91C_UDP_CSR.byteEndian=little
2532
+ AT91C_UDP_IDR.name="AT91C_UDP_IDR"
2533
+ AT91C_UDP_IDR.description="Interrupt Disable Register"
2534
+ AT91C_UDP_IDR.helpkey="Interrupt Disable Register"
2535
+ AT91C_UDP_IDR.access=memorymapped
2536
+ AT91C_UDP_IDR.address=0xFFFB0014
2537
+ AT91C_UDP_IDR.width=32
2538
+ AT91C_UDP_IDR.byteEndian=little
2539
+ AT91C_UDP_IDR.type=enum
2540
+ AT91C_UDP_IDR.enum.0.name=*** Write only ***
2541
+ AT91C_UDP_IDR.enum.1.name=Error
2542
+ AT91C_UDP_ICR.name="AT91C_UDP_ICR"
2543
+ AT91C_UDP_ICR.description="Interrupt Clear Register"
2544
+ AT91C_UDP_ICR.helpkey="Interrupt Clear Register"
2545
+ AT91C_UDP_ICR.access=memorymapped
2546
+ AT91C_UDP_ICR.address=0xFFFB0020
2547
+ AT91C_UDP_ICR.width=32
2548
+ AT91C_UDP_ICR.byteEndian=little
2549
+ AT91C_UDP_ICR.permission.write=none
2550
+ AT91C_UDP_RSTEP.name="AT91C_UDP_RSTEP"
2551
+ AT91C_UDP_RSTEP.description="Reset Endpoint Register"
2552
+ AT91C_UDP_RSTEP.helpkey="Reset Endpoint Register"
2553
+ AT91C_UDP_RSTEP.access=memorymapped
2554
+ AT91C_UDP_RSTEP.address=0xFFFB0028
2555
+ AT91C_UDP_RSTEP.width=32
2556
+ AT91C_UDP_RSTEP.byteEndian=little
2557
+ AT91C_UDP_RSTEP.permission.write=none
2558
+ AT91C_UDP_TXVC.name="AT91C_UDP_TXVC"
2559
+ AT91C_UDP_TXVC.description="Transceiver Control Register"
2560
+ AT91C_UDP_TXVC.helpkey="Transceiver Control Register"
2561
+ AT91C_UDP_TXVC.access=memorymapped
2562
+ AT91C_UDP_TXVC.address=0xFFFB0074
2563
+ AT91C_UDP_TXVC.width=32
2564
+ AT91C_UDP_TXVC.byteEndian=little
2565
+ AT91C_UDP_GLBSTATE.name="AT91C_UDP_GLBSTATE"
2566
+ AT91C_UDP_GLBSTATE.description="Global State Register"
2567
+ AT91C_UDP_GLBSTATE.helpkey="Global State Register"
2568
+ AT91C_UDP_GLBSTATE.access=memorymapped
2569
+ AT91C_UDP_GLBSTATE.address=0xFFFB0004
2570
+ AT91C_UDP_GLBSTATE.width=32
2571
+ AT91C_UDP_GLBSTATE.byteEndian=little
2572
+ AT91C_UDP_IER.name="AT91C_UDP_IER"
2573
+ AT91C_UDP_IER.description="Interrupt Enable Register"
2574
+ AT91C_UDP_IER.helpkey="Interrupt Enable Register"
2575
+ AT91C_UDP_IER.access=memorymapped
2576
+ AT91C_UDP_IER.address=0xFFFB0010
2577
+ AT91C_UDP_IER.width=32
2578
+ AT91C_UDP_IER.byteEndian=little
2579
+ AT91C_UDP_IER.type=enum
2580
+ AT91C_UDP_IER.enum.0.name=*** Write only ***
2581
+ AT91C_UDP_IER.enum.1.name=Error
2582
+ # ========== Register definition for TC0 peripheral ==========
2583
+ AT91C_TC0_SR.name="AT91C_TC0_SR"
2584
+ AT91C_TC0_SR.description="Status Register"
2585
+ AT91C_TC0_SR.helpkey="Status Register"
2586
+ AT91C_TC0_SR.access=memorymapped
2587
+ AT91C_TC0_SR.address=0xFFFA0020
2588
+ AT91C_TC0_SR.width=32
2589
+ AT91C_TC0_SR.byteEndian=little
2590
+ AT91C_TC0_SR.permission.write=none
2591
+ AT91C_TC0_RC.name="AT91C_TC0_RC"
2592
+ AT91C_TC0_RC.description="Register C"
2593
+ AT91C_TC0_RC.helpkey="Register C"
2594
+ AT91C_TC0_RC.access=memorymapped
2595
+ AT91C_TC0_RC.address=0xFFFA001C
2596
+ AT91C_TC0_RC.width=32
2597
+ AT91C_TC0_RC.byteEndian=little
2598
+ AT91C_TC0_RB.name="AT91C_TC0_RB"
2599
+ AT91C_TC0_RB.description="Register B"
2600
+ AT91C_TC0_RB.helpkey="Register B"
2601
+ AT91C_TC0_RB.access=memorymapped
2602
+ AT91C_TC0_RB.address=0xFFFA0018
2603
+ AT91C_TC0_RB.width=32
2604
+ AT91C_TC0_RB.byteEndian=little
2605
+ AT91C_TC0_CCR.name="AT91C_TC0_CCR"
2606
+ AT91C_TC0_CCR.description="Channel Control Register"
2607
+ AT91C_TC0_CCR.helpkey="Channel Control Register"
2608
+ AT91C_TC0_CCR.access=memorymapped
2609
+ AT91C_TC0_CCR.address=0xFFFA0000
2610
+ AT91C_TC0_CCR.width=32
2611
+ AT91C_TC0_CCR.byteEndian=little
2612
+ AT91C_TC0_CCR.type=enum
2613
+ AT91C_TC0_CCR.enum.0.name=*** Write only ***
2614
+ AT91C_TC0_CCR.enum.1.name=Error
2615
+ AT91C_TC0_CMR.name="AT91C_TC0_CMR"
2616
+ AT91C_TC0_CMR.description="Channel Mode Register (Capture Mode / Waveform Mode)"
2617
+ AT91C_TC0_CMR.helpkey="Channel Mode Register (Capture Mode / Waveform Mode)"
2618
+ AT91C_TC0_CMR.access=memorymapped
2619
+ AT91C_TC0_CMR.address=0xFFFA0004
2620
+ AT91C_TC0_CMR.width=32
2621
+ AT91C_TC0_CMR.byteEndian=little
2622
+ AT91C_TC0_IER.name="AT91C_TC0_IER"
2623
+ AT91C_TC0_IER.description="Interrupt Enable Register"
2624
+ AT91C_TC0_IER.helpkey="Interrupt Enable Register"
2625
+ AT91C_TC0_IER.access=memorymapped
2626
+ AT91C_TC0_IER.address=0xFFFA0024
2627
+ AT91C_TC0_IER.width=32
2628
+ AT91C_TC0_IER.byteEndian=little
2629
+ AT91C_TC0_IER.type=enum
2630
+ AT91C_TC0_IER.enum.0.name=*** Write only ***
2631
+ AT91C_TC0_IER.enum.1.name=Error
2632
+ AT91C_TC0_RA.name="AT91C_TC0_RA"
2633
+ AT91C_TC0_RA.description="Register A"
2634
+ AT91C_TC0_RA.helpkey="Register A"
2635
+ AT91C_TC0_RA.access=memorymapped
2636
+ AT91C_TC0_RA.address=0xFFFA0014
2637
+ AT91C_TC0_RA.width=32
2638
+ AT91C_TC0_RA.byteEndian=little
2639
+ AT91C_TC0_IDR.name="AT91C_TC0_IDR"
2640
+ AT91C_TC0_IDR.description="Interrupt Disable Register"
2641
+ AT91C_TC0_IDR.helpkey="Interrupt Disable Register"
2642
+ AT91C_TC0_IDR.access=memorymapped
2643
+ AT91C_TC0_IDR.address=0xFFFA0028
2644
+ AT91C_TC0_IDR.width=32
2645
+ AT91C_TC0_IDR.byteEndian=little
2646
+ AT91C_TC0_IDR.type=enum
2647
+ AT91C_TC0_IDR.enum.0.name=*** Write only ***
2648
+ AT91C_TC0_IDR.enum.1.name=Error
2649
+ AT91C_TC0_CV.name="AT91C_TC0_CV"
2650
+ AT91C_TC0_CV.description="Counter Value"
2651
+ AT91C_TC0_CV.helpkey="Counter Value"
2652
+ AT91C_TC0_CV.access=memorymapped
2653
+ AT91C_TC0_CV.address=0xFFFA0010
2654
+ AT91C_TC0_CV.width=32
2655
+ AT91C_TC0_CV.byteEndian=little
2656
+ AT91C_TC0_IMR.name="AT91C_TC0_IMR"
2657
+ AT91C_TC0_IMR.description="Interrupt Mask Register"
2658
+ AT91C_TC0_IMR.helpkey="Interrupt Mask Register"
2659
+ AT91C_TC0_IMR.access=memorymapped
2660
+ AT91C_TC0_IMR.address=0xFFFA002C
2661
+ AT91C_TC0_IMR.width=32
2662
+ AT91C_TC0_IMR.byteEndian=little
2663
+ AT91C_TC0_IMR.permission.write=none
2664
+ # ========== Register definition for TC1 peripheral ==========
2665
+ AT91C_TC1_RB.name="AT91C_TC1_RB"
2666
+ AT91C_TC1_RB.description="Register B"
2667
+ AT91C_TC1_RB.helpkey="Register B"
2668
+ AT91C_TC1_RB.access=memorymapped
2669
+ AT91C_TC1_RB.address=0xFFFA0058
2670
+ AT91C_TC1_RB.width=32
2671
+ AT91C_TC1_RB.byteEndian=little
2672
+ AT91C_TC1_CCR.name="AT91C_TC1_CCR"
2673
+ AT91C_TC1_CCR.description="Channel Control Register"
2674
+ AT91C_TC1_CCR.helpkey="Channel Control Register"
2675
+ AT91C_TC1_CCR.access=memorymapped
2676
+ AT91C_TC1_CCR.address=0xFFFA0040
2677
+ AT91C_TC1_CCR.width=32
2678
+ AT91C_TC1_CCR.byteEndian=little
2679
+ AT91C_TC1_CCR.type=enum
2680
+ AT91C_TC1_CCR.enum.0.name=*** Write only ***
2681
+ AT91C_TC1_CCR.enum.1.name=Error
2682
+ AT91C_TC1_IER.name="AT91C_TC1_IER"
2683
+ AT91C_TC1_IER.description="Interrupt Enable Register"
2684
+ AT91C_TC1_IER.helpkey="Interrupt Enable Register"
2685
+ AT91C_TC1_IER.access=memorymapped
2686
+ AT91C_TC1_IER.address=0xFFFA0064
2687
+ AT91C_TC1_IER.width=32
2688
+ AT91C_TC1_IER.byteEndian=little
2689
+ AT91C_TC1_IER.type=enum
2690
+ AT91C_TC1_IER.enum.0.name=*** Write only ***
2691
+ AT91C_TC1_IER.enum.1.name=Error
2692
+ AT91C_TC1_IDR.name="AT91C_TC1_IDR"
2693
+ AT91C_TC1_IDR.description="Interrupt Disable Register"
2694
+ AT91C_TC1_IDR.helpkey="Interrupt Disable Register"
2695
+ AT91C_TC1_IDR.access=memorymapped
2696
+ AT91C_TC1_IDR.address=0xFFFA0068
2697
+ AT91C_TC1_IDR.width=32
2698
+ AT91C_TC1_IDR.byteEndian=little
2699
+ AT91C_TC1_IDR.type=enum
2700
+ AT91C_TC1_IDR.enum.0.name=*** Write only ***
2701
+ AT91C_TC1_IDR.enum.1.name=Error
2702
+ AT91C_TC1_SR.name="AT91C_TC1_SR"
2703
+ AT91C_TC1_SR.description="Status Register"
2704
+ AT91C_TC1_SR.helpkey="Status Register"
2705
+ AT91C_TC1_SR.access=memorymapped
2706
+ AT91C_TC1_SR.address=0xFFFA0060
2707
+ AT91C_TC1_SR.width=32
2708
+ AT91C_TC1_SR.byteEndian=little
2709
+ AT91C_TC1_SR.permission.write=none
2710
+ AT91C_TC1_CMR.name="AT91C_TC1_CMR"
2711
+ AT91C_TC1_CMR.description="Channel Mode Register (Capture Mode / Waveform Mode)"
2712
+ AT91C_TC1_CMR.helpkey="Channel Mode Register (Capture Mode / Waveform Mode)"
2713
+ AT91C_TC1_CMR.access=memorymapped
2714
+ AT91C_TC1_CMR.address=0xFFFA0044
2715
+ AT91C_TC1_CMR.width=32
2716
+ AT91C_TC1_CMR.byteEndian=little
2717
+ AT91C_TC1_RA.name="AT91C_TC1_RA"
2718
+ AT91C_TC1_RA.description="Register A"
2719
+ AT91C_TC1_RA.helpkey="Register A"
2720
+ AT91C_TC1_RA.access=memorymapped
2721
+ AT91C_TC1_RA.address=0xFFFA0054
2722
+ AT91C_TC1_RA.width=32
2723
+ AT91C_TC1_RA.byteEndian=little
2724
+ AT91C_TC1_RC.name="AT91C_TC1_RC"
2725
+ AT91C_TC1_RC.description="Register C"
2726
+ AT91C_TC1_RC.helpkey="Register C"
2727
+ AT91C_TC1_RC.access=memorymapped
2728
+ AT91C_TC1_RC.address=0xFFFA005C
2729
+ AT91C_TC1_RC.width=32
2730
+ AT91C_TC1_RC.byteEndian=little
2731
+ AT91C_TC1_IMR.name="AT91C_TC1_IMR"
2732
+ AT91C_TC1_IMR.description="Interrupt Mask Register"
2733
+ AT91C_TC1_IMR.helpkey="Interrupt Mask Register"
2734
+ AT91C_TC1_IMR.access=memorymapped
2735
+ AT91C_TC1_IMR.address=0xFFFA006C
2736
+ AT91C_TC1_IMR.width=32
2737
+ AT91C_TC1_IMR.byteEndian=little
2738
+ AT91C_TC1_IMR.permission.write=none
2739
+ AT91C_TC1_CV.name="AT91C_TC1_CV"
2740
+ AT91C_TC1_CV.description="Counter Value"
2741
+ AT91C_TC1_CV.helpkey="Counter Value"
2742
+ AT91C_TC1_CV.access=memorymapped
2743
+ AT91C_TC1_CV.address=0xFFFA0050
2744
+ AT91C_TC1_CV.width=32
2745
+ AT91C_TC1_CV.byteEndian=little
2746
+ # ========== Register definition for TC2 peripheral ==========
2747
+ AT91C_TC2_CMR.name="AT91C_TC2_CMR"
2748
+ AT91C_TC2_CMR.description="Channel Mode Register (Capture Mode / Waveform Mode)"
2749
+ AT91C_TC2_CMR.helpkey="Channel Mode Register (Capture Mode / Waveform Mode)"
2750
+ AT91C_TC2_CMR.access=memorymapped
2751
+ AT91C_TC2_CMR.address=0xFFFA0084
2752
+ AT91C_TC2_CMR.width=32
2753
+ AT91C_TC2_CMR.byteEndian=little
2754
+ AT91C_TC2_CCR.name="AT91C_TC2_CCR"
2755
+ AT91C_TC2_CCR.description="Channel Control Register"
2756
+ AT91C_TC2_CCR.helpkey="Channel Control Register"
2757
+ AT91C_TC2_CCR.access=memorymapped
2758
+ AT91C_TC2_CCR.address=0xFFFA0080
2759
+ AT91C_TC2_CCR.width=32
2760
+ AT91C_TC2_CCR.byteEndian=little
2761
+ AT91C_TC2_CCR.type=enum
2762
+ AT91C_TC2_CCR.enum.0.name=*** Write only ***
2763
+ AT91C_TC2_CCR.enum.1.name=Error
2764
+ AT91C_TC2_CV.name="AT91C_TC2_CV"
2765
+ AT91C_TC2_CV.description="Counter Value"
2766
+ AT91C_TC2_CV.helpkey="Counter Value"
2767
+ AT91C_TC2_CV.access=memorymapped
2768
+ AT91C_TC2_CV.address=0xFFFA0090
2769
+ AT91C_TC2_CV.width=32
2770
+ AT91C_TC2_CV.byteEndian=little
2771
+ AT91C_TC2_RA.name="AT91C_TC2_RA"
2772
+ AT91C_TC2_RA.description="Register A"
2773
+ AT91C_TC2_RA.helpkey="Register A"
2774
+ AT91C_TC2_RA.access=memorymapped
2775
+ AT91C_TC2_RA.address=0xFFFA0094
2776
+ AT91C_TC2_RA.width=32
2777
+ AT91C_TC2_RA.byteEndian=little
2778
+ AT91C_TC2_RB.name="AT91C_TC2_RB"
2779
+ AT91C_TC2_RB.description="Register B"
2780
+ AT91C_TC2_RB.helpkey="Register B"
2781
+ AT91C_TC2_RB.access=memorymapped
2782
+ AT91C_TC2_RB.address=0xFFFA0098
2783
+ AT91C_TC2_RB.width=32
2784
+ AT91C_TC2_RB.byteEndian=little
2785
+ AT91C_TC2_IDR.name="AT91C_TC2_IDR"
2786
+ AT91C_TC2_IDR.description="Interrupt Disable Register"
2787
+ AT91C_TC2_IDR.helpkey="Interrupt Disable Register"
2788
+ AT91C_TC2_IDR.access=memorymapped
2789
+ AT91C_TC2_IDR.address=0xFFFA00A8
2790
+ AT91C_TC2_IDR.width=32
2791
+ AT91C_TC2_IDR.byteEndian=little
2792
+ AT91C_TC2_IDR.type=enum
2793
+ AT91C_TC2_IDR.enum.0.name=*** Write only ***
2794
+ AT91C_TC2_IDR.enum.1.name=Error
2795
+ AT91C_TC2_IMR.name="AT91C_TC2_IMR"
2796
+ AT91C_TC2_IMR.description="Interrupt Mask Register"
2797
+ AT91C_TC2_IMR.helpkey="Interrupt Mask Register"
2798
+ AT91C_TC2_IMR.access=memorymapped
2799
+ AT91C_TC2_IMR.address=0xFFFA00AC
2800
+ AT91C_TC2_IMR.width=32
2801
+ AT91C_TC2_IMR.byteEndian=little
2802
+ AT91C_TC2_IMR.permission.write=none
2803
+ AT91C_TC2_RC.name="AT91C_TC2_RC"
2804
+ AT91C_TC2_RC.description="Register C"
2805
+ AT91C_TC2_RC.helpkey="Register C"
2806
+ AT91C_TC2_RC.access=memorymapped
2807
+ AT91C_TC2_RC.address=0xFFFA009C
2808
+ AT91C_TC2_RC.width=32
2809
+ AT91C_TC2_RC.byteEndian=little
2810
+ AT91C_TC2_IER.name="AT91C_TC2_IER"
2811
+ AT91C_TC2_IER.description="Interrupt Enable Register"
2812
+ AT91C_TC2_IER.helpkey="Interrupt Enable Register"
2813
+ AT91C_TC2_IER.access=memorymapped
2814
+ AT91C_TC2_IER.address=0xFFFA00A4
2815
+ AT91C_TC2_IER.width=32
2816
+ AT91C_TC2_IER.byteEndian=little
2817
+ AT91C_TC2_IER.type=enum
2818
+ AT91C_TC2_IER.enum.0.name=*** Write only ***
2819
+ AT91C_TC2_IER.enum.1.name=Error
2820
+ AT91C_TC2_SR.name="AT91C_TC2_SR"
2821
+ AT91C_TC2_SR.description="Status Register"
2822
+ AT91C_TC2_SR.helpkey="Status Register"
2823
+ AT91C_TC2_SR.access=memorymapped
2824
+ AT91C_TC2_SR.address=0xFFFA00A0
2825
+ AT91C_TC2_SR.width=32
2826
+ AT91C_TC2_SR.byteEndian=little
2827
+ AT91C_TC2_SR.permission.write=none
2828
+ # ========== Register definition for TCB peripheral ==========
2829
+ AT91C_TCB_BMR.name="AT91C_TCB_BMR"
2830
+ AT91C_TCB_BMR.description="TC Block Mode Register"
2831
+ AT91C_TCB_BMR.helpkey="TC Block Mode Register"
2832
+ AT91C_TCB_BMR.access=memorymapped
2833
+ AT91C_TCB_BMR.address=0xFFFA00C4
2834
+ AT91C_TCB_BMR.width=32
2835
+ AT91C_TCB_BMR.byteEndian=little
2836
+ AT91C_TCB_BCR.name="AT91C_TCB_BCR"
2837
+ AT91C_TCB_BCR.description="TC Block Control Register"
2838
+ AT91C_TCB_BCR.helpkey="TC Block Control Register"
2839
+ AT91C_TCB_BCR.access=memorymapped
2840
+ AT91C_TCB_BCR.address=0xFFFA00C0
2841
+ AT91C_TCB_BCR.width=32
2842
+ AT91C_TCB_BCR.byteEndian=little
2843
+ AT91C_TCB_BCR.type=enum
2844
+ AT91C_TCB_BCR.enum.0.name=*** Write only ***
2845
+ AT91C_TCB_BCR.enum.1.name=Error
2846
+ # ========== Register definition for CAN_MB0 peripheral ==========
2847
+ AT91C_CAN_MB0_MDL.name="AT91C_CAN_MB0_MDL"
2848
+ AT91C_CAN_MB0_MDL.description="MailBox Data Low Register"
2849
+ AT91C_CAN_MB0_MDL.helpkey="MailBox Data Low Register"
2850
+ AT91C_CAN_MB0_MDL.access=memorymapped
2851
+ AT91C_CAN_MB0_MDL.address=0xFFFD0214
2852
+ AT91C_CAN_MB0_MDL.width=32
2853
+ AT91C_CAN_MB0_MDL.byteEndian=little
2854
+ AT91C_CAN_MB0_MAM.name="AT91C_CAN_MB0_MAM"
2855
+ AT91C_CAN_MB0_MAM.description="MailBox Acceptance Mask Register"
2856
+ AT91C_CAN_MB0_MAM.helpkey="MailBox Acceptance Mask Register"
2857
+ AT91C_CAN_MB0_MAM.access=memorymapped
2858
+ AT91C_CAN_MB0_MAM.address=0xFFFD0204
2859
+ AT91C_CAN_MB0_MAM.width=32
2860
+ AT91C_CAN_MB0_MAM.byteEndian=little
2861
+ AT91C_CAN_MB0_MCR.name="AT91C_CAN_MB0_MCR"
2862
+ AT91C_CAN_MB0_MCR.description="MailBox Control Register"
2863
+ AT91C_CAN_MB0_MCR.helpkey="MailBox Control Register"
2864
+ AT91C_CAN_MB0_MCR.access=memorymapped
2865
+ AT91C_CAN_MB0_MCR.address=0xFFFD021C
2866
+ AT91C_CAN_MB0_MCR.width=32
2867
+ AT91C_CAN_MB0_MCR.byteEndian=little
2868
+ AT91C_CAN_MB0_MCR.type=enum
2869
+ AT91C_CAN_MB0_MCR.enum.0.name=*** Write only ***
2870
+ AT91C_CAN_MB0_MCR.enum.1.name=Error
2871
+ AT91C_CAN_MB0_MID.name="AT91C_CAN_MB0_MID"
2872
+ AT91C_CAN_MB0_MID.description="MailBox ID Register"
2873
+ AT91C_CAN_MB0_MID.helpkey="MailBox ID Register"
2874
+ AT91C_CAN_MB0_MID.access=memorymapped
2875
+ AT91C_CAN_MB0_MID.address=0xFFFD0208
2876
+ AT91C_CAN_MB0_MID.width=32
2877
+ AT91C_CAN_MB0_MID.byteEndian=little
2878
+ AT91C_CAN_MB0_MSR.name="AT91C_CAN_MB0_MSR"
2879
+ AT91C_CAN_MB0_MSR.description="MailBox Status Register"
2880
+ AT91C_CAN_MB0_MSR.helpkey="MailBox Status Register"
2881
+ AT91C_CAN_MB0_MSR.access=memorymapped
2882
+ AT91C_CAN_MB0_MSR.address=0xFFFD0210
2883
+ AT91C_CAN_MB0_MSR.width=32
2884
+ AT91C_CAN_MB0_MSR.byteEndian=little
2885
+ AT91C_CAN_MB0_MSR.permission.write=none
2886
+ AT91C_CAN_MB0_MFID.name="AT91C_CAN_MB0_MFID"
2887
+ AT91C_CAN_MB0_MFID.description="MailBox Family ID Register"
2888
+ AT91C_CAN_MB0_MFID.helpkey="MailBox Family ID Register"
2889
+ AT91C_CAN_MB0_MFID.access=memorymapped
2890
+ AT91C_CAN_MB0_MFID.address=0xFFFD020C
2891
+ AT91C_CAN_MB0_MFID.width=32
2892
+ AT91C_CAN_MB0_MFID.byteEndian=little
2893
+ AT91C_CAN_MB0_MFID.permission.write=none
2894
+ AT91C_CAN_MB0_MDH.name="AT91C_CAN_MB0_MDH"
2895
+ AT91C_CAN_MB0_MDH.description="MailBox Data High Register"
2896
+ AT91C_CAN_MB0_MDH.helpkey="MailBox Data High Register"
2897
+ AT91C_CAN_MB0_MDH.access=memorymapped
2898
+ AT91C_CAN_MB0_MDH.address=0xFFFD0218
2899
+ AT91C_CAN_MB0_MDH.width=32
2900
+ AT91C_CAN_MB0_MDH.byteEndian=little
2901
+ AT91C_CAN_MB0_MMR.name="AT91C_CAN_MB0_MMR"
2902
+ AT91C_CAN_MB0_MMR.description="MailBox Mode Register"
2903
+ AT91C_CAN_MB0_MMR.helpkey="MailBox Mode Register"
2904
+ AT91C_CAN_MB0_MMR.access=memorymapped
2905
+ AT91C_CAN_MB0_MMR.address=0xFFFD0200
2906
+ AT91C_CAN_MB0_MMR.width=32
2907
+ AT91C_CAN_MB0_MMR.byteEndian=little
2908
+ # ========== Register definition for CAN_MB1 peripheral ==========
2909
+ AT91C_CAN_MB1_MDL.name="AT91C_CAN_MB1_MDL"
2910
+ AT91C_CAN_MB1_MDL.description="MailBox Data Low Register"
2911
+ AT91C_CAN_MB1_MDL.helpkey="MailBox Data Low Register"
2912
+ AT91C_CAN_MB1_MDL.access=memorymapped
2913
+ AT91C_CAN_MB1_MDL.address=0xFFFD0234
2914
+ AT91C_CAN_MB1_MDL.width=32
2915
+ AT91C_CAN_MB1_MDL.byteEndian=little
2916
+ AT91C_CAN_MB1_MID.name="AT91C_CAN_MB1_MID"
2917
+ AT91C_CAN_MB1_MID.description="MailBox ID Register"
2918
+ AT91C_CAN_MB1_MID.helpkey="MailBox ID Register"
2919
+ AT91C_CAN_MB1_MID.access=memorymapped
2920
+ AT91C_CAN_MB1_MID.address=0xFFFD0228
2921
+ AT91C_CAN_MB1_MID.width=32
2922
+ AT91C_CAN_MB1_MID.byteEndian=little
2923
+ AT91C_CAN_MB1_MMR.name="AT91C_CAN_MB1_MMR"
2924
+ AT91C_CAN_MB1_MMR.description="MailBox Mode Register"
2925
+ AT91C_CAN_MB1_MMR.helpkey="MailBox Mode Register"
2926
+ AT91C_CAN_MB1_MMR.access=memorymapped
2927
+ AT91C_CAN_MB1_MMR.address=0xFFFD0220
2928
+ AT91C_CAN_MB1_MMR.width=32
2929
+ AT91C_CAN_MB1_MMR.byteEndian=little
2930
+ AT91C_CAN_MB1_MSR.name="AT91C_CAN_MB1_MSR"
2931
+ AT91C_CAN_MB1_MSR.description="MailBox Status Register"
2932
+ AT91C_CAN_MB1_MSR.helpkey="MailBox Status Register"
2933
+ AT91C_CAN_MB1_MSR.access=memorymapped
2934
+ AT91C_CAN_MB1_MSR.address=0xFFFD0230
2935
+ AT91C_CAN_MB1_MSR.width=32
2936
+ AT91C_CAN_MB1_MSR.byteEndian=little
2937
+ AT91C_CAN_MB1_MSR.permission.write=none
2938
+ AT91C_CAN_MB1_MAM.name="AT91C_CAN_MB1_MAM"
2939
+ AT91C_CAN_MB1_MAM.description="MailBox Acceptance Mask Register"
2940
+ AT91C_CAN_MB1_MAM.helpkey="MailBox Acceptance Mask Register"
2941
+ AT91C_CAN_MB1_MAM.access=memorymapped
2942
+ AT91C_CAN_MB1_MAM.address=0xFFFD0224
2943
+ AT91C_CAN_MB1_MAM.width=32
2944
+ AT91C_CAN_MB1_MAM.byteEndian=little
2945
+ AT91C_CAN_MB1_MDH.name="AT91C_CAN_MB1_MDH"
2946
+ AT91C_CAN_MB1_MDH.description="MailBox Data High Register"
2947
+ AT91C_CAN_MB1_MDH.helpkey="MailBox Data High Register"
2948
+ AT91C_CAN_MB1_MDH.access=memorymapped
2949
+ AT91C_CAN_MB1_MDH.address=0xFFFD0238
2950
+ AT91C_CAN_MB1_MDH.width=32
2951
+ AT91C_CAN_MB1_MDH.byteEndian=little
2952
+ AT91C_CAN_MB1_MCR.name="AT91C_CAN_MB1_MCR"
2953
+ AT91C_CAN_MB1_MCR.description="MailBox Control Register"
2954
+ AT91C_CAN_MB1_MCR.helpkey="MailBox Control Register"
2955
+ AT91C_CAN_MB1_MCR.access=memorymapped
2956
+ AT91C_CAN_MB1_MCR.address=0xFFFD023C
2957
+ AT91C_CAN_MB1_MCR.width=32
2958
+ AT91C_CAN_MB1_MCR.byteEndian=little
2959
+ AT91C_CAN_MB1_MCR.type=enum
2960
+ AT91C_CAN_MB1_MCR.enum.0.name=*** Write only ***
2961
+ AT91C_CAN_MB1_MCR.enum.1.name=Error
2962
+ AT91C_CAN_MB1_MFID.name="AT91C_CAN_MB1_MFID"
2963
+ AT91C_CAN_MB1_MFID.description="MailBox Family ID Register"
2964
+ AT91C_CAN_MB1_MFID.helpkey="MailBox Family ID Register"
2965
+ AT91C_CAN_MB1_MFID.access=memorymapped
2966
+ AT91C_CAN_MB1_MFID.address=0xFFFD022C
2967
+ AT91C_CAN_MB1_MFID.width=32
2968
+ AT91C_CAN_MB1_MFID.byteEndian=little
2969
+ AT91C_CAN_MB1_MFID.permission.write=none
2970
+ # ========== Register definition for CAN_MB2 peripheral ==========
2971
+ AT91C_CAN_MB2_MCR.name="AT91C_CAN_MB2_MCR"
2972
+ AT91C_CAN_MB2_MCR.description="MailBox Control Register"
2973
+ AT91C_CAN_MB2_MCR.helpkey="MailBox Control Register"
2974
+ AT91C_CAN_MB2_MCR.access=memorymapped
2975
+ AT91C_CAN_MB2_MCR.address=0xFFFD025C
2976
+ AT91C_CAN_MB2_MCR.width=32
2977
+ AT91C_CAN_MB2_MCR.byteEndian=little
2978
+ AT91C_CAN_MB2_MCR.type=enum
2979
+ AT91C_CAN_MB2_MCR.enum.0.name=*** Write only ***
2980
+ AT91C_CAN_MB2_MCR.enum.1.name=Error
2981
+ AT91C_CAN_MB2_MDH.name="AT91C_CAN_MB2_MDH"
2982
+ AT91C_CAN_MB2_MDH.description="MailBox Data High Register"
2983
+ AT91C_CAN_MB2_MDH.helpkey="MailBox Data High Register"
2984
+ AT91C_CAN_MB2_MDH.access=memorymapped
2985
+ AT91C_CAN_MB2_MDH.address=0xFFFD0258
2986
+ AT91C_CAN_MB2_MDH.width=32
2987
+ AT91C_CAN_MB2_MDH.byteEndian=little
2988
+ AT91C_CAN_MB2_MID.name="AT91C_CAN_MB2_MID"
2989
+ AT91C_CAN_MB2_MID.description="MailBox ID Register"
2990
+ AT91C_CAN_MB2_MID.helpkey="MailBox ID Register"
2991
+ AT91C_CAN_MB2_MID.access=memorymapped
2992
+ AT91C_CAN_MB2_MID.address=0xFFFD0248
2993
+ AT91C_CAN_MB2_MID.width=32
2994
+ AT91C_CAN_MB2_MID.byteEndian=little
2995
+ AT91C_CAN_MB2_MDL.name="AT91C_CAN_MB2_MDL"
2996
+ AT91C_CAN_MB2_MDL.description="MailBox Data Low Register"
2997
+ AT91C_CAN_MB2_MDL.helpkey="MailBox Data Low Register"
2998
+ AT91C_CAN_MB2_MDL.access=memorymapped
2999
+ AT91C_CAN_MB2_MDL.address=0xFFFD0254
3000
+ AT91C_CAN_MB2_MDL.width=32
3001
+ AT91C_CAN_MB2_MDL.byteEndian=little
3002
+ AT91C_CAN_MB2_MMR.name="AT91C_CAN_MB2_MMR"
3003
+ AT91C_CAN_MB2_MMR.description="MailBox Mode Register"
3004
+ AT91C_CAN_MB2_MMR.helpkey="MailBox Mode Register"
3005
+ AT91C_CAN_MB2_MMR.access=memorymapped
3006
+ AT91C_CAN_MB2_MMR.address=0xFFFD0240
3007
+ AT91C_CAN_MB2_MMR.width=32
3008
+ AT91C_CAN_MB2_MMR.byteEndian=little
3009
+ AT91C_CAN_MB2_MAM.name="AT91C_CAN_MB2_MAM"
3010
+ AT91C_CAN_MB2_MAM.description="MailBox Acceptance Mask Register"
3011
+ AT91C_CAN_MB2_MAM.helpkey="MailBox Acceptance Mask Register"
3012
+ AT91C_CAN_MB2_MAM.access=memorymapped
3013
+ AT91C_CAN_MB2_MAM.address=0xFFFD0244
3014
+ AT91C_CAN_MB2_MAM.width=32
3015
+ AT91C_CAN_MB2_MAM.byteEndian=little
3016
+ AT91C_CAN_MB2_MFID.name="AT91C_CAN_MB2_MFID"
3017
+ AT91C_CAN_MB2_MFID.description="MailBox Family ID Register"
3018
+ AT91C_CAN_MB2_MFID.helpkey="MailBox Family ID Register"
3019
+ AT91C_CAN_MB2_MFID.access=memorymapped
3020
+ AT91C_CAN_MB2_MFID.address=0xFFFD024C
3021
+ AT91C_CAN_MB2_MFID.width=32
3022
+ AT91C_CAN_MB2_MFID.byteEndian=little
3023
+ AT91C_CAN_MB2_MFID.permission.write=none
3024
+ AT91C_CAN_MB2_MSR.name="AT91C_CAN_MB2_MSR"
3025
+ AT91C_CAN_MB2_MSR.description="MailBox Status Register"
3026
+ AT91C_CAN_MB2_MSR.helpkey="MailBox Status Register"
3027
+ AT91C_CAN_MB2_MSR.access=memorymapped
3028
+ AT91C_CAN_MB2_MSR.address=0xFFFD0250
3029
+ AT91C_CAN_MB2_MSR.width=32
3030
+ AT91C_CAN_MB2_MSR.byteEndian=little
3031
+ AT91C_CAN_MB2_MSR.permission.write=none
3032
+ # ========== Register definition for CAN_MB3 peripheral ==========
3033
+ AT91C_CAN_MB3_MFID.name="AT91C_CAN_MB3_MFID"
3034
+ AT91C_CAN_MB3_MFID.description="MailBox Family ID Register"
3035
+ AT91C_CAN_MB3_MFID.helpkey="MailBox Family ID Register"
3036
+ AT91C_CAN_MB3_MFID.access=memorymapped
3037
+ AT91C_CAN_MB3_MFID.address=0xFFFD026C
3038
+ AT91C_CAN_MB3_MFID.width=32
3039
+ AT91C_CAN_MB3_MFID.byteEndian=little
3040
+ AT91C_CAN_MB3_MFID.permission.write=none
3041
+ AT91C_CAN_MB3_MAM.name="AT91C_CAN_MB3_MAM"
3042
+ AT91C_CAN_MB3_MAM.description="MailBox Acceptance Mask Register"
3043
+ AT91C_CAN_MB3_MAM.helpkey="MailBox Acceptance Mask Register"
3044
+ AT91C_CAN_MB3_MAM.access=memorymapped
3045
+ AT91C_CAN_MB3_MAM.address=0xFFFD0264
3046
+ AT91C_CAN_MB3_MAM.width=32
3047
+ AT91C_CAN_MB3_MAM.byteEndian=little
3048
+ AT91C_CAN_MB3_MID.name="AT91C_CAN_MB3_MID"
3049
+ AT91C_CAN_MB3_MID.description="MailBox ID Register"
3050
+ AT91C_CAN_MB3_MID.helpkey="MailBox ID Register"
3051
+ AT91C_CAN_MB3_MID.access=memorymapped
3052
+ AT91C_CAN_MB3_MID.address=0xFFFD0268
3053
+ AT91C_CAN_MB3_MID.width=32
3054
+ AT91C_CAN_MB3_MID.byteEndian=little
3055
+ AT91C_CAN_MB3_MCR.name="AT91C_CAN_MB3_MCR"
3056
+ AT91C_CAN_MB3_MCR.description="MailBox Control Register"
3057
+ AT91C_CAN_MB3_MCR.helpkey="MailBox Control Register"
3058
+ AT91C_CAN_MB3_MCR.access=memorymapped
3059
+ AT91C_CAN_MB3_MCR.address=0xFFFD027C
3060
+ AT91C_CAN_MB3_MCR.width=32
3061
+ AT91C_CAN_MB3_MCR.byteEndian=little
3062
+ AT91C_CAN_MB3_MCR.type=enum
3063
+ AT91C_CAN_MB3_MCR.enum.0.name=*** Write only ***
3064
+ AT91C_CAN_MB3_MCR.enum.1.name=Error
3065
+ AT91C_CAN_MB3_MMR.name="AT91C_CAN_MB3_MMR"
3066
+ AT91C_CAN_MB3_MMR.description="MailBox Mode Register"
3067
+ AT91C_CAN_MB3_MMR.helpkey="MailBox Mode Register"
3068
+ AT91C_CAN_MB3_MMR.access=memorymapped
3069
+ AT91C_CAN_MB3_MMR.address=0xFFFD0260
3070
+ AT91C_CAN_MB3_MMR.width=32
3071
+ AT91C_CAN_MB3_MMR.byteEndian=little
3072
+ AT91C_CAN_MB3_MSR.name="AT91C_CAN_MB3_MSR"
3073
+ AT91C_CAN_MB3_MSR.description="MailBox Status Register"
3074
+ AT91C_CAN_MB3_MSR.helpkey="MailBox Status Register"
3075
+ AT91C_CAN_MB3_MSR.access=memorymapped
3076
+ AT91C_CAN_MB3_MSR.address=0xFFFD0270
3077
+ AT91C_CAN_MB3_MSR.width=32
3078
+ AT91C_CAN_MB3_MSR.byteEndian=little
3079
+ AT91C_CAN_MB3_MSR.permission.write=none
3080
+ AT91C_CAN_MB3_MDL.name="AT91C_CAN_MB3_MDL"
3081
+ AT91C_CAN_MB3_MDL.description="MailBox Data Low Register"
3082
+ AT91C_CAN_MB3_MDL.helpkey="MailBox Data Low Register"
3083
+ AT91C_CAN_MB3_MDL.access=memorymapped
3084
+ AT91C_CAN_MB3_MDL.address=0xFFFD0274
3085
+ AT91C_CAN_MB3_MDL.width=32
3086
+ AT91C_CAN_MB3_MDL.byteEndian=little
3087
+ AT91C_CAN_MB3_MDH.name="AT91C_CAN_MB3_MDH"
3088
+ AT91C_CAN_MB3_MDH.description="MailBox Data High Register"
3089
+ AT91C_CAN_MB3_MDH.helpkey="MailBox Data High Register"
3090
+ AT91C_CAN_MB3_MDH.access=memorymapped
3091
+ AT91C_CAN_MB3_MDH.address=0xFFFD0278
3092
+ AT91C_CAN_MB3_MDH.width=32
3093
+ AT91C_CAN_MB3_MDH.byteEndian=little
3094
+ # ========== Register definition for CAN_MB4 peripheral ==========
3095
+ AT91C_CAN_MB4_MID.name="AT91C_CAN_MB4_MID"
3096
+ AT91C_CAN_MB4_MID.description="MailBox ID Register"
3097
+ AT91C_CAN_MB4_MID.helpkey="MailBox ID Register"
3098
+ AT91C_CAN_MB4_MID.access=memorymapped
3099
+ AT91C_CAN_MB4_MID.address=0xFFFD0288
3100
+ AT91C_CAN_MB4_MID.width=32
3101
+ AT91C_CAN_MB4_MID.byteEndian=little
3102
+ AT91C_CAN_MB4_MMR.name="AT91C_CAN_MB4_MMR"
3103
+ AT91C_CAN_MB4_MMR.description="MailBox Mode Register"
3104
+ AT91C_CAN_MB4_MMR.helpkey="MailBox Mode Register"
3105
+ AT91C_CAN_MB4_MMR.access=memorymapped
3106
+ AT91C_CAN_MB4_MMR.address=0xFFFD0280
3107
+ AT91C_CAN_MB4_MMR.width=32
3108
+ AT91C_CAN_MB4_MMR.byteEndian=little
3109
+ AT91C_CAN_MB4_MDH.name="AT91C_CAN_MB4_MDH"
3110
+ AT91C_CAN_MB4_MDH.description="MailBox Data High Register"
3111
+ AT91C_CAN_MB4_MDH.helpkey="MailBox Data High Register"
3112
+ AT91C_CAN_MB4_MDH.access=memorymapped
3113
+ AT91C_CAN_MB4_MDH.address=0xFFFD0298
3114
+ AT91C_CAN_MB4_MDH.width=32
3115
+ AT91C_CAN_MB4_MDH.byteEndian=little
3116
+ AT91C_CAN_MB4_MFID.name="AT91C_CAN_MB4_MFID"
3117
+ AT91C_CAN_MB4_MFID.description="MailBox Family ID Register"
3118
+ AT91C_CAN_MB4_MFID.helpkey="MailBox Family ID Register"
3119
+ AT91C_CAN_MB4_MFID.access=memorymapped
3120
+ AT91C_CAN_MB4_MFID.address=0xFFFD028C
3121
+ AT91C_CAN_MB4_MFID.width=32
3122
+ AT91C_CAN_MB4_MFID.byteEndian=little
3123
+ AT91C_CAN_MB4_MFID.permission.write=none
3124
+ AT91C_CAN_MB4_MSR.name="AT91C_CAN_MB4_MSR"
3125
+ AT91C_CAN_MB4_MSR.description="MailBox Status Register"
3126
+ AT91C_CAN_MB4_MSR.helpkey="MailBox Status Register"
3127
+ AT91C_CAN_MB4_MSR.access=memorymapped
3128
+ AT91C_CAN_MB4_MSR.address=0xFFFD0290
3129
+ AT91C_CAN_MB4_MSR.width=32
3130
+ AT91C_CAN_MB4_MSR.byteEndian=little
3131
+ AT91C_CAN_MB4_MSR.permission.write=none
3132
+ AT91C_CAN_MB4_MCR.name="AT91C_CAN_MB4_MCR"
3133
+ AT91C_CAN_MB4_MCR.description="MailBox Control Register"
3134
+ AT91C_CAN_MB4_MCR.helpkey="MailBox Control Register"
3135
+ AT91C_CAN_MB4_MCR.access=memorymapped
3136
+ AT91C_CAN_MB4_MCR.address=0xFFFD029C
3137
+ AT91C_CAN_MB4_MCR.width=32
3138
+ AT91C_CAN_MB4_MCR.byteEndian=little
3139
+ AT91C_CAN_MB4_MCR.type=enum
3140
+ AT91C_CAN_MB4_MCR.enum.0.name=*** Write only ***
3141
+ AT91C_CAN_MB4_MCR.enum.1.name=Error
3142
+ AT91C_CAN_MB4_MDL.name="AT91C_CAN_MB4_MDL"
3143
+ AT91C_CAN_MB4_MDL.description="MailBox Data Low Register"
3144
+ AT91C_CAN_MB4_MDL.helpkey="MailBox Data Low Register"
3145
+ AT91C_CAN_MB4_MDL.access=memorymapped
3146
+ AT91C_CAN_MB4_MDL.address=0xFFFD0294
3147
+ AT91C_CAN_MB4_MDL.width=32
3148
+ AT91C_CAN_MB4_MDL.byteEndian=little
3149
+ AT91C_CAN_MB4_MAM.name="AT91C_CAN_MB4_MAM"
3150
+ AT91C_CAN_MB4_MAM.description="MailBox Acceptance Mask Register"
3151
+ AT91C_CAN_MB4_MAM.helpkey="MailBox Acceptance Mask Register"
3152
+ AT91C_CAN_MB4_MAM.access=memorymapped
3153
+ AT91C_CAN_MB4_MAM.address=0xFFFD0284
3154
+ AT91C_CAN_MB4_MAM.width=32
3155
+ AT91C_CAN_MB4_MAM.byteEndian=little
3156
+ # ========== Register definition for CAN_MB5 peripheral ==========
3157
+ AT91C_CAN_MB5_MSR.name="AT91C_CAN_MB5_MSR"
3158
+ AT91C_CAN_MB5_MSR.description="MailBox Status Register"
3159
+ AT91C_CAN_MB5_MSR.helpkey="MailBox Status Register"
3160
+ AT91C_CAN_MB5_MSR.access=memorymapped
3161
+ AT91C_CAN_MB5_MSR.address=0xFFFD02B0
3162
+ AT91C_CAN_MB5_MSR.width=32
3163
+ AT91C_CAN_MB5_MSR.byteEndian=little
3164
+ AT91C_CAN_MB5_MSR.permission.write=none
3165
+ AT91C_CAN_MB5_MCR.name="AT91C_CAN_MB5_MCR"
3166
+ AT91C_CAN_MB5_MCR.description="MailBox Control Register"
3167
+ AT91C_CAN_MB5_MCR.helpkey="MailBox Control Register"
3168
+ AT91C_CAN_MB5_MCR.access=memorymapped
3169
+ AT91C_CAN_MB5_MCR.address=0xFFFD02BC
3170
+ AT91C_CAN_MB5_MCR.width=32
3171
+ AT91C_CAN_MB5_MCR.byteEndian=little
3172
+ AT91C_CAN_MB5_MCR.type=enum
3173
+ AT91C_CAN_MB5_MCR.enum.0.name=*** Write only ***
3174
+ AT91C_CAN_MB5_MCR.enum.1.name=Error
3175
+ AT91C_CAN_MB5_MFID.name="AT91C_CAN_MB5_MFID"
3176
+ AT91C_CAN_MB5_MFID.description="MailBox Family ID Register"
3177
+ AT91C_CAN_MB5_MFID.helpkey="MailBox Family ID Register"
3178
+ AT91C_CAN_MB5_MFID.access=memorymapped
3179
+ AT91C_CAN_MB5_MFID.address=0xFFFD02AC
3180
+ AT91C_CAN_MB5_MFID.width=32
3181
+ AT91C_CAN_MB5_MFID.byteEndian=little
3182
+ AT91C_CAN_MB5_MFID.permission.write=none
3183
+ AT91C_CAN_MB5_MDH.name="AT91C_CAN_MB5_MDH"
3184
+ AT91C_CAN_MB5_MDH.description="MailBox Data High Register"
3185
+ AT91C_CAN_MB5_MDH.helpkey="MailBox Data High Register"
3186
+ AT91C_CAN_MB5_MDH.access=memorymapped
3187
+ AT91C_CAN_MB5_MDH.address=0xFFFD02B8
3188
+ AT91C_CAN_MB5_MDH.width=32
3189
+ AT91C_CAN_MB5_MDH.byteEndian=little
3190
+ AT91C_CAN_MB5_MID.name="AT91C_CAN_MB5_MID"
3191
+ AT91C_CAN_MB5_MID.description="MailBox ID Register"
3192
+ AT91C_CAN_MB5_MID.helpkey="MailBox ID Register"
3193
+ AT91C_CAN_MB5_MID.access=memorymapped
3194
+ AT91C_CAN_MB5_MID.address=0xFFFD02A8
3195
+ AT91C_CAN_MB5_MID.width=32
3196
+ AT91C_CAN_MB5_MID.byteEndian=little
3197
+ AT91C_CAN_MB5_MMR.name="AT91C_CAN_MB5_MMR"
3198
+ AT91C_CAN_MB5_MMR.description="MailBox Mode Register"
3199
+ AT91C_CAN_MB5_MMR.helpkey="MailBox Mode Register"
3200
+ AT91C_CAN_MB5_MMR.access=memorymapped
3201
+ AT91C_CAN_MB5_MMR.address=0xFFFD02A0
3202
+ AT91C_CAN_MB5_MMR.width=32
3203
+ AT91C_CAN_MB5_MMR.byteEndian=little
3204
+ AT91C_CAN_MB5_MDL.name="AT91C_CAN_MB5_MDL"
3205
+ AT91C_CAN_MB5_MDL.description="MailBox Data Low Register"
3206
+ AT91C_CAN_MB5_MDL.helpkey="MailBox Data Low Register"
3207
+ AT91C_CAN_MB5_MDL.access=memorymapped
3208
+ AT91C_CAN_MB5_MDL.address=0xFFFD02B4
3209
+ AT91C_CAN_MB5_MDL.width=32
3210
+ AT91C_CAN_MB5_MDL.byteEndian=little
3211
+ AT91C_CAN_MB5_MAM.name="AT91C_CAN_MB5_MAM"
3212
+ AT91C_CAN_MB5_MAM.description="MailBox Acceptance Mask Register"
3213
+ AT91C_CAN_MB5_MAM.helpkey="MailBox Acceptance Mask Register"
3214
+ AT91C_CAN_MB5_MAM.access=memorymapped
3215
+ AT91C_CAN_MB5_MAM.address=0xFFFD02A4
3216
+ AT91C_CAN_MB5_MAM.width=32
3217
+ AT91C_CAN_MB5_MAM.byteEndian=little
3218
+ # ========== Register definition for CAN_MB6 peripheral ==========
3219
+ AT91C_CAN_MB6_MFID.name="AT91C_CAN_MB6_MFID"
3220
+ AT91C_CAN_MB6_MFID.description="MailBox Family ID Register"
3221
+ AT91C_CAN_MB6_MFID.helpkey="MailBox Family ID Register"
3222
+ AT91C_CAN_MB6_MFID.access=memorymapped
3223
+ AT91C_CAN_MB6_MFID.address=0xFFFD02CC
3224
+ AT91C_CAN_MB6_MFID.width=32
3225
+ AT91C_CAN_MB6_MFID.byteEndian=little
3226
+ AT91C_CAN_MB6_MFID.permission.write=none
3227
+ AT91C_CAN_MB6_MID.name="AT91C_CAN_MB6_MID"
3228
+ AT91C_CAN_MB6_MID.description="MailBox ID Register"
3229
+ AT91C_CAN_MB6_MID.helpkey="MailBox ID Register"
3230
+ AT91C_CAN_MB6_MID.access=memorymapped
3231
+ AT91C_CAN_MB6_MID.address=0xFFFD02C8
3232
+ AT91C_CAN_MB6_MID.width=32
3233
+ AT91C_CAN_MB6_MID.byteEndian=little
3234
+ AT91C_CAN_MB6_MAM.name="AT91C_CAN_MB6_MAM"
3235
+ AT91C_CAN_MB6_MAM.description="MailBox Acceptance Mask Register"
3236
+ AT91C_CAN_MB6_MAM.helpkey="MailBox Acceptance Mask Register"
3237
+ AT91C_CAN_MB6_MAM.access=memorymapped
3238
+ AT91C_CAN_MB6_MAM.address=0xFFFD02C4
3239
+ AT91C_CAN_MB6_MAM.width=32
3240
+ AT91C_CAN_MB6_MAM.byteEndian=little
3241
+ AT91C_CAN_MB6_MSR.name="AT91C_CAN_MB6_MSR"
3242
+ AT91C_CAN_MB6_MSR.description="MailBox Status Register"
3243
+ AT91C_CAN_MB6_MSR.helpkey="MailBox Status Register"
3244
+ AT91C_CAN_MB6_MSR.access=memorymapped
3245
+ AT91C_CAN_MB6_MSR.address=0xFFFD02D0
3246
+ AT91C_CAN_MB6_MSR.width=32
3247
+ AT91C_CAN_MB6_MSR.byteEndian=little
3248
+ AT91C_CAN_MB6_MSR.permission.write=none
3249
+ AT91C_CAN_MB6_MDL.name="AT91C_CAN_MB6_MDL"
3250
+ AT91C_CAN_MB6_MDL.description="MailBox Data Low Register"
3251
+ AT91C_CAN_MB6_MDL.helpkey="MailBox Data Low Register"
3252
+ AT91C_CAN_MB6_MDL.access=memorymapped
3253
+ AT91C_CAN_MB6_MDL.address=0xFFFD02D4
3254
+ AT91C_CAN_MB6_MDL.width=32
3255
+ AT91C_CAN_MB6_MDL.byteEndian=little
3256
+ AT91C_CAN_MB6_MCR.name="AT91C_CAN_MB6_MCR"
3257
+ AT91C_CAN_MB6_MCR.description="MailBox Control Register"
3258
+ AT91C_CAN_MB6_MCR.helpkey="MailBox Control Register"
3259
+ AT91C_CAN_MB6_MCR.access=memorymapped
3260
+ AT91C_CAN_MB6_MCR.address=0xFFFD02DC
3261
+ AT91C_CAN_MB6_MCR.width=32
3262
+ AT91C_CAN_MB6_MCR.byteEndian=little
3263
+ AT91C_CAN_MB6_MCR.type=enum
3264
+ AT91C_CAN_MB6_MCR.enum.0.name=*** Write only ***
3265
+ AT91C_CAN_MB6_MCR.enum.1.name=Error
3266
+ AT91C_CAN_MB6_MDH.name="AT91C_CAN_MB6_MDH"
3267
+ AT91C_CAN_MB6_MDH.description="MailBox Data High Register"
3268
+ AT91C_CAN_MB6_MDH.helpkey="MailBox Data High Register"
3269
+ AT91C_CAN_MB6_MDH.access=memorymapped
3270
+ AT91C_CAN_MB6_MDH.address=0xFFFD02D8
3271
+ AT91C_CAN_MB6_MDH.width=32
3272
+ AT91C_CAN_MB6_MDH.byteEndian=little
3273
+ AT91C_CAN_MB6_MMR.name="AT91C_CAN_MB6_MMR"
3274
+ AT91C_CAN_MB6_MMR.description="MailBox Mode Register"
3275
+ AT91C_CAN_MB6_MMR.helpkey="MailBox Mode Register"
3276
+ AT91C_CAN_MB6_MMR.access=memorymapped
3277
+ AT91C_CAN_MB6_MMR.address=0xFFFD02C0
3278
+ AT91C_CAN_MB6_MMR.width=32
3279
+ AT91C_CAN_MB6_MMR.byteEndian=little
3280
+ # ========== Register definition for CAN_MB7 peripheral ==========
3281
+ AT91C_CAN_MB7_MCR.name="AT91C_CAN_MB7_MCR"
3282
+ AT91C_CAN_MB7_MCR.description="MailBox Control Register"
3283
+ AT91C_CAN_MB7_MCR.helpkey="MailBox Control Register"
3284
+ AT91C_CAN_MB7_MCR.access=memorymapped
3285
+ AT91C_CAN_MB7_MCR.address=0xFFFD02FC
3286
+ AT91C_CAN_MB7_MCR.width=32
3287
+ AT91C_CAN_MB7_MCR.byteEndian=little
3288
+ AT91C_CAN_MB7_MCR.type=enum
3289
+ AT91C_CAN_MB7_MCR.enum.0.name=*** Write only ***
3290
+ AT91C_CAN_MB7_MCR.enum.1.name=Error
3291
+ AT91C_CAN_MB7_MDH.name="AT91C_CAN_MB7_MDH"
3292
+ AT91C_CAN_MB7_MDH.description="MailBox Data High Register"
3293
+ AT91C_CAN_MB7_MDH.helpkey="MailBox Data High Register"
3294
+ AT91C_CAN_MB7_MDH.access=memorymapped
3295
+ AT91C_CAN_MB7_MDH.address=0xFFFD02F8
3296
+ AT91C_CAN_MB7_MDH.width=32
3297
+ AT91C_CAN_MB7_MDH.byteEndian=little
3298
+ AT91C_CAN_MB7_MFID.name="AT91C_CAN_MB7_MFID"
3299
+ AT91C_CAN_MB7_MFID.description="MailBox Family ID Register"
3300
+ AT91C_CAN_MB7_MFID.helpkey="MailBox Family ID Register"
3301
+ AT91C_CAN_MB7_MFID.access=memorymapped
3302
+ AT91C_CAN_MB7_MFID.address=0xFFFD02EC
3303
+ AT91C_CAN_MB7_MFID.width=32
3304
+ AT91C_CAN_MB7_MFID.byteEndian=little
3305
+ AT91C_CAN_MB7_MFID.permission.write=none
3306
+ AT91C_CAN_MB7_MDL.name="AT91C_CAN_MB7_MDL"
3307
+ AT91C_CAN_MB7_MDL.description="MailBox Data Low Register"
3308
+ AT91C_CAN_MB7_MDL.helpkey="MailBox Data Low Register"
3309
+ AT91C_CAN_MB7_MDL.access=memorymapped
3310
+ AT91C_CAN_MB7_MDL.address=0xFFFD02F4
3311
+ AT91C_CAN_MB7_MDL.width=32
3312
+ AT91C_CAN_MB7_MDL.byteEndian=little
3313
+ AT91C_CAN_MB7_MID.name="AT91C_CAN_MB7_MID"
3314
+ AT91C_CAN_MB7_MID.description="MailBox ID Register"
3315
+ AT91C_CAN_MB7_MID.helpkey="MailBox ID Register"
3316
+ AT91C_CAN_MB7_MID.access=memorymapped
3317
+ AT91C_CAN_MB7_MID.address=0xFFFD02E8
3318
+ AT91C_CAN_MB7_MID.width=32
3319
+ AT91C_CAN_MB7_MID.byteEndian=little
3320
+ AT91C_CAN_MB7_MMR.name="AT91C_CAN_MB7_MMR"
3321
+ AT91C_CAN_MB7_MMR.description="MailBox Mode Register"
3322
+ AT91C_CAN_MB7_MMR.helpkey="MailBox Mode Register"
3323
+ AT91C_CAN_MB7_MMR.access=memorymapped
3324
+ AT91C_CAN_MB7_MMR.address=0xFFFD02E0
3325
+ AT91C_CAN_MB7_MMR.width=32
3326
+ AT91C_CAN_MB7_MMR.byteEndian=little
3327
+ AT91C_CAN_MB7_MAM.name="AT91C_CAN_MB7_MAM"
3328
+ AT91C_CAN_MB7_MAM.description="MailBox Acceptance Mask Register"
3329
+ AT91C_CAN_MB7_MAM.helpkey="MailBox Acceptance Mask Register"
3330
+ AT91C_CAN_MB7_MAM.access=memorymapped
3331
+ AT91C_CAN_MB7_MAM.address=0xFFFD02E4
3332
+ AT91C_CAN_MB7_MAM.width=32
3333
+ AT91C_CAN_MB7_MAM.byteEndian=little
3334
+ AT91C_CAN_MB7_MSR.name="AT91C_CAN_MB7_MSR"
3335
+ AT91C_CAN_MB7_MSR.description="MailBox Status Register"
3336
+ AT91C_CAN_MB7_MSR.helpkey="MailBox Status Register"
3337
+ AT91C_CAN_MB7_MSR.access=memorymapped
3338
+ AT91C_CAN_MB7_MSR.address=0xFFFD02F0
3339
+ AT91C_CAN_MB7_MSR.width=32
3340
+ AT91C_CAN_MB7_MSR.byteEndian=little
3341
+ AT91C_CAN_MB7_MSR.permission.write=none
3342
+ # ========== Register definition for CAN peripheral ==========
3343
+ AT91C_CAN_TCR.name="AT91C_CAN_TCR"
3344
+ AT91C_CAN_TCR.description="Transfer Command Register"
3345
+ AT91C_CAN_TCR.helpkey="Transfer Command Register"
3346
+ AT91C_CAN_TCR.access=memorymapped
3347
+ AT91C_CAN_TCR.address=0xFFFD0024
3348
+ AT91C_CAN_TCR.width=32
3349
+ AT91C_CAN_TCR.byteEndian=little
3350
+ AT91C_CAN_TCR.type=enum
3351
+ AT91C_CAN_TCR.enum.0.name=*** Write only ***
3352
+ AT91C_CAN_TCR.enum.1.name=Error
3353
+ AT91C_CAN_IMR.name="AT91C_CAN_IMR"
3354
+ AT91C_CAN_IMR.description="Interrupt Mask Register"
3355
+ AT91C_CAN_IMR.helpkey="Interrupt Mask Register"
3356
+ AT91C_CAN_IMR.access=memorymapped
3357
+ AT91C_CAN_IMR.address=0xFFFD000C
3358
+ AT91C_CAN_IMR.width=32
3359
+ AT91C_CAN_IMR.byteEndian=little
3360
+ AT91C_CAN_IMR.permission.write=none
3361
+ AT91C_CAN_IER.name="AT91C_CAN_IER"
3362
+ AT91C_CAN_IER.description="Interrupt Enable Register"
3363
+ AT91C_CAN_IER.helpkey="Interrupt Enable Register"
3364
+ AT91C_CAN_IER.access=memorymapped
3365
+ AT91C_CAN_IER.address=0xFFFD0004
3366
+ AT91C_CAN_IER.width=32
3367
+ AT91C_CAN_IER.byteEndian=little
3368
+ AT91C_CAN_IER.type=enum
3369
+ AT91C_CAN_IER.enum.0.name=*** Write only ***
3370
+ AT91C_CAN_IER.enum.1.name=Error
3371
+ AT91C_CAN_ECR.name="AT91C_CAN_ECR"
3372
+ AT91C_CAN_ECR.description="Error Counter Register"
3373
+ AT91C_CAN_ECR.helpkey="Error Counter Register"
3374
+ AT91C_CAN_ECR.access=memorymapped
3375
+ AT91C_CAN_ECR.address=0xFFFD0020
3376
+ AT91C_CAN_ECR.width=32
3377
+ AT91C_CAN_ECR.byteEndian=little
3378
+ AT91C_CAN_ECR.permission.write=none
3379
+ AT91C_CAN_TIMESTP.name="AT91C_CAN_TIMESTP"
3380
+ AT91C_CAN_TIMESTP.description="Time Stamp Register"
3381
+ AT91C_CAN_TIMESTP.helpkey="Time Stamp Register"
3382
+ AT91C_CAN_TIMESTP.access=memorymapped
3383
+ AT91C_CAN_TIMESTP.address=0xFFFD001C
3384
+ AT91C_CAN_TIMESTP.width=32
3385
+ AT91C_CAN_TIMESTP.byteEndian=little
3386
+ AT91C_CAN_TIMESTP.permission.write=none
3387
+ AT91C_CAN_MR.name="AT91C_CAN_MR"
3388
+ AT91C_CAN_MR.description="Mode Register"
3389
+ AT91C_CAN_MR.helpkey="Mode Register"
3390
+ AT91C_CAN_MR.access=memorymapped
3391
+ AT91C_CAN_MR.address=0xFFFD0000
3392
+ AT91C_CAN_MR.width=32
3393
+ AT91C_CAN_MR.byteEndian=little
3394
+ AT91C_CAN_IDR.name="AT91C_CAN_IDR"
3395
+ AT91C_CAN_IDR.description="Interrupt Disable Register"
3396
+ AT91C_CAN_IDR.helpkey="Interrupt Disable Register"
3397
+ AT91C_CAN_IDR.access=memorymapped
3398
+ AT91C_CAN_IDR.address=0xFFFD0008
3399
+ AT91C_CAN_IDR.width=32
3400
+ AT91C_CAN_IDR.byteEndian=little
3401
+ AT91C_CAN_IDR.type=enum
3402
+ AT91C_CAN_IDR.enum.0.name=*** Write only ***
3403
+ AT91C_CAN_IDR.enum.1.name=Error
3404
+ AT91C_CAN_ACR.name="AT91C_CAN_ACR"
3405
+ AT91C_CAN_ACR.description="Abort Command Register"
3406
+ AT91C_CAN_ACR.helpkey="Abort Command Register"
3407
+ AT91C_CAN_ACR.access=memorymapped
3408
+ AT91C_CAN_ACR.address=0xFFFD0028
3409
+ AT91C_CAN_ACR.width=32
3410
+ AT91C_CAN_ACR.byteEndian=little
3411
+ AT91C_CAN_ACR.type=enum
3412
+ AT91C_CAN_ACR.enum.0.name=*** Write only ***
3413
+ AT91C_CAN_ACR.enum.1.name=Error
3414
+ AT91C_CAN_TIM.name="AT91C_CAN_TIM"
3415
+ AT91C_CAN_TIM.description="Timer Register"
3416
+ AT91C_CAN_TIM.helpkey="Timer Register"
3417
+ AT91C_CAN_TIM.access=memorymapped
3418
+ AT91C_CAN_TIM.address=0xFFFD0018
3419
+ AT91C_CAN_TIM.width=32
3420
+ AT91C_CAN_TIM.byteEndian=little
3421
+ AT91C_CAN_TIM.permission.write=none
3422
+ AT91C_CAN_SR.name="AT91C_CAN_SR"
3423
+ AT91C_CAN_SR.description="Status Register"
3424
+ AT91C_CAN_SR.helpkey="Status Register"
3425
+ AT91C_CAN_SR.access=memorymapped
3426
+ AT91C_CAN_SR.address=0xFFFD0010
3427
+ AT91C_CAN_SR.width=32
3428
+ AT91C_CAN_SR.byteEndian=little
3429
+ AT91C_CAN_SR.permission.write=none
3430
+ AT91C_CAN_BR.name="AT91C_CAN_BR"
3431
+ AT91C_CAN_BR.description="Baudrate Register"
3432
+ AT91C_CAN_BR.helpkey="Baudrate Register"
3433
+ AT91C_CAN_BR.access=memorymapped
3434
+ AT91C_CAN_BR.address=0xFFFD0014
3435
+ AT91C_CAN_BR.width=32
3436
+ AT91C_CAN_BR.byteEndian=little
3437
+ AT91C_CAN_VR.name="AT91C_CAN_VR"
3438
+ AT91C_CAN_VR.description="Version Register"
3439
+ AT91C_CAN_VR.helpkey="Version Register"
3440
+ AT91C_CAN_VR.access=memorymapped
3441
+ AT91C_CAN_VR.address=0xFFFD00FC
3442
+ AT91C_CAN_VR.width=32
3443
+ AT91C_CAN_VR.byteEndian=little
3444
+ AT91C_CAN_VR.permission.write=none
3445
+ # ========== Register definition for EMAC peripheral ==========
3446
+ AT91C_EMAC_ISR.name="AT91C_EMAC_ISR"
3447
+ AT91C_EMAC_ISR.description="Interrupt Status Register"
3448
+ AT91C_EMAC_ISR.helpkey="Interrupt Status Register"
3449
+ AT91C_EMAC_ISR.access=memorymapped
3450
+ AT91C_EMAC_ISR.address=0xFFFDC024
3451
+ AT91C_EMAC_ISR.width=32
3452
+ AT91C_EMAC_ISR.byteEndian=little
3453
+ AT91C_EMAC_SA4H.name="AT91C_EMAC_SA4H"
3454
+ AT91C_EMAC_SA4H.description="Specific Address 4 Top, Last 2 bytes"
3455
+ AT91C_EMAC_SA4H.helpkey="Specific Address 4 Top, Last 2 bytes"
3456
+ AT91C_EMAC_SA4H.access=memorymapped
3457
+ AT91C_EMAC_SA4H.address=0xFFFDC0B4
3458
+ AT91C_EMAC_SA4H.width=32
3459
+ AT91C_EMAC_SA4H.byteEndian=little
3460
+ AT91C_EMAC_SA1L.name="AT91C_EMAC_SA1L"
3461
+ AT91C_EMAC_SA1L.description="Specific Address 1 Bottom, First 4 bytes"
3462
+ AT91C_EMAC_SA1L.helpkey="Specific Address 1 Bottom, First 4 bytes"
3463
+ AT91C_EMAC_SA1L.access=memorymapped
3464
+ AT91C_EMAC_SA1L.address=0xFFFDC098
3465
+ AT91C_EMAC_SA1L.width=32
3466
+ AT91C_EMAC_SA1L.byteEndian=little
3467
+ AT91C_EMAC_ELE.name="AT91C_EMAC_ELE"
3468
+ AT91C_EMAC_ELE.description="Excessive Length Errors Register"
3469
+ AT91C_EMAC_ELE.helpkey="Excessive Length Errors Register"
3470
+ AT91C_EMAC_ELE.access=memorymapped
3471
+ AT91C_EMAC_ELE.address=0xFFFDC078
3472
+ AT91C_EMAC_ELE.width=32
3473
+ AT91C_EMAC_ELE.byteEndian=little
3474
+ AT91C_EMAC_LCOL.name="AT91C_EMAC_LCOL"
3475
+ AT91C_EMAC_LCOL.description="Late Collision Register"
3476
+ AT91C_EMAC_LCOL.helpkey="Late Collision Register"
3477
+ AT91C_EMAC_LCOL.access=memorymapped
3478
+ AT91C_EMAC_LCOL.address=0xFFFDC05C
3479
+ AT91C_EMAC_LCOL.width=32
3480
+ AT91C_EMAC_LCOL.byteEndian=little
3481
+ AT91C_EMAC_RLE.name="AT91C_EMAC_RLE"
3482
+ AT91C_EMAC_RLE.description="Receive Length Field Mismatch Register"
3483
+ AT91C_EMAC_RLE.helpkey="Receive Length Field Mismatch Register"
3484
+ AT91C_EMAC_RLE.access=memorymapped
3485
+ AT91C_EMAC_RLE.address=0xFFFDC088
3486
+ AT91C_EMAC_RLE.width=32
3487
+ AT91C_EMAC_RLE.byteEndian=little
3488
+ AT91C_EMAC_WOL.name="AT91C_EMAC_WOL"
3489
+ AT91C_EMAC_WOL.description="Wake On LAN Register"
3490
+ AT91C_EMAC_WOL.helpkey="Wake On LAN Register"
3491
+ AT91C_EMAC_WOL.access=memorymapped
3492
+ AT91C_EMAC_WOL.address=0xFFFDC0C4
3493
+ AT91C_EMAC_WOL.width=32
3494
+ AT91C_EMAC_WOL.byteEndian=little
3495
+ AT91C_EMAC_DTF.name="AT91C_EMAC_DTF"
3496
+ AT91C_EMAC_DTF.description="Deferred Transmission Frame Register"
3497
+ AT91C_EMAC_DTF.helpkey="Deferred Transmission Frame Register"
3498
+ AT91C_EMAC_DTF.access=memorymapped
3499
+ AT91C_EMAC_DTF.address=0xFFFDC058
3500
+ AT91C_EMAC_DTF.width=32
3501
+ AT91C_EMAC_DTF.byteEndian=little
3502
+ AT91C_EMAC_TUND.name="AT91C_EMAC_TUND"
3503
+ AT91C_EMAC_TUND.description="Transmit Underrun Error Register"
3504
+ AT91C_EMAC_TUND.helpkey="Transmit Underrun Error Register"
3505
+ AT91C_EMAC_TUND.access=memorymapped
3506
+ AT91C_EMAC_TUND.address=0xFFFDC064
3507
+ AT91C_EMAC_TUND.width=32
3508
+ AT91C_EMAC_TUND.byteEndian=little
3509
+ AT91C_EMAC_NCR.name="AT91C_EMAC_NCR"
3510
+ AT91C_EMAC_NCR.description="Network Control Register"
3511
+ AT91C_EMAC_NCR.helpkey="Network Control Register"
3512
+ AT91C_EMAC_NCR.access=memorymapped
3513
+ AT91C_EMAC_NCR.address=0xFFFDC000
3514
+ AT91C_EMAC_NCR.width=32
3515
+ AT91C_EMAC_NCR.byteEndian=little
3516
+ AT91C_EMAC_SA4L.name="AT91C_EMAC_SA4L"
3517
+ AT91C_EMAC_SA4L.description="Specific Address 4 Bottom, First 4 bytes"
3518
+ AT91C_EMAC_SA4L.helpkey="Specific Address 4 Bottom, First 4 bytes"
3519
+ AT91C_EMAC_SA4L.access=memorymapped
3520
+ AT91C_EMAC_SA4L.address=0xFFFDC0B0
3521
+ AT91C_EMAC_SA4L.width=32
3522
+ AT91C_EMAC_SA4L.byteEndian=little
3523
+ AT91C_EMAC_RSR.name="AT91C_EMAC_RSR"
3524
+ AT91C_EMAC_RSR.description="Receive Status Register"
3525
+ AT91C_EMAC_RSR.helpkey="Receive Status Register"
3526
+ AT91C_EMAC_RSR.access=memorymapped
3527
+ AT91C_EMAC_RSR.address=0xFFFDC020
3528
+ AT91C_EMAC_RSR.width=32
3529
+ AT91C_EMAC_RSR.byteEndian=little
3530
+ AT91C_EMAC_SA3L.name="AT91C_EMAC_SA3L"
3531
+ AT91C_EMAC_SA3L.description="Specific Address 3 Bottom, First 4 bytes"
3532
+ AT91C_EMAC_SA3L.helpkey="Specific Address 3 Bottom, First 4 bytes"
3533
+ AT91C_EMAC_SA3L.access=memorymapped
3534
+ AT91C_EMAC_SA3L.address=0xFFFDC0A8
3535
+ AT91C_EMAC_SA3L.width=32
3536
+ AT91C_EMAC_SA3L.byteEndian=little
3537
+ AT91C_EMAC_TSR.name="AT91C_EMAC_TSR"
3538
+ AT91C_EMAC_TSR.description="Transmit Status Register"
3539
+ AT91C_EMAC_TSR.helpkey="Transmit Status Register"
3540
+ AT91C_EMAC_TSR.access=memorymapped
3541
+ AT91C_EMAC_TSR.address=0xFFFDC014
3542
+ AT91C_EMAC_TSR.width=32
3543
+ AT91C_EMAC_TSR.byteEndian=little
3544
+ AT91C_EMAC_IDR.name="AT91C_EMAC_IDR"
3545
+ AT91C_EMAC_IDR.description="Interrupt Disable Register"
3546
+ AT91C_EMAC_IDR.helpkey="Interrupt Disable Register"
3547
+ AT91C_EMAC_IDR.access=memorymapped
3548
+ AT91C_EMAC_IDR.address=0xFFFDC02C
3549
+ AT91C_EMAC_IDR.width=32
3550
+ AT91C_EMAC_IDR.byteEndian=little
3551
+ AT91C_EMAC_IDR.type=enum
3552
+ AT91C_EMAC_IDR.enum.0.name=*** Write only ***
3553
+ AT91C_EMAC_IDR.enum.1.name=Error
3554
+ AT91C_EMAC_RSE.name="AT91C_EMAC_RSE"
3555
+ AT91C_EMAC_RSE.description="Receive Symbol Errors Register"
3556
+ AT91C_EMAC_RSE.helpkey="Receive Symbol Errors Register"
3557
+ AT91C_EMAC_RSE.access=memorymapped
3558
+ AT91C_EMAC_RSE.address=0xFFFDC074
3559
+ AT91C_EMAC_RSE.width=32
3560
+ AT91C_EMAC_RSE.byteEndian=little
3561
+ AT91C_EMAC_ECOL.name="AT91C_EMAC_ECOL"
3562
+ AT91C_EMAC_ECOL.description="Excessive Collision Register"
3563
+ AT91C_EMAC_ECOL.helpkey="Excessive Collision Register"
3564
+ AT91C_EMAC_ECOL.access=memorymapped
3565
+ AT91C_EMAC_ECOL.address=0xFFFDC060
3566
+ AT91C_EMAC_ECOL.width=32
3567
+ AT91C_EMAC_ECOL.byteEndian=little
3568
+ AT91C_EMAC_TID.name="AT91C_EMAC_TID"
3569
+ AT91C_EMAC_TID.description="Type ID Checking Register"
3570
+ AT91C_EMAC_TID.helpkey="Type ID Checking Register"
3571
+ AT91C_EMAC_TID.access=memorymapped
3572
+ AT91C_EMAC_TID.address=0xFFFDC0B8
3573
+ AT91C_EMAC_TID.width=32
3574
+ AT91C_EMAC_TID.byteEndian=little
3575
+ AT91C_EMAC_HRB.name="AT91C_EMAC_HRB"
3576
+ AT91C_EMAC_HRB.description="Hash Address Bottom[31:0]"
3577
+ AT91C_EMAC_HRB.helpkey="Hash Address Bottom[31:0]"
3578
+ AT91C_EMAC_HRB.access=memorymapped
3579
+ AT91C_EMAC_HRB.address=0xFFFDC090
3580
+ AT91C_EMAC_HRB.width=32
3581
+ AT91C_EMAC_HRB.byteEndian=little
3582
+ AT91C_EMAC_TBQP.name="AT91C_EMAC_TBQP"
3583
+ AT91C_EMAC_TBQP.description="Transmit Buffer Queue Pointer"
3584
+ AT91C_EMAC_TBQP.helpkey="Transmit Buffer Queue Pointer"
3585
+ AT91C_EMAC_TBQP.access=memorymapped
3586
+ AT91C_EMAC_TBQP.address=0xFFFDC01C
3587
+ AT91C_EMAC_TBQP.width=32
3588
+ AT91C_EMAC_TBQP.byteEndian=little
3589
+ AT91C_EMAC_USRIO.name="AT91C_EMAC_USRIO"
3590
+ AT91C_EMAC_USRIO.description="USER Input/Output Register"
3591
+ AT91C_EMAC_USRIO.helpkey="USER Input/Output Register"
3592
+ AT91C_EMAC_USRIO.access=memorymapped
3593
+ AT91C_EMAC_USRIO.address=0xFFFDC0C0
3594
+ AT91C_EMAC_USRIO.width=32
3595
+ AT91C_EMAC_USRIO.byteEndian=little
3596
+ AT91C_EMAC_PTR.name="AT91C_EMAC_PTR"
3597
+ AT91C_EMAC_PTR.description="Pause Time Register"
3598
+ AT91C_EMAC_PTR.helpkey="Pause Time Register"
3599
+ AT91C_EMAC_PTR.access=memorymapped
3600
+ AT91C_EMAC_PTR.address=0xFFFDC038
3601
+ AT91C_EMAC_PTR.width=32
3602
+ AT91C_EMAC_PTR.byteEndian=little
3603
+ AT91C_EMAC_SA2H.name="AT91C_EMAC_SA2H"
3604
+ AT91C_EMAC_SA2H.description="Specific Address 2 Top, Last 2 bytes"
3605
+ AT91C_EMAC_SA2H.helpkey="Specific Address 2 Top, Last 2 bytes"
3606
+ AT91C_EMAC_SA2H.access=memorymapped
3607
+ AT91C_EMAC_SA2H.address=0xFFFDC0A4
3608
+ AT91C_EMAC_SA2H.width=32
3609
+ AT91C_EMAC_SA2H.byteEndian=little
3610
+ AT91C_EMAC_ROV.name="AT91C_EMAC_ROV"
3611
+ AT91C_EMAC_ROV.description="Receive Overrun Errors Register"
3612
+ AT91C_EMAC_ROV.helpkey="Receive Overrun Errors Register"
3613
+ AT91C_EMAC_ROV.access=memorymapped
3614
+ AT91C_EMAC_ROV.address=0xFFFDC070
3615
+ AT91C_EMAC_ROV.width=32
3616
+ AT91C_EMAC_ROV.byteEndian=little
3617
+ AT91C_EMAC_ALE.name="AT91C_EMAC_ALE"
3618
+ AT91C_EMAC_ALE.description="Alignment Error Register"
3619
+ AT91C_EMAC_ALE.helpkey="Alignment Error Register"
3620
+ AT91C_EMAC_ALE.access=memorymapped
3621
+ AT91C_EMAC_ALE.address=0xFFFDC054
3622
+ AT91C_EMAC_ALE.width=32
3623
+ AT91C_EMAC_ALE.byteEndian=little
3624
+ AT91C_EMAC_RJA.name="AT91C_EMAC_RJA"
3625
+ AT91C_EMAC_RJA.description="Receive Jabbers Register"
3626
+ AT91C_EMAC_RJA.helpkey="Receive Jabbers Register"
3627
+ AT91C_EMAC_RJA.access=memorymapped
3628
+ AT91C_EMAC_RJA.address=0xFFFDC07C
3629
+ AT91C_EMAC_RJA.width=32
3630
+ AT91C_EMAC_RJA.byteEndian=little
3631
+ AT91C_EMAC_RBQP.name="AT91C_EMAC_RBQP"
3632
+ AT91C_EMAC_RBQP.description="Receive Buffer Queue Pointer"
3633
+ AT91C_EMAC_RBQP.helpkey="Receive Buffer Queue Pointer"
3634
+ AT91C_EMAC_RBQP.access=memorymapped
3635
+ AT91C_EMAC_RBQP.address=0xFFFDC018
3636
+ AT91C_EMAC_RBQP.width=32
3637
+ AT91C_EMAC_RBQP.byteEndian=little
3638
+ AT91C_EMAC_TPF.name="AT91C_EMAC_TPF"
3639
+ AT91C_EMAC_TPF.description="Transmitted Pause Frames Register"
3640
+ AT91C_EMAC_TPF.helpkey="Transmitted Pause Frames Register"
3641
+ AT91C_EMAC_TPF.access=memorymapped
3642
+ AT91C_EMAC_TPF.address=0xFFFDC08C
3643
+ AT91C_EMAC_TPF.width=32
3644
+ AT91C_EMAC_TPF.byteEndian=little
3645
+ AT91C_EMAC_NCFGR.name="AT91C_EMAC_NCFGR"
3646
+ AT91C_EMAC_NCFGR.description="Network Configuration Register"
3647
+ AT91C_EMAC_NCFGR.helpkey="Network Configuration Register"
3648
+ AT91C_EMAC_NCFGR.access=memorymapped
3649
+ AT91C_EMAC_NCFGR.address=0xFFFDC004
3650
+ AT91C_EMAC_NCFGR.width=32
3651
+ AT91C_EMAC_NCFGR.byteEndian=little
3652
+ AT91C_EMAC_HRT.name="AT91C_EMAC_HRT"
3653
+ AT91C_EMAC_HRT.description="Hash Address Top[63:32]"
3654
+ AT91C_EMAC_HRT.helpkey="Hash Address Top[63:32]"
3655
+ AT91C_EMAC_HRT.access=memorymapped
3656
+ AT91C_EMAC_HRT.address=0xFFFDC094
3657
+ AT91C_EMAC_HRT.width=32
3658
+ AT91C_EMAC_HRT.byteEndian=little
3659
+ AT91C_EMAC_USF.name="AT91C_EMAC_USF"
3660
+ AT91C_EMAC_USF.description="Undersize Frames Register"
3661
+ AT91C_EMAC_USF.helpkey="Undersize Frames Register"
3662
+ AT91C_EMAC_USF.access=memorymapped
3663
+ AT91C_EMAC_USF.address=0xFFFDC080
3664
+ AT91C_EMAC_USF.width=32
3665
+ AT91C_EMAC_USF.byteEndian=little
3666
+ AT91C_EMAC_FCSE.name="AT91C_EMAC_FCSE"
3667
+ AT91C_EMAC_FCSE.description="Frame Check Sequence Error Register"
3668
+ AT91C_EMAC_FCSE.helpkey="Frame Check Sequence Error Register"
3669
+ AT91C_EMAC_FCSE.access=memorymapped
3670
+ AT91C_EMAC_FCSE.address=0xFFFDC050
3671
+ AT91C_EMAC_FCSE.width=32
3672
+ AT91C_EMAC_FCSE.byteEndian=little
3673
+ AT91C_EMAC_TPQ.name="AT91C_EMAC_TPQ"
3674
+ AT91C_EMAC_TPQ.description="Transmit Pause Quantum Register"
3675
+ AT91C_EMAC_TPQ.helpkey="Transmit Pause Quantum Register"
3676
+ AT91C_EMAC_TPQ.access=memorymapped
3677
+ AT91C_EMAC_TPQ.address=0xFFFDC0BC
3678
+ AT91C_EMAC_TPQ.width=32
3679
+ AT91C_EMAC_TPQ.byteEndian=little
3680
+ AT91C_EMAC_MAN.name="AT91C_EMAC_MAN"
3681
+ AT91C_EMAC_MAN.description="PHY Maintenance Register"
3682
+ AT91C_EMAC_MAN.helpkey="PHY Maintenance Register"
3683
+ AT91C_EMAC_MAN.access=memorymapped
3684
+ AT91C_EMAC_MAN.address=0xFFFDC034
3685
+ AT91C_EMAC_MAN.width=32
3686
+ AT91C_EMAC_MAN.byteEndian=little
3687
+ AT91C_EMAC_FTO.name="AT91C_EMAC_FTO"
3688
+ AT91C_EMAC_FTO.description="Frames Transmitted OK Register"
3689
+ AT91C_EMAC_FTO.helpkey="Frames Transmitted OK Register"
3690
+ AT91C_EMAC_FTO.access=memorymapped
3691
+ AT91C_EMAC_FTO.address=0xFFFDC040
3692
+ AT91C_EMAC_FTO.width=32
3693
+ AT91C_EMAC_FTO.byteEndian=little
3694
+ AT91C_EMAC_REV.name="AT91C_EMAC_REV"
3695
+ AT91C_EMAC_REV.description="Revision Register"
3696
+ AT91C_EMAC_REV.helpkey="Revision Register"
3697
+ AT91C_EMAC_REV.access=memorymapped
3698
+ AT91C_EMAC_REV.address=0xFFFDC0FC
3699
+ AT91C_EMAC_REV.width=32
3700
+ AT91C_EMAC_REV.byteEndian=little
3701
+ AT91C_EMAC_REV.permission.write=none
3702
+ AT91C_EMAC_IMR.name="AT91C_EMAC_IMR"
3703
+ AT91C_EMAC_IMR.description="Interrupt Mask Register"
3704
+ AT91C_EMAC_IMR.helpkey="Interrupt Mask Register"
3705
+ AT91C_EMAC_IMR.access=memorymapped
3706
+ AT91C_EMAC_IMR.address=0xFFFDC030
3707
+ AT91C_EMAC_IMR.width=32
3708
+ AT91C_EMAC_IMR.byteEndian=little
3709
+ AT91C_EMAC_IMR.permission.write=none
3710
+ AT91C_EMAC_SCF.name="AT91C_EMAC_SCF"
3711
+ AT91C_EMAC_SCF.description="Single Collision Frame Register"
3712
+ AT91C_EMAC_SCF.helpkey="Single Collision Frame Register"
3713
+ AT91C_EMAC_SCF.access=memorymapped
3714
+ AT91C_EMAC_SCF.address=0xFFFDC044
3715
+ AT91C_EMAC_SCF.width=32
3716
+ AT91C_EMAC_SCF.byteEndian=little
3717
+ AT91C_EMAC_PFR.name="AT91C_EMAC_PFR"
3718
+ AT91C_EMAC_PFR.description="Pause Frames received Register"
3719
+ AT91C_EMAC_PFR.helpkey="Pause Frames received Register"
3720
+ AT91C_EMAC_PFR.access=memorymapped
3721
+ AT91C_EMAC_PFR.address=0xFFFDC03C
3722
+ AT91C_EMAC_PFR.width=32
3723
+ AT91C_EMAC_PFR.byteEndian=little
3724
+ AT91C_EMAC_MCF.name="AT91C_EMAC_MCF"
3725
+ AT91C_EMAC_MCF.description="Multiple Collision Frame Register"
3726
+ AT91C_EMAC_MCF.helpkey="Multiple Collision Frame Register"
3727
+ AT91C_EMAC_MCF.access=memorymapped
3728
+ AT91C_EMAC_MCF.address=0xFFFDC048
3729
+ AT91C_EMAC_MCF.width=32
3730
+ AT91C_EMAC_MCF.byteEndian=little
3731
+ AT91C_EMAC_NSR.name="AT91C_EMAC_NSR"
3732
+ AT91C_EMAC_NSR.description="Network Status Register"
3733
+ AT91C_EMAC_NSR.helpkey="Network Status Register"
3734
+ AT91C_EMAC_NSR.access=memorymapped
3735
+ AT91C_EMAC_NSR.address=0xFFFDC008
3736
+ AT91C_EMAC_NSR.width=32
3737
+ AT91C_EMAC_NSR.byteEndian=little
3738
+ AT91C_EMAC_NSR.permission.write=none
3739
+ AT91C_EMAC_SA2L.name="AT91C_EMAC_SA2L"
3740
+ AT91C_EMAC_SA2L.description="Specific Address 2 Bottom, First 4 bytes"
3741
+ AT91C_EMAC_SA2L.helpkey="Specific Address 2 Bottom, First 4 bytes"
3742
+ AT91C_EMAC_SA2L.access=memorymapped
3743
+ AT91C_EMAC_SA2L.address=0xFFFDC0A0
3744
+ AT91C_EMAC_SA2L.width=32
3745
+ AT91C_EMAC_SA2L.byteEndian=little
3746
+ AT91C_EMAC_FRO.name="AT91C_EMAC_FRO"
3747
+ AT91C_EMAC_FRO.description="Frames Received OK Register"
3748
+ AT91C_EMAC_FRO.helpkey="Frames Received OK Register"
3749
+ AT91C_EMAC_FRO.access=memorymapped
3750
+ AT91C_EMAC_FRO.address=0xFFFDC04C
3751
+ AT91C_EMAC_FRO.width=32
3752
+ AT91C_EMAC_FRO.byteEndian=little
3753
+ AT91C_EMAC_IER.name="AT91C_EMAC_IER"
3754
+ AT91C_EMAC_IER.description="Interrupt Enable Register"
3755
+ AT91C_EMAC_IER.helpkey="Interrupt Enable Register"
3756
+ AT91C_EMAC_IER.access=memorymapped
3757
+ AT91C_EMAC_IER.address=0xFFFDC028
3758
+ AT91C_EMAC_IER.width=32
3759
+ AT91C_EMAC_IER.byteEndian=little
3760
+ AT91C_EMAC_IER.type=enum
3761
+ AT91C_EMAC_IER.enum.0.name=*** Write only ***
3762
+ AT91C_EMAC_IER.enum.1.name=Error
3763
+ AT91C_EMAC_SA1H.name="AT91C_EMAC_SA1H"
3764
+ AT91C_EMAC_SA1H.description="Specific Address 1 Top, Last 2 bytes"
3765
+ AT91C_EMAC_SA1H.helpkey="Specific Address 1 Top, Last 2 bytes"
3766
+ AT91C_EMAC_SA1H.access=memorymapped
3767
+ AT91C_EMAC_SA1H.address=0xFFFDC09C
3768
+ AT91C_EMAC_SA1H.width=32
3769
+ AT91C_EMAC_SA1H.byteEndian=little
3770
+ AT91C_EMAC_CSE.name="AT91C_EMAC_CSE"
3771
+ AT91C_EMAC_CSE.description="Carrier Sense Error Register"
3772
+ AT91C_EMAC_CSE.helpkey="Carrier Sense Error Register"
3773
+ AT91C_EMAC_CSE.access=memorymapped
3774
+ AT91C_EMAC_CSE.address=0xFFFDC068
3775
+ AT91C_EMAC_CSE.width=32
3776
+ AT91C_EMAC_CSE.byteEndian=little
3777
+ AT91C_EMAC_SA3H.name="AT91C_EMAC_SA3H"
3778
+ AT91C_EMAC_SA3H.description="Specific Address 3 Top, Last 2 bytes"
3779
+ AT91C_EMAC_SA3H.helpkey="Specific Address 3 Top, Last 2 bytes"
3780
+ AT91C_EMAC_SA3H.access=memorymapped
3781
+ AT91C_EMAC_SA3H.address=0xFFFDC0AC
3782
+ AT91C_EMAC_SA3H.width=32
3783
+ AT91C_EMAC_SA3H.byteEndian=little
3784
+ AT91C_EMAC_RRE.name="AT91C_EMAC_RRE"
3785
+ AT91C_EMAC_RRE.description="Receive Ressource Error Register"
3786
+ AT91C_EMAC_RRE.helpkey="Receive Ressource Error Register"
3787
+ AT91C_EMAC_RRE.access=memorymapped
3788
+ AT91C_EMAC_RRE.address=0xFFFDC06C
3789
+ AT91C_EMAC_RRE.width=32
3790
+ AT91C_EMAC_RRE.byteEndian=little
3791
+ AT91C_EMAC_STE.name="AT91C_EMAC_STE"
3792
+ AT91C_EMAC_STE.description="SQE Test Error Register"
3793
+ AT91C_EMAC_STE.helpkey="SQE Test Error Register"
3794
+ AT91C_EMAC_STE.access=memorymapped
3795
+ AT91C_EMAC_STE.address=0xFFFDC084
3796
+ AT91C_EMAC_STE.width=32
3797
+ AT91C_EMAC_STE.byteEndian=little
3798
+ # ========== Register definition for PDC_ADC peripheral ==========
3799
+ AT91C_ADC_PTSR.name="AT91C_ADC_PTSR"
3800
+ AT91C_ADC_PTSR.description="PDC Transfer Status Register"
3801
+ AT91C_ADC_PTSR.helpkey="PDC Transfer Status Register"
3802
+ AT91C_ADC_PTSR.access=memorymapped
3803
+ AT91C_ADC_PTSR.address=0xFFFD8124
3804
+ AT91C_ADC_PTSR.width=32
3805
+ AT91C_ADC_PTSR.byteEndian=little
3806
+ AT91C_ADC_PTSR.permission.write=none
3807
+ AT91C_ADC_PTCR.name="AT91C_ADC_PTCR"
3808
+ AT91C_ADC_PTCR.description="PDC Transfer Control Register"
3809
+ AT91C_ADC_PTCR.helpkey="PDC Transfer Control Register"
3810
+ AT91C_ADC_PTCR.access=memorymapped
3811
+ AT91C_ADC_PTCR.address=0xFFFD8120
3812
+ AT91C_ADC_PTCR.width=32
3813
+ AT91C_ADC_PTCR.byteEndian=little
3814
+ AT91C_ADC_PTCR.type=enum
3815
+ AT91C_ADC_PTCR.enum.0.name=*** Write only ***
3816
+ AT91C_ADC_PTCR.enum.1.name=Error
3817
+ AT91C_ADC_TNPR.name="AT91C_ADC_TNPR"
3818
+ AT91C_ADC_TNPR.description="Transmit Next Pointer Register"
3819
+ AT91C_ADC_TNPR.helpkey="Transmit Next Pointer Register"
3820
+ AT91C_ADC_TNPR.access=memorymapped
3821
+ AT91C_ADC_TNPR.address=0xFFFD8118
3822
+ AT91C_ADC_TNPR.width=32
3823
+ AT91C_ADC_TNPR.byteEndian=little
3824
+ AT91C_ADC_TNCR.name="AT91C_ADC_TNCR"
3825
+ AT91C_ADC_TNCR.description="Transmit Next Counter Register"
3826
+ AT91C_ADC_TNCR.helpkey="Transmit Next Counter Register"
3827
+ AT91C_ADC_TNCR.access=memorymapped
3828
+ AT91C_ADC_TNCR.address=0xFFFD811C
3829
+ AT91C_ADC_TNCR.width=32
3830
+ AT91C_ADC_TNCR.byteEndian=little
3831
+ AT91C_ADC_RNPR.name="AT91C_ADC_RNPR"
3832
+ AT91C_ADC_RNPR.description="Receive Next Pointer Register"
3833
+ AT91C_ADC_RNPR.helpkey="Receive Next Pointer Register"
3834
+ AT91C_ADC_RNPR.access=memorymapped
3835
+ AT91C_ADC_RNPR.address=0xFFFD8110
3836
+ AT91C_ADC_RNPR.width=32
3837
+ AT91C_ADC_RNPR.byteEndian=little
3838
+ AT91C_ADC_RNCR.name="AT91C_ADC_RNCR"
3839
+ AT91C_ADC_RNCR.description="Receive Next Counter Register"
3840
+ AT91C_ADC_RNCR.helpkey="Receive Next Counter Register"
3841
+ AT91C_ADC_RNCR.access=memorymapped
3842
+ AT91C_ADC_RNCR.address=0xFFFD8114
3843
+ AT91C_ADC_RNCR.width=32
3844
+ AT91C_ADC_RNCR.byteEndian=little
3845
+ AT91C_ADC_RPR.name="AT91C_ADC_RPR"
3846
+ AT91C_ADC_RPR.description="Receive Pointer Register"
3847
+ AT91C_ADC_RPR.helpkey="Receive Pointer Register"
3848
+ AT91C_ADC_RPR.access=memorymapped
3849
+ AT91C_ADC_RPR.address=0xFFFD8100
3850
+ AT91C_ADC_RPR.width=32
3851
+ AT91C_ADC_RPR.byteEndian=little
3852
+ AT91C_ADC_TCR.name="AT91C_ADC_TCR"
3853
+ AT91C_ADC_TCR.description="Transmit Counter Register"
3854
+ AT91C_ADC_TCR.helpkey="Transmit Counter Register"
3855
+ AT91C_ADC_TCR.access=memorymapped
3856
+ AT91C_ADC_TCR.address=0xFFFD810C
3857
+ AT91C_ADC_TCR.width=32
3858
+ AT91C_ADC_TCR.byteEndian=little
3859
+ AT91C_ADC_TPR.name="AT91C_ADC_TPR"
3860
+ AT91C_ADC_TPR.description="Transmit Pointer Register"
3861
+ AT91C_ADC_TPR.helpkey="Transmit Pointer Register"
3862
+ AT91C_ADC_TPR.access=memorymapped
3863
+ AT91C_ADC_TPR.address=0xFFFD8108
3864
+ AT91C_ADC_TPR.width=32
3865
+ AT91C_ADC_TPR.byteEndian=little
3866
+ AT91C_ADC_RCR.name="AT91C_ADC_RCR"
3867
+ AT91C_ADC_RCR.description="Receive Counter Register"
3868
+ AT91C_ADC_RCR.helpkey="Receive Counter Register"
3869
+ AT91C_ADC_RCR.access=memorymapped
3870
+ AT91C_ADC_RCR.address=0xFFFD8104
3871
+ AT91C_ADC_RCR.width=32
3872
+ AT91C_ADC_RCR.byteEndian=little
3873
+ # ========== Register definition for ADC peripheral ==========
3874
+ AT91C_ADC_CDR2.name="AT91C_ADC_CDR2"
3875
+ AT91C_ADC_CDR2.description="ADC Channel Data Register 2"
3876
+ AT91C_ADC_CDR2.helpkey="ADC Channel Data Register 2"
3877
+ AT91C_ADC_CDR2.access=memorymapped
3878
+ AT91C_ADC_CDR2.address=0xFFFD8038
3879
+ AT91C_ADC_CDR2.width=32
3880
+ AT91C_ADC_CDR2.byteEndian=little
3881
+ AT91C_ADC_CDR2.permission.write=none
3882
+ AT91C_ADC_CDR3.name="AT91C_ADC_CDR3"
3883
+ AT91C_ADC_CDR3.description="ADC Channel Data Register 3"
3884
+ AT91C_ADC_CDR3.helpkey="ADC Channel Data Register 3"
3885
+ AT91C_ADC_CDR3.access=memorymapped
3886
+ AT91C_ADC_CDR3.address=0xFFFD803C
3887
+ AT91C_ADC_CDR3.width=32
3888
+ AT91C_ADC_CDR3.byteEndian=little
3889
+ AT91C_ADC_CDR3.permission.write=none
3890
+ AT91C_ADC_CDR0.name="AT91C_ADC_CDR0"
3891
+ AT91C_ADC_CDR0.description="ADC Channel Data Register 0"
3892
+ AT91C_ADC_CDR0.helpkey="ADC Channel Data Register 0"
3893
+ AT91C_ADC_CDR0.access=memorymapped
3894
+ AT91C_ADC_CDR0.address=0xFFFD8030
3895
+ AT91C_ADC_CDR0.width=32
3896
+ AT91C_ADC_CDR0.byteEndian=little
3897
+ AT91C_ADC_CDR0.permission.write=none
3898
+ AT91C_ADC_CDR5.name="AT91C_ADC_CDR5"
3899
+ AT91C_ADC_CDR5.description="ADC Channel Data Register 5"
3900
+ AT91C_ADC_CDR5.helpkey="ADC Channel Data Register 5"
3901
+ AT91C_ADC_CDR5.access=memorymapped
3902
+ AT91C_ADC_CDR5.address=0xFFFD8044
3903
+ AT91C_ADC_CDR5.width=32
3904
+ AT91C_ADC_CDR5.byteEndian=little
3905
+ AT91C_ADC_CDR5.permission.write=none
3906
+ AT91C_ADC_CHDR.name="AT91C_ADC_CHDR"
3907
+ AT91C_ADC_CHDR.description="ADC Channel Disable Register"
3908
+ AT91C_ADC_CHDR.helpkey="ADC Channel Disable Register"
3909
+ AT91C_ADC_CHDR.access=memorymapped
3910
+ AT91C_ADC_CHDR.address=0xFFFD8014
3911
+ AT91C_ADC_CHDR.width=32
3912
+ AT91C_ADC_CHDR.byteEndian=little
3913
+ AT91C_ADC_CHDR.type=enum
3914
+ AT91C_ADC_CHDR.enum.0.name=*** Write only ***
3915
+ AT91C_ADC_CHDR.enum.1.name=Error
3916
+ AT91C_ADC_SR.name="AT91C_ADC_SR"
3917
+ AT91C_ADC_SR.description="ADC Status Register"
3918
+ AT91C_ADC_SR.helpkey="ADC Status Register"
3919
+ AT91C_ADC_SR.access=memorymapped
3920
+ AT91C_ADC_SR.address=0xFFFD801C
3921
+ AT91C_ADC_SR.width=32
3922
+ AT91C_ADC_SR.byteEndian=little
3923
+ AT91C_ADC_SR.permission.write=none
3924
+ AT91C_ADC_CDR4.name="AT91C_ADC_CDR4"
3925
+ AT91C_ADC_CDR4.description="ADC Channel Data Register 4"
3926
+ AT91C_ADC_CDR4.helpkey="ADC Channel Data Register 4"
3927
+ AT91C_ADC_CDR4.access=memorymapped
3928
+ AT91C_ADC_CDR4.address=0xFFFD8040
3929
+ AT91C_ADC_CDR4.width=32
3930
+ AT91C_ADC_CDR4.byteEndian=little
3931
+ AT91C_ADC_CDR4.permission.write=none
3932
+ AT91C_ADC_CDR1.name="AT91C_ADC_CDR1"
3933
+ AT91C_ADC_CDR1.description="ADC Channel Data Register 1"
3934
+ AT91C_ADC_CDR1.helpkey="ADC Channel Data Register 1"
3935
+ AT91C_ADC_CDR1.access=memorymapped
3936
+ AT91C_ADC_CDR1.address=0xFFFD8034
3937
+ AT91C_ADC_CDR1.width=32
3938
+ AT91C_ADC_CDR1.byteEndian=little
3939
+ AT91C_ADC_CDR1.permission.write=none
3940
+ AT91C_ADC_LCDR.name="AT91C_ADC_LCDR"
3941
+ AT91C_ADC_LCDR.description="ADC Last Converted Data Register"
3942
+ AT91C_ADC_LCDR.helpkey="ADC Last Converted Data Register"
3943
+ AT91C_ADC_LCDR.access=memorymapped
3944
+ AT91C_ADC_LCDR.address=0xFFFD8020
3945
+ AT91C_ADC_LCDR.width=32
3946
+ AT91C_ADC_LCDR.byteEndian=little
3947
+ AT91C_ADC_LCDR.permission.write=none
3948
+ AT91C_ADC_IDR.name="AT91C_ADC_IDR"
3949
+ AT91C_ADC_IDR.description="ADC Interrupt Disable Register"
3950
+ AT91C_ADC_IDR.helpkey="ADC Interrupt Disable Register"
3951
+ AT91C_ADC_IDR.access=memorymapped
3952
+ AT91C_ADC_IDR.address=0xFFFD8028
3953
+ AT91C_ADC_IDR.width=32
3954
+ AT91C_ADC_IDR.byteEndian=little
3955
+ AT91C_ADC_IDR.type=enum
3956
+ AT91C_ADC_IDR.enum.0.name=*** Write only ***
3957
+ AT91C_ADC_IDR.enum.1.name=Error
3958
+ AT91C_ADC_CR.name="AT91C_ADC_CR"
3959
+ AT91C_ADC_CR.description="ADC Control Register"
3960
+ AT91C_ADC_CR.helpkey="ADC Control Register"
3961
+ AT91C_ADC_CR.access=memorymapped
3962
+ AT91C_ADC_CR.address=0xFFFD8000
3963
+ AT91C_ADC_CR.width=32
3964
+ AT91C_ADC_CR.byteEndian=little
3965
+ AT91C_ADC_CR.type=enum
3966
+ AT91C_ADC_CR.enum.0.name=*** Write only ***
3967
+ AT91C_ADC_CR.enum.1.name=Error
3968
+ AT91C_ADC_CDR7.name="AT91C_ADC_CDR7"
3969
+ AT91C_ADC_CDR7.description="ADC Channel Data Register 7"
3970
+ AT91C_ADC_CDR7.helpkey="ADC Channel Data Register 7"
3971
+ AT91C_ADC_CDR7.access=memorymapped
3972
+ AT91C_ADC_CDR7.address=0xFFFD804C
3973
+ AT91C_ADC_CDR7.width=32
3974
+ AT91C_ADC_CDR7.byteEndian=little
3975
+ AT91C_ADC_CDR7.permission.write=none
3976
+ AT91C_ADC_CDR6.name="AT91C_ADC_CDR6"
3977
+ AT91C_ADC_CDR6.description="ADC Channel Data Register 6"
3978
+ AT91C_ADC_CDR6.helpkey="ADC Channel Data Register 6"
3979
+ AT91C_ADC_CDR6.access=memorymapped
3980
+ AT91C_ADC_CDR6.address=0xFFFD8048
3981
+ AT91C_ADC_CDR6.width=32
3982
+ AT91C_ADC_CDR6.byteEndian=little
3983
+ AT91C_ADC_CDR6.permission.write=none
3984
+ AT91C_ADC_IER.name="AT91C_ADC_IER"
3985
+ AT91C_ADC_IER.description="ADC Interrupt Enable Register"
3986
+ AT91C_ADC_IER.helpkey="ADC Interrupt Enable Register"
3987
+ AT91C_ADC_IER.access=memorymapped
3988
+ AT91C_ADC_IER.address=0xFFFD8024
3989
+ AT91C_ADC_IER.width=32
3990
+ AT91C_ADC_IER.byteEndian=little
3991
+ AT91C_ADC_IER.type=enum
3992
+ AT91C_ADC_IER.enum.0.name=*** Write only ***
3993
+ AT91C_ADC_IER.enum.1.name=Error
3994
+ AT91C_ADC_CHER.name="AT91C_ADC_CHER"
3995
+ AT91C_ADC_CHER.description="ADC Channel Enable Register"
3996
+ AT91C_ADC_CHER.helpkey="ADC Channel Enable Register"
3997
+ AT91C_ADC_CHER.access=memorymapped
3998
+ AT91C_ADC_CHER.address=0xFFFD8010
3999
+ AT91C_ADC_CHER.width=32
4000
+ AT91C_ADC_CHER.byteEndian=little
4001
+ AT91C_ADC_CHER.type=enum
4002
+ AT91C_ADC_CHER.enum.0.name=*** Write only ***
4003
+ AT91C_ADC_CHER.enum.1.name=Error
4004
+ AT91C_ADC_CHSR.name="AT91C_ADC_CHSR"
4005
+ AT91C_ADC_CHSR.description="ADC Channel Status Register"
4006
+ AT91C_ADC_CHSR.helpkey="ADC Channel Status Register"
4007
+ AT91C_ADC_CHSR.access=memorymapped
4008
+ AT91C_ADC_CHSR.address=0xFFFD8018
4009
+ AT91C_ADC_CHSR.width=32
4010
+ AT91C_ADC_CHSR.byteEndian=little
4011
+ AT91C_ADC_CHSR.permission.write=none
4012
+ AT91C_ADC_MR.name="AT91C_ADC_MR"
4013
+ AT91C_ADC_MR.description="ADC Mode Register"
4014
+ AT91C_ADC_MR.helpkey="ADC Mode Register"
4015
+ AT91C_ADC_MR.access=memorymapped
4016
+ AT91C_ADC_MR.address=0xFFFD8004
4017
+ AT91C_ADC_MR.width=32
4018
+ AT91C_ADC_MR.byteEndian=little
4019
+ AT91C_ADC_IMR.name="AT91C_ADC_IMR"
4020
+ AT91C_ADC_IMR.description="ADC Interrupt Mask Register"
4021
+ AT91C_ADC_IMR.helpkey="ADC Interrupt Mask Register"
4022
+ AT91C_ADC_IMR.access=memorymapped
4023
+ AT91C_ADC_IMR.address=0xFFFD802C
4024
+ AT91C_ADC_IMR.width=32
4025
+ AT91C_ADC_IMR.byteEndian=little
4026
+ AT91C_ADC_IMR.permission.write=none
4027
+ # ========== Group definition for SYS peripheral ==========
4028
+ group.SYS.description="ATMEL SYS Registers"
4029
+ group.SYS.helpkey="ATMEL SYS Registers"
4030
+ # ========== Group definition for AIC peripheral ==========
4031
+ group.AIC.description="ATMEL AIC Registers"
4032
+ group.AIC.helpkey="ATMEL AIC Registers"
4033
+ group.AIC.register.0=AT91C_AIC_IVR
4034
+ group.AIC.register.1=AT91C_AIC_SMR
4035
+ group.AIC.register.2=AT91C_AIC_FVR
4036
+ group.AIC.register.3=AT91C_AIC_DCR
4037
+ group.AIC.register.4=AT91C_AIC_EOICR
4038
+ group.AIC.register.5=AT91C_AIC_SVR
4039
+ group.AIC.register.6=AT91C_AIC_FFSR
4040
+ group.AIC.register.7=AT91C_AIC_ICCR
4041
+ group.AIC.register.8=AT91C_AIC_ISR
4042
+ group.AIC.register.9=AT91C_AIC_IMR
4043
+ group.AIC.register.10=AT91C_AIC_IPR
4044
+ group.AIC.register.11=AT91C_AIC_FFER
4045
+ group.AIC.register.12=AT91C_AIC_IECR
4046
+ group.AIC.register.13=AT91C_AIC_ISCR
4047
+ group.AIC.register.14=AT91C_AIC_FFDR
4048
+ group.AIC.register.15=AT91C_AIC_CISR
4049
+ group.AIC.register.16=AT91C_AIC_IDCR
4050
+ group.AIC.register.17=AT91C_AIC_SPU
4051
+ # ========== Group definition for PDC_DBGU peripheral ==========
4052
+ group.PDC_DBGU.description="ATMEL PDC_DBGU Registers"
4053
+ group.PDC_DBGU.helpkey="ATMEL PDC_DBGU Registers"
4054
+ group.PDC_DBGU.register.0=AT91C_DBGU_TCR
4055
+ group.PDC_DBGU.register.1=AT91C_DBGU_RNPR
4056
+ group.PDC_DBGU.register.2=AT91C_DBGU_TNPR
4057
+ group.PDC_DBGU.register.3=AT91C_DBGU_TPR
4058
+ group.PDC_DBGU.register.4=AT91C_DBGU_RPR
4059
+ group.PDC_DBGU.register.5=AT91C_DBGU_RCR
4060
+ group.PDC_DBGU.register.6=AT91C_DBGU_RNCR
4061
+ group.PDC_DBGU.register.7=AT91C_DBGU_PTCR
4062
+ group.PDC_DBGU.register.8=AT91C_DBGU_PTSR
4063
+ group.PDC_DBGU.register.9=AT91C_DBGU_TNCR
4064
+ # ========== Group definition for DBGU peripheral ==========
4065
+ group.DBGU.description="ATMEL DBGU Registers"
4066
+ group.DBGU.helpkey="ATMEL DBGU Registers"
4067
+ group.DBGU.register.0=AT91C_DBGU_EXID
4068
+ group.DBGU.register.1=AT91C_DBGU_BRGR
4069
+ group.DBGU.register.2=AT91C_DBGU_IDR
4070
+ group.DBGU.register.3=AT91C_DBGU_CSR
4071
+ group.DBGU.register.4=AT91C_DBGU_CIDR
4072
+ group.DBGU.register.5=AT91C_DBGU_MR
4073
+ group.DBGU.register.6=AT91C_DBGU_IMR
4074
+ group.DBGU.register.7=AT91C_DBGU_CR
4075
+ group.DBGU.register.8=AT91C_DBGU_FNTR
4076
+ group.DBGU.register.9=AT91C_DBGU_THR
4077
+ group.DBGU.register.10=AT91C_DBGU_RHR
4078
+ group.DBGU.register.11=AT91C_DBGU_IER
4079
+ # ========== Group definition for PIOA peripheral ==========
4080
+ group.PIOA.description="ATMEL PIOA Registers"
4081
+ group.PIOA.helpkey="ATMEL PIOA Registers"
4082
+ group.PIOA.register.0=AT91C_PIOA_ODR
4083
+ group.PIOA.register.1=AT91C_PIOA_SODR
4084
+ group.PIOA.register.2=AT91C_PIOA_ISR
4085
+ group.PIOA.register.3=AT91C_PIOA_ABSR
4086
+ group.PIOA.register.4=AT91C_PIOA_IER
4087
+ group.PIOA.register.5=AT91C_PIOA_PPUDR
4088
+ group.PIOA.register.6=AT91C_PIOA_IMR
4089
+ group.PIOA.register.7=AT91C_PIOA_PER
4090
+ group.PIOA.register.8=AT91C_PIOA_IFDR
4091
+ group.PIOA.register.9=AT91C_PIOA_OWDR
4092
+ group.PIOA.register.10=AT91C_PIOA_MDSR
4093
+ group.PIOA.register.11=AT91C_PIOA_IDR
4094
+ group.PIOA.register.12=AT91C_PIOA_ODSR
4095
+ group.PIOA.register.13=AT91C_PIOA_PPUSR
4096
+ group.PIOA.register.14=AT91C_PIOA_OWSR
4097
+ group.PIOA.register.15=AT91C_PIOA_BSR
4098
+ group.PIOA.register.16=AT91C_PIOA_OWER
4099
+ group.PIOA.register.17=AT91C_PIOA_IFER
4100
+ group.PIOA.register.18=AT91C_PIOA_PDSR
4101
+ group.PIOA.register.19=AT91C_PIOA_PPUER
4102
+ group.PIOA.register.20=AT91C_PIOA_OSR
4103
+ group.PIOA.register.21=AT91C_PIOA_ASR
4104
+ group.PIOA.register.22=AT91C_PIOA_MDDR
4105
+ group.PIOA.register.23=AT91C_PIOA_CODR
4106
+ group.PIOA.register.24=AT91C_PIOA_MDER
4107
+ group.PIOA.register.25=AT91C_PIOA_PDR
4108
+ group.PIOA.register.26=AT91C_PIOA_IFSR
4109
+ group.PIOA.register.27=AT91C_PIOA_OER
4110
+ group.PIOA.register.28=AT91C_PIOA_PSR
4111
+ # ========== Group definition for PIOB peripheral ==========
4112
+ group.PIOB.description="ATMEL PIOB Registers"
4113
+ group.PIOB.helpkey="ATMEL PIOB Registers"
4114
+ group.PIOB.register.0=AT91C_PIOB_OWDR
4115
+ group.PIOB.register.1=AT91C_PIOB_MDER
4116
+ group.PIOB.register.2=AT91C_PIOB_PPUSR
4117
+ group.PIOB.register.3=AT91C_PIOB_IMR
4118
+ group.PIOB.register.4=AT91C_PIOB_ASR
4119
+ group.PIOB.register.5=AT91C_PIOB_PPUDR
4120
+ group.PIOB.register.6=AT91C_PIOB_PSR
4121
+ group.PIOB.register.7=AT91C_PIOB_IER
4122
+ group.PIOB.register.8=AT91C_PIOB_CODR
4123
+ group.PIOB.register.9=AT91C_PIOB_OWER
4124
+ group.PIOB.register.10=AT91C_PIOB_ABSR
4125
+ group.PIOB.register.11=AT91C_PIOB_IFDR
4126
+ group.PIOB.register.12=AT91C_PIOB_PDSR
4127
+ group.PIOB.register.13=AT91C_PIOB_IDR
4128
+ group.PIOB.register.14=AT91C_PIOB_OWSR
4129
+ group.PIOB.register.15=AT91C_PIOB_PDR
4130
+ group.PIOB.register.16=AT91C_PIOB_ODR
4131
+ group.PIOB.register.17=AT91C_PIOB_IFSR
4132
+ group.PIOB.register.18=AT91C_PIOB_PPUER
4133
+ group.PIOB.register.19=AT91C_PIOB_SODR
4134
+ group.PIOB.register.20=AT91C_PIOB_ISR
4135
+ group.PIOB.register.21=AT91C_PIOB_ODSR
4136
+ group.PIOB.register.22=AT91C_PIOB_OSR
4137
+ group.PIOB.register.23=AT91C_PIOB_MDSR
4138
+ group.PIOB.register.24=AT91C_PIOB_IFER
4139
+ group.PIOB.register.25=AT91C_PIOB_BSR
4140
+ group.PIOB.register.26=AT91C_PIOB_MDDR
4141
+ group.PIOB.register.27=AT91C_PIOB_OER
4142
+ group.PIOB.register.28=AT91C_PIOB_PER
4143
+ # ========== Group definition for CKGR peripheral ==========
4144
+ group.CKGR.description="ATMEL CKGR Registers"
4145
+ group.CKGR.helpkey="ATMEL CKGR Registers"
4146
+ group.CKGR.register.0=AT91C_CKGR_MOR
4147
+ group.CKGR.register.1=AT91C_CKGR_PLLR
4148
+ group.CKGR.register.2=AT91C_CKGR_MCFR
4149
+ # ========== Group definition for PMC peripheral ==========
4150
+ group.PMC.description="ATMEL PMC Registers"
4151
+ group.PMC.helpkey="ATMEL PMC Registers"
4152
+ group.PMC.register.0=AT91C_PMC_IDR
4153
+ group.PMC.register.1=AT91C_PMC_MOR
4154
+ group.PMC.register.2=AT91C_PMC_PLLR
4155
+ group.PMC.register.3=AT91C_PMC_PCER
4156
+ group.PMC.register.4=AT91C_PMC_PCKR
4157
+ group.PMC.register.5=AT91C_PMC_MCKR
4158
+ group.PMC.register.6=AT91C_PMC_SCDR
4159
+ group.PMC.register.7=AT91C_PMC_PCDR
4160
+ group.PMC.register.8=AT91C_PMC_SCSR
4161
+ group.PMC.register.9=AT91C_PMC_PCSR
4162
+ group.PMC.register.10=AT91C_PMC_MCFR
4163
+ group.PMC.register.11=AT91C_PMC_SCER
4164
+ group.PMC.register.12=AT91C_PMC_IMR
4165
+ group.PMC.register.13=AT91C_PMC_IER
4166
+ group.PMC.register.14=AT91C_PMC_SR
4167
+ # ========== Group definition for RSTC peripheral ==========
4168
+ group.RSTC.description="ATMEL RSTC Registers"
4169
+ group.RSTC.helpkey="ATMEL RSTC Registers"
4170
+ group.RSTC.register.0=AT91C_RSTC_RCR
4171
+ group.RSTC.register.1=AT91C_RSTC_RMR
4172
+ group.RSTC.register.2=AT91C_RSTC_RSR
4173
+ # ========== Group definition for RTTC peripheral ==========
4174
+ group.RTTC.description="ATMEL RTTC Registers"
4175
+ group.RTTC.helpkey="ATMEL RTTC Registers"
4176
+ group.RTTC.register.0=AT91C_RTTC_RTSR
4177
+ group.RTTC.register.1=AT91C_RTTC_RTMR
4178
+ group.RTTC.register.2=AT91C_RTTC_RTVR
4179
+ group.RTTC.register.3=AT91C_RTTC_RTAR
4180
+ # ========== Group definition for PITC peripheral ==========
4181
+ group.PITC.description="ATMEL PITC Registers"
4182
+ group.PITC.helpkey="ATMEL PITC Registers"
4183
+ group.PITC.register.0=AT91C_PITC_PIVR
4184
+ group.PITC.register.1=AT91C_PITC_PISR
4185
+ group.PITC.register.2=AT91C_PITC_PIIR
4186
+ group.PITC.register.3=AT91C_PITC_PIMR
4187
+ # ========== Group definition for WDTC peripheral ==========
4188
+ group.WDTC.description="ATMEL WDTC Registers"
4189
+ group.WDTC.helpkey="ATMEL WDTC Registers"
4190
+ group.WDTC.register.0=AT91C_WDTC_WDCR
4191
+ group.WDTC.register.1=AT91C_WDTC_WDSR
4192
+ group.WDTC.register.2=AT91C_WDTC_WDMR
4193
+ # ========== Group definition for VREG peripheral ==========
4194
+ group.VREG.description="ATMEL VREG Registers"
4195
+ group.VREG.helpkey="ATMEL VREG Registers"
4196
+ group.VREG.register.0=AT91C_VREG_MR
4197
+ # ========== Group definition for MC peripheral ==========
4198
+ group.MC.description="ATMEL MC Registers"
4199
+ group.MC.helpkey="ATMEL MC Registers"
4200
+ group.MC.register.0=AT91C_MC_ASR
4201
+ group.MC.register.1=AT91C_MC_RCR
4202
+ group.MC.register.2=AT91C_MC_FCR
4203
+ group.MC.register.3=AT91C_MC_AASR
4204
+ group.MC.register.4=AT91C_MC_FSR
4205
+ group.MC.register.5=AT91C_MC_FMR
4206
+ # ========== Group definition for PDC_SPI1 peripheral ==========
4207
+ group.PDC_SPI1.description="ATMEL PDC_SPI1 Registers"
4208
+ group.PDC_SPI1.helpkey="ATMEL PDC_SPI1 Registers"
4209
+ group.PDC_SPI1.register.0=AT91C_SPI1_PTCR
4210
+ group.PDC_SPI1.register.1=AT91C_SPI1_RPR
4211
+ group.PDC_SPI1.register.2=AT91C_SPI1_TNCR
4212
+ group.PDC_SPI1.register.3=AT91C_SPI1_TPR
4213
+ group.PDC_SPI1.register.4=AT91C_SPI1_TNPR
4214
+ group.PDC_SPI1.register.5=AT91C_SPI1_TCR
4215
+ group.PDC_SPI1.register.6=AT91C_SPI1_RCR
4216
+ group.PDC_SPI1.register.7=AT91C_SPI1_RNPR
4217
+ group.PDC_SPI1.register.8=AT91C_SPI1_RNCR
4218
+ group.PDC_SPI1.register.9=AT91C_SPI1_PTSR
4219
+ # ========== Group definition for SPI1 peripheral ==========
4220
+ group.SPI1.description="ATMEL SPI1 Registers"
4221
+ group.SPI1.helpkey="ATMEL SPI1 Registers"
4222
+ group.SPI1.register.0=AT91C_SPI1_IMR
4223
+ group.SPI1.register.1=AT91C_SPI1_IER
4224
+ group.SPI1.register.2=AT91C_SPI1_MR
4225
+ group.SPI1.register.3=AT91C_SPI1_RDR
4226
+ group.SPI1.register.4=AT91C_SPI1_IDR
4227
+ group.SPI1.register.5=AT91C_SPI1_SR
4228
+ group.SPI1.register.6=AT91C_SPI1_TDR
4229
+ group.SPI1.register.7=AT91C_SPI1_CR
4230
+ group.SPI1.register.8=AT91C_SPI1_CSR
4231
+ # ========== Group definition for PDC_SPI0 peripheral ==========
4232
+ group.PDC_SPI0.description="ATMEL PDC_SPI0 Registers"
4233
+ group.PDC_SPI0.helpkey="ATMEL PDC_SPI0 Registers"
4234
+ group.PDC_SPI0.register.0=AT91C_SPI0_PTCR
4235
+ group.PDC_SPI0.register.1=AT91C_SPI0_TPR
4236
+ group.PDC_SPI0.register.2=AT91C_SPI0_TCR
4237
+ group.PDC_SPI0.register.3=AT91C_SPI0_RCR
4238
+ group.PDC_SPI0.register.4=AT91C_SPI0_PTSR
4239
+ group.PDC_SPI0.register.5=AT91C_SPI0_RNPR
4240
+ group.PDC_SPI0.register.6=AT91C_SPI0_RPR
4241
+ group.PDC_SPI0.register.7=AT91C_SPI0_TNCR
4242
+ group.PDC_SPI0.register.8=AT91C_SPI0_RNCR
4243
+ group.PDC_SPI0.register.9=AT91C_SPI0_TNPR
4244
+ # ========== Group definition for SPI0 peripheral ==========
4245
+ group.SPI0.description="ATMEL SPI0 Registers"
4246
+ group.SPI0.helpkey="ATMEL SPI0 Registers"
4247
+ group.SPI0.register.0=AT91C_SPI0_IER
4248
+ group.SPI0.register.1=AT91C_SPI0_SR
4249
+ group.SPI0.register.2=AT91C_SPI0_IDR
4250
+ group.SPI0.register.3=AT91C_SPI0_CR
4251
+ group.SPI0.register.4=AT91C_SPI0_MR
4252
+ group.SPI0.register.5=AT91C_SPI0_IMR
4253
+ group.SPI0.register.6=AT91C_SPI0_TDR
4254
+ group.SPI0.register.7=AT91C_SPI0_RDR
4255
+ group.SPI0.register.8=AT91C_SPI0_CSR
4256
+ # ========== Group definition for PDC_US1 peripheral ==========
4257
+ group.PDC_US1.description="ATMEL PDC_US1 Registers"
4258
+ group.PDC_US1.helpkey="ATMEL PDC_US1 Registers"
4259
+ group.PDC_US1.register.0=AT91C_US1_RNCR
4260
+ group.PDC_US1.register.1=AT91C_US1_PTCR
4261
+ group.PDC_US1.register.2=AT91C_US1_TCR
4262
+ group.PDC_US1.register.3=AT91C_US1_PTSR
4263
+ group.PDC_US1.register.4=AT91C_US1_TNPR
4264
+ group.PDC_US1.register.5=AT91C_US1_RCR
4265
+ group.PDC_US1.register.6=AT91C_US1_RNPR
4266
+ group.PDC_US1.register.7=AT91C_US1_RPR
4267
+ group.PDC_US1.register.8=AT91C_US1_TNCR
4268
+ group.PDC_US1.register.9=AT91C_US1_TPR
4269
+ # ========== Group definition for US1 peripheral ==========
4270
+ group.US1.description="ATMEL US1 Registers"
4271
+ group.US1.helpkey="ATMEL US1 Registers"
4272
+ group.US1.register.0=AT91C_US1_IF
4273
+ group.US1.register.1=AT91C_US1_NER
4274
+ group.US1.register.2=AT91C_US1_RTOR
4275
+ group.US1.register.3=AT91C_US1_CSR
4276
+ group.US1.register.4=AT91C_US1_IDR
4277
+ group.US1.register.5=AT91C_US1_IER
4278
+ group.US1.register.6=AT91C_US1_THR
4279
+ group.US1.register.7=AT91C_US1_TTGR
4280
+ group.US1.register.8=AT91C_US1_RHR
4281
+ group.US1.register.9=AT91C_US1_BRGR
4282
+ group.US1.register.10=AT91C_US1_IMR
4283
+ group.US1.register.11=AT91C_US1_FIDI
4284
+ group.US1.register.12=AT91C_US1_CR
4285
+ group.US1.register.13=AT91C_US1_MR
4286
+ # ========== Group definition for PDC_US0 peripheral ==========
4287
+ group.PDC_US0.description="ATMEL PDC_US0 Registers"
4288
+ group.PDC_US0.helpkey="ATMEL PDC_US0 Registers"
4289
+ group.PDC_US0.register.0=AT91C_US0_TNPR
4290
+ group.PDC_US0.register.1=AT91C_US0_RNPR
4291
+ group.PDC_US0.register.2=AT91C_US0_TCR
4292
+ group.PDC_US0.register.3=AT91C_US0_PTCR
4293
+ group.PDC_US0.register.4=AT91C_US0_PTSR
4294
+ group.PDC_US0.register.5=AT91C_US0_TNCR
4295
+ group.PDC_US0.register.6=AT91C_US0_TPR
4296
+ group.PDC_US0.register.7=AT91C_US0_RCR
4297
+ group.PDC_US0.register.8=AT91C_US0_RPR
4298
+ group.PDC_US0.register.9=AT91C_US0_RNCR
4299
+ # ========== Group definition for US0 peripheral ==========
4300
+ group.US0.description="ATMEL US0 Registers"
4301
+ group.US0.helpkey="ATMEL US0 Registers"
4302
+ group.US0.register.0=AT91C_US0_BRGR
4303
+ group.US0.register.1=AT91C_US0_NER
4304
+ group.US0.register.2=AT91C_US0_CR
4305
+ group.US0.register.3=AT91C_US0_IMR
4306
+ group.US0.register.4=AT91C_US0_FIDI
4307
+ group.US0.register.5=AT91C_US0_TTGR
4308
+ group.US0.register.6=AT91C_US0_MR
4309
+ group.US0.register.7=AT91C_US0_RTOR
4310
+ group.US0.register.8=AT91C_US0_CSR
4311
+ group.US0.register.9=AT91C_US0_RHR
4312
+ group.US0.register.10=AT91C_US0_IDR
4313
+ group.US0.register.11=AT91C_US0_THR
4314
+ group.US0.register.12=AT91C_US0_IF
4315
+ group.US0.register.13=AT91C_US0_IER
4316
+ # ========== Group definition for PDC_SSC peripheral ==========
4317
+ group.PDC_SSC.description="ATMEL PDC_SSC Registers"
4318
+ group.PDC_SSC.helpkey="ATMEL PDC_SSC Registers"
4319
+ group.PDC_SSC.register.0=AT91C_SSC_TNCR
4320
+ group.PDC_SSC.register.1=AT91C_SSC_RPR
4321
+ group.PDC_SSC.register.2=AT91C_SSC_RNCR
4322
+ group.PDC_SSC.register.3=AT91C_SSC_TPR
4323
+ group.PDC_SSC.register.4=AT91C_SSC_PTCR
4324
+ group.PDC_SSC.register.5=AT91C_SSC_TCR
4325
+ group.PDC_SSC.register.6=AT91C_SSC_RCR
4326
+ group.PDC_SSC.register.7=AT91C_SSC_RNPR
4327
+ group.PDC_SSC.register.8=AT91C_SSC_TNPR
4328
+ group.PDC_SSC.register.9=AT91C_SSC_PTSR
4329
+ # ========== Group definition for SSC peripheral ==========
4330
+ group.SSC.description="ATMEL SSC Registers"
4331
+ group.SSC.helpkey="ATMEL SSC Registers"
4332
+ group.SSC.register.0=AT91C_SSC_RHR
4333
+ group.SSC.register.1=AT91C_SSC_RSHR
4334
+ group.SSC.register.2=AT91C_SSC_TFMR
4335
+ group.SSC.register.3=AT91C_SSC_IDR
4336
+ group.SSC.register.4=AT91C_SSC_THR
4337
+ group.SSC.register.5=AT91C_SSC_RCMR
4338
+ group.SSC.register.6=AT91C_SSC_IER
4339
+ group.SSC.register.7=AT91C_SSC_TSHR
4340
+ group.SSC.register.8=AT91C_SSC_SR
4341
+ group.SSC.register.9=AT91C_SSC_CMR
4342
+ group.SSC.register.10=AT91C_SSC_TCMR
4343
+ group.SSC.register.11=AT91C_SSC_CR
4344
+ group.SSC.register.12=AT91C_SSC_IMR
4345
+ group.SSC.register.13=AT91C_SSC_RFMR
4346
+ # ========== Group definition for TWI peripheral ==========
4347
+ group.TWI.description="ATMEL TWI Registers"
4348
+ group.TWI.helpkey="ATMEL TWI Registers"
4349
+ group.TWI.register.0=AT91C_TWI_IER
4350
+ group.TWI.register.1=AT91C_TWI_CR
4351
+ group.TWI.register.2=AT91C_TWI_SR
4352
+ group.TWI.register.3=AT91C_TWI_IMR
4353
+ group.TWI.register.4=AT91C_TWI_THR
4354
+ group.TWI.register.5=AT91C_TWI_IDR
4355
+ group.TWI.register.6=AT91C_TWI_IADR
4356
+ group.TWI.register.7=AT91C_TWI_MMR
4357
+ group.TWI.register.8=AT91C_TWI_CWGR
4358
+ group.TWI.register.9=AT91C_TWI_RHR
4359
+ # ========== Group definition for PWMC_CH3 peripheral ==========
4360
+ group.PWMC_CH3.description="ATMEL PWMC_CH3 Registers"
4361
+ group.PWMC_CH3.helpkey="ATMEL PWMC_CH3 Registers"
4362
+ group.PWMC_CH3.register.0=AT91C_PWMC_CH3_CUPDR
4363
+ group.PWMC_CH3.register.1=AT91C_PWMC_CH3_Reserved
4364
+ group.PWMC_CH3.register.2=AT91C_PWMC_CH3_CPRDR
4365
+ group.PWMC_CH3.register.3=AT91C_PWMC_CH3_CDTYR
4366
+ group.PWMC_CH3.register.4=AT91C_PWMC_CH3_CCNTR
4367
+ group.PWMC_CH3.register.5=AT91C_PWMC_CH3_CMR
4368
+ # ========== Group definition for PWMC_CH2 peripheral ==========
4369
+ group.PWMC_CH2.description="ATMEL PWMC_CH2 Registers"
4370
+ group.PWMC_CH2.helpkey="ATMEL PWMC_CH2 Registers"
4371
+ group.PWMC_CH2.register.0=AT91C_PWMC_CH2_Reserved
4372
+ group.PWMC_CH2.register.1=AT91C_PWMC_CH2_CMR
4373
+ group.PWMC_CH2.register.2=AT91C_PWMC_CH2_CCNTR
4374
+ group.PWMC_CH2.register.3=AT91C_PWMC_CH2_CPRDR
4375
+ group.PWMC_CH2.register.4=AT91C_PWMC_CH2_CUPDR
4376
+ group.PWMC_CH2.register.5=AT91C_PWMC_CH2_CDTYR
4377
+ # ========== Group definition for PWMC_CH1 peripheral ==========
4378
+ group.PWMC_CH1.description="ATMEL PWMC_CH1 Registers"
4379
+ group.PWMC_CH1.helpkey="ATMEL PWMC_CH1 Registers"
4380
+ group.PWMC_CH1.register.0=AT91C_PWMC_CH1_Reserved
4381
+ group.PWMC_CH1.register.1=AT91C_PWMC_CH1_CUPDR
4382
+ group.PWMC_CH1.register.2=AT91C_PWMC_CH1_CPRDR
4383
+ group.PWMC_CH1.register.3=AT91C_PWMC_CH1_CCNTR
4384
+ group.PWMC_CH1.register.4=AT91C_PWMC_CH1_CDTYR
4385
+ group.PWMC_CH1.register.5=AT91C_PWMC_CH1_CMR
4386
+ # ========== Group definition for PWMC_CH0 peripheral ==========
4387
+ group.PWMC_CH0.description="ATMEL PWMC_CH0 Registers"
4388
+ group.PWMC_CH0.helpkey="ATMEL PWMC_CH0 Registers"
4389
+ group.PWMC_CH0.register.0=AT91C_PWMC_CH0_Reserved
4390
+ group.PWMC_CH0.register.1=AT91C_PWMC_CH0_CPRDR
4391
+ group.PWMC_CH0.register.2=AT91C_PWMC_CH0_CDTYR
4392
+ group.PWMC_CH0.register.3=AT91C_PWMC_CH0_CMR
4393
+ group.PWMC_CH0.register.4=AT91C_PWMC_CH0_CUPDR
4394
+ group.PWMC_CH0.register.5=AT91C_PWMC_CH0_CCNTR
4395
+ # ========== Group definition for PWMC peripheral ==========
4396
+ group.PWMC.description="ATMEL PWMC Registers"
4397
+ group.PWMC.helpkey="ATMEL PWMC Registers"
4398
+ group.PWMC.register.0=AT91C_PWMC_IDR
4399
+ group.PWMC.register.1=AT91C_PWMC_DIS
4400
+ group.PWMC.register.2=AT91C_PWMC_IER
4401
+ group.PWMC.register.3=AT91C_PWMC_VR
4402
+ group.PWMC.register.4=AT91C_PWMC_ISR
4403
+ group.PWMC.register.5=AT91C_PWMC_SR
4404
+ group.PWMC.register.6=AT91C_PWMC_IMR
4405
+ group.PWMC.register.7=AT91C_PWMC_MR
4406
+ group.PWMC.register.8=AT91C_PWMC_ENA
4407
+ # ========== Group definition for UDP peripheral ==========
4408
+ group.UDP.description="ATMEL UDP Registers"
4409
+ group.UDP.helpkey="ATMEL UDP Registers"
4410
+ group.UDP.register.0=AT91C_UDP_IMR
4411
+ group.UDP.register.1=AT91C_UDP_FADDR
4412
+ group.UDP.register.2=AT91C_UDP_NUM
4413
+ group.UDP.register.3=AT91C_UDP_FDR
4414
+ group.UDP.register.4=AT91C_UDP_ISR
4415
+ group.UDP.register.5=AT91C_UDP_CSR
4416
+ group.UDP.register.6=AT91C_UDP_IDR
4417
+ group.UDP.register.7=AT91C_UDP_ICR
4418
+ group.UDP.register.8=AT91C_UDP_RSTEP
4419
+ group.UDP.register.9=AT91C_UDP_TXVC
4420
+ group.UDP.register.10=AT91C_UDP_GLBSTATE
4421
+ group.UDP.register.11=AT91C_UDP_IER
4422
+ # ========== Group definition for TC0 peripheral ==========
4423
+ group.TC0.description="ATMEL TC0 Registers"
4424
+ group.TC0.helpkey="ATMEL TC0 Registers"
4425
+ group.TC0.register.0=AT91C_TC0_SR
4426
+ group.TC0.register.1=AT91C_TC0_RC
4427
+ group.TC0.register.2=AT91C_TC0_RB
4428
+ group.TC0.register.3=AT91C_TC0_CCR
4429
+ group.TC0.register.4=AT91C_TC0_CMR
4430
+ group.TC0.register.5=AT91C_TC0_IER
4431
+ group.TC0.register.6=AT91C_TC0_RA
4432
+ group.TC0.register.7=AT91C_TC0_IDR
4433
+ group.TC0.register.8=AT91C_TC0_CV
4434
+ group.TC0.register.9=AT91C_TC0_IMR
4435
+ # ========== Group definition for TC1 peripheral ==========
4436
+ group.TC1.description="ATMEL TC1 Registers"
4437
+ group.TC1.helpkey="ATMEL TC1 Registers"
4438
+ group.TC1.register.0=AT91C_TC1_RB
4439
+ group.TC1.register.1=AT91C_TC1_CCR
4440
+ group.TC1.register.2=AT91C_TC1_IER
4441
+ group.TC1.register.3=AT91C_TC1_IDR
4442
+ group.TC1.register.4=AT91C_TC1_SR
4443
+ group.TC1.register.5=AT91C_TC1_CMR
4444
+ group.TC1.register.6=AT91C_TC1_RA
4445
+ group.TC1.register.7=AT91C_TC1_RC
4446
+ group.TC1.register.8=AT91C_TC1_IMR
4447
+ group.TC1.register.9=AT91C_TC1_CV
4448
+ # ========== Group definition for TC2 peripheral ==========
4449
+ group.TC2.description="ATMEL TC2 Registers"
4450
+ group.TC2.helpkey="ATMEL TC2 Registers"
4451
+ group.TC2.register.0=AT91C_TC2_CMR
4452
+ group.TC2.register.1=AT91C_TC2_CCR
4453
+ group.TC2.register.2=AT91C_TC2_CV
4454
+ group.TC2.register.3=AT91C_TC2_RA
4455
+ group.TC2.register.4=AT91C_TC2_RB
4456
+ group.TC2.register.5=AT91C_TC2_IDR
4457
+ group.TC2.register.6=AT91C_TC2_IMR
4458
+ group.TC2.register.7=AT91C_TC2_RC
4459
+ group.TC2.register.8=AT91C_TC2_IER
4460
+ group.TC2.register.9=AT91C_TC2_SR
4461
+ # ========== Group definition for TCB peripheral ==========
4462
+ group.TCB.description="ATMEL TCB Registers"
4463
+ group.TCB.helpkey="ATMEL TCB Registers"
4464
+ group.TCB.register.0=AT91C_TCB_BMR
4465
+ group.TCB.register.1=AT91C_TCB_BCR
4466
+ # ========== Group definition for CAN_MB0 peripheral ==========
4467
+ group.CAN_MB0.description="ATMEL CAN_MB0 Registers"
4468
+ group.CAN_MB0.helpkey="ATMEL CAN_MB0 Registers"
4469
+ group.CAN_MB0.register.0=AT91C_CAN_MB0_MDL
4470
+ group.CAN_MB0.register.1=AT91C_CAN_MB0_MAM
4471
+ group.CAN_MB0.register.2=AT91C_CAN_MB0_MCR
4472
+ group.CAN_MB0.register.3=AT91C_CAN_MB0_MID
4473
+ group.CAN_MB0.register.4=AT91C_CAN_MB0_MSR
4474
+ group.CAN_MB0.register.5=AT91C_CAN_MB0_MFID
4475
+ group.CAN_MB0.register.6=AT91C_CAN_MB0_MDH
4476
+ group.CAN_MB0.register.7=AT91C_CAN_MB0_MMR
4477
+ # ========== Group definition for CAN_MB1 peripheral ==========
4478
+ group.CAN_MB1.description="ATMEL CAN_MB1 Registers"
4479
+ group.CAN_MB1.helpkey="ATMEL CAN_MB1 Registers"
4480
+ group.CAN_MB1.register.0=AT91C_CAN_MB1_MDL
4481
+ group.CAN_MB1.register.1=AT91C_CAN_MB1_MID
4482
+ group.CAN_MB1.register.2=AT91C_CAN_MB1_MMR
4483
+ group.CAN_MB1.register.3=AT91C_CAN_MB1_MSR
4484
+ group.CAN_MB1.register.4=AT91C_CAN_MB1_MAM
4485
+ group.CAN_MB1.register.5=AT91C_CAN_MB1_MDH
4486
+ group.CAN_MB1.register.6=AT91C_CAN_MB1_MCR
4487
+ group.CAN_MB1.register.7=AT91C_CAN_MB1_MFID
4488
+ # ========== Group definition for CAN_MB2 peripheral ==========
4489
+ group.CAN_MB2.description="ATMEL CAN_MB2 Registers"
4490
+ group.CAN_MB2.helpkey="ATMEL CAN_MB2 Registers"
4491
+ group.CAN_MB2.register.0=AT91C_CAN_MB2_MCR
4492
+ group.CAN_MB2.register.1=AT91C_CAN_MB2_MDH
4493
+ group.CAN_MB2.register.2=AT91C_CAN_MB2_MID
4494
+ group.CAN_MB2.register.3=AT91C_CAN_MB2_MDL
4495
+ group.CAN_MB2.register.4=AT91C_CAN_MB2_MMR
4496
+ group.CAN_MB2.register.5=AT91C_CAN_MB2_MAM
4497
+ group.CAN_MB2.register.6=AT91C_CAN_MB2_MFID
4498
+ group.CAN_MB2.register.7=AT91C_CAN_MB2_MSR
4499
+ # ========== Group definition for CAN_MB3 peripheral ==========
4500
+ group.CAN_MB3.description="ATMEL CAN_MB3 Registers"
4501
+ group.CAN_MB3.helpkey="ATMEL CAN_MB3 Registers"
4502
+ group.CAN_MB3.register.0=AT91C_CAN_MB3_MFID
4503
+ group.CAN_MB3.register.1=AT91C_CAN_MB3_MAM
4504
+ group.CAN_MB3.register.2=AT91C_CAN_MB3_MID
4505
+ group.CAN_MB3.register.3=AT91C_CAN_MB3_MCR
4506
+ group.CAN_MB3.register.4=AT91C_CAN_MB3_MMR
4507
+ group.CAN_MB3.register.5=AT91C_CAN_MB3_MSR
4508
+ group.CAN_MB3.register.6=AT91C_CAN_MB3_MDL
4509
+ group.CAN_MB3.register.7=AT91C_CAN_MB3_MDH
4510
+ # ========== Group definition for CAN_MB4 peripheral ==========
4511
+ group.CAN_MB4.description="ATMEL CAN_MB4 Registers"
4512
+ group.CAN_MB4.helpkey="ATMEL CAN_MB4 Registers"
4513
+ group.CAN_MB4.register.0=AT91C_CAN_MB4_MID
4514
+ group.CAN_MB4.register.1=AT91C_CAN_MB4_MMR
4515
+ group.CAN_MB4.register.2=AT91C_CAN_MB4_MDH
4516
+ group.CAN_MB4.register.3=AT91C_CAN_MB4_MFID
4517
+ group.CAN_MB4.register.4=AT91C_CAN_MB4_MSR
4518
+ group.CAN_MB4.register.5=AT91C_CAN_MB4_MCR
4519
+ group.CAN_MB4.register.6=AT91C_CAN_MB4_MDL
4520
+ group.CAN_MB4.register.7=AT91C_CAN_MB4_MAM
4521
+ # ========== Group definition for CAN_MB5 peripheral ==========
4522
+ group.CAN_MB5.description="ATMEL CAN_MB5 Registers"
4523
+ group.CAN_MB5.helpkey="ATMEL CAN_MB5 Registers"
4524
+ group.CAN_MB5.register.0=AT91C_CAN_MB5_MSR
4525
+ group.CAN_MB5.register.1=AT91C_CAN_MB5_MCR
4526
+ group.CAN_MB5.register.2=AT91C_CAN_MB5_MFID
4527
+ group.CAN_MB5.register.3=AT91C_CAN_MB5_MDH
4528
+ group.CAN_MB5.register.4=AT91C_CAN_MB5_MID
4529
+ group.CAN_MB5.register.5=AT91C_CAN_MB5_MMR
4530
+ group.CAN_MB5.register.6=AT91C_CAN_MB5_MDL
4531
+ group.CAN_MB5.register.7=AT91C_CAN_MB5_MAM
4532
+ # ========== Group definition for CAN_MB6 peripheral ==========
4533
+ group.CAN_MB6.description="ATMEL CAN_MB6 Registers"
4534
+ group.CAN_MB6.helpkey="ATMEL CAN_MB6 Registers"
4535
+ group.CAN_MB6.register.0=AT91C_CAN_MB6_MFID
4536
+ group.CAN_MB6.register.1=AT91C_CAN_MB6_MID
4537
+ group.CAN_MB6.register.2=AT91C_CAN_MB6_MAM
4538
+ group.CAN_MB6.register.3=AT91C_CAN_MB6_MSR
4539
+ group.CAN_MB6.register.4=AT91C_CAN_MB6_MDL
4540
+ group.CAN_MB6.register.5=AT91C_CAN_MB6_MCR
4541
+ group.CAN_MB6.register.6=AT91C_CAN_MB6_MDH
4542
+ group.CAN_MB6.register.7=AT91C_CAN_MB6_MMR
4543
+ # ========== Group definition for CAN_MB7 peripheral ==========
4544
+ group.CAN_MB7.description="ATMEL CAN_MB7 Registers"
4545
+ group.CAN_MB7.helpkey="ATMEL CAN_MB7 Registers"
4546
+ group.CAN_MB7.register.0=AT91C_CAN_MB7_MCR
4547
+ group.CAN_MB7.register.1=AT91C_CAN_MB7_MDH
4548
+ group.CAN_MB7.register.2=AT91C_CAN_MB7_MFID
4549
+ group.CAN_MB7.register.3=AT91C_CAN_MB7_MDL
4550
+ group.CAN_MB7.register.4=AT91C_CAN_MB7_MID
4551
+ group.CAN_MB7.register.5=AT91C_CAN_MB7_MMR
4552
+ group.CAN_MB7.register.6=AT91C_CAN_MB7_MAM
4553
+ group.CAN_MB7.register.7=AT91C_CAN_MB7_MSR
4554
+ # ========== Group definition for CAN peripheral ==========
4555
+ group.CAN.description="ATMEL CAN Registers"
4556
+ group.CAN.helpkey="ATMEL CAN Registers"
4557
+ group.CAN.register.0=AT91C_CAN_TCR
4558
+ group.CAN.register.1=AT91C_CAN_IMR
4559
+ group.CAN.register.2=AT91C_CAN_IER
4560
+ group.CAN.register.3=AT91C_CAN_ECR
4561
+ group.CAN.register.4=AT91C_CAN_TIMESTP
4562
+ group.CAN.register.5=AT91C_CAN_MR
4563
+ group.CAN.register.6=AT91C_CAN_IDR
4564
+ group.CAN.register.7=AT91C_CAN_ACR
4565
+ group.CAN.register.8=AT91C_CAN_TIM
4566
+ group.CAN.register.9=AT91C_CAN_SR
4567
+ group.CAN.register.10=AT91C_CAN_BR
4568
+ group.CAN.register.11=AT91C_CAN_VR
4569
+ # ========== Group definition for EMAC peripheral ==========
4570
+ group.EMAC.description="ATMEL EMAC Registers"
4571
+ group.EMAC.helpkey="ATMEL EMAC Registers"
4572
+ group.EMAC.register.0=AT91C_EMAC_ISR
4573
+ group.EMAC.register.1=AT91C_EMAC_SA4H
4574
+ group.EMAC.register.2=AT91C_EMAC_SA1L
4575
+ group.EMAC.register.3=AT91C_EMAC_ELE
4576
+ group.EMAC.register.4=AT91C_EMAC_LCOL
4577
+ group.EMAC.register.5=AT91C_EMAC_RLE
4578
+ group.EMAC.register.6=AT91C_EMAC_WOL
4579
+ group.EMAC.register.7=AT91C_EMAC_DTF
4580
+ group.EMAC.register.8=AT91C_EMAC_TUND
4581
+ group.EMAC.register.9=AT91C_EMAC_NCR
4582
+ group.EMAC.register.10=AT91C_EMAC_SA4L
4583
+ group.EMAC.register.11=AT91C_EMAC_RSR
4584
+ group.EMAC.register.12=AT91C_EMAC_SA3L
4585
+ group.EMAC.register.13=AT91C_EMAC_TSR
4586
+ group.EMAC.register.14=AT91C_EMAC_IDR
4587
+ group.EMAC.register.15=AT91C_EMAC_RSE
4588
+ group.EMAC.register.16=AT91C_EMAC_ECOL
4589
+ group.EMAC.register.17=AT91C_EMAC_TID
4590
+ group.EMAC.register.18=AT91C_EMAC_HRB
4591
+ group.EMAC.register.19=AT91C_EMAC_TBQP
4592
+ group.EMAC.register.20=AT91C_EMAC_USRIO
4593
+ group.EMAC.register.21=AT91C_EMAC_PTR
4594
+ group.EMAC.register.22=AT91C_EMAC_SA2H
4595
+ group.EMAC.register.23=AT91C_EMAC_ROV
4596
+ group.EMAC.register.24=AT91C_EMAC_ALE
4597
+ group.EMAC.register.25=AT91C_EMAC_RJA
4598
+ group.EMAC.register.26=AT91C_EMAC_RBQP
4599
+ group.EMAC.register.27=AT91C_EMAC_TPF
4600
+ group.EMAC.register.28=AT91C_EMAC_NCFGR
4601
+ group.EMAC.register.29=AT91C_EMAC_HRT
4602
+ group.EMAC.register.30=AT91C_EMAC_USF
4603
+ group.EMAC.register.31=AT91C_EMAC_FCSE
4604
+ group.EMAC.register.32=AT91C_EMAC_TPQ
4605
+ group.EMAC.register.33=AT91C_EMAC_MAN
4606
+ group.EMAC.register.34=AT91C_EMAC_FTO
4607
+ group.EMAC.register.35=AT91C_EMAC_REV
4608
+ group.EMAC.register.36=AT91C_EMAC_IMR
4609
+ group.EMAC.register.37=AT91C_EMAC_SCF
4610
+ group.EMAC.register.38=AT91C_EMAC_PFR
4611
+ group.EMAC.register.39=AT91C_EMAC_MCF
4612
+ group.EMAC.register.40=AT91C_EMAC_NSR
4613
+ group.EMAC.register.41=AT91C_EMAC_SA2L
4614
+ group.EMAC.register.42=AT91C_EMAC_FRO
4615
+ group.EMAC.register.43=AT91C_EMAC_IER
4616
+ group.EMAC.register.44=AT91C_EMAC_SA1H
4617
+ group.EMAC.register.45=AT91C_EMAC_CSE
4618
+ group.EMAC.register.46=AT91C_EMAC_SA3H
4619
+ group.EMAC.register.47=AT91C_EMAC_RRE
4620
+ group.EMAC.register.48=AT91C_EMAC_STE
4621
+ # ========== Group definition for PDC_ADC peripheral ==========
4622
+ group.PDC_ADC.description="ATMEL PDC_ADC Registers"
4623
+ group.PDC_ADC.helpkey="ATMEL PDC_ADC Registers"
4624
+ group.PDC_ADC.register.0=AT91C_ADC_PTSR
4625
+ group.PDC_ADC.register.1=AT91C_ADC_PTCR
4626
+ group.PDC_ADC.register.2=AT91C_ADC_TNPR
4627
+ group.PDC_ADC.register.3=AT91C_ADC_TNCR
4628
+ group.PDC_ADC.register.4=AT91C_ADC_RNPR
4629
+ group.PDC_ADC.register.5=AT91C_ADC_RNCR
4630
+ group.PDC_ADC.register.6=AT91C_ADC_RPR
4631
+ group.PDC_ADC.register.7=AT91C_ADC_TCR
4632
+ group.PDC_ADC.register.8=AT91C_ADC_TPR
4633
+ group.PDC_ADC.register.9=AT91C_ADC_RCR
4634
+ # ========== Group definition for ADC peripheral ==========
4635
+ group.ADC.description="ATMEL ADC Registers"
4636
+ group.ADC.helpkey="ATMEL ADC Registers"
4637
+ group.ADC.register.0=AT91C_ADC_CDR2
4638
+ group.ADC.register.1=AT91C_ADC_CDR3
4639
+ group.ADC.register.2=AT91C_ADC_CDR0
4640
+ group.ADC.register.3=AT91C_ADC_CDR5
4641
+ group.ADC.register.4=AT91C_ADC_CHDR
4642
+ group.ADC.register.5=AT91C_ADC_SR
4643
+ group.ADC.register.6=AT91C_ADC_CDR4
4644
+ group.ADC.register.7=AT91C_ADC_CDR1
4645
+ group.ADC.register.8=AT91C_ADC_LCDR
4646
+ group.ADC.register.9=AT91C_ADC_IDR
4647
+ group.ADC.register.10=AT91C_ADC_CR
4648
+ group.ADC.register.11=AT91C_ADC_CDR7
4649
+ group.ADC.register.12=AT91C_ADC_CDR6
4650
+ group.ADC.register.13=AT91C_ADC_IER
4651
+ group.ADC.register.14=AT91C_ADC_CHER
4652
+ group.ADC.register.15=AT91C_ADC_CHSR
4653
+ group.ADC.register.16=AT91C_ADC_MR
4654
+ group.ADC.register.17=AT91C_ADC_IMR
4655
+ group.AT91SAM7X256.description="ATMEL AT91SAM7X256 Registers"
4656
+ group.AT91SAM7X256.helpkey="ATMEL AT91SAM7X256 Registers"
4657
+ group.AT91SAM7X256.topLevelIndex=100
4658
+ group.AT91SAM7X256.group.0=SYS
4659
+ group.AT91SAM7X256.group.1=AIC
4660
+ group.AT91SAM7X256.group.2=PDC_DBGU
4661
+ group.AT91SAM7X256.group.3=DBGU
4662
+ group.AT91SAM7X256.group.4=PIOA
4663
+ group.AT91SAM7X256.group.5=PIOB
4664
+ group.AT91SAM7X256.group.6=CKGR
4665
+ group.AT91SAM7X256.group.7=PMC
4666
+ group.AT91SAM7X256.group.8=RSTC
4667
+ group.AT91SAM7X256.group.9=RTTC
4668
+ group.AT91SAM7X256.group.10=PITC
4669
+ group.AT91SAM7X256.group.11=WDTC
4670
+ group.AT91SAM7X256.group.12=VREG
4671
+ group.AT91SAM7X256.group.13=MC
4672
+ group.AT91SAM7X256.group.14=PDC_SPI1
4673
+ group.AT91SAM7X256.group.15=SPI1
4674
+ group.AT91SAM7X256.group.16=PDC_SPI0
4675
+ group.AT91SAM7X256.group.17=SPI0
4676
+ group.AT91SAM7X256.group.18=PDC_US1
4677
+ group.AT91SAM7X256.group.19=US1
4678
+ group.AT91SAM7X256.group.20=PDC_US0
4679
+ group.AT91SAM7X256.group.21=US0
4680
+ group.AT91SAM7X256.group.22=PDC_SSC
4681
+ group.AT91SAM7X256.group.23=SSC
4682
+ group.AT91SAM7X256.group.24=TWI
4683
+ group.AT91SAM7X256.group.25=PWMC_CH3
4684
+ group.AT91SAM7X256.group.26=PWMC_CH2
4685
+ group.AT91SAM7X256.group.27=PWMC_CH1
4686
+ group.AT91SAM7X256.group.28=PWMC_CH0
4687
+ group.AT91SAM7X256.group.29=PWMC
4688
+ group.AT91SAM7X256.group.30=UDP
4689
+ group.AT91SAM7X256.group.31=TC0
4690
+ group.AT91SAM7X256.group.32=TC1
4691
+ group.AT91SAM7X256.group.33=TC2
4692
+ group.AT91SAM7X256.group.34=TCB
4693
+ group.AT91SAM7X256.group.35=CAN_MB0
4694
+ group.AT91SAM7X256.group.36=CAN_MB1
4695
+ group.AT91SAM7X256.group.37=CAN_MB2
4696
+ group.AT91SAM7X256.group.38=CAN_MB3
4697
+ group.AT91SAM7X256.group.39=CAN_MB4
4698
+ group.AT91SAM7X256.group.40=CAN_MB5
4699
+ group.AT91SAM7X256.group.41=CAN_MB6
4700
+ group.AT91SAM7X256.group.42=CAN_MB7
4701
+ group.AT91SAM7X256.group.43=CAN
4702
+ group.AT91SAM7X256.group.44=EMAC
4703
+ group.AT91SAM7X256.group.45=PDC_ADC
4704
+ group.AT91SAM7X256.group.46=ADC