HDLRuby 2.0.8
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +7 -0
- data/.gitignore +9 -0
- data/.travis.yml +5 -0
- data/.yardopts +1 -0
- data/Gemfile +4 -0
- data/HDLRuby.gemspec +36 -0
- data/LICENSE.txt +21 -0
- data/README.md +2774 -0
- data/README.pdf +0 -0
- data/Rakefile +10 -0
- data/bin/console +14 -0
- data/bin/setup +8 -0
- data/exe/hdrcc +3 -0
- data/lib/HDLRuby/alcc.rb +137 -0
- data/lib/HDLRuby/backend/hruby_allocator.rb +69 -0
- data/lib/HDLRuby/backend/hruby_c_allocator.rb +76 -0
- data/lib/HDLRuby/hdr_samples/adder.rb +7 -0
- data/lib/HDLRuby/hdr_samples/adder_assign_error.rb +11 -0
- data/lib/HDLRuby/hdr_samples/adder_bench.rb +27 -0
- data/lib/HDLRuby/hdr_samples/adder_gen.rb +7 -0
- data/lib/HDLRuby/hdr_samples/adder_nodef_error.rb +7 -0
- data/lib/HDLRuby/hdr_samples/addsub.rb +19 -0
- data/lib/HDLRuby/hdr_samples/addsubz.rb +22 -0
- data/lib/HDLRuby/hdr_samples/alu.rb +47 -0
- data/lib/HDLRuby/hdr_samples/calculator.rb +48 -0
- data/lib/HDLRuby/hdr_samples/counter_bench.rb +83 -0
- data/lib/HDLRuby/hdr_samples/dff.rb +9 -0
- data/lib/HDLRuby/hdr_samples/dff_bench.rb +66 -0
- data/lib/HDLRuby/hdr_samples/dff_counter.rb +20 -0
- data/lib/HDLRuby/hdr_samples/include.rb +14 -0
- data/lib/HDLRuby/hdr_samples/instance_open.rb +23 -0
- data/lib/HDLRuby/hdr_samples/mei8.rb +256 -0
- data/lib/HDLRuby/hdr_samples/mei8_bench.rb +309 -0
- data/lib/HDLRuby/hdr_samples/multer_gen.rb +8 -0
- data/lib/HDLRuby/hdr_samples/multer_seq.rb +29 -0
- data/lib/HDLRuby/hdr_samples/neural/a.rb +9 -0
- data/lib/HDLRuby/hdr_samples/neural/a_sub.rb +5 -0
- data/lib/HDLRuby/hdr_samples/neural/bw.rb +23 -0
- data/lib/HDLRuby/hdr_samples/neural/counter.rb +16 -0
- data/lib/HDLRuby/hdr_samples/neural/dadz.rb +9 -0
- data/lib/HDLRuby/hdr_samples/neural/dadz_sub.rb +4 -0
- data/lib/HDLRuby/hdr_samples/neural/forward.rb +153 -0
- data/lib/HDLRuby/hdr_samples/neural/forward_sub.rb +62 -0
- data/lib/HDLRuby/hdr_samples/neural/forward_sub_rand.rb +41 -0
- data/lib/HDLRuby/hdr_samples/neural/forward_sub_rand_typedef.rb +47 -0
- data/lib/HDLRuby/hdr_samples/neural/mem.rb +30 -0
- data/lib/HDLRuby/hdr_samples/neural/random.rb +23 -0
- data/lib/HDLRuby/hdr_samples/neural/selector.rb +29 -0
- data/lib/HDLRuby/hdr_samples/neural/sigmoid.rb +20 -0
- data/lib/HDLRuby/hdr_samples/neural/z.rb +33 -0
- data/lib/HDLRuby/hdr_samples/prog.obj +256 -0
- data/lib/HDLRuby/hdr_samples/ram.rb +18 -0
- data/lib/HDLRuby/hdr_samples/register_with_code_bench.rb +98 -0
- data/lib/HDLRuby/hdr_samples/rom.rb +10 -0
- data/lib/HDLRuby/hdr_samples/struct.rb +14 -0
- data/lib/HDLRuby/hdr_samples/sumprod.rb +29 -0
- data/lib/HDLRuby/hdr_samples/sw_encrypt_bench.rb +103 -0
- data/lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb +261 -0
- data/lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb +302 -0
- data/lib/HDLRuby/hdr_samples/system_open.rb +11 -0
- data/lib/HDLRuby/hdr_samples/tuple.rb +16 -0
- data/lib/HDLRuby/hdr_samples/with_channel.rb +118 -0
- data/lib/HDLRuby/hdr_samples/with_class.rb +199 -0
- data/lib/HDLRuby/hdr_samples/with_decoder.rb +17 -0
- data/lib/HDLRuby/hdr_samples/with_fsm.rb +34 -0
- data/lib/HDLRuby/hdr_samples/with_reconf.rb +103 -0
- data/lib/HDLRuby/hdrcc.rb +623 -0
- data/lib/HDLRuby/high_samples/_adder_fault.rb +23 -0
- data/lib/HDLRuby/high_samples/_generic_transmission2.rb +146 -0
- data/lib/HDLRuby/high_samples/adder.rb +21 -0
- data/lib/HDLRuby/high_samples/adder_common_errors.rb +25 -0
- data/lib/HDLRuby/high_samples/addsub.rb +33 -0
- data/lib/HDLRuby/high_samples/addsubz.rb +37 -0
- data/lib/HDLRuby/high_samples/after.rb +28 -0
- data/lib/HDLRuby/high_samples/all_signals.rb +29 -0
- data/lib/HDLRuby/high_samples/alu.rb +61 -0
- data/lib/HDLRuby/high_samples/anonymous.rb +41 -0
- data/lib/HDLRuby/high_samples/before.rb +28 -0
- data/lib/HDLRuby/high_samples/blockblock.rb +26 -0
- data/lib/HDLRuby/high_samples/bugs/dadz.rb +22 -0
- data/lib/HDLRuby/high_samples/bugs/misample_instan.rb +20 -0
- data/lib/HDLRuby/high_samples/bugs/misample_updown.rb +22 -0
- data/lib/HDLRuby/high_samples/bugs/sample_add.rb +16 -0
- data/lib/HDLRuby/high_samples/bugs/sample_barrel.rb +13 -0
- data/lib/HDLRuby/high_samples/bugs/sample_daice.rb +57 -0
- data/lib/HDLRuby/high_samples/bugs/sample_kumiawase.rb +52 -0
- data/lib/HDLRuby/high_samples/bugs/sample_multi.rb +18 -0
- data/lib/HDLRuby/high_samples/bugs/sample_sub.rb +14 -0
- data/lib/HDLRuby/high_samples/bugs/z2.rb +32 -0
- data/lib/HDLRuby/high_samples/case.rb +32 -0
- data/lib/HDLRuby/high_samples/case2.rb +30 -0
- data/lib/HDLRuby/high_samples/change.rb +23 -0
- data/lib/HDLRuby/high_samples/clocks.rb +35 -0
- data/lib/HDLRuby/high_samples/comparer.rb +21 -0
- data/lib/HDLRuby/high_samples/conditionals.rb +29 -0
- data/lib/HDLRuby/high_samples/dff.rb +23 -0
- data/lib/HDLRuby/high_samples/each.rb +28 -0
- data/lib/HDLRuby/high_samples/exporter.rb +42 -0
- data/lib/HDLRuby/high_samples/functions.rb +60 -0
- data/lib/HDLRuby/high_samples/if_seq.rb +26 -0
- data/lib/HDLRuby/high_samples/inherit_as_dff.rb +32 -0
- data/lib/HDLRuby/high_samples/inherit_dff.rb +36 -0
- data/lib/HDLRuby/high_samples/instance.rb +37 -0
- data/lib/HDLRuby/high_samples/memory.rb +64 -0
- data/lib/HDLRuby/high_samples/multi_file.rb +27 -0
- data/lib/HDLRuby/high_samples/overload.rb +32 -0
- data/lib/HDLRuby/high_samples/paper_after.rb +49 -0
- data/lib/HDLRuby/high_samples/ram.rb +27 -0
- data/lib/HDLRuby/high_samples/registers.rb +139 -0
- data/lib/HDLRuby/high_samples/rom.rb +23 -0
- data/lib/HDLRuby/high_samples/scopeblockname.rb +37 -0
- data/lib/HDLRuby/high_samples/scopescope.rb +26 -0
- data/lib/HDLRuby/high_samples/shift.rb +31 -0
- data/lib/HDLRuby/high_samples/shift2.rb +40 -0
- data/lib/HDLRuby/high_samples/simple_instance.rb +31 -0
- data/lib/HDLRuby/high_samples/test_all.sh +10 -0
- data/lib/HDLRuby/high_samples/typedef.rb +24 -0
- data/lib/HDLRuby/high_samples/values.rb +70 -0
- data/lib/HDLRuby/high_samples/vector.rb +22 -0
- data/lib/HDLRuby/high_samples/with_decoder.rb +30 -0
- data/lib/HDLRuby/high_samples/with_fsm.rb +46 -0
- data/lib/HDLRuby/high_samples/with_pipe.rb +43 -0
- data/lib/HDLRuby/high_samples/with_seq.rb +25 -0
- data/lib/HDLRuby/hruby_bstr.rb +1085 -0
- data/lib/HDLRuby/hruby_check.rb +317 -0
- data/lib/HDLRuby/hruby_db.rb +432 -0
- data/lib/HDLRuby/hruby_error.rb +44 -0
- data/lib/HDLRuby/hruby_high.rb +4103 -0
- data/lib/HDLRuby/hruby_low.rb +4735 -0
- data/lib/HDLRuby/hruby_low2c.rb +1986 -0
- data/lib/HDLRuby/hruby_low2high.rb +738 -0
- data/lib/HDLRuby/hruby_low2seq.rb +248 -0
- data/lib/HDLRuby/hruby_low2sym.rb +126 -0
- data/lib/HDLRuby/hruby_low2vhd.rb +1437 -0
- data/lib/HDLRuby/hruby_low_bool2select.rb +295 -0
- data/lib/HDLRuby/hruby_low_cleanup.rb +193 -0
- data/lib/HDLRuby/hruby_low_fix_types.rb +437 -0
- data/lib/HDLRuby/hruby_low_mutable.rb +1803 -0
- data/lib/HDLRuby/hruby_low_resolve.rb +165 -0
- data/lib/HDLRuby/hruby_low_skeleton.rb +129 -0
- data/lib/HDLRuby/hruby_low_with_bool.rb +141 -0
- data/lib/HDLRuby/hruby_low_with_port.rb +167 -0
- data/lib/HDLRuby/hruby_low_with_var.rb +302 -0
- data/lib/HDLRuby/hruby_low_without_bit2vector.rb +88 -0
- data/lib/HDLRuby/hruby_low_without_concat.rb +162 -0
- data/lib/HDLRuby/hruby_low_without_connection.rb +113 -0
- data/lib/HDLRuby/hruby_low_without_namespace.rb +718 -0
- data/lib/HDLRuby/hruby_low_without_outread.rb +107 -0
- data/lib/HDLRuby/hruby_low_without_select.rb +206 -0
- data/lib/HDLRuby/hruby_serializer.rb +398 -0
- data/lib/HDLRuby/hruby_tools.rb +37 -0
- data/lib/HDLRuby/hruby_types.rb +239 -0
- data/lib/HDLRuby/hruby_values.rb +64 -0
- data/lib/HDLRuby/hruby_verilog.rb +1888 -0
- data/lib/HDLRuby/hruby_verilog_name.rb +52 -0
- data/lib/HDLRuby/low_samples/adder.yaml +97 -0
- data/lib/HDLRuby/low_samples/after.yaml +228 -0
- data/lib/HDLRuby/low_samples/before.yaml +223 -0
- data/lib/HDLRuby/low_samples/blockblock.yaml +48 -0
- data/lib/HDLRuby/low_samples/bugs/sample_add.yaml +97 -0
- data/lib/HDLRuby/low_samples/bugs/sample_daice.yaml +444 -0
- data/lib/HDLRuby/low_samples/bugs/sample_kumiawase.yaml +332 -0
- data/lib/HDLRuby/low_samples/bugs/sample_sub.yaml +97 -0
- data/lib/HDLRuby/low_samples/bugs/seqpar.yaml +184 -0
- data/lib/HDLRuby/low_samples/case.yaml +327 -0
- data/lib/HDLRuby/low_samples/change.yaml +135 -0
- data/lib/HDLRuby/low_samples/clocks.yaml +674 -0
- data/lib/HDLRuby/low_samples/cloner.rb +22 -0
- data/lib/HDLRuby/low_samples/comparer.yaml +85 -0
- data/lib/HDLRuby/low_samples/conditionals.yaml +133 -0
- data/lib/HDLRuby/low_samples/dff.yaml +107 -0
- data/lib/HDLRuby/low_samples/each.yaml +1328 -0
- data/lib/HDLRuby/low_samples/exporter.yaml +226 -0
- data/lib/HDLRuby/low_samples/functions.yaml +298 -0
- data/lib/HDLRuby/low_samples/generic_transmission.yaml +597 -0
- data/lib/HDLRuby/low_samples/inherit_as_dff.yaml +125 -0
- data/lib/HDLRuby/low_samples/inherit_dff.yaml +107 -0
- data/lib/HDLRuby/low_samples/load_yaml.rb +11 -0
- data/lib/HDLRuby/low_samples/memory.yaml +678 -0
- data/lib/HDLRuby/low_samples/namespace_extractor.rb +23 -0
- data/lib/HDLRuby/low_samples/overload.yaml +226 -0
- data/lib/HDLRuby/low_samples/paper_after.yaml +431 -0
- data/lib/HDLRuby/low_samples/port_maker.rb +14 -0
- data/lib/HDLRuby/low_samples/ram.yaml +207 -0
- data/lib/HDLRuby/low_samples/registers.yaml +228 -0
- data/lib/HDLRuby/low_samples/rom.yaml +2950 -0
- data/lib/HDLRuby/low_samples/shift.yaml +230 -0
- data/lib/HDLRuby/low_samples/shift2.yaml +2095 -0
- data/lib/HDLRuby/low_samples/simple_instance.yaml +102 -0
- data/lib/HDLRuby/low_samples/test_all.sh +43 -0
- data/lib/HDLRuby/low_samples/typedef.yaml +115 -0
- data/lib/HDLRuby/low_samples/values.yaml +577 -0
- data/lib/HDLRuby/low_samples/variable_maker.rb +14 -0
- data/lib/HDLRuby/low_samples/vector.yaml +56 -0
- data/lib/HDLRuby/low_samples/with_seq.yaml +188 -0
- data/lib/HDLRuby/low_samples/yaml2hdr.rb +10 -0
- data/lib/HDLRuby/low_samples/yaml2vhd.rb +19 -0
- data/lib/HDLRuby/sim/Makefile +19 -0
- data/lib/HDLRuby/sim/hruby_sim.h +590 -0
- data/lib/HDLRuby/sim/hruby_sim_calc.c +2362 -0
- data/lib/HDLRuby/sim/hruby_sim_core.c +589 -0
- data/lib/HDLRuby/sim/hruby_sim_list.c +93 -0
- data/lib/HDLRuby/sim/hruby_sim_vizualize.c +91 -0
- data/lib/HDLRuby/sim/hruby_value_pool.c +64 -0
- data/lib/HDLRuby/std/channel.rb +354 -0
- data/lib/HDLRuby/std/clocks.rb +165 -0
- data/lib/HDLRuby/std/counters.rb +82 -0
- data/lib/HDLRuby/std/decoder.rb +214 -0
- data/lib/HDLRuby/std/fsm.rb +516 -0
- data/lib/HDLRuby/std/pipeline.rb +220 -0
- data/lib/HDLRuby/std/reconf.rb +309 -0
- data/lib/HDLRuby/test_hruby_bstr.rb +2259 -0
- data/lib/HDLRuby/test_hruby_high.rb +594 -0
- data/lib/HDLRuby/test_hruby_high_low.rb +99 -0
- data/lib/HDLRuby/test_hruby_low.rb +934 -0
- data/lib/HDLRuby/v_samples/adder.v +10 -0
- data/lib/HDLRuby/v_samples/dff.v +12 -0
- data/lib/HDLRuby/v_samples/ram.v +20 -0
- data/lib/HDLRuby/v_samples/rom.v +270 -0
- data/lib/HDLRuby/version.rb +3 -0
- data/lib/HDLRuby.rb +11 -0
- data/makedoc +1 -0
- data/metadata.yaml +4 -0
- metadata +299 -0
@@ -0,0 +1,199 @@
|
|
1
|
+
# A class for a handshake transmission.
|
2
|
+
|
3
|
+
class Handshaker
|
4
|
+
|
5
|
+
## Create a new handshaker for transmitting +type+ data.
|
6
|
+
def initialize(type)
|
7
|
+
# Sets the date type.
|
8
|
+
type = type.to_type
|
9
|
+
@type = type
|
10
|
+
buffer = read_valid = read_ready = write_valid = write_ready = nil
|
11
|
+
HDLRuby::High.cur_system.open do
|
12
|
+
# Declares the registers used for the handshake
|
13
|
+
# The data buffer.
|
14
|
+
buffer = type.inner(HDLRuby.uniq_name)
|
15
|
+
# Declares the handshake control singals.
|
16
|
+
read_valid = inner(HDLRuby.uniq_name)
|
17
|
+
read_ready = inner(HDLRuby.uniq_name)
|
18
|
+
write_valid = inner(HDLRuby.uniq_name)
|
19
|
+
write_ready = inner(HDLRuby.uniq_name)
|
20
|
+
end
|
21
|
+
@buffer = buffer
|
22
|
+
@read_valid = read_valid
|
23
|
+
@read_ready = read_ready
|
24
|
+
@write_valid = write_valid
|
25
|
+
@write_ready = write_ready
|
26
|
+
# puts "@buffer=#{@buffer}"
|
27
|
+
# puts "@read_valid=#{@read_valid}"
|
28
|
+
end
|
29
|
+
|
30
|
+
# Generate the reset of the handshaker.
|
31
|
+
def reset
|
32
|
+
read_valid = @read_valid
|
33
|
+
read_ready = @read_ready
|
34
|
+
write_valid = @write_valid
|
35
|
+
write_ready = @write_ready
|
36
|
+
HDLRuby::High.cur_system.open do
|
37
|
+
par do
|
38
|
+
read_valid <= 0
|
39
|
+
read_ready <= 0
|
40
|
+
write_valid <= 1
|
41
|
+
write_ready <= 1
|
42
|
+
end
|
43
|
+
end
|
44
|
+
end
|
45
|
+
|
46
|
+
## Declares the signals used for input from the handshaker and
|
47
|
+
# do the connections of the upper SystemI
|
48
|
+
def input
|
49
|
+
ibuffer = iread_valid = iread_ready = iwrite_valid = iwrite_ready =nil
|
50
|
+
type = @type
|
51
|
+
buffer = @buffer
|
52
|
+
read_valid = @read_valid
|
53
|
+
read_ready = @read_ready
|
54
|
+
write_valid = @write_valid
|
55
|
+
write_ready = @write_ready
|
56
|
+
HDLRuby::High.cur_system.open do
|
57
|
+
# Declares the input signals
|
58
|
+
ibuffer = type.input(HDLRuby.uniq_name)
|
59
|
+
iread_valid = input(HDLRuby.uniq_name)
|
60
|
+
iread_ready = input(HDLRuby.uniq_name)
|
61
|
+
iwrite_valid = output(HDLRuby.uniq_name)
|
62
|
+
iwrite_ready = output(HDLRuby.uniq_name)
|
63
|
+
end
|
64
|
+
@ibuffer = ibuffer
|
65
|
+
@iread_valid = iread_valid
|
66
|
+
@iread_ready = iread_ready
|
67
|
+
@iwrite_valid = iwrite_valid
|
68
|
+
@iwrite_ready = iwrite_ready
|
69
|
+
end
|
70
|
+
|
71
|
+
## Declares the signals used for output to the handshaker and
|
72
|
+
# do the connections of the upper SystemI
|
73
|
+
def output
|
74
|
+
obuffer = oread_valid = oread_ready = owrite_valid = owrite_ready =nil
|
75
|
+
type = @type
|
76
|
+
buffer = @buffer
|
77
|
+
read_valid = @read_valid
|
78
|
+
read_ready = @read_ready
|
79
|
+
write_valid = @write_valid
|
80
|
+
write_ready = @write_ready
|
81
|
+
HDLRuby::High.cur_system.open do
|
82
|
+
obuffer = type.output(HDLRuby.uniq_name)
|
83
|
+
oread_valid = output(HDLRuby.uniq_name)
|
84
|
+
oread_ready = output(HDLRuby.uniq_name)
|
85
|
+
owrite_valid = input(HDLRuby.uniq_name)
|
86
|
+
owrite_ready = input(HDLRuby.uniq_name)
|
87
|
+
end
|
88
|
+
@obuffer = obuffer
|
89
|
+
@oread_valid = oread_valid
|
90
|
+
@oread_ready = oread_ready
|
91
|
+
@owrite_valid = owrite_valid
|
92
|
+
@owrite_ready = owrite_ready
|
93
|
+
end
|
94
|
+
|
95
|
+
## Gets the port of the handshaker as a list of signals.
|
96
|
+
def get_port
|
97
|
+
return [@buffer,@read_valid,@read_ready,@write_valid,@write_ready]
|
98
|
+
end
|
99
|
+
alias_method :to_a, :get_port
|
100
|
+
|
101
|
+
## Generates a blocking read.
|
102
|
+
def read(target,&blk)
|
103
|
+
ibuffer = @ibuffer
|
104
|
+
iread_valid = @iread_valid
|
105
|
+
iread_ready = @iread_ready
|
106
|
+
iwrite_valid = @iwrite_valid
|
107
|
+
iwrite_ready = @iwrite_ready
|
108
|
+
HDLRuby::High.cur_block.open do
|
109
|
+
hif(iread_valid) do
|
110
|
+
iwrite_valid <= 0
|
111
|
+
iwrite_ready <= 0
|
112
|
+
hif(iread_ready) do
|
113
|
+
target <= ibuffer
|
114
|
+
iwrite_valid <= 1
|
115
|
+
blk.call if blk
|
116
|
+
end
|
117
|
+
end
|
118
|
+
helse do
|
119
|
+
iwrite_ready <= 1
|
120
|
+
end
|
121
|
+
end
|
122
|
+
end
|
123
|
+
|
124
|
+
## Generates a blocking write.
|
125
|
+
def write(target,&blk)
|
126
|
+
obuffer = @obuffer
|
127
|
+
oread_valid = @oread_valid
|
128
|
+
oread_ready = @oread_ready
|
129
|
+
owrite_valid = @owrite_valid
|
130
|
+
owrite_ready = @owrite_ready
|
131
|
+
HDLRuby::High.cur_block.open do
|
132
|
+
hif(owrite_valid) do
|
133
|
+
oread_valid <= 0
|
134
|
+
oread_ready <= 0
|
135
|
+
hif(owrite_ready) do
|
136
|
+
obuffer <= target
|
137
|
+
oread_valid <= 1
|
138
|
+
blk.call if blk
|
139
|
+
end
|
140
|
+
end
|
141
|
+
helse do
|
142
|
+
oread_ready <= 1
|
143
|
+
end
|
144
|
+
end
|
145
|
+
end
|
146
|
+
end
|
147
|
+
|
148
|
+
|
149
|
+
|
150
|
+
# A system generating data and sending them through hadnshake.
|
151
|
+
# +hs_port+ is the handshaker.
|
152
|
+
system :hs_producer do |hs_port|
|
153
|
+
input :clk
|
154
|
+
input :rst
|
155
|
+
hs_port.output
|
156
|
+
|
157
|
+
[8].inner :counter
|
158
|
+
|
159
|
+
par(clk.posedge) do
|
160
|
+
hif(rst) { counter <= 0 }
|
161
|
+
helse do
|
162
|
+
hs_port.write(counter) { counter <= counter + 1 }
|
163
|
+
end
|
164
|
+
end
|
165
|
+
end
|
166
|
+
|
167
|
+
# A system consuming data obtained from a handshaker.
|
168
|
+
# +hs_port+ is the handshaker.
|
169
|
+
system :hs_consummer do |hs_port|
|
170
|
+
input :clk
|
171
|
+
hs_port.input
|
172
|
+
|
173
|
+
[8].inner :value
|
174
|
+
|
175
|
+
par(clk.posedge) do
|
176
|
+
hs_port.read(value)
|
177
|
+
end
|
178
|
+
end
|
179
|
+
|
180
|
+
# A system testing the producer/consumer.
|
181
|
+
system :hs_test do
|
182
|
+
input :clk,:rst
|
183
|
+
|
184
|
+
# Declares the handshaker
|
185
|
+
hs = Handshaker.new([8])
|
186
|
+
|
187
|
+
# Sets the reset.
|
188
|
+
hs.reset.at(rst.posedge)
|
189
|
+
|
190
|
+
# Instantiate the producer.
|
191
|
+
hs_producer(hs).(:producer).(clk,rst,*hs)
|
192
|
+
# Instantiate the consummer.
|
193
|
+
hs_consummer(hs).(:consummer).(clk,*hs)
|
194
|
+
end
|
195
|
+
|
196
|
+
|
197
|
+
|
198
|
+
# Idea: core / container / ?
|
199
|
+
# -> pour SW et reconfigurable.
|
@@ -0,0 +1,17 @@
|
|
1
|
+
require '../std/decoder.rb'
|
2
|
+
include HDLRuby::High::Std
|
3
|
+
|
4
|
+
# Implementation of a decoder.
|
5
|
+
system :my_decoder do
|
6
|
+
[7..0].input :a
|
7
|
+
[7..0].output :z
|
8
|
+
|
9
|
+
decoder(a) do
|
10
|
+
entry("1000uuvv") { z <= u + v }
|
11
|
+
entry("101uuuvv") { z <= u - v }
|
12
|
+
entry("1100uuvv") { z <= u & v }
|
13
|
+
entry("1101uuvv") { z <= u | v }
|
14
|
+
entry("1110uuvv") { z <= u ^ v }
|
15
|
+
default { z <= 0 }
|
16
|
+
end
|
17
|
+
end
|
@@ -0,0 +1,34 @@
|
|
1
|
+
require '../std/fsm.rb'
|
2
|
+
|
3
|
+
include HDLRuby::High::Std
|
4
|
+
|
5
|
+
# Implementation of a fsm.
|
6
|
+
system :my_fsm do
|
7
|
+
input :clk,:rst
|
8
|
+
[7..0].input :a, :b
|
9
|
+
[7..0].output :z
|
10
|
+
|
11
|
+
# fsm :fsmI
|
12
|
+
# fsmI.for_event { clk.posedge }
|
13
|
+
# # Shortcut: fsmI.for_event(clk)
|
14
|
+
# fsmI.for_reset { rst }
|
15
|
+
# # Shortcut: fsmI.for_reset(rst)
|
16
|
+
# fsmI do
|
17
|
+
# state { z <= 0 }
|
18
|
+
# state(:there) { z <= a+b }
|
19
|
+
# state do
|
20
|
+
# hif (a>0) { z <= a-b }
|
21
|
+
# helse { goto(:there) }
|
22
|
+
# end
|
23
|
+
# end
|
24
|
+
# Other alternative:
|
25
|
+
fsm(clk.posedge,rst) do
|
26
|
+
reset { z <= 0 }
|
27
|
+
state { z <= a+b }
|
28
|
+
state(:there) do
|
29
|
+
hif (z!=0) { z <= a-b }
|
30
|
+
goto(z==0,:end,:there)
|
31
|
+
end
|
32
|
+
state(:end) { goto(:end) }
|
33
|
+
end
|
34
|
+
end
|
@@ -0,0 +1,103 @@
|
|
1
|
+
require '../std/reconf.rb'
|
2
|
+
|
3
|
+
include HDLRuby::High::Std
|
4
|
+
|
5
|
+
|
6
|
+
|
7
|
+
|
8
|
+
# Implementation of a vivado partial reconfiguration system.
|
9
|
+
reconf(:vivado_reconf) do |clk,rst|
|
10
|
+
|
11
|
+
# Get access to the interface of the reconfigurable component.
|
12
|
+
inputs = each_input
|
13
|
+
outputs = each_output
|
14
|
+
inouts = each_inout
|
15
|
+
|
16
|
+
# Create the main system with the interface and a channel for
|
17
|
+
# handling the reconfiguration.
|
18
|
+
main = system do
|
19
|
+
# Declares the inputs.
|
20
|
+
inputs.each do |i|
|
21
|
+
i.type.input(i.name)
|
22
|
+
end
|
23
|
+
# Declares the outputs.
|
24
|
+
outputs.each do |o|
|
25
|
+
o.type.output(o.name)
|
26
|
+
end
|
27
|
+
# Declares the inouts.
|
28
|
+
inouts.each do |io|
|
29
|
+
io.type.inout(io.name)
|
30
|
+
end
|
31
|
+
# An that's all: in vivado the main system is to be a black-box.
|
32
|
+
end
|
33
|
+
|
34
|
+
# And set it as the main system.
|
35
|
+
set_main(main)
|
36
|
+
|
37
|
+
# The switching circuit.
|
38
|
+
# reconfer = vivado_reconfigurer :do_reconf # Will be that later
|
39
|
+
# reconfer.clk <= clk
|
40
|
+
# reconfer.rst <= rst
|
41
|
+
reconfer = proc do |idx|
|
42
|
+
puts "Instantiating reconfiguration circuits with #{idx}"
|
43
|
+
end
|
44
|
+
|
45
|
+
# Defines the reconfiguring procedure: switch to system idx.
|
46
|
+
switcher do |idx,ruby_block|
|
47
|
+
reconfer.call(idx)
|
48
|
+
ruby_block.call
|
49
|
+
end
|
50
|
+
|
51
|
+
end
|
52
|
+
|
53
|
+
|
54
|
+
# Some system that can be used for recponfiguration.
|
55
|
+
system :sys0 do
|
56
|
+
input :clk,:rst
|
57
|
+
input :d
|
58
|
+
output :q
|
59
|
+
|
60
|
+
q <= d
|
61
|
+
end
|
62
|
+
|
63
|
+
system :sys1 do
|
64
|
+
input :clk,:rst
|
65
|
+
input :d
|
66
|
+
output :q
|
67
|
+
|
68
|
+
(q <= d).at(clk.posedge)
|
69
|
+
end
|
70
|
+
|
71
|
+
system :sys2 do
|
72
|
+
input :clk,:rst
|
73
|
+
input :d
|
74
|
+
output :q
|
75
|
+
|
76
|
+
(q <= d & ~rst).at(clk.posedge)
|
77
|
+
end
|
78
|
+
|
79
|
+
# A system with a reconfifurable part.
|
80
|
+
system :with_reconf do
|
81
|
+
input :clk,:rst
|
82
|
+
input :d
|
83
|
+
output :q
|
84
|
+
[2].input :conf # The configuration number
|
85
|
+
|
86
|
+
inner :wait_reconf
|
87
|
+
|
88
|
+
# Create a reconfigurable component.
|
89
|
+
vivado_reconf(clk,rst).(:my_reconf)
|
90
|
+
# It is to be reconfigured to sys0, sys1 or sys2
|
91
|
+
my_reconf.(sys0, sys1, sys2)
|
92
|
+
|
93
|
+
# Connect the reconfigurable instance.
|
94
|
+
my_reconf.instance.(clk,rst,d,q)
|
95
|
+
|
96
|
+
par(clk.posedge) do
|
97
|
+
hif(rst) { wait_reconf <= 0 }
|
98
|
+
helsif(conf != 0 && my_reconf.index != conf && wait_reconf == 0) do
|
99
|
+
wait_reconf <= 1
|
100
|
+
my_reconf.switch(conf) { wait_reconf <= 0 }
|
101
|
+
end
|
102
|
+
end
|
103
|
+
end
|