HDLRuby 2.0.8

data/lib/HDLRuby/hdr_samples/with_class.rb

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+# A class for a handshake transmission.
+
+class Handshaker
+
+    ## Create a new handshaker for transmitting +type+ data.
+    def initialize(type)
+        # Sets the date type.
+        type = type.to_type
+        @type = type
+        buffer = read_valid = read_ready = write_valid = write_ready = nil
+        HDLRuby::High.cur_system.open do
+            # Declares the registers used for the handshake
+            # The data buffer.
+            buffer = type.inner(HDLRuby.uniq_name)
+            # Declares the handshake control singals.
+            read_valid  = inner(HDLRuby.uniq_name)
+            read_ready  = inner(HDLRuby.uniq_name)
+            write_valid = inner(HDLRuby.uniq_name)
+            write_ready = inner(HDLRuby.uniq_name)
+        end
+        @buffer = buffer
+        @read_valid  = read_valid
+        @read_ready  = read_ready
+        @write_valid = write_valid
+        @write_ready = write_ready
+        # puts "@buffer=#{@buffer}"
+        # puts "@read_valid=#{@read_valid}"
+    end
+
+    # Generate the reset of the handshaker.
+    def reset
+        read_valid  = @read_valid
+        read_ready  = @read_ready
+        write_valid = @write_valid
+        write_ready = @write_ready
+        HDLRuby::High.cur_system.open do
+            par do
+                read_valid  <= 0
+                read_ready  <= 0
+                write_valid <= 1
+                write_ready <= 1
+            end
+        end
+    end
+
+    ## Declares the signals used for input from the handshaker and
+    # do the connections of the upper SystemI
+    def input
+        ibuffer = iread_valid = iread_ready = iwrite_valid = iwrite_ready =nil
+        type = @type
+        buffer = @buffer
+        read_valid  = @read_valid 
+        read_ready  = @read_ready 
+        write_valid = @write_valid 
+        write_ready = @write_ready 
+        HDLRuby::High.cur_system.open do
+            # Declares the input signals
+            ibuffer = type.input(HDLRuby.uniq_name)
+            iread_valid  = input(HDLRuby.uniq_name)
+            iread_ready  = input(HDLRuby.uniq_name)
+            iwrite_valid = output(HDLRuby.uniq_name)
+            iwrite_ready = output(HDLRuby.uniq_name)
+        end
+        @ibuffer = ibuffer
+        @iread_valid   = iread_valid
+        @iread_ready   = iread_ready
+        @iwrite_valid  = iwrite_valid
+        @iwrite_ready  = iwrite_ready
+    end
+
+    ## Declares the signals used for output to the handshaker and
+    # do the connections of the upper SystemI
+    def output
+        obuffer = oread_valid = oread_ready = owrite_valid = owrite_ready =nil
+        type = @type
+        buffer = @buffer
+        read_valid  = @read_valid 
+        read_ready  = @read_ready 
+        write_valid = @write_valid 
+        write_ready = @write_ready 
+        HDLRuby::High.cur_system.open do
+            obuffer = type.output(HDLRuby.uniq_name)
+            oread_valid  = output(HDLRuby.uniq_name)
+            oread_ready  = output(HDLRuby.uniq_name)
+            owrite_valid = input(HDLRuby.uniq_name)
+            owrite_ready = input(HDLRuby.uniq_name)
+        end
+        @obuffer = obuffer
+        @oread_valid   = oread_valid
+        @oread_ready   = oread_ready
+        @owrite_valid  = owrite_valid
+        @owrite_ready  = owrite_ready
+    end
+
+    ## Gets the port of the handshaker as a list of signals.
+    def get_port
+        return [@buffer,@read_valid,@read_ready,@write_valid,@write_ready]
+    end
+    alias_method :to_a, :get_port
+
+    ## Generates a blocking read.
+    def read(target,&blk)
+        ibuffer = @ibuffer
+        iread_valid  = @iread_valid
+        iread_ready  = @iread_ready
+        iwrite_valid = @iwrite_valid
+        iwrite_ready = @iwrite_ready
+        HDLRuby::High.cur_block.open do
+            hif(iread_valid) do
+                iwrite_valid <= 0
+                iwrite_ready <= 0
+                hif(iread_ready) do
+                    target <= ibuffer
+                    iwrite_valid <= 1
+                    blk.call if blk
+                end
+            end
+            helse do
+                iwrite_ready <= 1
+            end
+        end
+    end
+
+    ## Generates a blocking write.
+    def write(target,&blk)
+        obuffer = @obuffer
+        oread_valid  = @oread_valid
+        oread_ready  = @oread_ready
+        owrite_valid = @owrite_valid
+        owrite_ready = @owrite_ready
+        HDLRuby::High.cur_block.open do
+            hif(owrite_valid) do
+                oread_valid <= 0
+                oread_ready <= 0
+                hif(owrite_ready) do
+                    obuffer <= target
+                    oread_valid <= 1
+                    blk.call if blk
+                end
+            end 
+            helse do
+                oread_ready <= 1
+            end
+        end
+    end
+end
+
+
+
+# A system generating data and sending them through hadnshake.
+# +hs_port+ is the handshaker.
+system :hs_producer do |hs_port|
+    input :clk
+    input :rst
+    hs_port.output
+
+    [8].inner :counter
+
+    par(clk.posedge) do
+        hif(rst) { counter <= 0 }
+        helse do
+            hs_port.write(counter) { counter <= counter + 1 }
+        end
+    end
+end
+
+# A system consuming data obtained from a handshaker.
+# +hs_port+ is the handshaker.
+system :hs_consummer do |hs_port|
+    input :clk
+    hs_port.input
+
+    [8].inner :value
+
+    par(clk.posedge) do
+        hs_port.read(value)
+    end
+end
+
+# A system testing the producer/consumer.
+system :hs_test do
+    input :clk,:rst
+
+    # Declares the handshaker
+    hs = Handshaker.new([8])
+
+    # Sets the reset.
+    hs.reset.at(rst.posedge)
+
+    # Instantiate the producer.
+    hs_producer(hs).(:producer).(clk,rst,*hs)
+    # Instantiate the consummer.
+    hs_consummer(hs).(:consummer).(clk,*hs)
+end
+
+
+
+# Idea: core / container / ?
+# -> pour SW et reconfigurable.

data/lib/HDLRuby/hdr_samples/with_decoder.rb

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+require '../std/decoder.rb'
+include HDLRuby::High::Std
+
+# Implementation of a decoder.
+system :my_decoder do
+    [7..0].input :a
+    [7..0].output :z
+
+    decoder(a) do
+        entry("1000uuvv") { z <= u + v }
+        entry("101uuuvv") { z <= u - v }
+        entry("1100uuvv") { z <= u & v }
+        entry("1101uuvv") { z <= u | v }
+        entry("1110uuvv") { z <= u ^ v }
+        default           { z <= 0     }
+    end
+end

data/lib/HDLRuby/hdr_samples/with_fsm.rb

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+require '../std/fsm.rb'
+
+include HDLRuby::High::Std
+
+# Implementation of a fsm.
+system :my_fsm do
+    input :clk,:rst
+    [7..0].input :a, :b
+    [7..0].output :z
+
+    # fsm :fsmI 
+    # fsmI.for_event { clk.posedge }
+    # # Shortcut: fsmI.for_event(clk)
+    # fsmI.for_reset { rst }
+    # # Shortcut: fsmI.for_reset(rst)
+    # fsmI do
+    #     state         { z <= 0 }
+    #     state(:there) { z <= a+b }
+    #     state do
+    #         hif (a>0) { z <= a-b }
+    #         helse { goto(:there) }
+    #     end
+    # end
+    # Other alternative:
+    fsm(clk.posedge,rst) do
+        reset         { z <= 0 }
+        state         { z <= a+b }
+        state(:there) do
+            hif (z!=0) { z <= a-b }
+            goto(z==0,:end,:there)
+        end
+        state(:end)   { goto(:end) }
+    end
+end

data/lib/HDLRuby/hdr_samples/with_reconf.rb

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+require '../std/reconf.rb'
+
+include HDLRuby::High::Std
+
+
+
+
+# Implementation of a vivado partial reconfiguration system.
+reconf(:vivado_reconf) do |clk,rst|
+
+    # Get access to the interface of the reconfigurable component.
+    inputs = each_input
+    outputs = each_output
+    inouts = each_inout
+
+    # Create the main system with the interface and a channel for
+    # handling the reconfiguration.
+    main = system do
+        # Declares the inputs.
+        inputs.each do |i|
+            i.type.input(i.name)
+        end
+        # Declares the outputs.
+        outputs.each do |o|
+            o.type.output(o.name)
+        end
+        # Declares the inouts.
+        inouts.each do |io|
+            io.type.inout(io.name)
+        end
+        # An that's all: in vivado the main system is to be a black-box.
+    end
+
+    # And set it as the main system.
+    set_main(main)
+
+    # The switching circuit.
+    # reconfer = vivado_reconfigurer :do_reconf # Will be that later
+    # reconfer.clk <= clk 
+    # reconfer.rst <= rst 
+    reconfer = proc do |idx|
+        puts "Instantiating reconfiguration circuits with #{idx}"
+    end
+
+    # Defines the reconfiguring procedure: switch to system idx.
+    switcher do |idx,ruby_block|
+        reconfer.call(idx)
+        ruby_block.call
+    end
+
+end
+
+
+# Some system that can be used for recponfiguration.
+system :sys0 do
+    input :clk,:rst
+    input :d
+    output :q
+
+    q <= d
+end
+
+system :sys1 do
+    input :clk,:rst
+    input :d
+    output :q
+
+    (q <= d).at(clk.posedge)
+end
+
+system :sys2 do
+    input :clk,:rst
+    input :d
+    output :q
+
+    (q <= d & ~rst).at(clk.posedge)
+end
+
+# A system with a reconfifurable part.
+system :with_reconf do
+    input :clk,:rst
+    input :d
+    output :q
+    [2].input :conf # The configuration number
+
+    inner :wait_reconf
+
+    # Create a reconfigurable component.
+    vivado_reconf(clk,rst).(:my_reconf)
+    # It is to be reconfigured to sys0, sys1 or sys2
+    my_reconf.(sys0, sys1, sys2)
+
+    # Connect the reconfigurable instance.
+    my_reconf.instance.(clk,rst,d,q)
+
+    par(clk.posedge) do
+        hif(rst) { wait_reconf <= 0 }
+        helsif(conf != 0 && my_reconf.index != conf && wait_reconf == 0) do
+            wait_reconf <= 1
+            my_reconf.switch(conf) { wait_reconf <= 0 }
+        end
+    end
+end