HDLRuby 2.0.8

data/lib/HDLRuby/hdr_samples/prog.obj

@@ -0,0 +1,256 @@
+            0b00110110, # 00: mov  0,G     ; Start writing a address 0
+            0b10101000, # 01: movl 0b1000
+            0b10110100, # 02: movh 0b0100  ; A <= 'H'
+            0b11111001, # 03: ++st         ; write it front
+            0b10100101, # 04: movl 0b0101
+            0b10110110, # 05: movh 0b0110  ; A <= 'e'
+            0b11111001, # 06: ++st         ; write it front
+            0b10101100, # 07: movl 0b1100
+            0b10110110, # 08: movh 0b0110  ; A <= 'l'
+            0b11111001, # 09: ++st         ; write it front
+            0b10101100, # 0A: movl 0b1100
+            0b10110110, # 0B: movh 0b0110  ; A <= 'l'
+            0b11111001, # 0C: ++st         ; write it front
+            0b10101111, # 0D: movl 0b1111
+            0b10110110, # 0E: movh 0b0110  ; A <= 'o'
+            0b11111001, # 0F: ++st         ; write it front
+            0b10100001, # 10: movl 0b0001
+            0b10110010, # 11: movh 0b0010  ; A <= '!'
+            0b11111001, # 12: ++st         ; write it front
+            0b00000000, # 13:
+            0b00000000, # 14:
+            0b10100000, # 15: movl 0b0000
+            0b10110010, # 16: movh 0b0010  ; A <= 20H 
+            0b00000001, # 17: mov  A,B     ; B <= A
+            0b10111000, # 18: movh 0b1000  ; A <= 80H
+            0b11111001, # 19: ++st         ; write A front
+            0b01001001, # 1A: sub B        ; A <= A-B
+            0b11101110, # 1B: brnz 0b110   ; to address 0x19 if non zero
+            0b00000000, # 1C: 
+            0b00000000, # 1D: 
+            0b10100101, # 1E: movl 0b0101
+            0b10111010, # 1F: movh 0b1010  ; A <= A5H
+            0b00000010, # 20: mov A,C      ; C <= A
+            0b10100110, # 21: movl 0b0110  ; A <= 06H
+            0b01000010, # 22: add C        ; A <= A+C
+            0b11111001, # 23: ++st         ; write A front
+            0b00000011, # 24: mov A,D      ; D <= A
+            0b01010011, # 25: inc D        ; D <= D+1
+            0b01100011, # 26: and D        ; A <= A&D
+            0b11111001, # 27: ++st         ; write A front
+            0b00000100, # 28: mov A,E      ; E <= A
+            0b01011100, # 29: dec E        ; E <= E-1
+            0b01101100, # 2A: or E         ; A <= A|E
+            0b11111011, # 2B: --st         ; write A back
+            0b00000101, # 2C: mov A,F      ; F <= A
+            0b01110101, # 2D: xor F        ; A <= A^F
+            0b10010101, # 2E: st F         ; write F
+            0b10000000, # 2F: cp A         ; A-A
+            0b11100010, # 30: brv 0b010    ; to address 0x32 if overflow
+            0b10010010, # 31: st C         ; write C
+            0b10010000, # 32: st A         ; write A
+            0b11010010, # 33: brc 0b010    ; to address 0x35 if carry
+            0b10010000, # 34: st A         ; write A
+            0b10010011, # 35: st D         ; write D
+            0b11011010, # 36: brs 0b010    ; to address 0x38 if negative
+            0b10010000, # 37: st A         ; write A
+            0b10010100, # 38: st E         ; write E
+            0b11001010, # 39: brz 0b010    ; to address 0x3B if zero
+            0b10010000, # 3A: st A         ; write A
+            0b10010101, # 3B: st F         ; write F
+            0b10001101, # 3C: ld F         ; read F
+            0b00101000, # 3D: mov F,A      ; A <= F 
+            0b10010000, # 3E: st A         ; write A
+            0b11110000, # 3F: neg          ; A <= -A
+            0b10010000, # 40: st A         ; write A
+            0b11110001, # 41: not          ; A <= !A
+            0b10010000, # 42: st A         ; write A
+            0b11110010, # 43: shl          ; A <= A << 1
+            0b10010000, # 44: st A         ; write A
+            0b10111100, # 45: movh 0b1100  ; AH <= C
+            0b11110100, # 46: sar          ; A <= A >> 1
+            0b10010000, # 47: st A         ; write A
+            0b11110011, # 48: shr          ; A <= A >>> 1
+            0b10010000, # 49: st A         ; write A
+            0b11110110, # 4A: trap         ; TRAP
+            0b11111000, # 4B: ++ld         ; read A front
+            0b10010000, # 4C: st           ; write A
+            0b11111010, # 4D: --ld         ; read A back
+            0b10010000, # 4E: st           ; write A
+            0b11111100, # 4F: push PC      ; push PC
+            0b11111110, # 50: halt
+            0b00000000, # 51:
+            0b00000000, # 52:
+            0b00000000, # 53:
+            0b00000000, # 54:
+            0b00000000, # 55:
+            0b00000000, # 56:
+            0b00000000, # 57:
+            0b00000000, # 58:
+            0b00000000, # 59:
+            0b00000000, # 5A:
+            0b00000000, # 5B:
+            0b00000000, # 5C:
+            0b00000000, # 5D:
+            0b00000000, # 5E:
+            0b00000000, # 5F:
+            0b00000000, # 60:
+            0b00000000, # 61:
+            0b00000000, # 62:
+            0b00000000, # 63:
+            0b00000000, # 64:
+            0b00000000, # 65:
+            0b00000000, # 66:
+            0b00000000, # 67:
+            0b00000000, # 68:
+            0b00000000, # 69:
+            0b00000000, # 6A:
+            0b00000000, # 6B:
+            0b00000000, # 6C:
+            0b00000000, # 6D:
+            0b00000000, # 6E:
+            0b00000000, # 6F:
+            0b00000000, # 70:
+            0b00000000, # 71:
+            0b00000000, # 72:
+            0b00000000, # 73:
+            0b00000000, # 74:
+            0b00000000, # 75:
+            0b00000000, # 76:
+            0b00000000, # 77:
+            0b00000000, # 78:
+            0b00000000, # 79:
+            0b00000000, # 7A:
+            0b00000000, # 7B:
+            0b00000000, # 7C:
+            0b00000000, # 7D:
+            0b00000000, # 7E:
+            0b00000000, # 7F:
+            0b00000000, # 80:
+            0b00000000, # 81:
+            0b00000000, # 82:
+            0b00000000, # 83:
+            0b00000000, # 84:
+            0b00000000, # 85:
+            0b00000000, # 86:
+            0b00000000, # 87:
+            0b00000000, # 88:
+            0b00000000, # 89:
+            0b00000000, # 8A:
+            0b00000000, # 8B:
+            0b00000000, # 8C:
+            0b00000000, # 8D:
+            0b00000000, # 8E:
+            0b00000000, # 8F:
+            0b00000000, # 90:
+            0b00000000, # 91:
+            0b00000000, # 92:
+            0b00000000, # 93:
+            0b00000000, # 94:
+            0b00000000, # 95:
+            0b00000000, # 96:
+            0b00000000, # 97:
+            0b00000000, # 98:
+            0b00000000, # 99:
+            0b00000000, # 9A:
+            0b00000000, # 9B:
+            0b00000000, # 9C:
+            0b00000000, # 9D:
+            0b00000000, # 9E:
+            0b00000000, # 9F;
+            0b00000000, # A0:
+            0b00000000, # A1:
+            0b00000000, # A2:
+            0b00000000, # A3:
+            0b00000000, # A4:
+            0b00000000, # A5:
+            0b00000000, # A6:
+            0b00000000, # A7:
+            0b00000000, # A8:
+            0b00000000, # A9:
+            0b00000000, # AA:
+            0b00000000, # AB:
+            0b00000000, # AC:
+            0b00000000, # AD:
+            0b00000000, # AE:
+            0b00000000, # AF:
+            0b00000000, # B0:
+            0b00000000, # B1:
+            0b00000000, # B2:
+            0b00000000, # B3:
+            0b00000000, # B4:
+            0b00000000, # B5:
+            0b00000000, # B6:
+            0b00000000, # B7:
+            0b00000000, # B8:
+            0b00000000, # B9:
+            0b00000000, # BA:
+            0b00000000, # BB:
+            0b00000000, # BC:
+            0b00000000, # BD:
+            0b00000000, # BE:
+            0b00000000, # BF:
+            0b00000000, # C0:
+            0b00000000, # C1:
+            0b00000000, # C2:
+            0b00000000, # C3:
+            0b00000000, # C4:
+            0b00000000, # C5:
+            0b00000000, # C6:
+            0b00000000, # C7:
+            0b00000000, # C8:
+            0b00000000, # C9:
+            0b00000000, # CA:
+            0b00000000, # CB:
+            0b00000000, # CC:
+            0b00000000, # CD:
+            0b00000000, # CE:
+            0b00000000, # CF:
+            0b00000000, # D0:
+            0b00000000, # D1:
+            0b00000000, # D2:
+            0b00000000, # D3:
+            0b00000000, # D4:
+            0b00000000, # D5:
+            0b00000000, # D6:
+            0b00000000, # D7:
+            0b00000000, # D8:
+            0b00000000, # D9:
+            0b00000000, # DA:
+            0b00000000, # DB:
+            0b00000000, # DC:
+            0b00000000, # DD:
+            0b00000000, # DE:
+            0b00000000, # DF:
+            0b00000000, # E0:
+            0b00000000, # E1:
+            0b00000000, # E2:
+            0b00000000, # E3:
+            0b00000000, # E4:
+            0b00000000, # E5:
+            0b00000000, # E6:
+            0b00000000, # E7:
+            0b00000000, # E8:
+            0b00000000, # E9:
+            0b00000000, # EA:
+            0b00000000, # EB:
+            0b00000000, # EC:
+            0b00000000, # ED:
+            0b00000000, # EE:
+            0b00000000, # EF:
+            0b00000000, # F0:
+            0b00000000, # F1:
+            0b00000000, # F2:
+            0b00000000, # F3:
+            0b00000000, # F4:
+            0b00000000, # F5:
+            0b00000000, # F6:
+            0b00000000, # F7:
+            0b10100011, # F8: movl 0b0011
+            0b11110111, # F9: xs
+            0b11111101, # FA; pop pc
+            0b00000000, # FB:
+            0b10101011, # FC: movl 0b1011
+            0b10110100, # FD: movh 0b0100  ; A <= 4BH 
+            0b10011000, # FE: jr A         ; PC <= A
+            0b11111111, # FF:

data/lib/HDLRuby/hdr_samples/ram.rb

@@ -0,0 +1,18 @@
+# Describes an 8-bit data 16-bit address RAM.
+system :ram8_16 do
+    input :clk, :rwb, :en
+    [7..0].input :addr
+    [7..0].inout :data
+
+    bit[7..0][2**8].inner :content
+
+    # Memory enabled?
+    par(clk.posedge) do
+        hif(en) do
+            # Read case
+            hif(rwb)   { data <= content[addr] }
+            helse      { content[addr] <= data }
+        end
+        helse { data <= _bZZZZZZZZ }
+    end
+end

data/lib/HDLRuby/hdr_samples/register_with_code_bench.rb

@@ -0,0 +1,98 @@
+# require "../hruby_low2c.rb"
+
+# A generic register with C printing the data to the standard output.
+system :register do |size|
+    input  :clk, :rst
+    [size].input :d
+    [size].output :q
+
+    (q <= d & ~rst).at(clk.posedge)
+
+    code clk.posedge, c: [ '
+#include <stdio.h>
+#include "hruby_sim.h"
+#include "hruby_sim_gen.h"
+
+void show() {
+    printf("######################## From software q=");
+    print_value(',q,');
+    printf("\n");
+}
+        ' ],
+        sim: "show"
+end
+
+# A benchmark for the register.
+system :register_bench do
+    [8].inner :d, :clk, :rst
+    [8].inner :q
+
+    register(8).(:my_register).(clk,rst,d,q)
+
+    timed do
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 0
+        rst <= 1
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 1
+        d   <= 0
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 1
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 2
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 2
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 255
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 255
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 255
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 0
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/rom.rb

@@ -0,0 +1,10 @@
+
+# Describes an 8-bit data 4-bit address ROM.
+system :rom4_8 do
+    [3..0].input :addr
+    [7..0].output :data
+
+    bit[7..0][2**4].constant content: (2**4).times.to_a
+
+    data <= content[addr]
+end

data/lib/HDLRuby/hdr_samples/struct.rb

@@ -0,0 +1,14 @@
+system :dff do
+   input :clk, :rst, :d
+   output :q
+
+   par(clk.posedge) { q <= d & ~rst }
+end
+
+system :my_system do
+   input :clk, :rst
+   { sub0: bit, sub1: bit}.inner :sig
+   
+   dff(:dff0).(clk: clk, rst: rst)
+   dff0.d <= sig.sub0
+end

data/lib/HDLRuby/hdr_samples/sumprod.rb

@@ -0,0 +1,29 @@
+system :sumprod do |typ,coefs|
+    typ[coefs.size].input :ins
+    typ.output :o
+
+    o <= coefs.each_with_index.reduce(_0) do |sum,(coef,i)|
+        sum + ins[i]*coef
+    end
+end
+
+
+typedef :sat do |width, max|
+    signed[width]
+end
+
+
+sat.define_operator(:+) do |width,max, x,y|
+    [width].inner :res
+    seq do
+        res <= x + y
+        ( res <= max ).hif(res > max)
+    end
+end
+
+
+
+system :sumprod_sat_16_1000, sumprod(sat(16,1000),
+                             [3,78,43,246, 3,67,1,8, 47,82,99,13, 5,77,2,4]) do
+end
+

data/lib/HDLRuby/hdr_samples/sw_encrypt_bench.rb

@@ -0,0 +1,103 @@
+# require "../hruby_low2c.rb"
+
+# An 8-bit register with C encrypting.
+system :encrypt_register do
+    input  :clk, :rst
+    [8].input :d
+    [8].output :q
+
+    code clk.posedge, c: [ "
+#include <stdio.h>
+#include \"hruby_sim.h\"
+#include \"hruby_sim_gen.h\"
+
+void encrypt() {
+    static char keys[] = { 'S', 'e', 'c', 'r', 'e', 't', ' ', '!' };
+    static int index  = 0;
+    char buf;
+    buf = read8(",d,");
+    printf(\"######################## From software: encrypting d=%x\\n\",buf);
+    buf = buf ^ (keys[index]);
+    index = (index + 1) & sizeof(keys)-1;
+    printf(\"######################## From software: result =%x\\n\",buf);
+    write8(buf,",q,");
+    
+}
+        " ],
+        sim: "encrypt"
+end
+
+# A benchmark for the register.
+system :encrypt_bench do
+    [8].inner :d, :clk, :rst
+    [8].inner :q
+
+    encrypt_register(:my_register).(clk,rst,d,q)
+
+    timed do
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 0
+        rst <= 1
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 1
+        d   <= 0
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 1
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 2
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 2
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 255
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 255
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 255
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 0
+        !10.ns
+    end
+end