HDLRuby 2.0.8

data/lib/HDLRuby/hruby_verilog_name.rb

@@ -0,0 +1,52 @@
+# Program with inverse conversion
+# last update 2019 01 29
+
+module HDLRuby::Verilog
+
+  # This is sample.
+  # n = "abc_ABC_いろは"
+  # puts n            
+  # name = n.split("") 
+
+  # Since it is possible to use $ and numbers other than the beginning of the character string, it is divided.
+  def name_to_verilog(name)
+    ref = ""         # For storing the converted character.
+    name = name.to_s # Ensure name is a string
+    
+    if (name[0] =~ /[a-zA-Z]/) then
+      ref << name[0]
+      # _ To convert it to __.
+    elsif (name[0] == "_") then
+      ref << "__"
+    # If it does not satisfy the above, it is another character.
+    # In that case, convert it to UTF-8 and convert it to a usable character string.
+    else
+      l = name[0].bytes.map{|v| v.to_s(16)}.join # Conversion to UTF-8 hexadecimal number.
+   
+      ref << "_" + l.rjust(6,"0")      # Add an underscore indicating conversion.
+                                       # The remainder of 6 digits is filled with 0.
+    end
+    
+    name[1..-1].each_char do |c|
+      # Confirmation of characters in array.
+      # If it is a-zA-Z 0 - 9, it is added to ref as it is.
+      if (c =~ /[a-zA-Z0-9]|\$/) then
+        ref << c
+      # _ To convert it to __.
+      elsif (c == "_") then
+        ref << "__"
+      # If it does not satisfy the above, it is another character.
+      # In that case, convert it to UTF-8 and convert it to a usable character string.
+      else
+        l = c.bytes.map{|v| v.to_s(16)}.join # Conversion to UTF-8 hexadecimal number.
+     
+        ref << "_" + l.rjust(6,"0")      # Add an underscore indicating conversion.
+                                         # The remainder of 6 digits is filled with 0.
+      end
+    end
+    return ref
+  end
+
+  #puts ref
+
+end

data/lib/HDLRuby/low_samples/adder.yaml

@@ -0,0 +1,97 @@
+---
+Type:
+  name: void
+---
+Type:
+  name: bit
+---
+SystemT:
+  name: adderI::T_
+  inputs:
+  - SignalI:
+      name: x
+      type:
+        TypeVector:
+          name: ''
+          base: bit
+          range:
+          - 15
+          - 0
+  - SignalI:
+      name: y
+      type:
+        TypeVector:
+          name: ''
+          base: bit
+          range:
+          - 15
+          - 0
+  outputs:
+  - SignalI:
+      name: s
+      type:
+        TypeVector:
+          name: ''
+          base: bit
+          range:
+          - 16
+          - 0
+  inouts: []
+  scope:
+    Scope:
+      name: ''
+      scopes: []
+      inners: []
+      systemIs: []
+      connections:
+      - Connection:
+          left:
+            RefName:
+              type:
+                TypeVector:
+                  name: ''
+                  base: bit
+                  range:
+                  - 16
+                  - 0
+              ref:
+                RefThis:
+                  type: void
+              name: s
+          right:
+            Binary:
+              type:
+                TypeVector:
+                  name: ''
+                  base: bit
+                  range:
+                  - 16
+                  - 0
+              operator: "+"
+              left:
+                RefName:
+                  type:
+                    TypeVector:
+                      name: ''
+                      base: bit
+                      range:
+                      - 15
+                      - 0
+                  ref:
+                    RefThis:
+                      type: void
+                  name: x
+              right:
+                RefName:
+                  type:
+                    TypeVector:
+                      name: ''
+                      base: bit
+                      range:
+                      - 15
+                      - 0
+                  ref:
+                    RefThis:
+                      type: void
+                  name: y
+      behaviors: []

data/lib/HDLRuby/low_samples/after.yaml

@@ -0,0 +1,228 @@
+---
+Type:
+  name: signed
+---
+TypeVector:
+  name: integer
+  base: signed
+  range:
+  - 31
+  - 0
+---
+Type:
+  name: void
+---
+Type:
+  name: bit
+---
+SystemT:
+  name: with_afterI::T_
+  inputs:
+  - SignalI:
+      name: clk
+      type: bit
+  - SignalI:
+      name: rst
+      type: bit
+  outputs:
+  - SignalI:
+      name: timeout
+      type: bit
+  inouts: []
+  scope:
+    Scope:
+      name: ''
+      scopes: []
+      inners: []
+      systemIs: []
+      connections: []
+      behaviors:
+      - Behavior:
+          events:
+          - Event:
+              type: posedge
+              ref:
+                RefName:
+                  type: bit
+                  ref:
+                    RefThis:
+                      type: void
+                  name: clk
+          - Event:
+              type: posedge
+              ref:
+                RefName:
+                  type: bit
+                  ref:
+                    RefThis:
+                      type: void
+                  name: rst
+          block:
+            Block:
+              mode: par
+              name: ''
+              inners:
+              - SignalI:
+                  name: ":0"
+                  type:
+                    TypeVector:
+                      name: ''
+                      base: bit
+                      range:
+                      - 30
+                      - 0
+              statements:
+              - Transmit:
+                  left:
+                    RefName:
+                      type: bit
+                      ref:
+                        RefThis:
+                          type: void
+                      name: timeout
+                  right:
+                    Value:
+                      type: integer
+                      content: 0
+              - Block:
+                  mode: seq
+                  name: ''
+                  inners: []
+                  statements:
+                  - If:
+                      condition:
+                        Binary:
+                          type:
+                            TypeVector:
+                              name: ''
+                              base: signed
+                              range:
+                              - 0
+                              - 31
+                          operator: "=="
+                          left:
+                            RefName:
+                              type: bit
+                              ref:
+                                RefThis:
+                                  type: void
+                              name: rst
+                          right:
+                            Value:
+                              type: integer
+                              content: 1
+                      'yes':
+                        Block:
+                          mode: seq
+                          name: ''
+                          inners: []
+                          statements:
+                          - Transmit:
+                              left:
+                                RefName:
+                                  type:
+                                    TypeVector:
+                                      name: ''
+                                      base: bit
+                                      range:
+                                      - 30
+                                      - 0
+                                  ref:
+                                    RefThis:
+                                      type: void
+                                  name: ":0"
+                              right:
+                                Value:
+                                  type: integer
+                                  content: 100
+                      'no':
+                        Block:
+                          mode: seq
+                          name: ''
+                          inners: []
+                          statements:
+                          - Transmit:
+                              left:
+                                RefName:
+                                  type:
+                                    TypeVector:
+                                      name: ''
+                                      base: bit
+                                      range:
+                                      - 30
+                                      - 0
+                                  ref:
+                                    RefThis:
+                                      type: void
+                                  name: ":0"
+                              right:
+                                Binary:
+                                  type:
+                                    TypeVector:
+                                      name: ''
+                                      base: signed
+                                      range:
+                                      - 32
+                                      - 0
+                                  operator: "-"
+                                  left:
+                                    RefName:
+                                      type:
+                                        TypeVector:
+                                          name: ''
+                                          base: bit
+                                          range:
+                                          - 30
+                                          - 0
+                                      ref:
+                                        RefThis:
+                                          type: void
+                                      name: ":0"
+                                  right:
+                                    Value:
+                                      type: integer
+                                      content: 1
+                      noifs:
+                      - - Binary:
+                            type:
+                              TypeVector:
+                                name: ''
+                                base: signed
+                                range:
+                                - 31
+                                - 0
+                            operator: "=="
+                            left:
+                              RefName:
+                                type:
+                                  TypeVector:
+                                    name: ''
+                                    base: bit
+                                    range:
+                                    - 30
+                                    - 0
+                                ref:
+                                  RefThis:
+                                    type: void
+                                name: ":0"
+                            right:
+                              Value:
+                                type: integer
+                                content: 0
+                        - Block:
+                            mode: seq
+                            name: ''
+                            inners: []
+                            statements:
+                            - Transmit:
+                                left:
+                                  RefName:
+                                    type: bit
+                                    ref:
+                                      RefThis:
+                                        type: void
+                                    name: timeout
+                                right:
+                                  Value:
+                                    type: integer
+                                    content: 1

data/lib/HDLRuby/low_samples/before.yaml

@@ -0,0 +1,223 @@
+---
+Type:
+  name: signed
+---
+TypeVector:
+  name: integer
+  base: signed
+  range:
+  - 31
+  - 0
+---
+Type:
+  name: void
+---
+Type:
+  name: bit
+---
+SystemT:
+  name: with_beforeI::T_
+  inputs:
+  - SignalI:
+      name: clk
+      type: bit
+  - SignalI:
+      name: rst
+      type: bit
+  outputs:
+  - SignalI:
+      name: timeout
+      type: bit
+  inouts: []
+  scope:
+    Scope:
+      name: ''
+      scopes: []
+      inners: []
+      systemIs: []
+      connections: []
+      behaviors:
+      - Behavior:
+          events:
+          - Event:
+              type: posedge
+              ref:
+                RefName:
+                  type: bit
+                  ref:
+                    RefThis:
+                      type: void
+                  name: clk
+          - Event:
+              type: posedge
+              ref:
+                RefName:
+                  type: bit
+                  ref:
+                    RefThis:
+                      type: void
+                  name: rst
+          block:
+            Block:
+              mode: par
+              name: ''
+              inners:
+              - SignalI:
+                  name: ":0"
+                  type:
+                    TypeVector:
+                      name: ''
+                      base: bit
+                      range:
+                      - 30
+                      - 0
+              statements:
+              - Transmit:
+                  left:
+                    RefName:
+                      type: bit
+                      ref:
+                        RefThis:
+                          type: void
+                      name: timeout
+                  right:
+                    Value:
+                      type: integer
+                      content: 1
+              - Block:
+                  mode: seq
+                  name: ''
+                  inners: []
+                  statements:
+                  - If:
+                      condition:
+                        Binary:
+                          type:
+                            TypeVector:
+                              name: ''
+                              base: signed
+                              range:
+                              - 0
+                              - 31
+                          operator: "=="
+                          left:
+                            RefName:
+                              type: bit
+                              ref:
+                                RefThis:
+                                  type: void
+                              name: rst
+                          right:
+                            Value:
+                              type: integer
+                              content: 1
+                      'yes':
+                        Block:
+                          mode: seq
+                          name: ''
+                          inners: []
+                          statements:
+                          - Transmit:
+                              left:
+                                RefName:
+                                  type:
+                                    TypeVector:
+                                      name: ''
+                                      base: bit
+                                      range:
+                                      - 30
+                                      - 0
+                                  ref:
+                                    RefThis:
+                                      type: void
+                                  name: ":0"
+                              right:
+                                Value:
+                                  type: integer
+                                  content: 100
+                      'no': 
+                      noifs:
+                      - - Binary:
+                            type:
+                              TypeVector:
+                                name: ''
+                                base: signed
+                                range:
+                                - 31
+                                - 0
+                            operator: "!="
+                            left:
+                              RefName:
+                                type:
+                                  TypeVector:
+                                    name: ''
+                                    base: bit
+                                    range:
+                                    - 30
+                                    - 0
+                                ref:
+                                  RefThis:
+                                    type: void
+                                name: ":0"
+                            right:
+                              Value:
+                                type: integer
+                                content: 0
+                        - Block:
+                            mode: seq
+                            name: ''
+                            inners: []
+                            statements:
+                            - Transmit:
+                                left:
+                                  RefName:
+                                    type:
+                                      TypeVector:
+                                        name: ''
+                                        base: bit
+                                        range:
+                                        - 30
+                                        - 0
+                                    ref:
+                                      RefThis:
+                                        type: void
+                                    name: ":0"
+                                right:
+                                  Binary:
+                                    type:
+                                      TypeVector:
+                                        name: ''
+                                        base: signed
+                                        range:
+                                        - 32
+                                        - 0
+                                    operator: "-"
+                                    left:
+                                      RefName:
+                                        type:
+                                          TypeVector:
+                                            name: ''
+                                            base: bit
+                                            range:
+                                            - 30
+                                            - 0
+                                        ref:
+                                          RefThis:
+                                            type: void
+                                        name: ":0"
+                                    right:
+                                      Value:
+                                        type: integer
+                                        content: 1
+                            - Transmit:
+                                left:
+                                  RefName:
+                                    type: bit
+                                    ref:
+                                      RefThis:
+                                        type: void
+                                    name: timeout
+                                right:
+                                  Value:
+                                    type: integer
+                                    ontent: 0

data/lib/HDLRuby/low_samples/blockblock.yaml

@@ -0,0 +1,48 @@
+---
+Type:
+  name: bit
+---
+SystemT:
+  name: blockblockI::T_
+  inputs:
+  - SignalI:
+      name: i0
+      type: bit
+  - SignalI:
+      name: i1
+      type: bit
+  outputs:
+  - SignalI:
+      name: o0
+      type: bit
+  - SignalI:
+      name: o1
+      type: bit
+  inouts: []
+  scope:
+    Scope:
+      scopes: []
+      inners:
+      - SignalI:
+          name: s0
+          type: bit
+      systemIs: []
+      connections: []
+      behaviors:
+      - Behavior:
+          events: []
+          block:
+            Block:
+              mode: par
+              inners:
+              - SignalI:
+                  name: s0
+                  type: bit
+              statements:
+              - Block:
+                  mode: par
+                  inners:
+                  - SignalI:
+                      name: s0
+                      type: bit
+                  statements: []