HDLRuby 2.0.8

data/lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb

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+require 'HDLRuby/backend/allocator'
+require 'HDLRuby/hdr_samples/mei8'
+
+## A generic CPU description
+class CPU
+
+    ## Allocator assotiated with the bus of the CPU
+    attr_reader :allocator
+
+    ## The clock.
+    attr_reader :clk
+    ## The reset.
+    attr_reader :rst
+
+    ## The address bus
+    attr_reader :abus
+    ## The data bus
+    attr_reader :dbus
+    ## The read/!write selection
+    attr_reader :rwb
+    ## The request
+    attr_reader :req
+    ## The acknowledge
+    attr_reader :ack
+
+    ## Creates a new generic CPU whose data bus is +dwidth+ bit wide,
+    #  address bus is +awidth+ bit wide, clock is +clk+, reset +rst+.
+    def initialize(dwidth,awidth,clk,rst)
+        # Check and set the word and address bus widths
+        awidth = awidth.to_i
+        dwidth = dwidth.to_i
+        @awidth = awidth
+        @dwidth = dwidth
+        # Check and set the signals.
+        @clk = clk.to_ref
+        @rst = rst.to_ref
+        # The allocator of the CPU
+        @allocator = Allocator.new(0..(2**@addr),@data)
+
+        # Declare the address and data buses and the
+        # rwb/req/ack control signals
+        abus,dbus    = nil,nil
+        rwb,req,ack  = nil,nil,nil
+        # Declares the data and address bus.
+        HDLRuby::High.cur_system.open do
+            abus = [awidth].input(HDLRuby.uniq_name)
+            dbus = [dwidth].input(HDLRuby.uniq_name)
+            rwb  = input(HDLRuby.uniq_name)
+            req  = input(HDLRuby.uniq_name)
+            ack  = output(HDLRuby.uniq_name)
+        end
+        @abus,@dbus    = abus,dbus
+        @rwb,@req,@ack = rwb,req,ack
+    end
+
+    ## Connect signal +sig+ to the bus allocating an address to access it.
+    def connect(sig)
+        # Allocates the signal in the address space.
+        @allocator.allocate(sig)
+    end
+
+    ## Generates the bus controller.
+    def controller
+        clk,rst,req,ack = @clk,@rst,@req,@ack
+        abus,dbus,rwb   = @abus,@dbus,@rwb
+        allocator       = @allocator
+        HDLRuby::High.cur_system.open do
+            par(clk) do
+                # Bus controller
+                hcase(abus)
+                hif(req) do
+                    ack <= 1
+                    allocator.each do |sig,addr|
+                        hwhen(addr) do
+                            hif(rwb) { dbus <= sig }
+                            helse    { sig <= dbus }
+                        end
+                    end
+                end
+                helse do
+                    ack <= 0
+                end
+            end
+        end
+
+        ## Generates a read of sig executing +ruby_block+ on the result.
+        def read(sig,&ruby_block)
+            addr = @allocator.get(sig)
+            hif(ack == 0) do
+                @abus <= addr
+                @rwb <= 1
+                @req <= 1
+            helse
+                @req <= 0
+                ruby_block.call(@dbus)
+            end
+        end
+
+        ## Generates a write +val+ to +sig+ executing +ruby_block+
+        #  in case of success.
+        def write(val,sig,&ruby_block)
+            addr = @allocator.get(sig)
+            hif(ack == 0) do
+                @abus <= addr
+                @dbus <= val
+                @rwb <= 0
+                @req <= 1
+            helse
+                @req <= 0
+                ruby_block.call
+            end
+        end
+    end
+end
+
+
+# Simulates an 8-bit data 8-bit address CPU
+class MEI8 < CPU
+
+
+    ## Creates a new CPU simulator.
+    def initialize(clk,rst)
+        super(8,8,clk,rst)
+
+        # Instantiate the mei processor.
+
+        mei8(:my_mei8).(self.clk,self.rst,
+                        self.req,self.rwb,
+                        self.abus,self.dbus,
+                        self.ack,
+                        0,0)
+    end
+
+
+
+
+    ## Generates a read of signal +sig+.
+    def read(code,sig)
+        # Generate the resulting SW access.
+        return "*(0x#{self.allocator.get(sig).to_s(16)})"
+    end
+
+    ## Generates a write of +val+ to signal +sig+.
+    def write(val,sig)
+        # Generate the resulting SW access.
+        return "*(0x#{self.allocator.get(sig).to_s(16)}) = #{val};\n"
+    end
+end
+
+
+
+
+
+
+# An 8-bit register with C encrypting.
+system :encrypt_register do |cpu|
+    input  :clk, :rst
+    [8].input :d
+    [8].output :q
+
+    my_cpy = cpu.new(clk,rst)
+
+    my_cpu.connect(d)
+    my_cpu.connect(q)
+    my_cpu.controller
+
+    code clk.posedge, c: [ "
+#include <stdio.h>
+#include \"hruby_sim.h\"
+#include \"hruby_sim_gen.h\"
+
+void encrypt() {
+    static char keys[] = { 'S', 'e', 'c', 'r', 'e', 't', ' ', '!' };
+    static int index  = 0;
+    char buf;
+    buf = ",my_cpu.read(d),";
+    printf(\"######################## From software: encrypting d=%x\\n\",buf);
+    buf = buf ^ (keys[index]);
+    index = (index + 1) & (sizeof(keys)-1);
+    printf(\"######################## From software: result =%x\\n\",buf);
+    ",my_cpu.write("buf",q),";
+    
+}
+        " ],
+        sim: "encrypt"
+end
+
+# A benchmark for the register.
+system :encrypt_bench do
+    [8].inner :d, :clk, :rst
+    [8].inner :q
+
+    encrypt_register(:my_register).(clk,rst,d,q)
+
+    timed do
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 0
+        rst <= 1
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 1
+        d   <= 0
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 1
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 2
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 2
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 255
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 255
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 255
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 0
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb

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+require 'HDLRuby/backend/allocator'
+
+## A generic CPU description
+class CPU
+
+    ## Allocator assotiated with the bus of the CPU
+    attr_reader :allocator
+
+    ## The clock.
+    attr_reader :clk
+    ## The reset.
+    attr_reader :rst
+
+    ## The address bus
+    attr_reader :abus
+    ## The data bus
+    attr_reader :dbus
+    ## The read/!write selection
+    attr_reader :rwb
+    ## The request
+    attr_reader :req
+    ## The acknowledge
+    attr_reader :ack
+
+    ## Creates a new generic CPU whose data bus is +dwidth+ bit wide,
+    #  address bus is +awidth+ bit wide, clock is +clk+, reset +rst+.
+    def initialize(dwidth,awidth,clk,rst)
+        # Check and set the word and address bus widths
+        awidth = awidth.to_i
+        dwidth = dwidth.to_i
+        @awidth = awidth
+        @dwidth = dwidth
+        # Check and set the signals.
+        @clk = clk.to_ref
+        @rst = rst.to_ref
+        # The allocator of the CPU
+        @allocator = Allocator.new(0..(2**@addr),@data)
+
+        # Declare the address and data buses and the
+        # rwb/req/ack control signals
+        abus,dbus    = nil,nil
+        rwb,req,ack  = nil,nil,nil
+        # Declares the data and address bus.
+        HDLRuby::High.cur_system.open do
+            abus = [awidth].input(HDLRuby.uniq_name)
+            dbus = [dwidth].input(HDLRuby.uniq_name)
+            rwb  = input(HDLRuby.uniq_name)
+            req  = input(HDLRuby.uniq_name)
+            ack  = output(HDLRuby.uniq_name)
+        end
+        @abus,@dbus    = abus,dbus
+        @rwb,@req,@ack = rwb,req,ack
+    end
+
+    ## Connect signal +sig+ to the bus allocating an address to access it.
+    def connect(sig)
+        # Allocates the signal in the address space.
+        @allocator.allocate(sig)
+    end
+
+    ## Generates the bus controller.
+    def controller
+        clk,rst,req,ack = @clk,@rst,@req,@ack
+        abus,dbus,rwb   = @abus,@dbus,@rwb
+        allocator       = @allocator
+        HDLRuby::High.cur_system.open do
+            par(clk) do
+                # Bus controller
+                hcase(abus)
+                hif(req) do
+                    ack <= 1
+                    allocator.each do |sig,addr|
+                        hwhen(addr) do
+                            hif(rwb) { dbus <= sig }
+                            helse    { sig <= dbus }
+                        end
+                    end
+                end
+                helse do
+                    ack <= 0
+                end
+            end
+        end
+
+        ## Generates a read of sig executing +ruby_block+ on the result.
+        def read(sig,&ruby_block)
+            addr = @allocator.get(sig)
+            hif(ack == 0) do
+                @abus <= addr
+                @rwb <= 1
+                @req <= 1
+            helse
+                @req <= 0
+                ruby_block.call(@dbus)
+            end
+        end
+
+        ## Generates a write +val+ to +sig+ executing +ruby_block+
+        #  in case of success.
+        def write(val,sig,&ruby_block)
+            addr = @allocator.get(sig)
+            hif(ack == 0) do
+                @abus <= addr
+                @dbus <= val
+                @rwb <= 0
+                @req <= 1
+            helse
+                @req <= 0
+                ruby_block.call
+            end
+        end
+    end
+end
+
+
+# Simulates an 8-bit data 8-bit address CPU
+class CPUSimu < CPU
+    # Read and write are overwritten, save them before.
+    alias_method :hw_read, :read
+    alias_method :hw_write, :write
+
+
+    ## Creates a new CPU simulator.
+    def initialize(clk,rst)
+        super(8,8,clk,rst)
+
+        # The read and write control signals.
+        @read_action  = inner(HDLRuby.uniq_name)
+        @write_action = inner(HDLRuby.uniq_name)
+        @value        = [8].inner(HDLRuby.uniq_name)
+
+        # The CPU simulator code.
+        this = self
+        read_action,write_action = @read_action, @write_action
+        value = @value
+        par(this.posedge) do
+            hif(this.rst) do
+                read_action <= 0
+                write_action <= 0
+            end
+            helse do
+                hif(read_action) do
+                    this.hw_read(this.target,value) do
+                        read_action <= 0
+                    end
+                end
+                helsif(write_action) do
+                    this.hw_write(this.target,write_value) do
+                        write_action <= 0
+                    end
+                end
+            end
+        end
+
+        # The runtime code.
+        code c: [
+"unsigned char mem_read(unsigned char addr) {
+    unsigned char res;
+    write8(1,",@read_action,");
+    wait_cond8(0,",@read_action,");
+    return read8(",@value,");
+}
+
+void mem_write(unsigned char val, unsigned char addr) {
+    unsigned char res;
+    write8(1,",@write_action,");
+    write8(val,",@value,");
+    wait_cond8(0,",@write_action,");
+}
+"], h:
+"extern unsigned char mem_read(unsigned char addr);
+extern void mem_write(unsigned char val, unsigned char addr);
+"
+    end
+
+
+
+    ## Generates a read of signal +sig+.
+    def read(code,sig)
+        # Generate the resulting SW access.
+        return ["mem_read(",code,"0x#{self.allocator.get(sig).to_s(16)})"]
+    end
+
+    ## Generates a write of +val+ to signal +sig+.
+    def write(val,sig)
+        # Generate the resulting SW access.
+        return ["mem_write(,",code,",#{val},#{self.allocator.get(sig).to_s(16)})"]
+    end
+end
+
+
+
+
+
+
+# An 8-bit register with C encrypting.
+system :encrypt_register do |cpu|
+    input  :clk, :rst
+    [8].input :d
+    [8].output :q
+
+    my_cpy = cpu.new(clk,rst)
+
+    my_cpu.connect(d)
+    my_cpu.connect(q)
+    my_cpu.controller
+
+    code clk.posedge, c: [ "
+#include <stdio.h>
+#include \"hruby_sim.h\"
+#include \"hruby_sim_gen.h\"
+
+void encrypt() {
+    static char keys[] = { 'S', 'e', 'c', 'r', 'e', 't', ' ', '!' };
+    static int index  = 0;
+    char buf;
+    buf = ",my_cpu.read(self,d),";
+    printf(\"######################## From software: encrypting d=%x\\n\",buf);
+    buf = buf ^ (keys[index]);
+    index = (index + 1) & sizeof(keys)-1;
+    printf(\"######################## From software: result =%x\\n\",buf);
+    ",my_cpu.write(self,"buf",q),";
+    
+}
+        " ],
+        sim: "encrypt"
+end
+
+# A benchmark for the register.
+system :encrypt_bench do
+    [8].inner :d, :clk, :rst
+    [8].inner :q
+
+    encrypt_register(:my_register).(clk,rst,d,q)
+
+    timed do
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 0
+        rst <= 1
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 1
+        d   <= 0
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 1
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 2
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 2
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 255
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 255
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 255
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 0
+        rst <= 0
+        d   <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        d   <= 0
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/system_open.rb

@@ -0,0 +1,11 @@
+system :dff do
+   input :clk, :rst, :d
+   output :q
+
+   (q <= d & ~rst).at(clk.posedge)
+end
+
+dff.open do
+   output :qb
+   qb <= ~q
+end

data/lib/HDLRuby/hdr_samples/tuple.rb

@@ -0,0 +1,16 @@
+system :dff do
+   input :clk, :rst, :d
+   output :q
+
+   par(clk.posedge) { q <= d & ~rst }
+end
+
+system :my_system do
+   input :clk, :rst
+   [bit, bit].inner :zig
+   
+   dff(:dff0).(clk: clk, rst: rst)
+   dff(:dff1).(clk: clk, rst: rst)
+   dff0.d <= zig[0]
+   dff1.d <= zig[1]
+end

data/lib/HDLRuby/hdr_samples/with_channel.rb

@@ -0,0 +1,118 @@
+
+require '../std/channel.rb'
+
+include HDLRuby::High::Std
+
+# Implementation of a handshaker channel transmitting generic values
+channel(:handshaker) do |typ|
+    # The buffer holding the value to transmit
+    typ.inner :buf
+    # The handshaking lock signals.
+    # Each signal is modified one-sided (reader or writer),
+    # hence a double lock valid/ready is required.
+    inner :read_valid, :read_ready, :write_valid, :write_ready
+    # Sets the reader inputs ports.
+    reader_input :buf, :read_valid, :read_ready
+    # Sets the reader output ports.
+    reader_output :write_valid, :write_ready
+
+    # Sets the writer input ports.
+    writer_input :write_valid, :write_ready
+    # Sets the writer output ports.
+    writer_output :buf, :read_valid, :read_ready
+
+    # Defines the reset command for the channel.
+    command(:reset) do
+        par do
+            # Fully locked reader side.
+            read_valid  <= 0
+            read_ready  <= 0
+            # Fully unlocked writer side.
+            write_valid <= 1
+            write_ready <= 1
+        end
+    end
+
+    # Defines the reader's access procedure.
+    reader do |blk,target|
+        hif(read_valid) do
+            write_valid <= 0
+            write_ready <= 0
+            hif(read_ready) do
+                target <= buf
+                write_valid <= 1
+                blk.call if blk
+            end
+        end
+        helse { write_ready <= 1 }
+    end
+
+    # Defines the writer's access procedure.
+    writer do |blk,target|
+        hif(write_valid) do
+            read_valid <= 0
+            read_ready <= 0
+            hif(write_ready) do
+                buf <= target
+                read_valid <= 1
+                blk.call if blk
+            end
+        end
+        helse { read_ready <= 1 }
+    end
+end
+
+
+
+
+# A system writing indefinitely to a channel.
+system :producer8 do |channel|
+    # puts "channel=#{channel}"
+    # Inputs of the producer: clock and reset.
+    input :clk, :rst
+    # Instantiate the channel ports
+    channel.writer_ports
+    # Inner 8-bit counter for generating values.
+    [8].inner :counter
+
+    # The value production process
+    par(clk.posedge) do
+        hif(rst) { counter <= 0 }
+        helse do
+            channel.write(counter) { counter <= counter + 1 }
+        end
+    end
+end
+
+# A system reading indefinitely from a channel.
+system :consummer8 do |channel|
+    # Input of the consummer: a clock is enough.
+    input :clk
+    # Instantiate the channel ports
+    channel.reader_ports
+    # Inner buffer for storing the cunsummed value.
+    [8].inner :buf
+
+    # The value consumption process
+    par(clk.posedge) do
+        channel.read(buf)
+    end
+end
+
+
+# A system testing the handshaker.
+system :hs_test do
+    input :clk,:rst
+
+    # Declares the handshaker
+    handshaker([8]).(:hs)
+
+    # Sets the reset.
+    hs.reset.at(rst.posedge)
+
+    # Instantiate the producer.
+    producer8(hs).(:producerI).(clk,rst,*hs.writer_signals)
+
+    # Instantiate the consummer.
+    consummer8(hs).(:consummerI).(clk,*hs.reader_signals)
+end