HDLRuby 2.0.8

data/lib/HDLRuby/high_samples/ram.rb

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+require 'HDLRuby'
+
+configure_high
+
+# Describes an 8-bit data 16-bit address RAM.
+system :ram8_16 do
+    input :rwb, :en
+    [15..0].input :addr
+    [7..0].inout :data
+
+    bit[7..0][2**16].inner :content
+
+    # Reading the memory
+    data <= mux(en && rwb, content[addr], _bhZZ)
+    # Writing the memory
+    ( content[addr] <= data ).hif(en && ~rwb)
+end
+
+# Instantiate it for checking.
+ram8_16 :ram8_16I
+
+
+# Generate the low level representation.
+low = ram8_16I.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/registers.rb

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+require 'HDLRuby'
+
+configure_high
+
+# Describes a simple D-FF
+system :dff0 do
+    bit.input :clk, :rst, :d
+    bit.output :q, :qb
+
+    qb <= ~q
+
+    par(clk.posedge) do
+        q <= d & ~rst
+    end
+end
+
+# Instantiate it for checking.
+dff0 :dff0I
+
+
+# Decribes another D-FF
+system :dff1 do
+    input :clk, :rst, :d
+    output :q, :qb
+
+    qb <= ~q
+    (q <= d & ~rst).at(clk.posedge)
+end
+
+# Instantiate it for checking.
+dff1 :dff1I
+
+
+# Describes an 8-bit register
+system :reg8 do
+    input :clk, :rst
+    [7..0].input :d
+    [7..0].output :q, :qb
+
+    qb <= ~q
+    (q <= d & [~rst]*8).at(clk.posedge)
+end
+
+# Instantiate it for checking.
+reg8 :reg8I
+
+
+# Describes a n-bit register.
+system :regn do |n|
+    input :clk, :rst
+    [n-1..0].input :d
+    [n-1..0].output :q,:qb
+
+    qb <= ~q
+    (q <= d & [~rst]*n).at(clk.posedge)
+end
+
+# Instantiate it for checking.
+regn :regn8I,8
+
+
+# Describes a register of generic type.
+system :reg do |typ|
+    input :clk, :rst
+    typ.input :d
+    typ.output :q,:qb
+
+    qb <= ~q
+    (q <= d & [~rst]*typ.width).at(clk.posedge)
+end
+
+# Instantiate it for checking.
+reg :regbit8I, bit[7..0]
+
+
+
+# Function generating the body of a register description.
+def make_reg_body(typ)
+    input :clk, :rst
+    typ.input :d
+    typ.output :q,:qb
+
+    qb <= ~q
+    (q <= d & [~rst]*typ.width).at(clk.posedge)
+end
+
+# Now declare the systems decribing the registers.
+system :dff_body do
+    make_reg_body(bit)
+end
+
+system :reg8_body do
+    make_reg_body(bit[7..0])
+end
+
+system :regn_body do |n|
+    make_reg_body(bit[n-1..0])
+end
+
+system :reg_body do |typ|
+    make_reg_body(typ)
+end
+
+# Instantiate these systems for checking them.
+dff_body  :dff_bodyI
+reg8_body :reg8_bodyI
+regn_body :regn_bodyI, 8
+reg_body  :reg_bodyI, bit[7..0]
+
+
+# Function generating a register declaration.
+def make_reg(name,&blk)
+    system name do |*arg|
+        input :clk, :rst
+        blk.(*arg).input :d
+        blk.(*arg).output :q,:qb
+
+        qb <= ~q
+        (q <= d & [~rst]*blk.(*arg).width).at(clk.posedge)
+    end
+end
+
+# Now let's generate the register declarations.
+make_reg(:dff_make) { bit }
+make_reg(:reg8_make){ bit[7..0] }
+make_reg(:regn_make){ |n| bit[n-1..0] }
+make_reg(:reg_make) { |typ| typ }
+
+# Instantiate these systems for checking them.
+dff_make  :dff_makeI
+reg8_make :reg8_makeI
+regn_make :regn_makeI, 8
+reg_make  :reg_makeI, bit[7..0]
+
+# Generate the low level representation.
+low = reg_makeI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/rom.rb

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+require 'HDLRuby'
+
+configure_high
+
+# Describes an 8-bit data 8-bit address ROM.
+system :rom8_8 do
+    [7..0].input :addr
+    [7..0].inout :data
+
+    bit[7..0][2**8].constant content: (2**8).times.to_a
+
+    data <= content[addr]
+end
+
+# Instantiate it for checking.
+rom8_8 :rom8_8I
+
+
+# Generate the low level representation.
+low = rom8_8I.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/scopeblockname.rb

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+require 'HDLRuby'
+
+configure_high
+
+
+# A system with named scopes and blocks.
+system :with_names do
+    [15..0].input  :x, :y, :z
+    [16..0].output :u, :v
+
+    sub :me do
+        inner :a
+        a <= x + y
+    end
+
+    par do
+        inner :a
+        a <= me.a * z
+
+        sub :myself do
+            inner :a
+            a <= y - z
+        end
+        u <= a * myself.a
+    end
+
+    v <= me.a - z
+end
+
+# Instantiate it for checking.
+with_names :with_namesI
+
+# Generate the low level representation.
+low = with_namesI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/scopescope.rb

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+require 'HDLRuby'
+
+configure_high
+
+# System with scopes within scopes.
+system :scopescope do
+    input  :i0,:i1
+    output :o0,:o1
+    inner  :s0
+
+    sub do
+        inner :s0
+        sub do
+            inner :s0
+        end
+    end
+end
+
+# Instantiate it for checking.
+scopescope :scopescopeI
+
+# Generate the low level representation.
+low = scopescopeI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/shift.rb

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+require 'HDLRuby'
+
+configure_high
+
+
+# Describes an 16-bit shift register.
+system :shift16 do
+    input :clk, :rst, :din
+    output :dout
+
+    [15..0].inner :reg
+
+    dout <= reg[15] # The output is the last bit of the register.
+
+    par(clk.posedge) do
+        hif(rst) { reg <= 0 }
+        helse seq do
+            reg[0] <= din
+            reg[15..1] <= reg[14..0]
+        end 
+    end
+end
+
+# Instantiate it for checking.
+shift16 :shift16I
+
+# Generate the low level representation.
+low = shift16I.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/shift2.rb

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+require 'HDLRuby'
+
+configure_high
+
+
+system :dff do
+   input :clk, :rst, :d
+   output :q, :qb
+
+   qb <= ~q
+
+   (q <= d & ~rst).at(clk.posedge)
+end
+
+system :shifter do |n|
+   input :i0
+   output :o0, :o0b
+
+   # Instantiating n D-FF
+   [n].dff :dffIs
+
+   # Interconnect them as a shift register
+   dffIs[0..-2].zip(dffIs[1..-1]) do |ff0,ff1|
+       ff1.d <= ff0.q 
+   end
+
+   # Connects the input and output of the circuit
+   dffIs[0].d <= i0
+   o0 <= dffIs[-1].q
+   o0b <= dffIs[-1].qb
+end
+
+# Instantiate it for checking.
+shifter(16).(:shifterI)
+
+# Generate the low level representation.
+low = shifterI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/simple_instance.rb

@@ -0,0 +1,31 @@
+require 'HDLRuby'
+
+configure_high
+
+# Simple test of instantiation.
+
+
+system :io do
+    input :i
+    output :o
+
+    i <= o
+end
+
+system :with_io do
+    input :i
+    output :o
+
+    io(:ioI).(i: i, o: o)
+end
+
+
+
+# Instantiate it for checking.
+with_io :with_ioI
+
+# Generate the low level representation.
+low = with_ioI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/test_all.sh

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+#!/bin/bash
+# Script for testing all the samples
+
+for file in *.rb
+do
+    # Skip the samples starting by "_" (they are WIP)
+    if [[ ${file:0:1} == "_" ]] ; then continue; fi
+    # A sample to check
+    bundle exec ruby "$file" || exit 1
+done

data/lib/HDLRuby/high_samples/typedef.rb

@@ -0,0 +1,24 @@
+require 'HDLRuby'
+
+configure_high
+
+# Definition of the word type.
+[15..0].typedef(:word)
+
+
+# A simple adder using previously defined type word
+system :adder do
+    word.input :x,:y
+    word.output :s
+
+    s <= x + y
+end
+
+# Instantiate it for checking.
+adder :adderI
+
+# Generate the low level representation.
+low = adderI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/values.rb

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+require 'HDLRuby'
+
+configure_high
+
+# Describes a system including several value.
+system :values do
+    [3..0].output :sig
+
+    timed do
+        !1.us
+        sig <= _1010
+        !1.us
+        sig <= _b4b1010
+        !1.us
+        sig <= _bb1001
+        !1.us
+        sig <= _b1100
+
+        !1.us
+        sig <= _u4b1010
+        !1.us
+        sig <= _ub1001
+        !1.us
+        sig <= _u1100
+
+        !1.us
+        sig <= _s4b1010
+        !1.us
+        sig <= _sb1001
+        !1.us
+        sig <= _s1100
+
+        !1.us
+        sig <= _b12o0623
+        !1.us
+        sig <= _bo0623
+        !1.us
+        sig <= _b12d0923
+        !1.us
+        sig <= _bd0923
+        !1.us
+        sig <= _b16h0F2E
+        !1.us
+        sig <= _bh0F2E
+
+        !1.us
+        sig <= _b1ZZX
+
+        !1.us
+        sig <= _b0110 + _b0110
+        !1.us
+        sig <= _b0110 - _b0110
+        !1.us
+        sig <= _b0110 * _b0010
+        !1.us
+        sig <= _b0110 / _b0010
+        !1.us
+        sig <= _b0110 % _b0010
+    end
+end
+
+
+# Instantiate it for checking.
+values :valuesI
+
+# Generate the low level representation.
+low = valuesI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/vector.rb

@@ -0,0 +1,22 @@
+require 'HDLRuby'
+
+configure_high
+
+# Describes a system including several vector types.
+system :vectors do
+    [7..0].input :byte
+    [ bit[8], signed[16], unsigned[16] ].output :bss
+
+    # For testing each_type, no hardware is generated.
+    bss.type.each_type {|t| }
+end
+
+
+# Instantiate it for checking.
+vectors :vectorsI
+
+# Generate the low level representation.
+low = vectorsI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/with_decoder.rb

@@ -0,0 +1,30 @@
+require 'HDLRuby'
+
+configure_high
+
+require 'HDLRuby/std/decoder'
+include HDLRuby::High::Std
+
+# Implementation of a decoder.
+system :my_decoder do
+    [7..0].input :a
+    [7..0].output :z
+
+    decoder(a) do
+        entry("1000uuvv") { z <= u + v }
+        entry("101uuuvv") { z <= u - v }
+        entry("1100uuvv") { z <= u & v }
+        entry("1101uuvv") { z <= u | v }
+        entry("1110uuvv") { z <= u ^ v }
+        default           { z <= 0     }
+    end
+end
+
+# Instantiate it for checking.
+my_decoder :my_decoderI
+
+# Generate the low level representation.
+low = my_decoderI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/with_fsm.rb

@@ -0,0 +1,46 @@
+require 'HDLRuby'
+
+configure_high
+
+require 'HDLRuby/std/fsm'
+include HDLRuby::High::Std
+
+# Implementation of a fsm.
+system :my_fsm do
+    input :clk,:rst
+    [7..0].input :a, :b
+    [7..0].output :z
+
+    # fsm :fsmI 
+    # fsmI.for_event { clk.posedge }
+    # # Shortcut: fsmI.for_event(clk)
+    # fsmI.for_reset { rst }
+    # # Shortcut: fsmI.for_reset(rst)
+    # fsmI do
+    #     state         { z <= 0 }
+    #     state(:there) { z <= a+b }
+    #     state do
+    #         hif (a>0) { z <= a-b }
+    #         helse { goto(:there) }
+    #     end
+    # end
+    # Other alternative:
+    fsm(clk.posedge,rst) do
+        reset         { z <= 0 }
+        state         { z <= a+b }
+        state(:there) do
+            hif (z!=0) { z <= a-b }
+            goto(z==0,:end,:there)
+        end
+        state(:end)   { goto(:end) }
+    end
+end
+
+# Instantiate it for checking.
+my_fsm :my_fsmI
+
+# Generate the low level representation.
+low = my_fsmI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/with_pipe.rb

@@ -0,0 +1,43 @@
+require 'HDLRuby'
+
+configure_high
+
+
+require 'HDLRuby/std/pipeline'
+include HDLRuby::High::Std
+
+
+# A simple test of the pipeline construct
+system :with_pipe do
+    input :clk,:rst
+    [15..0].input :x, :y
+    [31..0].input :z
+    [31..0].output :u, :v
+
+
+    pipeline :pipeI # Shortcut: pipeline(clk,rst).(:fsmI)
+    pipeI.for_event { clk.posedge }
+    # Shortcut: pipeI.clk = clk
+    pipeI.for_reset { rst }
+    # Shortcut: pipeI.rst = rst
+
+    pipeI do
+        stage        { a <= x + y }
+        stage(:a) do
+            b <= a + z
+            c <= a - z
+            d <= a * z
+        end
+        stage(:b,:c) { e <= b + c }
+        stage(:d,:e) { v <= d + e }
+    end
+end
+
+# Instantiate it for checking.
+with_pipe :with_pipeI
+
+# Generate the low level representation.
+low = with_pipeI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/with_seq.rb

@@ -0,0 +1,25 @@
+require 'HDLRuby'
+
+configure_high
+
+
+# A example of behavior with default seq
+system :with_seq do
+    [15..0].input :x,:y, :clk
+    [16..0].inner :w
+    [16..0].output :o
+
+    seq(clk.posedge) do
+       w <= x + y
+       o <= w + y
+    end
+end
+
+# Instantiate it for checking.
+with_seq :with_seqI
+
+# Generate the low level representation.
+low = with_seqI.systemT.to_low
+
+# Displays it
+puts low.to_yaml