HDLRuby 2.0.8

data/lib/HDLRuby/hruby_low_with_var.rb

@@ -0,0 +1,302 @@
+require "HDLRuby/hruby_error"
+require "HDLRuby/hruby_low_mutable"
+require "HDLRuby/hruby_low2sym"
+require "HDLRuby/hruby_low2seq"
+
+
+##
+# Explicitely seperate variables from signals in an HDLRuby::Low
+# description.
+#
+# NOTE: variable and signal are to be taken in the VHDL meaning.
+#
+########################################################################
+module HDLRuby::Low
+
+    ## Extends the SystemT class with separation between signals and variables.
+    class SystemT
+        # Converts to a variable-compatible system.
+        #
+        # NOTE: the result is the same systemT.
+        def with_var!
+            self.each_behavior { |behavior| behavior.with_var! }
+            return self
+        end
+    end
+
+
+    ## Extends the SystemI class with separation between signals and variables.
+    class SystemI
+        # Converts to a variable-compatible system.
+        #
+        # NOTE: the result is the same systemT.
+        def with_var!
+            self.systemT.with_var!
+            return self
+        end
+    end
+
+
+    ## Extends the Behavior class with separation between signals and variables.
+    class Behavior
+        # Converts to a variable-compatible behavior.
+        #
+        # NOTE: the result is the same systemT.
+        def with_var!(upper = nil)
+            @block = @block.with_var
+            @block.parent = self
+            return self
+        end
+    end
+
+
+    ## Extends the Block class with separation between signals and variables.
+    class Block
+
+        # Converts a variable to a reference to it.
+        def var2ref(var)
+            return RefName.new(var.type,RefThis.new,var.name)
+        end
+
+        # Converts symbol +sym+ representing an HDLRuby reference to a variable
+        # name.
+        def sym2var_name(sym)
+            return ("%" + sym.to_s).to_sym
+        end
+
+        # Converts a variable +name+ to the symbol giving the corresponding
+        # HDLRuby reference.
+        def var_name2sym(name)
+            return name[1..-1].to_sym
+        end
+
+        # Tell if a name is a variable one.
+        def variable_name?(name)
+            name[0] == "%"
+        end
+
+        # Extract the variables corresponding to external signals from
+        # block-based statement +stmnt+, and put the extraction result is
+        # table +sym2var+ that associate variable with corresponding signal
+        # name.
+        def extract_from_externals!(stmnt,sym2var)
+            if (stmnt.is_a?(Block)) then
+                # Block case, gather its declared and signals variables.
+                vars = {}
+                sigs = {}
+                stmnt.each_inner do |inner|
+                    if variable_name?(inner.name) then
+                        vars[inner.name] = inner
+                    else
+                        sigs[inner.name] = inner
+                    end
+                end
+                # Select the variables that correspond to external signals.
+                vars.each do |name,inner|
+                    sym = var_name2sym(name)
+                    unless sigs.key?(sym) then
+                        # The variable correspond to an external signal,
+                        # extract it.
+                        sym2var[sym] = inner
+                        stmnt.delete_inner(inner)
+                    end
+                end
+            elsif
+                # Other case, recurse on the sub blocks.
+                stmnt.each_block do |block|
+                    extract_from_externals!(block,sym2var)
+                end
+            end
+        end
+
+
+        # Replaces the references by corresponding variables in +stmnt+ from
+        # +sym2var+ table.
+        def refs_by_variables!(stmnt,sym2var)
+            # First, recurse.
+            if stmnt.respond_to?(:each_node) then
+                stmnt.each_node {|elem| refs_by_variables!(elem,sym2var) }
+            end
+            # Now replace an element if required.
+            if stmnt.respond_to?(:map_nodes!) then
+                stmnt.map_nodes! do |elem| 
+                    var = sym2var[elem.to_sym]
+                    var ? var2ref(var) : elem
+                end
+            end
+        end
+
+        # Get access to the variables
+        def variables
+            # Initializes the set of variables if required.
+            @variables ||= {}
+            return @variables
+        end
+       
+        # Adds variable +name+ with +type+.
+        def add_variable(name,type)
+            # Ensure name is a symbol.
+            name = name.to_sym
+            # Declares the variable as an inner.
+            inner = add_inner(SignalI.new(name,type))
+            # And register it as a variable.
+            variables[name] = inner 
+        end
+
+        # Gets a variable by +name+.
+        def get_variable(name)
+            # Ensure name is a symbol.
+            name = name.to_sym
+            # Get the variable.
+            return variables[name]
+        end
+
+
+        # Converts to a variable-compatible block where +upper+ is
+        # the upper block if any.
+        #
+        # NOTE: the result is a new block.
+        def with_var(upper = nil)
+            # puts "with_var for #{self} with upper=#{upper}"
+            # Recurse on the statements.
+            new_stmnts = []
+            self.each_statement do |stmnt|
+                # Process stmnt
+                if stmnt.respond_to?(:with_var) then
+                    # Can be converted
+                    stmnt = stmnt.with_var(self)
+                else
+                    # Cannot be converted, simply clone.
+                    stmnt = stmnt.clone
+                end
+                # Adds the result.
+                new_stmnts << stmnt
+            end
+            # Handle the cases that does not need directly a variable
+            # convertion
+            # Is the block a par?
+            if self.mode == :par then
+                # Yes, creates a new block with the new statements.
+                block = Block.new(self.mode)
+                self.each_inner { |inner| block.add_inner(inner.clone) }
+                new_stmnts.each {|stmnt| block.add_statement(stmnt) }
+                # Is the block within a seq?
+                if upper && upper.mode == :seq then
+                    # Yes, converts to seq.
+                    # return self.to_seq
+                    return block.blocks2seq!
+                end
+                # No, simply return the block.
+                # block = self.clone
+                return block
+            end
+
+            # The block is a seq, convert it.
+            # Treat the block
+            sym2var = {} # The table of variable by corresponding signal name
+            # Generate and replace the variables
+            new_stmnts.each do |stmnt|
+                unless stmnt.is_a?(Transmit) then
+                    # The statement is not a transmission, extract the
+                    # variables that correspond to external signals.
+                    extract_from_externals!(stmnt,sym2var)
+                else 
+                    # Other case: transmission, the left value is to convert
+                    # to a variable, and the right values are to be updated
+                    # with the existing variables.
+                    # First convert the left value to the corresponding symbol.
+                    sym = stmnt.left.to_sym
+                    # puts "sym=#{sym}"
+                    var = sym2var[sym]
+                    unless var then
+                        var = SignalI.new(sym2var_name(sym),stmnt.left.type)
+                        sym2var[sym] = var
+                    end
+                    # Then replace the relevant references by corresponding
+                    # variables
+                    refs_by_variables!(stmnt,sym2var)
+                end
+            end
+            # puts "sym2var=#{sym2var}"
+            # Declare the variables in the top block.
+            top = self.top_block
+            # puts "top=#{top}"
+            sym2var.each_value do |var|
+                # puts "Adding var=#{var.name}"
+                top.add_inner(var.clone) unless top.each_inner.find {|v| v.eql?(var) }
+            end
+            # Generate the new block.
+            result = self.class.new(self.mode,self.name)
+            # Adds the inner signals of current block.
+            self.each_inner do |inner|
+                result.add_inner(inner.clone)
+            end
+            # Adds the new statements.
+            new_stmnts.each do |stmnt|
+                result.add_statement(stmnt)
+            end
+            # Adds final statements assigning variables back to the orginal
+            # signals.
+            sym2var.each do |sym,var|
+                result.add_statement(
+                    Transmit.new(sym.to_hdr.clone,var2ref(var)))
+            end
+            # End of the conversion.
+            return result
+        end
+
+    end
+
+    ## Extends the If class with separation between signals and variables.
+    class If
+        # Converts to a variable-compatible if where +upper+ is
+        # the upper block if any.
+        #
+        # NOTE: the result is a new if.
+        def with_var(upper = nil)
+            # Treat the sub nodes.
+            # Condition.
+            ncond = self.condition.clone
+            # Yes.
+            nyes =self.yes.with_var(upper)
+            # Noifs.
+            noifs = self.each_noif.map do |cond,stmnt|
+                [cond.clone,stmnt.with_var(upper)]
+            end
+            # No.
+            nno = self.no ? self.no.with_var(upper) : nil
+            # Create the resulting If.
+            res= If.new(ncond,nyes, nno)
+            noifs.each do |cond,stmnt|
+                res.add_noif(cond,stmnt)
+            end
+            return res
+        end
+    end
+
+
+    ## Extends the When class with separation between signals and variables.
+    class When
+        # Converts to a variable-compatible case where +upper+ is
+        # the upper block if any.
+        #
+        # NOTE: the result is a new case.
+        def with_var(upper = nil)
+            return When.new(self.match.clone,self.statement.with_var(upper))
+        end
+    end
+
+
+    ## Extends the Case class with separation between signals and variables.
+    class Case
+        # Converts to a variable-compatible case where +upper+ is
+        # the upper block if any.
+        #
+        # NOTE: the result is a new case.
+        def with_var(upper = nil)
+            ndefault = self.default ? self.default.clone : nil
+            return Case.new(self.value.clone,ndefault,
+                            self.each_when.map {|w| w.with_var(upper) })
+        end
+    end
+end

data/lib/HDLRuby/hruby_low_without_bit2vector.rb

@@ -0,0 +1,88 @@
+require "HDLRuby/hruby_error"
+require "HDLRuby/hruby_low_mutable"
+
+
+##
+# Ensures that there is no conversion of bit types to vector types.
+#
+#
+# NOTE: Used for instance for converting to old versions of VHDL where
+#       bit types cannot be casted to vector types.
+#
+########################################################################
+module HDLRuby::Low
+
+
+
+    ## Extends the SystemT class for removing bit to vector conversions.
+    class SystemT
+        # Replace bit to vector conversions by assignment to on bit of
+        # an intermediate inner vector.
+        #
+        # NOTE: the result is the same systemT.
+        def bit2vector2inner!
+            # puts "For system: #{self.name}"
+            # First gather the bit conversions to vector.
+            bits2vectors = Set.new
+            gather_bits2vectors = proc do |node|
+                if node.is_a?(Expression) && node.type == Bit &&
+                        node.parent.is_a?(Expression) && 
+                        # References are not relevant parents
+                        !node.parent.is_a?(Ref) && 
+                        # Neither do concat that are processed separatly
+                        !node.parent.is_a?(Concat) && 
+                        node.parent.type != Bit then
+                    # puts "node=#{node.to_high}, node.parent=#{node.parent}"
+                    bits2vectors.add(node)
+                end
+            end
+            # Apply the procedure for gathering the read on outputs signals.
+            self.scope.each_scope_deep do |scope|
+                scope.each_connection do |connection|
+                    # Recurse on the connection.
+                    connection.each_node_deep(&gather_bits2vectors)
+                end
+                scope.each_behavior do |behavior|
+                    behavior.each_event do |event|
+                        gather_bits2vectors.(event.ref)
+                    end
+                    behavior.each_statement do |statement|
+                        # puts "statement=#{statement.class}"
+                        statement.each_node_deep(&gather_bits2vectors)
+                    end
+                end
+            end
+            # puts "bits2vectors=#{bits2vectors.size}"
+
+            # Create the 1-bit-vector type.
+            vec1T = TypeVector.new(:"bit1",Bit,0..0)
+            # Generate one inner 1-bit-vector signal per read output.
+            bit2inner = {}
+            bits2vectors.each do |node|
+                # Generate the inner variable.
+                sig = self.scope.add_inner(SignalI.new(HDLRuby::uniq_name,vec1T))
+                ref = RefName.new(vec1T,RefThis.new,sig.name)
+                bit2inner[node] = 
+                    [ ref, RefIndex.new(Bit,ref,Value.new(Integer,0)) ]
+                # puts "new inner=#{out2inner[name].name}"
+            end
+
+            # Apply the replacement procedure on the code
+            self.scope.each_scope_deep do |scope|
+                scope.each_connection.to_a.each do |connection|
+                    connection.reassign_expressions!(bit2inner)
+                end
+                scope.each_behavior do |behavior|
+                    behavior.each_event do |event|
+                        event.reassign_expressions!(bit2inner)
+                    end
+                    behavior.block.reassign_expressions!(bit2inner)
+                end
+            end
+
+            return self
+        end
+    end
+
+
+end

data/lib/HDLRuby/hruby_low_without_concat.rb

@@ -0,0 +1,162 @@
+require 'HDLRuby'
+require 'HDLRuby/hruby_tools'
+require 'HDLRuby/hruby_low_mutable'
+
+
+module HDLRuby::Low
+
+
+##
+# Breaks the concat assigments.
+# Makes handling by some synthesis tools easier.
+#
+########################################################################
+    
+
+    ## Extends the SystemT class with functionality for breaking assingments
+    #  to concats.
+    class SystemT
+
+        # Breaks the assignments to concats.
+        def break_concat_assigns!
+            self.scope.break_concat_assigns!
+        end
+
+    end
+
+    ## Extends the Scope class with functionality for breaking assingments
+    #  to concats.
+    class Scope
+        # Breaks the assignments to concats.
+        def break_concat_assigns!
+            # Recruse on the sub scopes.
+            self.each_scope(&:break_concat_assigns!)
+            # Recurse on the statements.
+            self.each_behavior do |behavior|
+                behavior.block.each_block_deep(&:break_concat_assigns!)
+            end
+            # Work on the connections.
+            self.each_connection.to_a.each do |connection|
+                nconnection = connection.break_concat_assigns
+                if nconnection.is_a?(Block) then
+                    # The connection has been broken, remove the former
+                    # version and add the generated block as a behavior.
+                    self.remove_connection(connection)
+                    self.add_behavior(Behavior.new(nconnection))
+                end
+            end
+        end
+    end
+
+    ## Extends the Block class with functionality for breaking assingments
+    #  to concats.
+    class Block
+        # Breaks the assignments to concats.
+        #
+        # NOTE: work on the direct sub statement only, not deeply.
+        def break_concat_assigns!
+            # Check each transmit.
+            self.each_statement.each.with_index do |stmnt,i|
+                if stmnt.is_a?(Transmit) then
+                    # Transmit, breaking may be necessary.
+                    nstmnt = stmnt.break_concat_assigns
+                    if nstmnt.is_a?(Block) then
+                        # The transmit has been broken, remove the former
+                        # version and add the generated block as a behavior.
+                        self.set_statement!(i,nstmnt)
+                    end
+                end
+            end
+        end
+    end
+
+
+    ## Extends the Transmit class with functionality for breaking assingments
+    #  to concats.
+    class Transmit
+        # Break the assignments to concats.
+        #
+        # NOTE: when breaking generates a new Block containing the broken
+        #       assignments.
+        def break_concat_assigns
+            # puts "break_concat_assigns with self=#{self}"
+            # Is the left value a RefConcat?
+            self.left.each_node_deep do |node|
+                if node.is_a?(RefConcat) then
+                    # Yes, must break. Create the resulting sequential
+                    # block that will contain the new assignements.
+                    block = Block.new(:seq)
+                    # Create an intermediate signal for storing the
+                    # right value. Put it in the top scope.
+                    top_block = self.top_block
+                    top_scope = top_block.top_scope
+                    aux = top_scope.add_inner(
+                        SignalI.new(HDLRuby.uniq_name,self.right.type) )
+                    # puts "new signal: #{aux.name}"
+                    aux = RefName.new(aux.type,RefThis.new,aux.name)
+                    # Is a default value required to avoid latch generation?
+                    unless top_block.parent.each_event.
+                            find {|ev| ev.type!=:change} then
+                        # Yes, generate it.
+                        top_block.insert_statement!(0,
+                            Transmit.new(aux.clone,Value.new(aux.type,0)))
+                    end
+                    # Replace the concat in the copy of the left value.
+                    if left.eql?(node) then
+                        # node was the top of left, replace here.
+                        nleft = aux
+                    else
+                        # node was inside left, replace within left.
+                        nleft = self.left.clone
+                        nleft.each_node_deep do |ref|
+                            ref.map_nodes! do |sub|
+                                sub.eql?(node) ? aux.clone : sub
+                            end
+                        end
+                    end
+                    # Recreate the transmit and add it to the block.
+                    block.add_statement(
+                        Transmit.new(nleft,self.right.clone) )
+                    # And assign its part to each reference of the
+                    # concat.
+                    pos = 0
+                    node.each_ref.reverse_each do |ref|
+                        # Compute the range to assign.
+                        range = ref.type.width-1+pos .. pos
+                        # Single or multi-bit range?
+                        sbit = range.first == range.last
+                        # Convert the range to an HDLRuby range for 
+                        # using is the resulting statement.
+                        # Create and add the statement.
+                        if sbit then
+                            # Single bit.
+                            # Generate the index.
+                            idx = Value.new(Integer,range.first)
+                            # Generate the assignment.
+                            block.add_statement(
+                                Transmit.new(ref.clone,
+                                RefIndex.new(aux.type.base, aux.clone, idx)))
+                        else
+                            # Multi-bits.
+                            # Compute the type of the right value.
+                            rtype = TypeVector.new(:"",aux.type.base,range)
+                            # Generate the range.
+                            range = Value.new(Integer,range.first) ..
+                                    Value.new(Integer,range.last)
+                            # Generate the assignment.
+                            block.add_statement(
+                                Transmit.new(ref.clone,
+                                RefRange.new(rtype, aux.clone, range)))
+                        end
+                        pos += ref.type.width
+                    end
+                    # puts "Resulting block=#{block.to_vhdl}"
+                    # Return the resulting block
+                    return block
+                end
+            end
+            # No, nothing to do.
+            return self
+        end
+    end
+end

data/lib/HDLRuby/hruby_low_without_connection.rb

@@ -0,0 +1,113 @@
+require 'HDLRuby'
+require 'HDLRuby/hruby_tools'
+require 'HDLRuby/hruby_low_resolve'
+require 'HDLRuby/hruby_low_mutable'
+
+
+module HDLRuby::Low
+
+
+##
+# Convert the connections to transmit statement within a behavior.
+# Used by the HDLRuby simulator.
+#
+########################################################################
+    
+
+    ## Extends the SystemT class with functionality for breaking assingments
+    #  to concats.
+    class SystemT
+
+        ## Remove the connections and replace them by behaviors.
+        #  NOTE: one behavior is created for input connections and
+        #        one for output ones while inout/inner-only connections
+        #        are copied in both behaviors.
+        def connections_to_behaviors!
+            # Process the connections: create a behavior containing
+            # them all within a par block.
+            self.scope.each_scope_deep do |scope|
+                if scope.each_connection.to_a.any? then
+                    inputs_blk = Block.new(:par)
+                    outputs_blk = Block.new(:par)
+                    scope.each_connection do |connection|
+                        # Check the left and right of the connection
+                        # for input or output port.
+                        left = connection.left
+                        left_r = left.resolve
+                        # puts "left_r=#{left_r.name}" if left_r
+                        # puts "left_r.parent=#{left_r.parent.name}" if left_r && left_r.parent
+                        right = connection.right
+                        right_r = right.resolve if right.respond_to?(:resolve)
+                        # puts "right_r=#{right_r.name}" if right_r
+                        # puts "right_r.parent=#{right_r.parent.name}" if right_r && right_r.parent
+                        # Check if left is an input or an output.
+                        left_is_i = left_is_o = false
+                        if left_r && left_r.parent.is_a?(SystemT) then
+                            if left_r.parent.each_input.include?(left_r) then
+                                # puts "Left is input."
+                                # puts "Left is from systemI: #{left.from_systemI?}"
+                                left_is_i = left.from_systemI?
+                                left_is_o = !left_is_i
+                            elsif left_r.parent.each_output.include?(left_r) then
+                                # puts "Left is output."
+                                # puts "Left is from systemI: #{left.from_systemI?}"
+                                left_is_o = left.from_systemI?
+                                left_is_i = !left_is_o
+                            end
+                        end
+                        # Check if right is an input or an output.
+                        right_is_i = right_is_o = false
+                        if right_r && right_r.parent.is_a?(SystemT) then
+                            if right_r.parent.each_input.include?(right_r) then
+                                # puts "Right is input."
+                                # puts "Right is from systemI: #{right.from_systemI?}"
+                                right_is_i = right.from_systemI?
+                                right_is_o = !right_is_i
+                            elsif right_r.parent.each_output.include?(right_r) then
+                                # puts "Right is output."
+                                # puts "Right is from systemI: #{right.from_systemI?}"
+                                right_is_o = right.from_systemI?
+                                right_is_i = !right_is_o
+                            end
+                        end
+                        # puts "left_is_i=#{left_is_i} left_is_o=#{left_is_o}"
+                        # puts "right_is_i=#{right_is_i} right_is_o=#{right_is_o}"
+                        # Fills the relevant block.
+                        if (left_is_i) then
+                            inputs_blk.add_statement(
+                                Transmit.new(left.clone,right.clone))
+                        elsif (right_is_i) then
+                            inputs_blk.add_statement(
+                                Transmit.new(right.clone,left.clone))
+                        elsif (left_is_o) then
+                            outputs_blk.add_statement(
+                                Transmit.new(right.clone,left.clone))
+                        elsif (right_is_o) then
+                            outputs_blk.add_statement(
+                                Transmit.new(left.clone,right.clone))
+                        else
+                            # puts "left/right is inout"
+                            if (left.is_a?(Ref)) then
+                                inputs_blk.add_statement(
+                                    Transmit.new(left.clone,right.clone))
+                            end
+                            if (right.is_a?(Ref)) then
+                                outputs_blk.add_statement(
+                                    Transmit.new(right.clone,left.clone))
+                            end
+                        end
+                    end
+                    # Adds the behaviors.
+                    if inputs_blk.each_statement.any? then
+                        scope.add_behavior(Behavior.new(inputs_blk))
+                    end
+                    if outputs_blk.each_statement.any? then
+                        scope.add_behavior(Behavior.new(outputs_blk))
+                    end
+                end
+            end
+        end
+
+    end
+
+end