HDLRuby 2.0.8

data/lib/HDLRuby/high_samples/_generic_transmission2.rb

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+require 'HDLRuby'
+
+configure_high
+
+require 'HDLRuby/std/channel'
+include HDLRuby::High::Std
+
+# Some very complex system which sends 8 bit values.
+system :systemA do |typ|
+    input :clk, :rst
+    typ :data
+    [7..0].inner :count
+
+    par(clk.posedge) do
+        hif data.can_write? do
+            # count <= mux(rst == 0, 0, count + 1)
+            count <= (rst == 0).mux(0, count + 1) 
+            data <= count
+        end
+    end
+end
+
+
+# Another extremly complex system which recieves 8 bit values.
+system :systemB do |typ|
+    input :clk
+    typ :data
+    output :result
+
+    par(clk.posedge) do
+        hif data.can_read? do
+            result <= mux(data == 0, 0, 1)
+        end
+    end
+end
+
+
+# A system connecting A to B directly.
+system :directAB do
+    input :clk, :rst
+    output :result
+
+    [7..0].inner :a2b
+
+    systemA(:sysA,[7..0]).(clk: clk, data: a2b, rst: rst)
+    systemB(:sysB,[7..0]).(clk: clk, data: a2b, result: result)
+end
+
+# Instantiate it for checking.
+directAB :directABI
+
+# The type used for the buffered serialized communication.
+channel :swriteT do
+    [7..0].output :data
+    output :ready
+    input :ack
+end
+swriteT.on_write! do |chan,stmnt|
+    hif chan.ready == 0 do
+        chan.ready <= 1
+    end
+    helse do
+        (chan.ready <= 0).hif(chan.ack == 1)
+    end
+    stmnt
+end
+swriteT.can_write! do |chan|
+    chan.ack == 1
+end
+channel :sreadT do
+    [7..0].input :data
+    input :ready
+    output :ack
+end
+sreadT.on_read! do |chan,ref,stmnt|
+    hif chan.ready == 1 & chan.ack == 0 do
+        chan.ack <= 1
+        ref <= chan.data
+    end
+    helse do
+        ack <= 0
+    end
+    stmnt
+end
+sreadT.can_read! do
+    ready == 1
+end
+
+# A system connecting A to B through a serial interface.
+system :serialAB do
+    input :clk, :rst
+    output :result
+
+    swriteT :swrite    # Channel for serial write
+    sreadT  :sread     # Channel for serial read
+
+    inner :sdat        # Serial data line
+    inner :ctrl        # Serial control line
+    inner :wr_cnt      # Serial write counter
+    inner :rd_cnt      # Serial read counter
+
+    # Handle the serial transmission writer side.
+    par(clk.posedge) do
+        hif (swrite.ready) {
+            wr_cnt <= 0
+            ctrl <= 1
+            swrite.ack <= 0
+        }
+        helsif (ctrl == 1) {
+            wr_scnt <= wr_scnt + 1
+            sdat <= swrite.data[wr_scnt]
+            hif (swrite.scnt == 7) {
+                ctrl <= 0
+                swrite.ack <= 1
+            }
+        }
+    end
+
+    # Handle the serial transmission reader side.
+    par(clk.negedge) do
+        hif (ctrl == 1) do
+            rd_scnt <= rd_scnt + 1
+            sread.data[rd_scnt] <= sdat
+            hif(rd_scnt == 7) do
+                sread.ready <= 1
+                rd_scnt = 0
+            end
+        end
+        hif(sread.ack) do
+            sread.ready <= 0
+        end
+    end
+
+    systemA(:sysA,bufT).(clk: clk, data: bufA, rst: rst)
+    systemB(:sysB,bufT).(clk: clk, data: bufB, result: result)
+end
+
+
+# Instantiate it for checking.
+serialAB :serialABI
+
+# Generate the low level representation.
+low = serialABI.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/adder.rb

@@ -0,0 +1,21 @@
+require 'HDLRuby'
+
+configure_high
+
+
+# A simple 16-bit adder
+system :adder do
+    [15..0].input :x,:y
+    [16..0].output :s
+
+    s <= x + y
+end
+
+# Instantiate it for checking.
+adder :adderI
+
+# Generate the low level representation.
+low = adderI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/adder_common_errors.rb

@@ -0,0 +1,25 @@
+require 'HDLRuby'
+
+configure_high
+
+
+# A simple 16-bit adder
+system :adder do
+    [15..0].input :x,:y
+    [16..0].output :s
+
+    s <= x + y
+
+    s = "tot"
+
+    S = "TT"
+end
+
+# Instantiate it for checking.
+adder :adderI
+
+# Generate the low level representation.
+low = adderI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/addsub.rb

@@ -0,0 +1,33 @@
+require 'HDLRuby'
+
+configure_high
+
+# An adder-suber
+system :addsub do
+    input  :opr
+    [15..0].input :x,:y
+    [16..0].output :s
+
+    # The only adder instance.
+    instance :add do
+        [15..0].input :x,:y
+        input :cin
+        [16..0].output :s
+
+        s <= x+y+cin
+    end
+
+    # Control part for choosing between add and sub.
+    hif(opr) { add.(x,~y,1,s) }
+    helse    { add.(x,y,0,s) }
+end
+
+
+# Instantiate it for checking.
+addsub :addsubI
+
+# Generate the low level representation.
+low = addsubI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/addsubz.rb

@@ -0,0 +1,37 @@
+require 'HDLRuby'
+
+configure_high
+
+# An extended adder-suber
+system :addsub do
+    [1..0].input  :opr
+    [15..0].input :x,:y
+    [16..0].output :s
+
+    # The only adder instance.
+    instance :add do
+        [15..0].input :x,:y
+        input :cin
+        [16..0].output :s
+        
+        s <= x+y+cin
+    end
+
+
+    # Some computation.
+    hcase(opr)
+    hwhen(0) { add.(0,0,0,s) }
+    hwhen(1) { add.(x,y,0,s) }
+    hwhen(2) { add.(x,~y,1,s) }
+    helse    { add.(0,~y,1,s) }
+end
+
+
+# Instantiate it for checking.
+addsub :addsubI
+
+# Generate the low level representation.
+low = addsubI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/after.rb

@@ -0,0 +1,28 @@
+require 'HDLRuby'
+
+configure_high
+
+
+require 'HDLRuby/std/counters'
+include HDLRuby::High::Std
+
+
+# A simple test of the after construct
+system :with_after do
+    input :clk,:rst
+    output :timeout
+
+    par(clk.posedge,rst.posedge) do
+        timeout <= 0
+        after(100,rst) { timeout <= 1 }
+    end
+end
+
+# Instantiate it for checking.
+with_after :with_afterI
+
+# Generate the low level representation.
+low = with_afterI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/all_signals.rb

@@ -0,0 +1,29 @@
+require 'HDLRuby'
+
+configure_high
+
+
+# A simple 16-bit adder
+system :adder do
+    [15..0].input :x,:y
+    [16..0].output :s
+
+    s <= x + y
+
+    cur_system.open do
+        puts "Inputs: ", cur_system.get_all_inputs
+        puts "Outputs: ", cur_system.get_all_outputs
+        puts "InOuts: ", cur_system.get_all_inouts
+        puts "Signals: ", cur_system.get_all_signals
+    end
+end
+
+
+# Instantiate it for checking.
+adder :adderI
+# 
+# # Generate the low level representation.
+# low = adderI.to_low
+# 
+# # Displays it
+# puts low.to_yaml

data/lib/HDLRuby/high_samples/alu.rb

@@ -0,0 +1,61 @@
+require 'HDLRuby'
+
+configure_high
+
+
+# A simple ALU
+system :alu do
+    [4].input  :opr
+    [16].input :x,:y
+    [16].output :s
+    output :zf, :cf, :sf, :vf
+
+    # The only adder instance.
+    instance :add do
+        [16].input :x,:y
+        input :cin
+        [17].output :s
+        
+        s <= x+y+cin
+    end
+
+    # The control part for choosing between 0, add, sub and neg.
+    par do
+        # The main computation: s and cf
+        # Default connections
+        cf <= 0
+        vf <= 0
+        add.(0,0,0)
+        # Depending on the operator
+        hcase(opr)
+        hwhen(1) { s <= x }
+        hwhen(2) { s <= y }
+        hwhen(3) { add.(x ,y ,0,[cf,s])
+                   vf <= (~x[15] & ~y[15] & s[15]) | (x[15] & y[15] & ~s[15]) }
+        hwhen(4) { add.(x ,~y,1,[cf,s])
+                   vf <= (~x[15] & y[15] & s[15]) | (x[15] & ~y[15] & ~s[15]) }
+        hwhen(5) { add.(0 ,~y,1,[cf,s])
+                   vf <= (~y[15] & s[15]) }
+        hwhen(6) { add.(~x,0 ,1,[cf,s])
+                   vf <= (x[15] & ~s[15]) }
+        hwhen(7) { s <= x & y }
+        hwhen(8) { s <= x | y }
+        hwhen(9) { s <= x ^ y }
+        hwhen(10){ s <= ~x }
+        hwhen(11){ s <= ~y }
+        helse    { s <= 0 }
+
+        # The remaining flags.
+        zf <= (s == 0)
+        sf <= s[15]
+    end
+end
+
+# Instantiate it for checking.
+alu :aluI
+
+# Generate the low level representation.
+low = aluI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/anonymous.rb

@@ -0,0 +1,41 @@
+require 'HDLRuby'
+
+configure_high
+
+
+# A 32-bit or made of two 16-bit ones declared with anonymous system.
+system :or32 do
+    [31..0].input :x,:y
+    [32..0].output :s
+
+    instance :or0 do
+        [15..0].input :x,:y
+        [16..0].output :s
+
+        s <= x | y
+    end
+
+    instance :or1 do
+        [15..0].input :x,:y
+        [16..0].output :s
+
+        s <= x | y
+    end
+
+    or0.x <= x[15..0]
+    or0.y <= y[15..0]
+    s[15..0] <= or0.s[15..0]
+
+    or1.x <= x[31..16]
+    or1.y <= y[31..16]
+    s[31..16] <= or0.s[31..16]
+end
+
+# Instantiate it for checking.
+or32 :or32I
+
+# Generate the low level representation.
+low = or32I.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/before.rb

@@ -0,0 +1,28 @@
+require 'HDLRuby'
+
+configure_high
+
+
+require 'HDLRuby/std/counters'
+include HDLRuby::High::Std
+
+
+# A simple test of the before construct
+system :with_before do
+    input :clk,:rst
+    output :timeout
+
+    par(clk.posedge,rst.posedge) do
+        timeout <= 1
+        before(100,rst) { timeout <= 0 }
+    end
+end
+
+# Instantiate it for checking.
+with_before :with_beforeI
+
+# Generate the low level representation.
+low = with_beforeI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/blockblock.rb

@@ -0,0 +1,26 @@
+require 'HDLRuby'
+
+configure_high
+
+# System with blocks in blocks.
+system :blockblock do
+    input  :i0,:i1
+    output :o0,:o1
+    inner  :s0
+
+    par do
+        inner :s0
+        sub do
+            inner :s0
+        end
+    end
+end
+
+# Instantiate it for checking.
+blockblock :blockblockI
+
+# Generate the low level representation.
+low = blockblockI.systemT.to_low
+
+# Displays it
+puts low.to_yaml

data/lib/HDLRuby/high_samples/bugs/dadz.rb

@@ -0,0 +1,22 @@
+require 'HDLRuby'
+configure_high
+
+system :dadz do
+	input :clk,:res
+	signed[31..0].input :a
+	signed[31..0].output :dadz
+	signed[63..0].inner :tmp_dadz
+	
+	par(clk.posedge,res.posedge)do
+		hif(res==_1)do
+			tmp_dadz<=0
+		end 
+		helse do
+			tmp_dadz<=(_00000001000000000000000000000000-a)*a
+		end
+	end
+	dadz<=tmp_dadz[55..24]
+end
+
+dadz :dadzI
+puts dadzI.to_low.to_yaml

data/lib/HDLRuby/high_samples/bugs/misample_instan.rb

@@ -0,0 +1,20 @@
+require 'HDLRuby'
+configure_high
+
+#インスタンス化
+system :top do
+	input   :a,:b
+	output  :c,:d
+	andgate(:i0).( a: a, b: b, y: d )
+	andgate(:i1).( c, a , b )
+end
+
+system :andgate do
+	input :a,:b
+	output :y
+	y <= a & b
+end
+
+top :topI
+
+puts topI.to_low.to_yaml

data/lib/HDLRuby/high_samples/bugs/misample_updown.rb

@@ -0,0 +1,22 @@
+require 'HDLRuby'
+configure_high
+
+system :updown_cnt do
+
+	input    :ck,:res,:down
+	[3..0].output  :q
+	[3..0].inner  :q
+	
+	hif (res) do
+		q<=_b4h0
+	end
+	helsif(down) do
+		q<=q-_b4h1	
+	end
+	helse do
+		q<=q+_b4h1
+	end
+end
+
+updown_cnt :updown_cntI
+puts updown_cntI.to_low.to_yaml

data/lib/HDLRuby/high_samples/bugs/sample_add.rb

@@ -0,0 +1,16 @@
+require 'HDLRuby'
+configure_high
+
+# 加算　HDLRuby
+system :adder do
+
+	[15..0].input :ina,:inb
+	[16..0].output :result
+	
+	result <=  ina + inb
+end
+
+
+adder :addI
+
+puts addI.to_low.to_yaml

data/lib/HDLRuby/high_samples/bugs/sample_barrel.rb

@@ -0,0 +1,13 @@
+require 'HDLRuby'
+configure_high
+
+system :barrel do
+	[7..0].input :din
+	[2..0].input :sft
+	[7..0].output :dout
+	dout<=din<<sft
+end
+
+barrel :barrelI
+
+puts barrelI.to_low.to_yaml

data/lib/HDLRuby/high_samples/bugs/sample_daice.rb

@@ -0,0 +1,57 @@
+require 'HDLRuby'
+configure_high
+
+#電子サイコロ
+system :saikoro do
+
+	input :ck,:reset,:enable
+	[6..0].output :lamp
+	[2..0].inner :cnt
+
+#1始まりの6進カウンタ
+	par(ck.posedge,reset.posedge) do
+	  hif(reset==_b1b1) do
+		cnt<=_b3h1
+	  end
+	  helsif(enable==_b1b1) do
+		hif(cnt<=_b3h6) do
+			cnt<=_b3h1
+	    end
+		helse do
+			cnt<=cnt+_b3h1
+		end
+	  end
+	end
+	
+	# [6..0].function :dec
+	# [2..0].input    :din
+	par do
+	    hcase(cnt) 
+		hwhen _b3h1 do
+			lamp <= _b7b0001000
+		end
+		hwhen _b3h2 do
+			lamp <= _b7b1000001
+		end
+		hwhen _b3h3 do 
+			lamp <= _b7b0011100
+		end
+		hwhen _b3h4 do 
+			lamp <= _b7b1010101
+		end
+		hwhen _b3h5 do 
+			lamp <= _b7b1011101
+		end
+		hwhen _b3h6 do
+			lamp <= _b7b1110111
+		end
+		helse do
+			lamp <= _b7bxxxxxxx
+	    end
+    end
+	
+	# lamp<=dec(cnt)
+end
+
+saikoro :saikoroI
+puts saikoroI.to_low.to_yaml

data/lib/HDLRuby/high_samples/bugs/sample_kumiawase.rb

@@ -0,0 +1,52 @@
+require 'HDLRuby'
+configure_high
+
+#組み合わせ回路
+system :led7seg do
+	[3..0].input :in0
+	[6..0].output :out
+	[6..0].inner :out
+	
+	par do
+		hcase(in0)
+			hwhen 0 do
+				out <= _b7b0111111
+			end
+			hwhen 1 do
+				out <= _b7b0000110
+			end
+			hwhen 2 do
+				out <= _b7b1011011
+			end
+			hwhen 3 do
+				out <= _b7b1001111
+			end
+			hwhen 4 do
+				out <= _b7b1100110
+			end
+			hwhen 5 do
+				out <= _b7b1111101
+			end
+			hwhen 6 do
+				out <= _b7b1111101
+			end
+			hwhen 7 do
+				out <= _b7b0000111
+			end
+			hwhen 8 do
+				out <= _b7b1111111
+			end
+			hwhen 9 do
+				out <= _b7b1100111
+			end
+			helse do 
+				out <= 0
+			end
+		
+		
+	end
+end
+
+led7seg :led7segI
+
+puts led7segI.to_low.to_yaml

data/lib/HDLRuby/high_samples/bugs/sample_multi.rb

@@ -0,0 +1,18 @@
+require 'HDLRuby'
+configure_high
+
+system :deconder do
+	
+	[7..0].input :address
+	[1..0].output :ce
+	
+	# bit[1..0].inner :ce
+	
+	ce[0]<= (address[7..0]==_b8h0)
+	ce[1]<= (address[7..0]==_b8h1)
+	
+end
+
+deconder :deconderI
+
+puts deconderI.to_low.to_yaml