@patleeman/pi-boy 0.1.0

package/mgba-bridge/vendor/mgba/src/arm/arm.c

@@ -0,0 +1,264 @@
+/* Copyright (c) 2013-2014 Jeffrey Pfau
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
+#include <mgba/internal/arm/arm.h>
+
+#include <mgba/internal/arm/isa-arm.h>
+#include <mgba/internal/arm/isa-inlines.h>
+#include <mgba/internal/arm/isa-thumb.h>
+
+void ARMSetPrivilegeMode(struct ARMCore* cpu, enum PrivilegeMode mode) {
+	if (mode == cpu->privilegeMode) {
+		// Not switching modes after all
+		return;
+	}
+
+	enum RegisterBank newBank = ARMSelectBank(mode);
+	enum RegisterBank oldBank = ARMSelectBank(cpu->privilegeMode);
+	if (newBank != oldBank) {
+		// Switch banked registers
+		if (mode == MODE_FIQ || cpu->privilegeMode == MODE_FIQ) {
+			int oldFIQBank = oldBank == BANK_FIQ;
+			int newFIQBank = newBank == BANK_FIQ;
+			cpu->bankedRegisters[oldFIQBank][2] = cpu->gprs[8];
+			cpu->bankedRegisters[oldFIQBank][3] = cpu->gprs[9];
+			cpu->bankedRegisters[oldFIQBank][4] = cpu->gprs[10];
+			cpu->bankedRegisters[oldFIQBank][5] = cpu->gprs[11];
+			cpu->bankedRegisters[oldFIQBank][6] = cpu->gprs[12];
+			cpu->gprs[8] = cpu->bankedRegisters[newFIQBank][2];
+			cpu->gprs[9] = cpu->bankedRegisters[newFIQBank][3];
+			cpu->gprs[10] = cpu->bankedRegisters[newFIQBank][4];
+			cpu->gprs[11] = cpu->bankedRegisters[newFIQBank][5];
+			cpu->gprs[12] = cpu->bankedRegisters[newFIQBank][6];
+		}
+		cpu->bankedRegisters[oldBank][0] = cpu->gprs[ARM_SP];
+		cpu->bankedRegisters[oldBank][1] = cpu->gprs[ARM_LR];
+		cpu->gprs[ARM_SP] = cpu->bankedRegisters[newBank][0];
+		cpu->gprs[ARM_LR] = cpu->bankedRegisters[newBank][1];
+
+		cpu->bankedSPSRs[oldBank] = cpu->spsr.packed;
+		cpu->spsr.packed = cpu->bankedSPSRs[newBank];
+	}
+	cpu->privilegeMode = mode;
+}
+
+void ARMInit(struct ARMCore* cpu) {
+	memset(cpu->cp, 0, sizeof(cpu->cp));
+	cpu->master->init(cpu, cpu->master);
+	size_t i;
+	for (i = 0; i < cpu->numComponents; ++i) {
+		if (cpu->components[i] && cpu->components[i]->init) {
+			cpu->components[i]->init(cpu, cpu->components[i]);
+		}
+	}
+}
+
+void ARMDeinit(struct ARMCore* cpu) {
+	if (cpu->master->deinit) {
+		cpu->master->deinit(cpu->master);
+	}
+	size_t i;
+	for (i = 0; i < cpu->numComponents; ++i) {
+		if (cpu->components[i] && cpu->components[i]->deinit) {
+			cpu->components[i]->deinit(cpu->components[i]);
+		}
+	}
+}
+
+void ARMSetComponents(struct ARMCore* cpu, struct mCPUComponent* master, int extra, struct mCPUComponent** extras) {
+	cpu->master = master;
+	cpu->numComponents = extra;
+	cpu->components = extras;
+}
+
+void ARMHotplugAttach(struct ARMCore* cpu, size_t slot) {
+	if (slot >= cpu->numComponents) {
+		return;
+	}
+	cpu->components[slot]->init(cpu, cpu->components[slot]);
+}
+
+void ARMHotplugDetach(struct ARMCore* cpu, size_t slot) {
+	if (slot >= cpu->numComponents) {
+		return;
+	}
+	cpu->components[slot]->deinit(cpu->components[slot]);
+}
+
+void ARMReset(struct ARMCore* cpu) {
+	int i;
+	for (i = 0; i < 16; ++i) {
+		cpu->gprs[i] = 0;
+	}
+	for (i = 0; i < 6; ++i) {
+		cpu->bankedRegisters[i][0] = 0;
+		cpu->bankedRegisters[i][1] = 0;
+		cpu->bankedRegisters[i][2] = 0;
+		cpu->bankedRegisters[i][3] = 0;
+		cpu->bankedRegisters[i][4] = 0;
+		cpu->bankedRegisters[i][5] = 0;
+		cpu->bankedRegisters[i][6] = 0;
+		cpu->bankedSPSRs[i] = 0;
+	}
+
+	cpu->privilegeMode = MODE_SYSTEM;
+	cpu->cpsr.packed = MODE_SYSTEM;
+	cpu->spsr.packed = 0;
+
+	cpu->shifterOperand = 0;
+	cpu->shifterCarryOut = 0;
+
+	cpu->executionMode = MODE_THUMB;
+	_ARMSetMode(cpu, MODE_ARM);
+	ARMWritePC(cpu);
+
+	cpu->cycles = 0;
+	cpu->nextEvent = 0;
+	cpu->halted = 0;
+
+	cpu->irqh.reset(cpu);
+}
+
+void ARMRaiseIRQ(struct ARMCore* cpu) {
+	if (cpu->cpsr.i) {
+		return;
+	}
+	union PSR cpsr = cpu->cpsr;
+	int instructionWidth;
+	if (cpu->executionMode == MODE_THUMB) {
+		instructionWidth = WORD_SIZE_THUMB;
+	} else {
+		instructionWidth = WORD_SIZE_ARM;
+	}
+	ARMSetPrivilegeMode(cpu, MODE_IRQ);
+	cpu->cpsr.priv = MODE_IRQ;
+	cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - instructionWidth + WORD_SIZE_ARM;
+	cpu->gprs[ARM_PC] = BASE_IRQ;
+	_ARMSetMode(cpu, MODE_ARM);
+	cpu->cycles += ARMWritePC(cpu);
+	cpu->spsr = cpsr;
+	cpu->cpsr.i = 1;
+	cpu->halted = 0;
+}
+
+void ARMRaiseSWI(struct ARMCore* cpu) {
+	union PSR cpsr = cpu->cpsr;
+	int instructionWidth;
+	if (cpu->executionMode == MODE_THUMB) {
+		instructionWidth = WORD_SIZE_THUMB;
+	} else {
+		instructionWidth = WORD_SIZE_ARM;
+	}
+	ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
+	cpu->cpsr.priv = MODE_SUPERVISOR;
+	cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - instructionWidth;
+	cpu->gprs[ARM_PC] = BASE_SWI;
+	_ARMSetMode(cpu, MODE_ARM);
+	cpu->cycles += ARMWritePC(cpu);
+	cpu->spsr = cpsr;
+	cpu->cpsr.i = 1;
+}
+
+void ARMRaiseUndefined(struct ARMCore* cpu) {
+	union PSR cpsr = cpu->cpsr;
+	int instructionWidth;
+	if (cpu->executionMode == MODE_THUMB) {
+		instructionWidth = WORD_SIZE_THUMB;
+	} else {
+		instructionWidth = WORD_SIZE_ARM;
+	}
+	ARMSetPrivilegeMode(cpu, MODE_UNDEFINED);
+	cpu->cpsr.priv = MODE_UNDEFINED;
+	cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - instructionWidth;
+	cpu->gprs[ARM_PC] = BASE_UNDEF;
+	_ARMSetMode(cpu, MODE_ARM);
+	cpu->cycles += ARMWritePC(cpu);
+	cpu->spsr = cpsr;
+	cpu->cpsr.i = 1;
+}
+
+static const uint16_t conditionLut[16] = {
+	0xF0F0, // EQ [-Z--]
+	0x0F0F, // NE [-z--]
+	0xCCCC, // CS [--C-]
+	0x3333, // CC [--c-]
+	0xFF00, // MI [N---]
+	0x00FF, // PL [n---]
+	0xAAAA, // VS [---V]
+	0x5555, // VC [---v]
+	0x0C0C, // HI [-zC-]
+	0xF3F3, // LS [-Z--] || [--c-]
+	0xAA55, // GE [N--V] || [n--v]
+	0x55AA, // LT [N--v] || [n--V]
+	0x0A05, // GT [Nz-V] || [nz-v]
+	0xF5FA, // LE [-Z--] || [Nz-v] || [nz-V]
+	0xFFFF, // AL [----]
+	0x0000 // NV
+};
+
+static inline void ARMStep(struct ARMCore* cpu) {
+	uint32_t opcode = cpu->prefetch[0];
+	cpu->prefetch[0] = cpu->prefetch[1];
+	cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
+	LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
+
+	unsigned condition = opcode >> 28;
+	if (condition != 0xE) {
+		unsigned flags = cpu->cpsr.flags >> 4;
+		bool conditionMet = conditionLut[condition] & (1 << flags);
+		if (!conditionMet) {
+			cpu->cycles += ARM_PREFETCH_CYCLES;
+			return;
+		}
+	}
+	ARMInstruction instruction = _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
+	instruction(cpu, opcode);
+}
+
+static inline void ThumbStep(struct ARMCore* cpu) {
+	uint32_t opcode = cpu->prefetch[0];
+	cpu->prefetch[0] = cpu->prefetch[1];
+	cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
+	LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
+	ThumbInstruction instruction = _thumbTable[opcode >> 6];
+	instruction(cpu, opcode);
+}
+
+void ARMRun(struct ARMCore* cpu) {
+	while (cpu->cycles >= cpu->nextEvent) {
+		cpu->irqh.processEvents(cpu);
+	}
+	if (cpu->executionMode == MODE_THUMB) {
+		ThumbStep(cpu);
+	} else {
+		ARMStep(cpu);
+	}
+	while (cpu->cycles >= cpu->nextEvent) {
+		cpu->irqh.processEvents(cpu);
+	}
+}
+
+void ARMRunLoop(struct ARMCore* cpu) {
+	if (cpu->executionMode == MODE_THUMB) {
+		while (cpu->cycles < cpu->nextEvent) {
+			ThumbStep(cpu);
+		}
+	} else {
+		while (cpu->cycles < cpu->nextEvent) {
+			ARMStep(cpu);
+		}
+	}
+	cpu->irqh.processEvents(cpu);
+}
+
+void ARMRunFake(struct ARMCore* cpu, uint32_t opcode) {
+	if (cpu->executionMode == MODE_ARM) {
+		cpu->gprs[ARM_PC] -= WORD_SIZE_ARM;
+	} else {
+		cpu->gprs[ARM_PC] -= WORD_SIZE_THUMB;
+	}
+	cpu->prefetch[1] = cpu->prefetch[0];
+	cpu->prefetch[0] = opcode;
+}

package/mgba-bridge/vendor/mgba/src/arm/debugger/cli-debugger.c

@@ -0,0 +1,187 @@
+/* Copyright (c) 2013-2016 Jeffrey Pfau
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
+#include <mgba/internal/arm/debugger/cli-debugger.h>
+
+#include <mgba/core/core.h>
+#include <mgba/core/timing.h>
+#include <mgba/internal/arm/debugger/debugger.h>
+#include <mgba/internal/arm/debugger/memory-debugger.h>
+#include <mgba/internal/arm/decoder.h>
+#include <mgba/internal/debugger/cli-debugger.h>
+
+static void _printStatus(struct CLIDebuggerSystem*);
+
+static void _disassembleArm(struct CLIDebugger*, struct CLIDebugVector*);
+static void _disassembleThumb(struct CLIDebugger*, struct CLIDebugVector*);
+static void _setBreakpointARM(struct CLIDebugger*, struct CLIDebugVector*);
+static void _setBreakpointThumb(struct CLIDebugger*, struct CLIDebugVector*);
+
+static void _disassembleMode(struct CLIDebugger*, struct CLIDebugVector*, enum ExecutionMode mode);
+static uint32_t _printLine(struct CLIDebugger* debugger, uint32_t address, enum ExecutionMode mode);
+
+static struct CLIDebuggerCommandSummary _armCommands[] = {
+	{ "break/a", _setBreakpointARM, "I", "Set a software breakpoint as ARM" },
+	{ "break/t", _setBreakpointThumb, "I", "Set a software breakpoint as Thumb" },
+	{ "disassemble/a", _disassembleArm, "Ii", "Disassemble instructions as ARM" },
+	{ "disassemble/t", _disassembleThumb, "Ii", "Disassemble instructions as Thumb" },
+	{ 0, 0, 0, 0 }
+};
+
+static struct CLIDebuggerCommandAlias _armCommandAliases[] = {
+	{ "b/a", "break/a" },
+	{ "b/t", "break/t" },
+	{ "dis/a", "disassemble/a" },
+	{ "dis/t", "disassemble/t" },
+	{ "disasm/a",  "disassemble/a" },
+	{ "disasm/t",  "disassemble/t" },
+	{ 0, 0 }
+};
+
+static inline void _printPSR(struct CLIDebuggerBackend* be, union PSR psr) {
+	be->printf(be, "%08X [%c%c%c%c%c%c%c]\n", psr.packed,
+	           psr.n ? 'N' : '-',
+	           psr.z ? 'Z' : '-',
+	           psr.c ? 'C' : '-',
+	           psr.v ? 'V' : '-',
+	           psr.i ? 'I' : '-',
+	           psr.f ? 'F' : '-',
+	           psr.t ? 'T' : '-');
+}
+
+static void _disassemble(struct CLIDebuggerSystem* debugger, struct CLIDebugVector* dv) {
+	struct ARMCore* cpu = debugger->p->d.p->core->cpu;
+	_disassembleMode(debugger->p, dv, cpu->executionMode);
+}
+
+static void _disassembleArm(struct CLIDebugger* debugger, struct CLIDebugVector* dv) {
+	_disassembleMode(debugger, dv, MODE_ARM);
+}
+
+static void _disassembleThumb(struct CLIDebugger* debugger, struct CLIDebugVector* dv) {
+	_disassembleMode(debugger, dv, MODE_THUMB);
+}
+
+static void _disassembleMode(struct CLIDebugger* debugger, struct CLIDebugVector* dv, enum ExecutionMode mode) {
+	struct ARMCore* cpu = debugger->d.p->core->cpu;
+	uint32_t address;
+	int size;
+	int wordSize;
+
+	if (mode == MODE_ARM) {
+		wordSize = WORD_SIZE_ARM;
+	} else {
+		wordSize = WORD_SIZE_THUMB;
+	}
+
+	if (!dv || dv->type != CLIDV_INT_TYPE) {
+		address = cpu->gprs[ARM_PC] - wordSize;
+	} else {
+		address = dv->intValue;
+		dv = dv->next;
+	}
+
+	if (!dv || dv->type != CLIDV_INT_TYPE) {
+		size = 1;
+	} else {
+		size = dv->intValue;
+		// TODO: Check for excess args
+	}
+
+	int i;
+	for (i = 0; i < size; ++i) {
+		address += _printLine(debugger, address, mode);
+	}
+}
+
+static inline uint32_t _printLine(struct CLIDebugger* debugger, uint32_t address, enum ExecutionMode mode) {
+	struct CLIDebuggerBackend* be = debugger->backend;
+	struct mCore* core = debugger->d.p->core;
+	char disassembly[64];
+	struct ARMInstructionInfo info;
+	address &= ~(WORD_SIZE_THUMB - 1);
+	be->printf(be, "%08X:  ", address);
+	if (mode == MODE_ARM) {
+		uint32_t instruction = core->busRead32(core, address & ~(WORD_SIZE_ARM - 1));
+		ARMDecodeARM(instruction, &info);
+		ARMDisassemble(&info, core->cpu, core->symbolTable, address + WORD_SIZE_ARM * 2, disassembly, sizeof(disassembly));
+		be->printf(be, "%08X\t%s\n", instruction, disassembly);
+		return WORD_SIZE_ARM;
+	} else {
+		struct ARMInstructionInfo info2;
+		struct ARMInstructionInfo combined;
+		uint16_t instruction = core->busRead16(core, address);
+		uint16_t instruction2 = core->busRead16(core, address + WORD_SIZE_THUMB);
+		ARMDecodeThumb(instruction, &info);
+		ARMDecodeThumb(instruction2, &info2);
+		if (ARMDecodeThumbCombine(&info, &info2, &combined)) {
+			ARMDisassemble(&combined, core->cpu, core->symbolTable, address + WORD_SIZE_THUMB * 2, disassembly, sizeof(disassembly));
+			be->printf(be, "%04X %04X\t%s\n", instruction, instruction2, disassembly);
+			return WORD_SIZE_THUMB * 2;
+		} else {
+			ARMDisassemble(&info, core->cpu, core->symbolTable, address + WORD_SIZE_THUMB * 2, disassembly, sizeof(disassembly));
+			be->printf(be, "%04X     \t%s\n", instruction, disassembly);
+			return WORD_SIZE_THUMB;
+		}
+	}
+}
+
+static void _printStatus(struct CLIDebuggerSystem* debugger) {
+	struct CLIDebuggerBackend* be = debugger->p->backend;
+	struct ARMCore* cpu = debugger->p->d.p->core->cpu;
+	int r;
+	for (r = 0; r < 16; r += 4) {
+		be->printf(be, "%sr%i: %08X  %sr%i: %08X  %sr%i: %08X  %sr%i: %08X\n",
+		    r < 10 ? " " : "", r, cpu->gprs[r],
+		    r < 9 ? " " : "", r + 1, cpu->gprs[r + 1],
+		    r < 8 ? " " : "", r + 2, cpu->gprs[r + 2],
+		    r < 7 ? " " : "", r + 3, cpu->gprs[r + 3]);
+	}
+	be->printf(be, "cpsr: ");
+	_printPSR(be, cpu->cpsr);
+	be->printf(be, "Cycle: %" PRIu64 "\n", mTimingGlobalTime(debugger->p->d.p->core->timing));
+	int instructionLength;
+	enum ExecutionMode mode = cpu->cpsr.t;
+	if (mode == MODE_ARM) {
+		instructionLength = WORD_SIZE_ARM;
+	} else {
+		instructionLength = WORD_SIZE_THUMB;
+	}
+	_printLine(debugger->p, cpu->gprs[ARM_PC] - instructionLength, mode);
+}
+
+static void _setBreakpointARM(struct CLIDebugger* debugger, struct CLIDebugVector* dv) {
+	struct CLIDebuggerBackend* be = debugger->backend;
+	if (!dv || dv->type != CLIDV_INT_TYPE) {
+		be->printf(be, "%s", ERROR_MISSING_ARGS);
+		return;
+	}
+	uint32_t address = dv->intValue;
+	ssize_t id = ARMDebuggerSetSoftwareBreakpoint(debugger->d.p->platform, &debugger->d, address, MODE_ARM);
+	if (id > 0) {
+		debugger->backend->printf(debugger->backend, INFO_BREAKPOINT_ADDED, id);
+	}
+}
+
+static void _setBreakpointThumb(struct CLIDebugger* debugger, struct CLIDebugVector* dv) {
+	struct CLIDebuggerBackend* be = debugger->backend;
+	if (!dv || dv->type != CLIDV_INT_TYPE) {
+		be->printf(be, "%s", ERROR_MISSING_ARGS);
+		return;
+	}
+	uint32_t address = dv->intValue;
+	ssize_t id = ARMDebuggerSetSoftwareBreakpoint(debugger->d.p->platform, &debugger->d, address, MODE_THUMB);
+	if (id > 0) {
+		debugger->backend->printf(debugger->backend, INFO_BREAKPOINT_ADDED, id);
+	}
+}
+
+void ARMCLIDebuggerCreate(struct CLIDebuggerSystem* debugger) {
+	debugger->printStatus = _printStatus;
+	debugger->disassemble = _disassemble;
+	debugger->platformName = "ARM";
+	debugger->platformCommands = _armCommands;
+	debugger->platformCommandAliases = _armCommandAliases;
+}