@patleeman/pi-boy 0.1.0

package/mgba-bridge/vendor/mgba/include/mgba/internal/arm/arm.h

@@ -0,0 +1,217 @@
+/* Copyright (c) 2013-2014 Jeffrey Pfau
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
+#ifndef ARM_H
+#define ARM_H
+
+#include <mgba-util/common.h>
+
+CXX_GUARD_START
+
+#include <mgba/core/cpu.h>
+
+enum {
+	ARM_SP = 13,
+	ARM_LR = 14,
+	ARM_PC = 15
+};
+
+enum ExecutionMode {
+	MODE_ARM = 0,
+	MODE_THUMB = 1
+};
+
+enum PrivilegeMode {
+	MODE_USER = 0x10,
+	MODE_FIQ = 0x11,
+	MODE_IRQ = 0x12,
+	MODE_SUPERVISOR = 0x13,
+	MODE_ABORT = 0x17,
+	MODE_UNDEFINED = 0x1B,
+	MODE_SYSTEM = 0x1F
+};
+
+enum WordSize {
+	WORD_SIZE_ARM = 4,
+	WORD_SIZE_THUMB = 2
+};
+
+enum ExecutionVector {
+	BASE_RESET = 0x00000000,
+	BASE_UNDEF = 0x00000004,
+	BASE_SWI = 0x00000008,
+	BASE_PABT = 0x0000000C,
+	BASE_DABT = 0x00000010,
+	BASE_IRQ = 0x00000018,
+	BASE_FIQ = 0x0000001C
+};
+
+enum RegisterBank {
+	BANK_NONE = 0,
+	BANK_FIQ = 1,
+	BANK_IRQ = 2,
+	BANK_SUPERVISOR = 3,
+	BANK_ABORT = 4,
+	BANK_UNDEFINED = 5
+};
+
+enum LSMDirection {
+	LSM_B = 1,
+	LSM_D = 2,
+	LSM_IA = 0,
+	LSM_IB = 1,
+	LSM_DA = 2,
+	LSM_DB = 3
+};
+
+struct ARMCore;
+
+union PSR {
+	struct {
+#ifdef __BIG_ENDIAN__
+		unsigned n : 1;
+		unsigned z : 1;
+		unsigned c : 1;
+		unsigned v : 1;
+		unsigned unused : 20;
+		unsigned i : 1;
+		unsigned f : 1;
+		unsigned t : 1;
+		unsigned priv : 5;
+#else
+		unsigned priv : 5;
+		unsigned t : 1;
+		unsigned f : 1;
+		unsigned i : 1;
+		unsigned unused : 20;
+		unsigned v : 1;
+		unsigned c : 1;
+		unsigned z : 1;
+		unsigned n : 1;
+#endif
+	};
+
+	struct {
+#ifdef __BIG_ENDIAN__
+		uint8_t flags;
+		uint8_t status;
+		uint8_t extension;
+		uint8_t control;
+#else
+		uint8_t control;
+		uint8_t extension;
+		uint8_t status;
+		uint8_t flags;
+#endif
+	};
+
+	int32_t packed;
+};
+
+struct ARMMemory {
+	uint32_t (*load32)(struct ARMCore*, uint32_t address, int* cycleCounter);
+	uint32_t (*load16)(struct ARMCore*, uint32_t address, int* cycleCounter);
+	uint32_t (*load8)(struct ARMCore*, uint32_t address, int* cycleCounter);
+
+	void (*store32)(struct ARMCore*, uint32_t address, int32_t value, int* cycleCounter);
+	void (*store16)(struct ARMCore*, uint32_t address, int16_t value, int* cycleCounter);
+	void (*store8)(struct ARMCore*, uint32_t address, int8_t value, int* cycleCounter);
+
+	uint32_t (*loadMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
+	                         int* cycleCounter);
+	uint32_t (*storeMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
+	                          int* cycleCounter);
+
+	const uint32_t* activeRegion;
+	uint32_t activeMask;
+	uint32_t activeSeqCycles32;
+	uint32_t activeSeqCycles16;
+	uint32_t activeNonseqCycles32;
+	uint32_t activeNonseqCycles16;
+	int32_t (*stall)(struct ARMCore*, int32_t wait);
+	void (*setActiveRegion)(struct ARMCore*, uint32_t address);
+
+	enum mMemoryAccessSource accessSource;
+};
+
+struct ARMCoprocessor {
+	int32_t (*mrc)(struct ARMCore*, int crn, int crm, int opcode1, int opcode2);
+	void (*mcr)(struct ARMCore*, int crn, int crm, int opcode1, int opcode2, int32_t value);
+	void (*cdp)(struct ARMCore*, int crn, int crm, int crd, int opcode1, int opcode2);
+};
+
+struct ARMInterruptHandler {
+	void (*reset)(struct ARMCore* cpu);
+	void (*processEvents)(struct ARMCore* cpu);
+	void (*swi16)(struct ARMCore* cpu, int immediate);
+	void (*swi32)(struct ARMCore* cpu, int immediate);
+	void (*hitIllegal)(struct ARMCore* cpu, uint32_t opcode);
+	void (*bkpt16)(struct ARMCore* cpu, int immediate);
+	void (*bkpt32)(struct ARMCore* cpu, int immediate);
+	void (*readCPSR)(struct ARMCore* cpu);
+
+	void (*hitStub)(struct ARMCore* cpu, uint32_t opcode);
+};
+
+#define ARM_REGISTER_FILE struct { \
+	int32_t gprs[16]; \
+	union PSR cpsr; \
+	union PSR spsr; \
+}
+
+struct ARMRegisterFile {
+	ARM_REGISTER_FILE;
+};
+
+struct ARMCore {
+	union {
+		struct ARMRegisterFile regs;
+		ARM_REGISTER_FILE;
+	};
+
+	int32_t cycles;
+	int32_t nextEvent;
+	int halted;
+
+	int32_t bankedRegisters[6][7];
+	int32_t bankedSPSRs[6];
+
+	int32_t shifterOperand;
+	int32_t shifterCarryOut;
+
+	uint32_t prefetch[2];
+	enum ExecutionMode executionMode;
+	enum PrivilegeMode privilegeMode;
+
+	struct ARMMemory memory;
+	struct ARMInterruptHandler irqh;
+	struct ARMCoprocessor cp[16];
+
+	struct mCPUComponent* master;
+
+	size_t numComponents;
+	struct mCPUComponent** components;
+};
+#undef ARM_REGISTER_FILE
+
+void ARMInit(struct ARMCore* cpu);
+void ARMDeinit(struct ARMCore* cpu);
+void ARMSetComponents(struct ARMCore* cpu, struct mCPUComponent* master, int extra, struct mCPUComponent** extras);
+void ARMHotplugAttach(struct ARMCore* cpu, size_t slot);
+void ARMHotplugDetach(struct ARMCore* cpu, size_t slot);
+
+void ARMReset(struct ARMCore* cpu);
+void ARMSetPrivilegeMode(struct ARMCore*, enum PrivilegeMode);
+void ARMRaiseIRQ(struct ARMCore*);
+void ARMRaiseSWI(struct ARMCore*);
+void ARMRaiseUndefined(struct ARMCore*);
+
+void ARMRun(struct ARMCore* cpu);
+void ARMRunLoop(struct ARMCore* cpu);
+void ARMRunFake(struct ARMCore* cpu, uint32_t opcode);
+
+CXX_GUARD_END
+
+#endif

package/mgba-bridge/vendor/mgba/include/mgba/internal/arm/debugger/cli-debugger.h

@@ -0,0 +1,18 @@
+/* Copyright (c) 2013-2016 Jeffrey Pfau
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
+#ifndef ARM_CLI_DEBUGGER_H
+#define ARM_CLI_DEBUGGER_H
+
+#include <mgba-util/common.h>
+
+CXX_GUARD_START
+
+struct CLIDebuggerSystem;
+void ARMCLIDebuggerCreate(struct CLIDebuggerSystem* debugger);
+
+CXX_GUARD_END
+
+#endif

package/mgba-bridge/vendor/mgba/include/mgba/internal/arm/debugger/debugger.h

@@ -0,0 +1,52 @@
+/* Copyright (c) 2013-2014 Jeffrey Pfau
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
+#ifndef ARM_DEBUGGER_H
+#define ARM_DEBUGGER_H
+
+#include <mgba-util/common.h>
+
+CXX_GUARD_START
+
+#include <mgba/debugger/debugger.h>
+
+#include <mgba/internal/arm/arm.h>
+#include <mgba-util/vector.h>
+
+struct ParseTree;
+struct ARMDebugBreakpoint {
+	struct mBreakpoint d;
+	struct {
+		uint32_t opcode;
+		enum ExecutionMode mode;
+	} sw;
+};
+
+DECLARE_VECTOR(ARMDebugBreakpointList, struct ARMDebugBreakpoint);
+
+struct ARMDebugger {
+	struct mDebuggerPlatform d;
+	struct ARMCore* cpu;
+
+	struct ARMDebugBreakpointList breakpoints;
+	struct ARMDebugBreakpointList swBreakpoints;
+	struct mWatchpointList watchpoints;
+	struct ARMMemory originalMemory;
+
+	ssize_t nextId;
+	enum mStackTraceMode stackTraceMode;
+
+	void (*entered)(struct mDebugger*, enum mDebuggerEntryReason, struct mDebuggerEntryInfo*);
+
+	bool (*setSoftwareBreakpoint)(struct ARMDebugger*, uint32_t address, enum ExecutionMode mode, uint32_t* opcode);
+	void (*clearSoftwareBreakpoint)(struct ARMDebugger*, const struct ARMDebugBreakpoint*);
+};
+
+struct mDebuggerPlatform* ARMDebuggerPlatformCreate(void);
+ssize_t ARMDebuggerSetSoftwareBreakpoint(struct mDebuggerPlatform* debugger, struct mDebuggerModule* owner, uint32_t address, enum ExecutionMode mode);
+
+CXX_GUARD_END
+
+#endif

package/mgba-bridge/vendor/mgba/include/mgba/internal/arm/debugger/memory-debugger.h

@@ -0,0 +1,20 @@
+/* Copyright (c) 2013-2014 Jeffrey Pfau
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
+#ifndef MEMORY_DEBUGGER_H
+#define MEMORY_DEBUGGER_H
+
+#include <mgba-util/common.h>
+
+CXX_GUARD_START
+
+struct ARMDebugger;
+
+void ARMDebuggerInstallMemoryShim(struct ARMDebugger* debugger);
+void ARMDebuggerRemoveMemoryShim(struct ARMDebugger* debugger);
+
+CXX_GUARD_END
+
+#endif

package/mgba-bridge/vendor/mgba/include/mgba/internal/arm/decoder-inlines.h

@@ -0,0 +1,37 @@
+/* Copyright (c) 2013-2014 Jeffrey Pfau
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
+#ifndef ARM_DECODER_INLINES_H
+#define ARM_DECODER_INLINES_H
+
+#include "decoder.h"
+
+#include "arm.h"
+
+#include <stdio.h>
+#include <string.h>
+
+#define LOAD_CYCLES    \
+	info->iCycles = 1; \
+	info->nDataCycles = 1;
+
+#define STORE_CYCLES              \
+	info->sInstructionCycles = 0; \
+	info->nInstructionCycles = 1; \
+	info->nDataCycles = 1;
+
+static inline bool ARMInstructionIsBranch(enum ARMMnemonic mnemonic) {
+	switch (mnemonic) {
+		case ARM_MN_B:
+		case ARM_MN_BL:
+		case ARM_MN_BX:
+			// TODO: case: ARM_MN_BLX:
+			return true;
+		default:
+			return false;
+	}
+}
+
+#endif

package/mgba-bridge/vendor/mgba/include/mgba/internal/arm/decoder.h

@@ -0,0 +1,231 @@
+/* Copyright (c) 2013-2014 Jeffrey Pfau
+ *
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
+#ifndef ARM_DECODER_H
+#define ARM_DECODER_H
+
+#include <mgba-util/common.h>
+
+CXX_GUARD_START
+
+#include <mgba/internal/arm/arm.h>
+
+// Bit 0: a register is involved with this operand
+// Bit 1: an immediate is invovled with this operand
+// Bit 2: a memory access is involved with this operand
+// Bit 3: the destination of this operand is affected by this opcode
+// Bit 4: this operand is shifted by a register
+// Bit 5: this operand is shifted by an immediate
+#define ARM_OPERAND_NONE                0x00000000
+#define ARM_OPERAND_REGISTER_1          0x00000001
+#define ARM_OPERAND_IMMEDIATE_1         0x00000002
+#define ARM_OPERAND_MEMORY_1            0x00000004
+#define ARM_OPERAND_AFFECTED_1          0x00000008
+#define ARM_OPERAND_SHIFT_REGISTER_1    0x00000010
+#define ARM_OPERAND_SHIFT_IMMEDIATE_1   0x00000020
+#define ARM_OPERAND_1                   0x000000FF
+
+#define ARM_OPERAND_REGISTER_2          0x00000100
+#define ARM_OPERAND_IMMEDIATE_2         0x00000200
+#define ARM_OPERAND_MEMORY_2            0x00000400
+#define ARM_OPERAND_AFFECTED_2          0x00000800
+#define ARM_OPERAND_SHIFT_REGISTER_2    0x00001000
+#define ARM_OPERAND_SHIFT_IMMEDIATE_2   0x00002000
+#define ARM_OPERAND_2                   0x0000FF00
+
+#define ARM_OPERAND_REGISTER_3          0x00010000
+#define ARM_OPERAND_IMMEDIATE_3         0x00020000
+#define ARM_OPERAND_MEMORY_3            0x00040000
+#define ARM_OPERAND_AFFECTED_3          0x00080000
+#define ARM_OPERAND_SHIFT_REGISTER_3    0x00100000
+#define ARM_OPERAND_SHIFT_IMMEDIATE_3   0x00200000
+#define ARM_OPERAND_3                   0x00FF0000
+
+#define ARM_OPERAND_REGISTER_4          0x01000000
+#define ARM_OPERAND_IMMEDIATE_4         0x02000000
+#define ARM_OPERAND_MEMORY_4            0x04000000
+#define ARM_OPERAND_AFFECTED_4          0x08000000
+#define ARM_OPERAND_SHIFT_REGISTER_4    0x10000000
+#define ARM_OPERAND_SHIFT_IMMEDIATE_4   0x20000000
+#define ARM_OPERAND_4                   0xFF000000
+
+#define ARM_OPERAND_MEMORY (ARM_OPERAND_MEMORY_1 | ARM_OPERAND_MEMORY_2 | ARM_OPERAND_MEMORY_3 | ARM_OPERAND_MEMORY_4)
+
+#define ARM_MEMORY_REGISTER_BASE     0x0001
+#define ARM_MEMORY_IMMEDIATE_OFFSET  0x0002
+#define ARM_MEMORY_REGISTER_OFFSET   0x0004
+#define ARM_MEMORY_SHIFTED_OFFSET    0x0008
+#define ARM_MEMORY_PRE_INCREMENT     0x0010
+#define ARM_MEMORY_POST_INCREMENT    0x0020
+#define ARM_MEMORY_OFFSET_SUBTRACT   0x0040
+#define ARM_MEMORY_WRITEBACK         0x0080
+#define ARM_MEMORY_DECREMENT_AFTER   0x0000
+#define ARM_MEMORY_INCREMENT_AFTER   0x0100
+#define ARM_MEMORY_DECREMENT_BEFORE  0x0200
+#define ARM_MEMORY_INCREMENT_BEFORE  0x0300
+#define ARM_MEMORY_SPSR_SWAP         0x0400
+#define ARM_MEMORY_STORE             0x1000
+#define ARM_MEMORY_LOAD              0x2000
+#define ARM_MEMORY_SWAP              0x3000
+
+#define ARM_PSR_C 1
+#define ARM_PSR_X 2
+#define ARM_PSR_S 4
+#define ARM_PSR_F 8
+#define ARM_PSR_MASK 0xF
+
+#define MEMORY_FORMAT_TO_DIRECTION(F) (((F) >> 8) & 0x3)
+
+enum ARMCondition {
+	ARM_CONDITION_EQ = 0x0,
+	ARM_CONDITION_NE = 0x1,
+	ARM_CONDITION_CS = 0x2,
+	ARM_CONDITION_CC = 0x3,
+	ARM_CONDITION_MI = 0x4,
+	ARM_CONDITION_PL = 0x5,
+	ARM_CONDITION_VS = 0x6,
+	ARM_CONDITION_VC = 0x7,
+	ARM_CONDITION_HI = 0x8,
+	ARM_CONDITION_LS = 0x9,
+	ARM_CONDITION_GE = 0xA,
+	ARM_CONDITION_LT = 0xB,
+	ARM_CONDITION_GT = 0xC,
+	ARM_CONDITION_LE = 0xD,
+	ARM_CONDITION_AL = 0xE,
+	ARM_CONDITION_NV = 0xF
+};
+
+enum ARMShifterOperation {
+	ARM_SHIFT_NONE = 0,
+	ARM_SHIFT_LSL,
+	ARM_SHIFT_LSR,
+	ARM_SHIFT_ASR,
+	ARM_SHIFT_ROR,
+	ARM_SHIFT_RRX
+};
+
+union ARMOperand {
+	struct {
+		uint8_t reg;
+		uint8_t shifterOp;
+		union {
+			uint8_t shifterReg;
+			uint8_t shifterImm;
+			uint8_t psrBits;
+		};
+	};
+	int32_t immediate;
+};
+
+enum ARMMemoryAccessType {
+	ARM_ACCESS_WORD = 4,
+	ARM_ACCESS_HALFWORD = 2,
+	ARM_ACCESS_SIGNED_HALFWORD = 10,
+	ARM_ACCESS_BYTE = 1,
+	ARM_ACCESS_SIGNED_BYTE = 9,
+	ARM_ACCESS_TRANSLATED_WORD = 20,
+	ARM_ACCESS_TRANSLATED_BYTE = 17
+};
+
+enum ARMBranchType {
+	ARM_BRANCH_NONE = 0,
+	ARM_BRANCH = 1,
+	ARM_BRANCH_INDIRECT = 2,
+	ARM_BRANCH_LINKED = 4
+};
+
+struct ARMMemoryAccess {
+	uint8_t baseReg;
+	uint8_t width;
+	uint16_t format;
+	union ARMOperand offset;
+};
+
+enum ARMMnemonic {
+	ARM_MN_ILL = 0,
+	ARM_MN_ADC,
+	ARM_MN_ADD,
+	ARM_MN_AND,
+	ARM_MN_ASR,
+	ARM_MN_B,
+	ARM_MN_BIC,
+	ARM_MN_BKPT,
+	ARM_MN_BL,
+	ARM_MN_BX,
+	ARM_MN_CMN,
+	ARM_MN_CMP,
+	ARM_MN_EOR,
+	ARM_MN_LDM,
+	ARM_MN_LDR,
+	ARM_MN_LSL,
+	ARM_MN_LSR,
+	ARM_MN_MLA,
+	ARM_MN_MOV,
+	ARM_MN_MRS,
+	ARM_MN_MSR,
+	ARM_MN_MUL,
+	ARM_MN_MVN,
+	ARM_MN_NEG,
+	ARM_MN_ORR,
+	ARM_MN_ROR,
+	ARM_MN_RSB,
+	ARM_MN_RSC,
+	ARM_MN_SBC,
+	ARM_MN_SMLAL,
+	ARM_MN_SMULL,
+	ARM_MN_STM,
+	ARM_MN_STR,
+	ARM_MN_SUB,
+	ARM_MN_SWI,
+	ARM_MN_SWP,
+	ARM_MN_TEQ,
+	ARM_MN_TST,
+	ARM_MN_UMLAL,
+	ARM_MN_UMULL,
+
+	ARM_MN_MAX
+};
+
+enum {
+	ARM_CPSR = 16,
+	ARM_SPSR = 17
+};
+
+struct ARMInstructionInfo {
+	uint32_t opcode;
+	union ARMOperand op1;
+	union ARMOperand op2;
+	union ARMOperand op3;
+	union ARMOperand op4;
+	struct ARMMemoryAccess memory;
+	int operandFormat;
+	unsigned execMode : 1;
+	bool traps : 1;
+	bool affectsCPSR : 1;
+	unsigned branchType : 3;
+	unsigned condition : 4;
+	unsigned mnemonic : 6;
+	unsigned iCycles : 3;
+	unsigned cCycles : 4;
+	unsigned sInstructionCycles : 4;
+	unsigned nInstructionCycles : 4;
+	unsigned sDataCycles : 10;
+	unsigned nDataCycles : 10;
+};
+
+void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info);
+void ARMDecodeThumb(uint16_t opcode, struct ARMInstructionInfo* info);
+bool ARMDecodeThumbCombine(struct ARMInstructionInfo* info1, struct ARMInstructionInfo* info2,
+                           struct ARMInstructionInfo* out);
+uint32_t ARMResolveMemoryAccess(struct ARMInstructionInfo* info, struct ARMRegisterFile* regs, uint32_t pc);
+
+#ifdef ENABLE_DEBUGGERS
+struct mDebuggerSymbols;
+int ARMDisassemble(const struct ARMInstructionInfo* info, struct ARMCore* core, const struct mDebuggerSymbols* symbols, uint32_t pc, char* buffer, int blen);
+#endif
+
+CXX_GUARD_END
+
+#endif