wasmtime 9.0.4 → 10.0.0
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- checksums.yaml +4 -4
- data/Cargo.lock +184 -101
- data/ext/Cargo.toml +6 -6
- data/ext/build.rs +2 -2
- data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
- data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
- data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
- data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
- data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
- data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
- data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
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use crate::{
|
6
|
-
ir::types,
|
7
|
-
ir::AtomicRmwOp,
|
8
|
-
machinst::{InputSourceInst, Reg, Writable},
|
9
|
-
};
|
10
|
-
use crate::{isle_common_prelude_methods, isle_lower_prelude_methods};
|
11
|
-
use generated_code::{Context, MInst, RegisterClass};
|
12
|
-
|
13
|
-
// Types that the generated ISLE code uses via `use super::*`.
|
14
|
-
use super::{is_int_or_ref_ty, is_mergeable_load, lower_to_amode, MergeableLoadSize};
|
15
|
-
use crate::ir::LibCall;
|
16
|
-
use crate::isa::x64::lower::emit_vm_call;
|
17
|
-
use crate::isa::x64::X64Backend;
|
18
|
-
use crate::{
|
19
|
-
ir::{
|
20
|
-
condcodes::{CondCode, FloatCC, IntCC},
|
21
|
-
immediates::*,
|
22
|
-
types::*,
|
23
|
-
BlockCall, Inst, InstructionData, MemFlags, Opcode, TrapCode, Value, ValueList,
|
24
|
-
},
|
25
|
-
isa::{
|
26
|
-
unwind::UnwindInst,
|
27
|
-
x64::{
|
28
|
-
abi::X64Caller,
|
29
|
-
inst::{args::*, regs, CallInfo},
|
30
|
-
},
|
31
|
-
},
|
32
|
-
machinst::{
|
33
|
-
isle::*, valueregs, ArgPair, InsnInput, InstOutput, Lower, MachAtomicRmwOp, MachInst,
|
34
|
-
VCodeConstant, VCodeConstantData,
|
35
|
-
},
|
36
|
-
};
|
37
|
-
use alloc::vec::Vec;
|
38
|
-
use regalloc2::PReg;
|
39
|
-
use smallvec::SmallVec;
|
40
|
-
use std::boxed::Box;
|
41
|
-
use std::convert::TryFrom;
|
42
|
-
|
43
|
-
type BoxCallInfo = Box<CallInfo>;
|
44
|
-
type BoxVecMachLabel = Box<SmallVec<[MachLabel; 4]>>;
|
45
|
-
type MachLabelSlice = [MachLabel];
|
46
|
-
type VecArgPair = Vec<ArgPair>;
|
47
|
-
|
48
|
-
pub struct SinkableLoad {
|
49
|
-
inst: Inst,
|
50
|
-
addr_input: InsnInput,
|
51
|
-
offset: i32,
|
52
|
-
}
|
53
|
-
|
54
|
-
/// The main entry point for lowering with ISLE.
|
55
|
-
pub(crate) fn lower(
|
56
|
-
lower_ctx: &mut Lower<MInst>,
|
57
|
-
backend: &X64Backend,
|
58
|
-
inst: Inst,
|
59
|
-
) -> Option<InstOutput> {
|
60
|
-
// TODO: reuse the ISLE context across lowerings so we can reuse its
|
61
|
-
// internal heap allocations.
|
62
|
-
let mut isle_ctx = IsleContext { lower_ctx, backend };
|
63
|
-
generated_code::constructor_lower(&mut isle_ctx, inst)
|
64
|
-
}
|
65
|
-
|
66
|
-
pub(crate) fn lower_branch(
|
67
|
-
lower_ctx: &mut Lower<MInst>,
|
68
|
-
backend: &X64Backend,
|
69
|
-
branch: Inst,
|
70
|
-
targets: &[MachLabel],
|
71
|
-
) -> Option<()> {
|
72
|
-
// TODO: reuse the ISLE context across lowerings so we can reuse its
|
73
|
-
// internal heap allocations.
|
74
|
-
let mut isle_ctx = IsleContext { lower_ctx, backend };
|
75
|
-
generated_code::constructor_lower_branch(&mut isle_ctx, branch, &targets.to_vec())
|
76
|
-
}
|
77
|
-
|
78
|
-
impl Context for IsleContext<'_, '_, MInst, X64Backend> {
|
79
|
-
isle_lower_prelude_methods!();
|
80
|
-
isle_prelude_caller_methods!(X64ABIMachineSpec, X64Caller);
|
81
|
-
|
82
|
-
#[inline]
|
83
|
-
fn operand_size_of_type_32_64(&mut self, ty: Type) -> OperandSize {
|
84
|
-
if ty.bits() == 64 {
|
85
|
-
OperandSize::Size64
|
86
|
-
} else {
|
87
|
-
OperandSize::Size32
|
88
|
-
}
|
89
|
-
}
|
90
|
-
|
91
|
-
#[inline]
|
92
|
-
fn raw_operand_size_of_type(&mut self, ty: Type) -> OperandSize {
|
93
|
-
OperandSize::from_ty(ty)
|
94
|
-
}
|
95
|
-
|
96
|
-
fn put_in_reg_mem_imm(&mut self, val: Value) -> RegMemImm {
|
97
|
-
let inputs = self.lower_ctx.get_value_as_source_or_const(val);
|
98
|
-
|
99
|
-
if let Some(c) = inputs.constant {
|
100
|
-
if let Some(imm) = to_simm32(c as i64) {
|
101
|
-
return imm.to_reg_mem_imm();
|
102
|
-
}
|
103
|
-
}
|
104
|
-
|
105
|
-
self.put_in_reg_mem(val).into()
|
106
|
-
}
|
107
|
-
|
108
|
-
fn put_in_xmm_mem_imm(&mut self, val: Value) -> XmmMemImm {
|
109
|
-
let inputs = self.lower_ctx.get_value_as_source_or_const(val);
|
110
|
-
|
111
|
-
if let Some(c) = inputs.constant {
|
112
|
-
if let Some(imm) = to_simm32(c as i64) {
|
113
|
-
return XmmMemImm::new(imm.to_reg_mem_imm()).unwrap();
|
114
|
-
}
|
115
|
-
}
|
116
|
-
|
117
|
-
let res = match self.put_in_xmm_mem(val).to_reg_mem() {
|
118
|
-
RegMem::Reg { reg } => RegMemImm::Reg { reg },
|
119
|
-
RegMem::Mem { addr } => RegMemImm::Mem { addr },
|
120
|
-
};
|
121
|
-
|
122
|
-
XmmMemImm::new(res).unwrap()
|
123
|
-
}
|
124
|
-
|
125
|
-
fn put_in_xmm_mem(&mut self, val: Value) -> XmmMem {
|
126
|
-
let inputs = self.lower_ctx.get_value_as_source_or_const(val);
|
127
|
-
|
128
|
-
if let Some(c) = inputs.constant {
|
129
|
-
// A load from the constant pool is better than a rematerialization into a register,
|
130
|
-
// because it reduces register pressure.
|
131
|
-
//
|
132
|
-
// NOTE: this is where behavior differs from `put_in_reg_mem`, as we always force
|
133
|
-
// constants to be 16 bytes when a constant will be used in place of an xmm register.
|
134
|
-
let vcode_constant = self.emit_u128_le_const(c as u128);
|
135
|
-
return XmmMem::new(RegMem::mem(SyntheticAmode::ConstantOffset(vcode_constant)))
|
136
|
-
.unwrap();
|
137
|
-
}
|
138
|
-
|
139
|
-
XmmMem::new(self.put_in_reg_mem(val)).unwrap()
|
140
|
-
}
|
141
|
-
|
142
|
-
fn put_in_reg_mem(&mut self, val: Value) -> RegMem {
|
143
|
-
let inputs = self.lower_ctx.get_value_as_source_or_const(val);
|
144
|
-
|
145
|
-
if let Some(c) = inputs.constant {
|
146
|
-
// A load from the constant pool is better than a
|
147
|
-
// rematerialization into a register, because it reduces
|
148
|
-
// register pressure.
|
149
|
-
let vcode_constant = self.emit_u64_le_const(c);
|
150
|
-
return RegMem::mem(SyntheticAmode::ConstantOffset(vcode_constant));
|
151
|
-
}
|
152
|
-
|
153
|
-
if let Some(load) = self.sinkable_load(val) {
|
154
|
-
return RegMem::Mem {
|
155
|
-
addr: self.sink_load(&load),
|
156
|
-
};
|
157
|
-
}
|
158
|
-
|
159
|
-
RegMem::reg(self.put_in_reg(val))
|
160
|
-
}
|
161
|
-
|
162
|
-
#[inline]
|
163
|
-
fn encode_fcmp_imm(&mut self, imm: &FcmpImm) -> u8 {
|
164
|
-
imm.encode()
|
165
|
-
}
|
166
|
-
|
167
|
-
#[inline]
|
168
|
-
fn encode_round_imm(&mut self, imm: &RoundImm) -> u8 {
|
169
|
-
imm.encode()
|
170
|
-
}
|
171
|
-
|
172
|
-
#[inline]
|
173
|
-
fn use_avx_simd(&mut self) -> bool {
|
174
|
-
self.backend.x64_flags.use_avx_simd()
|
175
|
-
}
|
176
|
-
|
177
|
-
#[inline]
|
178
|
-
fn use_avx2_simd(&mut self) -> bool {
|
179
|
-
self.backend.x64_flags.use_avx2_simd()
|
180
|
-
}
|
181
|
-
|
182
|
-
#[inline]
|
183
|
-
fn avx512vl_enabled(&mut self, _: Type) -> bool {
|
184
|
-
self.backend.x64_flags.use_avx512vl_simd()
|
185
|
-
}
|
186
|
-
|
187
|
-
#[inline]
|
188
|
-
fn avx512dq_enabled(&mut self, _: Type) -> bool {
|
189
|
-
self.backend.x64_flags.use_avx512dq_simd()
|
190
|
-
}
|
191
|
-
|
192
|
-
#[inline]
|
193
|
-
fn avx512f_enabled(&mut self, _: Type) -> bool {
|
194
|
-
self.backend.x64_flags.use_avx512f_simd()
|
195
|
-
}
|
196
|
-
|
197
|
-
#[inline]
|
198
|
-
fn avx512bitalg_enabled(&mut self, _: Type) -> bool {
|
199
|
-
self.backend.x64_flags.use_avx512bitalg_simd()
|
200
|
-
}
|
201
|
-
|
202
|
-
#[inline]
|
203
|
-
fn avx512vbmi_enabled(&mut self, _: Type) -> bool {
|
204
|
-
self.backend.x64_flags.use_avx512vbmi_simd()
|
205
|
-
}
|
206
|
-
|
207
|
-
#[inline]
|
208
|
-
fn use_lzcnt(&mut self, _: Type) -> bool {
|
209
|
-
self.backend.x64_flags.use_lzcnt()
|
210
|
-
}
|
211
|
-
|
212
|
-
#[inline]
|
213
|
-
fn use_bmi1(&mut self, _: Type) -> bool {
|
214
|
-
self.backend.x64_flags.use_bmi1()
|
215
|
-
}
|
216
|
-
|
217
|
-
#[inline]
|
218
|
-
fn use_popcnt(&mut self, _: Type) -> bool {
|
219
|
-
self.backend.x64_flags.use_popcnt()
|
220
|
-
}
|
221
|
-
|
222
|
-
#[inline]
|
223
|
-
fn use_fma(&mut self) -> bool {
|
224
|
-
self.backend.x64_flags.use_fma()
|
225
|
-
}
|
226
|
-
|
227
|
-
#[inline]
|
228
|
-
fn use_sse41(&mut self) -> bool {
|
229
|
-
self.backend.x64_flags.use_sse41()
|
230
|
-
}
|
231
|
-
|
232
|
-
#[inline]
|
233
|
-
fn use_sse42(&mut self) -> bool {
|
234
|
-
self.backend.x64_flags.use_sse42()
|
235
|
-
}
|
236
|
-
|
237
|
-
#[inline]
|
238
|
-
fn imm8_from_value(&mut self, val: Value) -> Option<Imm8Reg> {
|
239
|
-
let inst = self.lower_ctx.dfg().value_def(val).inst()?;
|
240
|
-
let constant = self.lower_ctx.get_constant(inst)?;
|
241
|
-
let imm = u8::try_from(constant).ok()?;
|
242
|
-
Some(Imm8Reg::Imm8 { imm })
|
243
|
-
}
|
244
|
-
|
245
|
-
#[inline]
|
246
|
-
fn const_to_type_masked_imm8(&mut self, c: u64, ty: Type) -> Imm8Gpr {
|
247
|
-
let mask = self.shift_mask(ty) as u64;
|
248
|
-
Imm8Gpr::new(Imm8Reg::Imm8 {
|
249
|
-
imm: (c & mask) as u8,
|
250
|
-
})
|
251
|
-
.unwrap()
|
252
|
-
}
|
253
|
-
|
254
|
-
#[inline]
|
255
|
-
fn shift_mask(&mut self, ty: Type) -> u32 {
|
256
|
-
debug_assert!(ty.lane_bits().is_power_of_two());
|
257
|
-
|
258
|
-
ty.lane_bits() - 1
|
259
|
-
}
|
260
|
-
|
261
|
-
fn shift_amount_masked(&mut self, ty: Type, val: Imm64) -> u32 {
|
262
|
-
(val.bits() as u32) & self.shift_mask(ty)
|
263
|
-
}
|
264
|
-
|
265
|
-
#[inline]
|
266
|
-
fn simm32_from_value(&mut self, val: Value) -> Option<GprMemImm> {
|
267
|
-
let inst = self.lower_ctx.dfg().value_def(val).inst()?;
|
268
|
-
let constant: u64 = self.lower_ctx.get_constant(inst)?;
|
269
|
-
let constant = constant as i64;
|
270
|
-
to_simm32(constant)
|
271
|
-
}
|
272
|
-
|
273
|
-
#[inline]
|
274
|
-
fn simm32_from_imm64(&mut self, imm: Imm64) -> Option<GprMemImm> {
|
275
|
-
to_simm32(imm.bits())
|
276
|
-
}
|
277
|
-
|
278
|
-
fn sinkable_load(&mut self, val: Value) -> Option<SinkableLoad> {
|
279
|
-
let input = self.lower_ctx.get_value_as_source_or_const(val);
|
280
|
-
if let InputSourceInst::UniqueUse(inst, 0) = input.inst {
|
281
|
-
if let Some((addr_input, offset)) =
|
282
|
-
is_mergeable_load(self.lower_ctx, inst, MergeableLoadSize::Min32)
|
283
|
-
{
|
284
|
-
return Some(SinkableLoad {
|
285
|
-
inst,
|
286
|
-
addr_input,
|
287
|
-
offset,
|
288
|
-
});
|
289
|
-
}
|
290
|
-
}
|
291
|
-
None
|
292
|
-
}
|
293
|
-
|
294
|
-
fn sinkable_load_exact(&mut self, val: Value) -> Option<SinkableLoad> {
|
295
|
-
let input = self.lower_ctx.get_value_as_source_or_const(val);
|
296
|
-
if let InputSourceInst::UniqueUse(inst, 0) = input.inst {
|
297
|
-
if let Some((addr_input, offset)) =
|
298
|
-
is_mergeable_load(self.lower_ctx, inst, MergeableLoadSize::Exact)
|
299
|
-
{
|
300
|
-
return Some(SinkableLoad {
|
301
|
-
inst,
|
302
|
-
addr_input,
|
303
|
-
offset,
|
304
|
-
});
|
305
|
-
}
|
306
|
-
}
|
307
|
-
None
|
308
|
-
}
|
309
|
-
|
310
|
-
fn sink_load(&mut self, load: &SinkableLoad) -> SyntheticAmode {
|
311
|
-
self.lower_ctx.sink_inst(load.inst);
|
312
|
-
let addr = lower_to_amode(self.lower_ctx, load.addr_input, load.offset);
|
313
|
-
SyntheticAmode::Real(addr)
|
314
|
-
}
|
315
|
-
|
316
|
-
#[inline]
|
317
|
-
fn ext_mode(&mut self, from_bits: u16, to_bits: u16) -> ExtMode {
|
318
|
-
ExtMode::new(from_bits, to_bits).unwrap()
|
319
|
-
}
|
320
|
-
|
321
|
-
fn emit(&mut self, inst: &MInst) -> Unit {
|
322
|
-
self.lower_ctx.emit(inst.clone());
|
323
|
-
}
|
324
|
-
|
325
|
-
#[inline]
|
326
|
-
fn nonzero_u64_fits_in_u32(&mut self, x: u64) -> Option<u64> {
|
327
|
-
if x != 0 && x < u64::from(u32::MAX) {
|
328
|
-
Some(x)
|
329
|
-
} else {
|
330
|
-
None
|
331
|
-
}
|
332
|
-
}
|
333
|
-
|
334
|
-
#[inline]
|
335
|
-
fn sse_insertps_lane_imm(&mut self, lane: u8) -> u8 {
|
336
|
-
// Insert 32-bits from replacement (at index 00, bits 7:8) to vector (lane
|
337
|
-
// shifted into bits 5:6).
|
338
|
-
0b00_00_00_00 | lane << 4
|
339
|
-
}
|
340
|
-
|
341
|
-
#[inline]
|
342
|
-
fn synthetic_amode_to_reg_mem(&mut self, addr: &SyntheticAmode) -> RegMem {
|
343
|
-
RegMem::mem(addr.clone())
|
344
|
-
}
|
345
|
-
|
346
|
-
#[inline]
|
347
|
-
fn amode_imm_reg_reg_shift(&mut self, simm32: u32, base: Gpr, index: Gpr, shift: u8) -> Amode {
|
348
|
-
Amode::imm_reg_reg_shift(simm32, base, index, shift)
|
349
|
-
}
|
350
|
-
|
351
|
-
#[inline]
|
352
|
-
fn amode_imm_reg(&mut self, simm32: u32, base: Gpr) -> Amode {
|
353
|
-
Amode::imm_reg(simm32, base.to_reg())
|
354
|
-
}
|
355
|
-
|
356
|
-
#[inline]
|
357
|
-
fn amode_with_flags(&mut self, amode: &Amode, flags: MemFlags) -> Amode {
|
358
|
-
amode.with_flags(flags)
|
359
|
-
}
|
360
|
-
|
361
|
-
#[inline]
|
362
|
-
fn amode_to_synthetic_amode(&mut self, amode: &Amode) -> SyntheticAmode {
|
363
|
-
amode.clone().into()
|
364
|
-
}
|
365
|
-
|
366
|
-
#[inline]
|
367
|
-
fn const_to_synthetic_amode(&mut self, c: VCodeConstant) -> SyntheticAmode {
|
368
|
-
SyntheticAmode::ConstantOffset(c)
|
369
|
-
}
|
370
|
-
|
371
|
-
#[inline]
|
372
|
-
fn writable_gpr_to_reg(&mut self, r: WritableGpr) -> WritableReg {
|
373
|
-
r.to_writable_reg()
|
374
|
-
}
|
375
|
-
|
376
|
-
#[inline]
|
377
|
-
fn writable_xmm_to_reg(&mut self, r: WritableXmm) -> WritableReg {
|
378
|
-
r.to_writable_reg()
|
379
|
-
}
|
380
|
-
|
381
|
-
fn ishl_i8x16_mask_for_const(&mut self, amt: u32) -> SyntheticAmode {
|
382
|
-
// When the shift amount is known, we can statically (i.e. at compile
|
383
|
-
// time) determine the mask to use and only emit that.
|
384
|
-
debug_assert!(amt < 8);
|
385
|
-
let mask_offset = amt as usize * 16;
|
386
|
-
let mask_constant = self.lower_ctx.use_constant(VCodeConstantData::WellKnown(
|
387
|
-
&I8X16_ISHL_MASKS[mask_offset..mask_offset + 16],
|
388
|
-
));
|
389
|
-
SyntheticAmode::ConstantOffset(mask_constant)
|
390
|
-
}
|
391
|
-
|
392
|
-
fn ishl_i8x16_mask_table(&mut self) -> SyntheticAmode {
|
393
|
-
let mask_table = self
|
394
|
-
.lower_ctx
|
395
|
-
.use_constant(VCodeConstantData::WellKnown(&I8X16_ISHL_MASKS));
|
396
|
-
SyntheticAmode::ConstantOffset(mask_table)
|
397
|
-
}
|
398
|
-
|
399
|
-
fn ushr_i8x16_mask_for_const(&mut self, amt: u32) -> SyntheticAmode {
|
400
|
-
// When the shift amount is known, we can statically (i.e. at compile
|
401
|
-
// time) determine the mask to use and only emit that.
|
402
|
-
debug_assert!(amt < 8);
|
403
|
-
let mask_offset = amt as usize * 16;
|
404
|
-
let mask_constant = self.lower_ctx.use_constant(VCodeConstantData::WellKnown(
|
405
|
-
&I8X16_USHR_MASKS[mask_offset..mask_offset + 16],
|
406
|
-
));
|
407
|
-
SyntheticAmode::ConstantOffset(mask_constant)
|
408
|
-
}
|
409
|
-
|
410
|
-
fn ushr_i8x16_mask_table(&mut self) -> SyntheticAmode {
|
411
|
-
let mask_table = self
|
412
|
-
.lower_ctx
|
413
|
-
.use_constant(VCodeConstantData::WellKnown(&I8X16_USHR_MASKS));
|
414
|
-
SyntheticAmode::ConstantOffset(mask_table)
|
415
|
-
}
|
416
|
-
|
417
|
-
fn popcount_4bit_table(&mut self) -> VCodeConstant {
|
418
|
-
self.lower_ctx
|
419
|
-
.use_constant(VCodeConstantData::WellKnown(&POPCOUNT_4BIT_TABLE))
|
420
|
-
}
|
421
|
-
|
422
|
-
fn popcount_low_mask(&mut self) -> VCodeConstant {
|
423
|
-
self.lower_ctx
|
424
|
-
.use_constant(VCodeConstantData::WellKnown(&POPCOUNT_LOW_MASK))
|
425
|
-
}
|
426
|
-
|
427
|
-
#[inline]
|
428
|
-
fn writable_reg_to_xmm(&mut self, r: WritableReg) -> WritableXmm {
|
429
|
-
Writable::from_reg(Xmm::new(r.to_reg()).unwrap())
|
430
|
-
}
|
431
|
-
|
432
|
-
#[inline]
|
433
|
-
fn writable_xmm_to_xmm(&mut self, r: WritableXmm) -> Xmm {
|
434
|
-
r.to_reg()
|
435
|
-
}
|
436
|
-
|
437
|
-
#[inline]
|
438
|
-
fn writable_gpr_to_gpr(&mut self, r: WritableGpr) -> Gpr {
|
439
|
-
r.to_reg()
|
440
|
-
}
|
441
|
-
|
442
|
-
#[inline]
|
443
|
-
fn gpr_to_reg(&mut self, r: Gpr) -> Reg {
|
444
|
-
r.into()
|
445
|
-
}
|
446
|
-
|
447
|
-
#[inline]
|
448
|
-
fn xmm_to_reg(&mut self, r: Xmm) -> Reg {
|
449
|
-
r.into()
|
450
|
-
}
|
451
|
-
|
452
|
-
#[inline]
|
453
|
-
fn xmm_to_xmm_mem_imm(&mut self, r: Xmm) -> XmmMemImm {
|
454
|
-
r.into()
|
455
|
-
}
|
456
|
-
|
457
|
-
#[inline]
|
458
|
-
fn xmm_mem_to_xmm_mem_imm(&mut self, r: &XmmMem) -> XmmMemImm {
|
459
|
-
XmmMemImm::new(r.clone().to_reg_mem().into()).unwrap()
|
460
|
-
}
|
461
|
-
|
462
|
-
#[inline]
|
463
|
-
fn temp_writable_gpr(&mut self) -> WritableGpr {
|
464
|
-
Writable::from_reg(Gpr::new(self.temp_writable_reg(I64).to_reg()).unwrap())
|
465
|
-
}
|
466
|
-
|
467
|
-
#[inline]
|
468
|
-
fn temp_writable_xmm(&mut self) -> WritableXmm {
|
469
|
-
Writable::from_reg(Xmm::new(self.temp_writable_reg(I8X16).to_reg()).unwrap())
|
470
|
-
}
|
471
|
-
|
472
|
-
#[inline]
|
473
|
-
fn reg_to_reg_mem_imm(&mut self, reg: Reg) -> RegMemImm {
|
474
|
-
RegMemImm::Reg { reg }
|
475
|
-
}
|
476
|
-
|
477
|
-
#[inline]
|
478
|
-
fn reg_mem_to_xmm_mem(&mut self, rm: &RegMem) -> XmmMem {
|
479
|
-
XmmMem::new(rm.clone()).unwrap()
|
480
|
-
}
|
481
|
-
|
482
|
-
#[inline]
|
483
|
-
fn gpr_mem_imm_new(&mut self, rmi: &RegMemImm) -> GprMemImm {
|
484
|
-
GprMemImm::new(rmi.clone()).unwrap()
|
485
|
-
}
|
486
|
-
|
487
|
-
#[inline]
|
488
|
-
fn xmm_mem_imm_new(&mut self, rmi: &RegMemImm) -> XmmMemImm {
|
489
|
-
XmmMemImm::new(rmi.clone()).unwrap()
|
490
|
-
}
|
491
|
-
|
492
|
-
#[inline]
|
493
|
-
fn xmm_to_xmm_mem(&mut self, r: Xmm) -> XmmMem {
|
494
|
-
r.into()
|
495
|
-
}
|
496
|
-
|
497
|
-
#[inline]
|
498
|
-
fn xmm_mem_to_reg_mem(&mut self, xm: &XmmMem) -> RegMem {
|
499
|
-
xm.clone().into()
|
500
|
-
}
|
501
|
-
|
502
|
-
#[inline]
|
503
|
-
fn gpr_mem_to_reg_mem(&mut self, gm: &GprMem) -> RegMem {
|
504
|
-
gm.clone().into()
|
505
|
-
}
|
506
|
-
|
507
|
-
#[inline]
|
508
|
-
fn xmm_new(&mut self, r: Reg) -> Xmm {
|
509
|
-
Xmm::new(r).unwrap()
|
510
|
-
}
|
511
|
-
|
512
|
-
#[inline]
|
513
|
-
fn gpr_new(&mut self, r: Reg) -> Gpr {
|
514
|
-
Gpr::new(r).unwrap()
|
515
|
-
}
|
516
|
-
|
517
|
-
#[inline]
|
518
|
-
fn reg_mem_to_gpr_mem(&mut self, rm: &RegMem) -> GprMem {
|
519
|
-
GprMem::new(rm.clone()).unwrap()
|
520
|
-
}
|
521
|
-
|
522
|
-
#[inline]
|
523
|
-
fn reg_to_gpr_mem(&mut self, r: Reg) -> GprMem {
|
524
|
-
GprMem::new(RegMem::reg(r)).unwrap()
|
525
|
-
}
|
526
|
-
|
527
|
-
#[inline]
|
528
|
-
fn imm8_reg_to_imm8_gpr(&mut self, ir: &Imm8Reg) -> Imm8Gpr {
|
529
|
-
Imm8Gpr::new(ir.clone()).unwrap()
|
530
|
-
}
|
531
|
-
|
532
|
-
#[inline]
|
533
|
-
fn gpr_to_gpr_mem(&mut self, gpr: Gpr) -> GprMem {
|
534
|
-
GprMem::from(gpr)
|
535
|
-
}
|
536
|
-
|
537
|
-
#[inline]
|
538
|
-
fn gpr_to_gpr_mem_imm(&mut self, gpr: Gpr) -> GprMemImm {
|
539
|
-
GprMemImm::from(gpr)
|
540
|
-
}
|
541
|
-
|
542
|
-
#[inline]
|
543
|
-
fn gpr_to_imm8_gpr(&mut self, gpr: Gpr) -> Imm8Gpr {
|
544
|
-
Imm8Gpr::from(gpr)
|
545
|
-
}
|
546
|
-
|
547
|
-
#[inline]
|
548
|
-
fn imm8_to_imm8_gpr(&mut self, imm: u8) -> Imm8Gpr {
|
549
|
-
Imm8Gpr::new(Imm8Reg::Imm8 { imm }).unwrap()
|
550
|
-
}
|
551
|
-
|
552
|
-
#[inline]
|
553
|
-
fn type_register_class(&mut self, ty: Type) -> Option<RegisterClass> {
|
554
|
-
if is_int_or_ref_ty(ty) || ty == I128 {
|
555
|
-
Some(RegisterClass::Gpr {
|
556
|
-
single_register: ty != I128,
|
557
|
-
})
|
558
|
-
} else if ty == F32 || ty == F64 || (ty.is_vector() && ty.bits() == 128) {
|
559
|
-
Some(RegisterClass::Xmm)
|
560
|
-
} else {
|
561
|
-
None
|
562
|
-
}
|
563
|
-
}
|
564
|
-
|
565
|
-
#[inline]
|
566
|
-
fn ty_int_bool_or_ref(&mut self, ty: Type) -> Option<()> {
|
567
|
-
match ty {
|
568
|
-
types::I8 | types::I16 | types::I32 | types::I64 | types::R64 => Some(()),
|
569
|
-
types::R32 => panic!("shouldn't have 32-bits refs on x64"),
|
570
|
-
_ => None,
|
571
|
-
}
|
572
|
-
}
|
573
|
-
|
574
|
-
#[inline]
|
575
|
-
fn intcc_without_eq(&mut self, x: &IntCC) -> IntCC {
|
576
|
-
x.without_equal()
|
577
|
-
}
|
578
|
-
|
579
|
-
#[inline]
|
580
|
-
fn intcc_to_cc(&mut self, intcc: &IntCC) -> CC {
|
581
|
-
CC::from_intcc(*intcc)
|
582
|
-
}
|
583
|
-
|
584
|
-
#[inline]
|
585
|
-
fn cc_invert(&mut self, cc: &CC) -> CC {
|
586
|
-
cc.invert()
|
587
|
-
}
|
588
|
-
|
589
|
-
#[inline]
|
590
|
-
fn cc_nz_or_z(&mut self, cc: &CC) -> Option<CC> {
|
591
|
-
match cc {
|
592
|
-
CC::Z => Some(*cc),
|
593
|
-
CC::NZ => Some(*cc),
|
594
|
-
_ => None,
|
595
|
-
}
|
596
|
-
}
|
597
|
-
|
598
|
-
#[inline]
|
599
|
-
fn sum_extend_fits_in_32_bits(
|
600
|
-
&mut self,
|
601
|
-
extend_from_ty: Type,
|
602
|
-
constant_value: Imm64,
|
603
|
-
offset: Offset32,
|
604
|
-
) -> Option<u32> {
|
605
|
-
let offset: i64 = offset.into();
|
606
|
-
let constant_value: u64 = constant_value.bits() as u64;
|
607
|
-
// If necessary, zero extend `constant_value` up to 64 bits.
|
608
|
-
let shift = 64 - extend_from_ty.bits();
|
609
|
-
let zero_extended_constant_value = (constant_value << shift) >> shift;
|
610
|
-
// Sum up the two operands.
|
611
|
-
let sum = offset.wrapping_add(zero_extended_constant_value as i64);
|
612
|
-
// Check that the sum will fit in 32-bits.
|
613
|
-
if sum == ((sum << 32) >> 32) {
|
614
|
-
Some(sum as u32)
|
615
|
-
} else {
|
616
|
-
None
|
617
|
-
}
|
618
|
-
}
|
619
|
-
|
620
|
-
#[inline]
|
621
|
-
fn amode_offset(&mut self, addr: &Amode, offset: u32) -> Amode {
|
622
|
-
addr.offset(offset)
|
623
|
-
}
|
624
|
-
|
625
|
-
#[inline]
|
626
|
-
fn zero_offset(&mut self) -> Offset32 {
|
627
|
-
Offset32::new(0)
|
628
|
-
}
|
629
|
-
|
630
|
-
#[inline]
|
631
|
-
fn atomic_rmw_op_to_mach_atomic_rmw_op(&mut self, op: &AtomicRmwOp) -> MachAtomicRmwOp {
|
632
|
-
MachAtomicRmwOp::from(*op)
|
633
|
-
}
|
634
|
-
|
635
|
-
#[inline]
|
636
|
-
fn preg_rbp(&mut self) -> PReg {
|
637
|
-
regs::rbp().to_real_reg().unwrap().into()
|
638
|
-
}
|
639
|
-
|
640
|
-
#[inline]
|
641
|
-
fn preg_rsp(&mut self) -> PReg {
|
642
|
-
regs::rsp().to_real_reg().unwrap().into()
|
643
|
-
}
|
644
|
-
|
645
|
-
#[inline]
|
646
|
-
fn preg_pinned(&mut self) -> PReg {
|
647
|
-
regs::pinned_reg().to_real_reg().unwrap().into()
|
648
|
-
}
|
649
|
-
|
650
|
-
fn libcall_1(&mut self, libcall: &LibCall, a: Reg) -> Reg {
|
651
|
-
let call_conv = self.lower_ctx.abi().call_conv(self.lower_ctx.sigs());
|
652
|
-
let ret_ty = libcall.signature(call_conv, I64).returns[0].value_type;
|
653
|
-
let output_reg = self.lower_ctx.alloc_tmp(ret_ty).only_reg().unwrap();
|
654
|
-
|
655
|
-
emit_vm_call(
|
656
|
-
self.lower_ctx,
|
657
|
-
&self.backend.flags,
|
658
|
-
&self.backend.triple,
|
659
|
-
libcall.clone(),
|
660
|
-
&[a],
|
661
|
-
&[output_reg],
|
662
|
-
)
|
663
|
-
.expect("Failed to emit LibCall");
|
664
|
-
|
665
|
-
output_reg.to_reg()
|
666
|
-
}
|
667
|
-
|
668
|
-
fn libcall_3(&mut self, libcall: &LibCall, a: Reg, b: Reg, c: Reg) -> Reg {
|
669
|
-
let call_conv = self.lower_ctx.abi().call_conv(self.lower_ctx.sigs());
|
670
|
-
let ret_ty = libcall.signature(call_conv, I64).returns[0].value_type;
|
671
|
-
let output_reg = self.lower_ctx.alloc_tmp(ret_ty).only_reg().unwrap();
|
672
|
-
|
673
|
-
emit_vm_call(
|
674
|
-
self.lower_ctx,
|
675
|
-
&self.backend.flags,
|
676
|
-
&self.backend.triple,
|
677
|
-
libcall.clone(),
|
678
|
-
&[a, b, c],
|
679
|
-
&[output_reg],
|
680
|
-
)
|
681
|
-
.expect("Failed to emit LibCall");
|
682
|
-
|
683
|
-
output_reg.to_reg()
|
684
|
-
}
|
685
|
-
|
686
|
-
#[inline]
|
687
|
-
fn single_target(&mut self, targets: &MachLabelSlice) -> Option<MachLabel> {
|
688
|
-
if targets.len() == 1 {
|
689
|
-
Some(targets[0])
|
690
|
-
} else {
|
691
|
-
None
|
692
|
-
}
|
693
|
-
}
|
694
|
-
|
695
|
-
#[inline]
|
696
|
-
fn two_targets(&mut self, targets: &MachLabelSlice) -> Option<(MachLabel, MachLabel)> {
|
697
|
-
if targets.len() == 2 {
|
698
|
-
Some((targets[0], targets[1]))
|
699
|
-
} else {
|
700
|
-
None
|
701
|
-
}
|
702
|
-
}
|
703
|
-
|
704
|
-
#[inline]
|
705
|
-
fn jump_table_targets(
|
706
|
-
&mut self,
|
707
|
-
targets: &MachLabelSlice,
|
708
|
-
) -> Option<(MachLabel, BoxVecMachLabel)> {
|
709
|
-
if targets.is_empty() {
|
710
|
-
return None;
|
711
|
-
}
|
712
|
-
|
713
|
-
let default_label = targets[0];
|
714
|
-
let jt_targets = Box::new(SmallVec::from(&targets[1..]));
|
715
|
-
Some((default_label, jt_targets))
|
716
|
-
}
|
717
|
-
|
718
|
-
#[inline]
|
719
|
-
fn jump_table_size(&mut self, targets: &BoxVecMachLabel) -> u32 {
|
720
|
-
targets.len() as u32
|
721
|
-
}
|
722
|
-
|
723
|
-
#[inline]
|
724
|
-
fn vconst_all_ones_or_all_zeros(&mut self, constant: Constant) -> Option<()> {
|
725
|
-
let const_data = self.lower_ctx.get_constant_data(constant);
|
726
|
-
if const_data.iter().all(|&b| b == 0 || b == 0xFF) {
|
727
|
-
return Some(());
|
728
|
-
}
|
729
|
-
None
|
730
|
-
}
|
731
|
-
|
732
|
-
#[inline]
|
733
|
-
fn fcvt_uint_mask_const(&mut self) -> VCodeConstant {
|
734
|
-
self.lower_ctx
|
735
|
-
.use_constant(VCodeConstantData::WellKnown(&UINT_MASK))
|
736
|
-
}
|
737
|
-
|
738
|
-
#[inline]
|
739
|
-
fn fcvt_uint_mask_high_const(&mut self) -> VCodeConstant {
|
740
|
-
self.lower_ctx
|
741
|
-
.use_constant(VCodeConstantData::WellKnown(&UINT_MASK_HIGH))
|
742
|
-
}
|
743
|
-
|
744
|
-
#[inline]
|
745
|
-
fn iadd_pairwise_mul_const_16(&mut self) -> VCodeConstant {
|
746
|
-
self.lower_ctx
|
747
|
-
.use_constant(VCodeConstantData::WellKnown(&IADD_PAIRWISE_MUL_CONST_16))
|
748
|
-
}
|
749
|
-
|
750
|
-
#[inline]
|
751
|
-
fn iadd_pairwise_mul_const_32(&mut self) -> VCodeConstant {
|
752
|
-
self.lower_ctx
|
753
|
-
.use_constant(VCodeConstantData::WellKnown(&IADD_PAIRWISE_MUL_CONST_32))
|
754
|
-
}
|
755
|
-
|
756
|
-
#[inline]
|
757
|
-
fn iadd_pairwise_xor_const_32(&mut self) -> VCodeConstant {
|
758
|
-
self.lower_ctx
|
759
|
-
.use_constant(VCodeConstantData::WellKnown(&IADD_PAIRWISE_XOR_CONST_32))
|
760
|
-
}
|
761
|
-
|
762
|
-
#[inline]
|
763
|
-
fn iadd_pairwise_addd_const_32(&mut self) -> VCodeConstant {
|
764
|
-
self.lower_ctx
|
765
|
-
.use_constant(VCodeConstantData::WellKnown(&IADD_PAIRWISE_ADDD_CONST_32))
|
766
|
-
}
|
767
|
-
|
768
|
-
#[inline]
|
769
|
-
fn snarrow_umax_mask(&mut self) -> VCodeConstant {
|
770
|
-
// 2147483647.0 is equivalent to 0x41DFFFFFFFC00000
|
771
|
-
static UMAX_MASK: [u8; 16] = [
|
772
|
-
0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xDF, 0x41, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF,
|
773
|
-
0xDF, 0x41,
|
774
|
-
];
|
775
|
-
self.lower_ctx
|
776
|
-
.use_constant(VCodeConstantData::WellKnown(&UMAX_MASK))
|
777
|
-
}
|
778
|
-
|
779
|
-
#[inline]
|
780
|
-
fn shuffle_0_31_mask(&mut self, mask: &VecMask) -> VCodeConstant {
|
781
|
-
let mask = mask
|
782
|
-
.iter()
|
783
|
-
.map(|&b| if b > 15 { b.wrapping_sub(16) } else { b })
|
784
|
-
.map(|b| if b > 15 { 0b10000000 } else { b })
|
785
|
-
.collect();
|
786
|
-
self.lower_ctx
|
787
|
-
.use_constant(VCodeConstantData::Generated(mask))
|
788
|
-
}
|
789
|
-
|
790
|
-
#[inline]
|
791
|
-
fn shuffle_0_15_mask(&mut self, mask: &VecMask) -> VCodeConstant {
|
792
|
-
let mask = mask
|
793
|
-
.iter()
|
794
|
-
.map(|&b| if b > 15 { 0b10000000 } else { b })
|
795
|
-
.collect();
|
796
|
-
self.lower_ctx
|
797
|
-
.use_constant(VCodeConstantData::Generated(mask))
|
798
|
-
}
|
799
|
-
|
800
|
-
#[inline]
|
801
|
-
fn shuffle_16_31_mask(&mut self, mask: &VecMask) -> VCodeConstant {
|
802
|
-
let mask = mask
|
803
|
-
.iter()
|
804
|
-
.map(|&b| b.wrapping_sub(16))
|
805
|
-
.map(|b| if b > 15 { 0b10000000 } else { b })
|
806
|
-
.collect();
|
807
|
-
self.lower_ctx
|
808
|
-
.use_constant(VCodeConstantData::Generated(mask))
|
809
|
-
}
|
810
|
-
|
811
|
-
#[inline]
|
812
|
-
fn perm_from_mask_with_zeros(
|
813
|
-
&mut self,
|
814
|
-
mask: &VecMask,
|
815
|
-
) -> Option<(VCodeConstant, VCodeConstant)> {
|
816
|
-
if !mask.iter().any(|&b| b > 31) {
|
817
|
-
return None;
|
818
|
-
}
|
819
|
-
|
820
|
-
let zeros = mask
|
821
|
-
.iter()
|
822
|
-
.map(|&b| if b > 31 { 0x00 } else { 0xff })
|
823
|
-
.collect();
|
824
|
-
|
825
|
-
Some((
|
826
|
-
self.perm_from_mask(mask),
|
827
|
-
self.lower_ctx
|
828
|
-
.use_constant(VCodeConstantData::Generated(zeros)),
|
829
|
-
))
|
830
|
-
}
|
831
|
-
|
832
|
-
#[inline]
|
833
|
-
fn perm_from_mask(&mut self, mask: &VecMask) -> VCodeConstant {
|
834
|
-
let mask = mask.iter().cloned().collect();
|
835
|
-
self.lower_ctx
|
836
|
-
.use_constant(VCodeConstantData::Generated(mask))
|
837
|
-
}
|
838
|
-
|
839
|
-
#[inline]
|
840
|
-
fn swizzle_zero_mask(&mut self) -> VCodeConstant {
|
841
|
-
static ZERO_MASK_VALUE: [u8; 16] = [0x70; 16];
|
842
|
-
self.lower_ctx
|
843
|
-
.use_constant(VCodeConstantData::WellKnown(&ZERO_MASK_VALUE))
|
844
|
-
}
|
845
|
-
|
846
|
-
#[inline]
|
847
|
-
fn sqmul_round_sat_mask(&mut self) -> VCodeConstant {
|
848
|
-
static SAT_MASK: [u8; 16] = [
|
849
|
-
0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80,
|
850
|
-
0x00, 0x80,
|
851
|
-
];
|
852
|
-
self.lower_ctx
|
853
|
-
.use_constant(VCodeConstantData::WellKnown(&SAT_MASK))
|
854
|
-
}
|
855
|
-
|
856
|
-
#[inline]
|
857
|
-
fn uunarrow_umax_mask(&mut self) -> VCodeConstant {
|
858
|
-
// 4294967295.0 is equivalent to 0x41EFFFFFFFE00000
|
859
|
-
static UMAX_MASK: [u8; 16] = [
|
860
|
-
0x00, 0x00, 0xE0, 0xFF, 0xFF, 0xFF, 0xEF, 0x41, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0xFF,
|
861
|
-
0xEF, 0x41,
|
862
|
-
];
|
863
|
-
|
864
|
-
self.lower_ctx
|
865
|
-
.use_constant(VCodeConstantData::WellKnown(&UMAX_MASK))
|
866
|
-
}
|
867
|
-
|
868
|
-
#[inline]
|
869
|
-
fn uunarrow_uint_mask(&mut self) -> VCodeConstant {
|
870
|
-
static UINT_MASK: [u8; 16] = [
|
871
|
-
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
872
|
-
0x30, 0x43,
|
873
|
-
];
|
874
|
-
|
875
|
-
self.lower_ctx
|
876
|
-
.use_constant(VCodeConstantData::WellKnown(&UINT_MASK))
|
877
|
-
}
|
878
|
-
|
879
|
-
fn xmm_mem_to_xmm_mem_aligned(&mut self, arg: &XmmMem) -> XmmMemAligned {
|
880
|
-
match XmmMemAligned::new(arg.clone().into()) {
|
881
|
-
Some(aligned) => aligned,
|
882
|
-
None => match arg.clone().into() {
|
883
|
-
RegMem::Mem { addr } => self.load_xmm_unaligned(addr).into(),
|
884
|
-
_ => unreachable!(),
|
885
|
-
},
|
886
|
-
}
|
887
|
-
}
|
888
|
-
|
889
|
-
fn xmm_mem_imm_to_xmm_mem_aligned_imm(&mut self, arg: &XmmMemImm) -> XmmMemAlignedImm {
|
890
|
-
match XmmMemAlignedImm::new(arg.clone().into()) {
|
891
|
-
Some(aligned) => aligned,
|
892
|
-
None => match arg.clone().into() {
|
893
|
-
RegMemImm::Mem { addr } => self.load_xmm_unaligned(addr).into(),
|
894
|
-
_ => unreachable!(),
|
895
|
-
},
|
896
|
-
}
|
897
|
-
}
|
898
|
-
|
899
|
-
fn pshufd_lhs_imm(&mut self, imm: Immediate) -> Option<u8> {
|
900
|
-
let (a, b, c, d) = self.shuffle32_from_imm(imm)?;
|
901
|
-
if a < 4 && b < 4 && c < 4 && d < 4 {
|
902
|
-
Some(a | (b << 2) | (c << 4) | (d << 6))
|
903
|
-
} else {
|
904
|
-
None
|
905
|
-
}
|
906
|
-
}
|
907
|
-
|
908
|
-
fn pshufd_rhs_imm(&mut self, imm: Immediate) -> Option<u8> {
|
909
|
-
let (a, b, c, d) = self.shuffle32_from_imm(imm)?;
|
910
|
-
// When selecting from the right-hand-side, subtract these all by 4
|
911
|
-
// which will bail out if anything is less than 4. Afterwards the check
|
912
|
-
// is the same as `pshufd_lhs_imm` above.
|
913
|
-
let a = a.checked_sub(4)?;
|
914
|
-
let b = b.checked_sub(4)?;
|
915
|
-
let c = c.checked_sub(4)?;
|
916
|
-
let d = d.checked_sub(4)?;
|
917
|
-
if a < 4 && b < 4 && c < 4 && d < 4 {
|
918
|
-
Some(a | (b << 2) | (c << 4) | (d << 6))
|
919
|
-
} else {
|
920
|
-
None
|
921
|
-
}
|
922
|
-
}
|
923
|
-
|
924
|
-
fn shufps_imm(&mut self, imm: Immediate) -> Option<u8> {
|
925
|
-
// The `shufps` instruction selects the first two elements from the
|
926
|
-
// first vector and the second two elements from the second vector, so
|
927
|
-
// offset the third/fourth selectors by 4 and then make sure everything
|
928
|
-
// fits in 32-bits.
|
929
|
-
let (a, b, c, d) = self.shuffle32_from_imm(imm)?;
|
930
|
-
let c = c.checked_sub(4)?;
|
931
|
-
let d = d.checked_sub(4)?;
|
932
|
-
if a < 4 && b < 4 && c < 4 && d < 4 {
|
933
|
-
Some(a | (b << 2) | (c << 4) | (d << 6))
|
934
|
-
} else {
|
935
|
-
None
|
936
|
-
}
|
937
|
-
}
|
938
|
-
|
939
|
-
fn shufps_rev_imm(&mut self, imm: Immediate) -> Option<u8> {
|
940
|
-
// This is almost the same as `shufps_imm` except the elements that are
|
941
|
-
// subtracted are reversed. This handles the case that `shufps`
|
942
|
-
// instruction can be emitted if the order of the operands are swapped.
|
943
|
-
let (a, b, c, d) = self.shuffle32_from_imm(imm)?;
|
944
|
-
let a = a.checked_sub(4)?;
|
945
|
-
let b = b.checked_sub(4)?;
|
946
|
-
if a < 4 && b < 4 && c < 4 && d < 4 {
|
947
|
-
Some(a | (b << 2) | (c << 4) | (d << 6))
|
948
|
-
} else {
|
949
|
-
None
|
950
|
-
}
|
951
|
-
}
|
952
|
-
|
953
|
-
fn pshuflw_lhs_imm(&mut self, imm: Immediate) -> Option<u8> {
|
954
|
-
// Similar to `shufps` except this operates over 16-bit values so four
|
955
|
-
// of them must be fixed and the other four must be in-range to encode
|
956
|
-
// in the immediate.
|
957
|
-
let (a, b, c, d, e, f, g, h) = self.shuffle16_from_imm(imm)?;
|
958
|
-
if a < 4 && b < 4 && c < 4 && d < 4 && [e, f, g, h] == [4, 5, 6, 7] {
|
959
|
-
Some(a | (b << 2) | (c << 4) | (d << 6))
|
960
|
-
} else {
|
961
|
-
None
|
962
|
-
}
|
963
|
-
}
|
964
|
-
|
965
|
-
fn pshuflw_rhs_imm(&mut self, imm: Immediate) -> Option<u8> {
|
966
|
-
let (a, b, c, d, e, f, g, h) = self.shuffle16_from_imm(imm)?;
|
967
|
-
let a = a.checked_sub(8)?;
|
968
|
-
let b = b.checked_sub(8)?;
|
969
|
-
let c = c.checked_sub(8)?;
|
970
|
-
let d = d.checked_sub(8)?;
|
971
|
-
let e = e.checked_sub(8)?;
|
972
|
-
let f = f.checked_sub(8)?;
|
973
|
-
let g = g.checked_sub(8)?;
|
974
|
-
let h = h.checked_sub(8)?;
|
975
|
-
if a < 4 && b < 4 && c < 4 && d < 4 && [e, f, g, h] == [4, 5, 6, 7] {
|
976
|
-
Some(a | (b << 2) | (c << 4) | (d << 6))
|
977
|
-
} else {
|
978
|
-
None
|
979
|
-
}
|
980
|
-
}
|
981
|
-
|
982
|
-
fn pshufhw_lhs_imm(&mut self, imm: Immediate) -> Option<u8> {
|
983
|
-
// Similar to `pshuflw` except that the first four operands must be
|
984
|
-
// fixed and the second four are offset by an extra 4 and tested to
|
985
|
-
// make sure they're all in the range [4, 8).
|
986
|
-
let (a, b, c, d, e, f, g, h) = self.shuffle16_from_imm(imm)?;
|
987
|
-
let e = e.checked_sub(4)?;
|
988
|
-
let f = f.checked_sub(4)?;
|
989
|
-
let g = g.checked_sub(4)?;
|
990
|
-
let h = h.checked_sub(4)?;
|
991
|
-
if e < 4 && f < 4 && g < 4 && h < 4 && [a, b, c, d] == [0, 1, 2, 3] {
|
992
|
-
Some(e | (f << 2) | (g << 4) | (h << 6))
|
993
|
-
} else {
|
994
|
-
None
|
995
|
-
}
|
996
|
-
}
|
997
|
-
|
998
|
-
fn pshufhw_rhs_imm(&mut self, imm: Immediate) -> Option<u8> {
|
999
|
-
// Note that everything here is offset by at least 8 and the upper
|
1000
|
-
// bits are offset by 12 to test they're in the range of [12, 16).
|
1001
|
-
let (a, b, c, d, e, f, g, h) = self.shuffle16_from_imm(imm)?;
|
1002
|
-
let a = a.checked_sub(8)?;
|
1003
|
-
let b = b.checked_sub(8)?;
|
1004
|
-
let c = c.checked_sub(8)?;
|
1005
|
-
let d = d.checked_sub(8)?;
|
1006
|
-
let e = e.checked_sub(12)?;
|
1007
|
-
let f = f.checked_sub(12)?;
|
1008
|
-
let g = g.checked_sub(12)?;
|
1009
|
-
let h = h.checked_sub(12)?;
|
1010
|
-
if e < 4 && f < 4 && g < 4 && h < 4 && [a, b, c, d] == [0, 1, 2, 3] {
|
1011
|
-
Some(e | (f << 2) | (g << 4) | (h << 6))
|
1012
|
-
} else {
|
1013
|
-
None
|
1014
|
-
}
|
1015
|
-
}
|
1016
|
-
|
1017
|
-
fn palignr_imm_from_immediate(&mut self, imm: Immediate) -> Option<u8> {
|
1018
|
-
let bytes = self.lower_ctx.get_immediate_data(imm).as_slice();
|
1019
|
-
|
1020
|
-
if bytes.windows(2).all(|a| a[0] + 1 == a[1]) {
|
1021
|
-
Some(bytes[0])
|
1022
|
-
} else {
|
1023
|
-
None
|
1024
|
-
}
|
1025
|
-
}
|
1026
|
-
|
1027
|
-
fn pblendw_imm(&mut self, imm: Immediate) -> Option<u8> {
|
1028
|
-
// First make sure that the shuffle immediate is selecting 16-bit lanes.
|
1029
|
-
let (a, b, c, d, e, f, g, h) = self.shuffle16_from_imm(imm)?;
|
1030
|
-
|
1031
|
-
// Next build up an 8-bit mask from each of the bits of the selected
|
1032
|
-
// lanes above. This instruction can only be used when each lane
|
1033
|
-
// selector chooses from the corresponding lane in either of the two
|
1034
|
-
// operands, meaning the Nth lane selection must satisfy `lane % 8 ==
|
1035
|
-
// N`.
|
1036
|
-
//
|
1037
|
-
// This helper closure is used to calculate the value of the
|
1038
|
-
// corresponding bit.
|
1039
|
-
let bit = |x: u8, c: u8| {
|
1040
|
-
if x % 8 == c {
|
1041
|
-
if x < 8 {
|
1042
|
-
Some(0)
|
1043
|
-
} else {
|
1044
|
-
Some(1 << c)
|
1045
|
-
}
|
1046
|
-
} else {
|
1047
|
-
None
|
1048
|
-
}
|
1049
|
-
};
|
1050
|
-
Some(
|
1051
|
-
bit(a, 0)?
|
1052
|
-
| bit(b, 1)?
|
1053
|
-
| bit(c, 2)?
|
1054
|
-
| bit(d, 3)?
|
1055
|
-
| bit(e, 4)?
|
1056
|
-
| bit(f, 5)?
|
1057
|
-
| bit(g, 6)?
|
1058
|
-
| bit(h, 7)?,
|
1059
|
-
)
|
1060
|
-
}
|
1061
|
-
|
1062
|
-
fn xmi_imm(&mut self, imm: u32) -> XmmMemImm {
|
1063
|
-
XmmMemImm::new(RegMemImm::imm(imm)).unwrap()
|
1064
|
-
}
|
1065
|
-
}
|
1066
|
-
|
1067
|
-
impl IsleContext<'_, '_, MInst, X64Backend> {
|
1068
|
-
isle_prelude_method_helpers!(X64Caller);
|
1069
|
-
|
1070
|
-
fn load_xmm_unaligned(&mut self, addr: SyntheticAmode) -> Xmm {
|
1071
|
-
let tmp = self.lower_ctx.alloc_tmp(types::F32X4).only_reg().unwrap();
|
1072
|
-
self.lower_ctx.emit(MInst::XmmUnaryRmRUnaligned {
|
1073
|
-
op: SseOpcode::Movdqu,
|
1074
|
-
src: XmmMem::new(RegMem::mem(addr)).unwrap(),
|
1075
|
-
dst: Writable::from_reg(Xmm::new(tmp.to_reg()).unwrap()),
|
1076
|
-
});
|
1077
|
-
Xmm::new(tmp.to_reg()).unwrap()
|
1078
|
-
}
|
1079
|
-
}
|
1080
|
-
|
1081
|
-
// Since x64 doesn't have 8x16 shifts and we must use a 16x8 shift instead, we
|
1082
|
-
// need to fix up the bits that migrate from one half of the lane to the
|
1083
|
-
// other. Each 16-byte mask is indexed by the shift amount: e.g. if we shift
|
1084
|
-
// right by 0 (no movement), we want to retain all the bits so we mask with
|
1085
|
-
// `0xff`; if we shift right by 1, we want to retain all bits except the MSB so
|
1086
|
-
// we mask with `0x7f`; etc.
|
1087
|
-
|
1088
|
-
#[rustfmt::skip] // Preserve 16 bytes (i.e. one mask) per row.
|
1089
|
-
const I8X16_ISHL_MASKS: [u8; 128] = [
|
1090
|
-
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
1091
|
-
0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
|
1092
|
-
0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc,
|
1093
|
-
0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8,
|
1094
|
-
0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0,
|
1095
|
-
0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0,
|
1096
|
-
0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0,
|
1097
|
-
0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
|
1098
|
-
];
|
1099
|
-
|
1100
|
-
#[rustfmt::skip] // Preserve 16 bytes (i.e. one mask) per row.
|
1101
|
-
const I8X16_USHR_MASKS: [u8; 128] = [
|
1102
|
-
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
1103
|
-
0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
|
1104
|
-
0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f,
|
1105
|
-
0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f,
|
1106
|
-
0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
|
1107
|
-
0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
|
1108
|
-
0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
|
1109
|
-
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
|
1110
|
-
];
|
1111
|
-
|
1112
|
-
/// Number of bits set in a given nibble (4-bit value). Used in the
|
1113
|
-
/// vector implementation of popcount.
|
1114
|
-
#[rustfmt::skip] // Preserve 4x4 layout.
|
1115
|
-
const POPCOUNT_4BIT_TABLE: [u8; 16] = [
|
1116
|
-
0x00, 0x01, 0x01, 0x02,
|
1117
|
-
0x01, 0x02, 0x02, 0x03,
|
1118
|
-
0x01, 0x02, 0x02, 0x03,
|
1119
|
-
0x02, 0x03, 0x03, 0x04,
|
1120
|
-
];
|
1121
|
-
|
1122
|
-
const POPCOUNT_LOW_MASK: [u8; 16] = [0x0f; 16];
|
1123
|
-
|
1124
|
-
#[inline]
|
1125
|
-
fn to_simm32(constant: i64) -> Option<GprMemImm> {
|
1126
|
-
if constant == ((constant << 32) >> 32) {
|
1127
|
-
Some(
|
1128
|
-
GprMemImm::new(RegMemImm::Imm {
|
1129
|
-
simm32: constant as u32,
|
1130
|
-
})
|
1131
|
-
.unwrap(),
|
1132
|
-
)
|
1133
|
-
} else {
|
1134
|
-
None
|
1135
|
-
}
|
1136
|
-
}
|
1137
|
-
|
1138
|
-
const UINT_MASK: [u8; 16] = [
|
1139
|
-
0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
1140
|
-
];
|
1141
|
-
|
1142
|
-
const UINT_MASK_HIGH: [u8; 16] = [
|
1143
|
-
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x43,
|
1144
|
-
];
|
1145
|
-
|
1146
|
-
const IADD_PAIRWISE_MUL_CONST_16: [u8; 16] = [0x01; 16];
|
1147
|
-
|
1148
|
-
const IADD_PAIRWISE_MUL_CONST_32: [u8; 16] = [
|
1149
|
-
0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00,
|
1150
|
-
];
|
1151
|
-
|
1152
|
-
const IADD_PAIRWISE_XOR_CONST_32: [u8; 16] = [
|
1153
|
-
0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80,
|
1154
|
-
];
|
1155
|
-
|
1156
|
-
const IADD_PAIRWISE_ADDD_CONST_32: [u8; 16] = [
|
1157
|
-
0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
|
1158
|
-
];
|