wasmtime 9.0.4 → 10.0.0
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- checksums.yaml +4 -4
- data/Cargo.lock +184 -101
- data/ext/Cargo.toml +6 -6
- data/ext/build.rs +2 -2
- data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
- data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
- data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
- data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
- data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
- data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
- data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
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use crate::isa::riscv64::inst::AllocationConsumer;
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use crate::isa::riscv64::inst::EmitState;
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use crate::isa::riscv64::lower::isle::generated_code::{
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4
|
+
VecAMode, VecAluOpRImm5, VecAluOpRR, VecAluOpRRImm5, VecAluOpRRR, VecAvl, VecElementWidth,
|
5
|
+
VecLmul, VecMaskMode, VecOpCategory, VecOpMasking, VecTailMode,
|
6
|
+
};
|
7
|
+
use crate::machinst::RegClass;
|
8
|
+
use crate::Reg;
|
9
|
+
use core::fmt;
|
10
|
+
|
11
|
+
use super::{Type, UImm5};
|
12
|
+
|
13
|
+
impl VecAvl {
|
14
|
+
pub fn _static(size: u32) -> Self {
|
15
|
+
VecAvl::Static {
|
16
|
+
size: UImm5::maybe_from_u8(size as u8).expect("Invalid size for AVL"),
|
17
|
+
}
|
18
|
+
}
|
19
|
+
|
20
|
+
pub fn is_static(&self) -> bool {
|
21
|
+
match self {
|
22
|
+
VecAvl::Static { .. } => true,
|
23
|
+
}
|
24
|
+
}
|
25
|
+
|
26
|
+
pub fn unwrap_static(&self) -> UImm5 {
|
27
|
+
match self {
|
28
|
+
VecAvl::Static { size } => *size,
|
29
|
+
}
|
30
|
+
}
|
31
|
+
}
|
32
|
+
|
33
|
+
// TODO: Can we tell ISLE to derive this?
|
34
|
+
impl Copy for VecAvl {}
|
35
|
+
|
36
|
+
// TODO: Can we tell ISLE to derive this?
|
37
|
+
impl PartialEq for VecAvl {
|
38
|
+
fn eq(&self, other: &Self) -> bool {
|
39
|
+
match (self, other) {
|
40
|
+
(VecAvl::Static { size: lhs }, VecAvl::Static { size: rhs }) => lhs == rhs,
|
41
|
+
}
|
42
|
+
}
|
43
|
+
}
|
44
|
+
|
45
|
+
impl fmt::Display for VecAvl {
|
46
|
+
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
47
|
+
match self {
|
48
|
+
VecAvl::Static { size } => write!(f, "{}", size),
|
49
|
+
}
|
50
|
+
}
|
51
|
+
}
|
52
|
+
|
53
|
+
impl VecElementWidth {
|
54
|
+
pub fn from_type(ty: Type) -> Self {
|
55
|
+
Self::from_bits(ty.lane_bits())
|
56
|
+
}
|
57
|
+
|
58
|
+
pub fn from_bits(bits: u32) -> Self {
|
59
|
+
match bits {
|
60
|
+
8 => VecElementWidth::E8,
|
61
|
+
16 => VecElementWidth::E16,
|
62
|
+
32 => VecElementWidth::E32,
|
63
|
+
64 => VecElementWidth::E64,
|
64
|
+
_ => panic!("Invalid number of bits for VecElementWidth: {}", bits),
|
65
|
+
}
|
66
|
+
}
|
67
|
+
|
68
|
+
pub fn bits(&self) -> u32 {
|
69
|
+
match self {
|
70
|
+
VecElementWidth::E8 => 8,
|
71
|
+
VecElementWidth::E16 => 16,
|
72
|
+
VecElementWidth::E32 => 32,
|
73
|
+
VecElementWidth::E64 => 64,
|
74
|
+
}
|
75
|
+
}
|
76
|
+
|
77
|
+
pub fn encode(&self) -> u32 {
|
78
|
+
match self {
|
79
|
+
VecElementWidth::E8 => 0b000,
|
80
|
+
VecElementWidth::E16 => 0b001,
|
81
|
+
VecElementWidth::E32 => 0b010,
|
82
|
+
VecElementWidth::E64 => 0b011,
|
83
|
+
}
|
84
|
+
}
|
85
|
+
}
|
86
|
+
|
87
|
+
impl fmt::Display for VecElementWidth {
|
88
|
+
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
89
|
+
write!(f, "e{}", self.bits())
|
90
|
+
}
|
91
|
+
}
|
92
|
+
|
93
|
+
impl VecLmul {
|
94
|
+
pub fn encode(&self) -> u32 {
|
95
|
+
match self {
|
96
|
+
VecLmul::LmulF8 => 0b101,
|
97
|
+
VecLmul::LmulF4 => 0b110,
|
98
|
+
VecLmul::LmulF2 => 0b111,
|
99
|
+
VecLmul::Lmul1 => 0b000,
|
100
|
+
VecLmul::Lmul2 => 0b001,
|
101
|
+
VecLmul::Lmul4 => 0b010,
|
102
|
+
VecLmul::Lmul8 => 0b011,
|
103
|
+
}
|
104
|
+
}
|
105
|
+
}
|
106
|
+
|
107
|
+
impl fmt::Display for VecLmul {
|
108
|
+
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
109
|
+
match self {
|
110
|
+
VecLmul::LmulF8 => write!(f, "mf8"),
|
111
|
+
VecLmul::LmulF4 => write!(f, "mf4"),
|
112
|
+
VecLmul::LmulF2 => write!(f, "mf2"),
|
113
|
+
VecLmul::Lmul1 => write!(f, "m1"),
|
114
|
+
VecLmul::Lmul2 => write!(f, "m2"),
|
115
|
+
VecLmul::Lmul4 => write!(f, "m4"),
|
116
|
+
VecLmul::Lmul8 => write!(f, "m8"),
|
117
|
+
}
|
118
|
+
}
|
119
|
+
}
|
120
|
+
|
121
|
+
impl VecTailMode {
|
122
|
+
pub fn encode(&self) -> u32 {
|
123
|
+
match self {
|
124
|
+
VecTailMode::Agnostic => 1,
|
125
|
+
VecTailMode::Undisturbed => 0,
|
126
|
+
}
|
127
|
+
}
|
128
|
+
}
|
129
|
+
|
130
|
+
impl fmt::Display for VecTailMode {
|
131
|
+
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
132
|
+
match self {
|
133
|
+
VecTailMode::Agnostic => write!(f, "ta"),
|
134
|
+
VecTailMode::Undisturbed => write!(f, "tu"),
|
135
|
+
}
|
136
|
+
}
|
137
|
+
}
|
138
|
+
|
139
|
+
impl VecMaskMode {
|
140
|
+
pub fn encode(&self) -> u32 {
|
141
|
+
match self {
|
142
|
+
VecMaskMode::Agnostic => 1,
|
143
|
+
VecMaskMode::Undisturbed => 0,
|
144
|
+
}
|
145
|
+
}
|
146
|
+
}
|
147
|
+
|
148
|
+
impl fmt::Display for VecMaskMode {
|
149
|
+
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
150
|
+
match self {
|
151
|
+
VecMaskMode::Agnostic => write!(f, "ma"),
|
152
|
+
VecMaskMode::Undisturbed => write!(f, "mu"),
|
153
|
+
}
|
154
|
+
}
|
155
|
+
}
|
156
|
+
|
157
|
+
/// Vector Type (VType)
|
158
|
+
///
|
159
|
+
/// vtype provides the default type used to interpret the contents of the vector register file.
|
160
|
+
#[derive(Clone, Copy, Debug, PartialEq)]
|
161
|
+
pub struct VType {
|
162
|
+
pub sew: VecElementWidth,
|
163
|
+
pub lmul: VecLmul,
|
164
|
+
pub tail_mode: VecTailMode,
|
165
|
+
pub mask_mode: VecMaskMode,
|
166
|
+
}
|
167
|
+
|
168
|
+
impl VType {
|
169
|
+
// https://github.com/riscv/riscv-v-spec/blob/master/vtype-format.adoc
|
170
|
+
pub fn encode(&self) -> u32 {
|
171
|
+
let mut bits = 0;
|
172
|
+
bits |= self.lmul.encode();
|
173
|
+
bits |= self.sew.encode() << 3;
|
174
|
+
bits |= self.tail_mode.encode() << 6;
|
175
|
+
bits |= self.mask_mode.encode() << 7;
|
176
|
+
bits
|
177
|
+
}
|
178
|
+
}
|
179
|
+
|
180
|
+
impl fmt::Display for VType {
|
181
|
+
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
182
|
+
write!(
|
183
|
+
f,
|
184
|
+
"{}, {}, {}, {}",
|
185
|
+
self.sew, self.lmul, self.tail_mode, self.mask_mode
|
186
|
+
)
|
187
|
+
}
|
188
|
+
}
|
189
|
+
|
190
|
+
/// Vector State (VState)
|
191
|
+
///
|
192
|
+
/// VState represents the state of the vector unit that each instruction expects before execution.
|
193
|
+
/// Unlike VType or any of the other types here, VState is not a part of the RISC-V ISA. It is
|
194
|
+
/// used by our instruction emission code to ensure that the vector unit is in the correct state.
|
195
|
+
#[derive(Clone, Copy, Debug, PartialEq)]
|
196
|
+
pub struct VState {
|
197
|
+
pub avl: VecAvl,
|
198
|
+
pub vtype: VType,
|
199
|
+
}
|
200
|
+
|
201
|
+
impl VState {
|
202
|
+
pub fn from_type(ty: Type) -> Self {
|
203
|
+
VState {
|
204
|
+
avl: VecAvl::_static(ty.lane_count()),
|
205
|
+
vtype: VType {
|
206
|
+
sew: VecElementWidth::from_type(ty),
|
207
|
+
lmul: VecLmul::Lmul1,
|
208
|
+
tail_mode: VecTailMode::Agnostic,
|
209
|
+
mask_mode: VecMaskMode::Agnostic,
|
210
|
+
},
|
211
|
+
}
|
212
|
+
}
|
213
|
+
}
|
214
|
+
|
215
|
+
impl fmt::Display for VState {
|
216
|
+
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
217
|
+
write!(f, "#avl={}, #vtype=({})", self.avl, self.vtype)
|
218
|
+
}
|
219
|
+
}
|
220
|
+
|
221
|
+
impl VecOpCategory {
|
222
|
+
pub fn encode(&self) -> u32 {
|
223
|
+
// See: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#101-vector-arithmetic-instruction-encoding
|
224
|
+
match self {
|
225
|
+
VecOpCategory::OPIVV => 0b000,
|
226
|
+
VecOpCategory::OPFVV => 0b001,
|
227
|
+
VecOpCategory::OPMVV => 0b010,
|
228
|
+
VecOpCategory::OPIVI => 0b011,
|
229
|
+
VecOpCategory::OPIVX => 0b100,
|
230
|
+
VecOpCategory::OPFVF => 0b101,
|
231
|
+
VecOpCategory::OPMVX => 0b110,
|
232
|
+
VecOpCategory::OPCFG => 0b111,
|
233
|
+
}
|
234
|
+
}
|
235
|
+
}
|
236
|
+
|
237
|
+
impl VecOpMasking {
|
238
|
+
pub fn encode(&self) -> u32 {
|
239
|
+
match self {
|
240
|
+
VecOpMasking::Enabled { .. } => 0,
|
241
|
+
VecOpMasking::Disabled => 1,
|
242
|
+
}
|
243
|
+
}
|
244
|
+
|
245
|
+
pub(crate) fn with_allocs(&self, allocs: &mut AllocationConsumer<'_>) -> Self {
|
246
|
+
match self {
|
247
|
+
VecOpMasking::Enabled { reg } => VecOpMasking::Enabled {
|
248
|
+
reg: allocs.next(*reg),
|
249
|
+
},
|
250
|
+
VecOpMasking::Disabled => VecOpMasking::Disabled,
|
251
|
+
}
|
252
|
+
}
|
253
|
+
}
|
254
|
+
|
255
|
+
impl VecAluOpRRR {
|
256
|
+
pub fn opcode(&self) -> u32 {
|
257
|
+
// Vector Opcode
|
258
|
+
0x57
|
259
|
+
}
|
260
|
+
pub fn funct3(&self) -> u32 {
|
261
|
+
self.category().encode()
|
262
|
+
}
|
263
|
+
pub fn funct6(&self) -> u32 {
|
264
|
+
// See: https://github.com/riscv/riscv-v-spec/blob/master/inst-table.adoc
|
265
|
+
match self {
|
266
|
+
VecAluOpRRR::VaddVV
|
267
|
+
| VecAluOpRRR::VaddVX
|
268
|
+
| VecAluOpRRR::VfaddVV
|
269
|
+
| VecAluOpRRR::VfaddVF => 0b000000,
|
270
|
+
VecAluOpRRR::VsubVV
|
271
|
+
| VecAluOpRRR::VsubVX
|
272
|
+
| VecAluOpRRR::VfsubVV
|
273
|
+
| VecAluOpRRR::VfsubVF => 0b000010,
|
274
|
+
VecAluOpRRR::VrsubVX => 0b000011,
|
275
|
+
VecAluOpRRR::VmulVV => 0b100101,
|
276
|
+
VecAluOpRRR::VmulhVV => 0b100111,
|
277
|
+
VecAluOpRRR::VmulhuVV | VecAluOpRRR::VfmulVV | VecAluOpRRR::VfmulVF => 0b100100,
|
278
|
+
VecAluOpRRR::VsllVV | VecAluOpRRR::VsllVX => 0b100101,
|
279
|
+
VecAluOpRRR::VsrlVV | VecAluOpRRR::VsrlVX => 0b101000,
|
280
|
+
VecAluOpRRR::VsraVV | VecAluOpRRR::VsraVX => 0b101001,
|
281
|
+
VecAluOpRRR::VandVV | VecAluOpRRR::VandVX => 0b001001,
|
282
|
+
VecAluOpRRR::VorVV | VecAluOpRRR::VorVX => 0b001010,
|
283
|
+
VecAluOpRRR::VxorVV | VecAluOpRRR::VxorVX => 0b001011,
|
284
|
+
VecAluOpRRR::VminuVV | VecAluOpRRR::VminuVX | VecAluOpRRR::VredminuVS => 0b000100,
|
285
|
+
VecAluOpRRR::VminVV | VecAluOpRRR::VminVX => 0b000101,
|
286
|
+
VecAluOpRRR::VmaxuVV | VecAluOpRRR::VmaxuVX | VecAluOpRRR::VredmaxuVS => 0b000110,
|
287
|
+
VecAluOpRRR::VmaxVV | VecAluOpRRR::VmaxVX => 0b000111,
|
288
|
+
VecAluOpRRR::VslidedownVX => 0b001111,
|
289
|
+
VecAluOpRRR::VfrsubVF => 0b100111,
|
290
|
+
VecAluOpRRR::VmergeVVM | VecAluOpRRR::VmergeVXM | VecAluOpRRR::VfmergeVFM => 0b010111,
|
291
|
+
VecAluOpRRR::VfdivVV
|
292
|
+
| VecAluOpRRR::VfdivVF
|
293
|
+
| VecAluOpRRR::VsadduVV
|
294
|
+
| VecAluOpRRR::VsadduVX => 0b100000,
|
295
|
+
VecAluOpRRR::VfrdivVF | VecAluOpRRR::VsaddVV | VecAluOpRRR::VsaddVX => 0b100001,
|
296
|
+
VecAluOpRRR::VssubuVV | VecAluOpRRR::VssubuVX => 0b100010,
|
297
|
+
VecAluOpRRR::VssubVV | VecAluOpRRR::VssubVX => 0b100011,
|
298
|
+
VecAluOpRRR::VfsgnjnVV => 0b001001,
|
299
|
+
VecAluOpRRR::VmsltVX => 0b011011,
|
300
|
+
}
|
301
|
+
}
|
302
|
+
|
303
|
+
pub fn category(&self) -> VecOpCategory {
|
304
|
+
match self {
|
305
|
+
VecAluOpRRR::VaddVV
|
306
|
+
| VecAluOpRRR::VsaddVV
|
307
|
+
| VecAluOpRRR::VsadduVV
|
308
|
+
| VecAluOpRRR::VsubVV
|
309
|
+
| VecAluOpRRR::VssubVV
|
310
|
+
| VecAluOpRRR::VssubuVV
|
311
|
+
| VecAluOpRRR::VsllVV
|
312
|
+
| VecAluOpRRR::VsrlVV
|
313
|
+
| VecAluOpRRR::VsraVV
|
314
|
+
| VecAluOpRRR::VandVV
|
315
|
+
| VecAluOpRRR::VorVV
|
316
|
+
| VecAluOpRRR::VxorVV
|
317
|
+
| VecAluOpRRR::VminuVV
|
318
|
+
| VecAluOpRRR::VminVV
|
319
|
+
| VecAluOpRRR::VmaxuVV
|
320
|
+
| VecAluOpRRR::VmaxVV
|
321
|
+
| VecAluOpRRR::VmergeVVM => VecOpCategory::OPIVV,
|
322
|
+
VecAluOpRRR::VmulVV
|
323
|
+
| VecAluOpRRR::VmulhVV
|
324
|
+
| VecAluOpRRR::VmulhuVV
|
325
|
+
| VecAluOpRRR::VredmaxuVS
|
326
|
+
| VecAluOpRRR::VredminuVS => VecOpCategory::OPMVV,
|
327
|
+
VecAluOpRRR::VaddVX
|
328
|
+
| VecAluOpRRR::VsaddVX
|
329
|
+
| VecAluOpRRR::VsadduVX
|
330
|
+
| VecAluOpRRR::VsubVX
|
331
|
+
| VecAluOpRRR::VssubVX
|
332
|
+
| VecAluOpRRR::VssubuVX
|
333
|
+
| VecAluOpRRR::VrsubVX
|
334
|
+
| VecAluOpRRR::VsllVX
|
335
|
+
| VecAluOpRRR::VsrlVX
|
336
|
+
| VecAluOpRRR::VsraVX
|
337
|
+
| VecAluOpRRR::VandVX
|
338
|
+
| VecAluOpRRR::VorVX
|
339
|
+
| VecAluOpRRR::VxorVX
|
340
|
+
| VecAluOpRRR::VminuVX
|
341
|
+
| VecAluOpRRR::VminVX
|
342
|
+
| VecAluOpRRR::VmaxuVX
|
343
|
+
| VecAluOpRRR::VmaxVX
|
344
|
+
| VecAluOpRRR::VslidedownVX
|
345
|
+
| VecAluOpRRR::VmergeVXM
|
346
|
+
| VecAluOpRRR::VmsltVX => VecOpCategory::OPIVX,
|
347
|
+
VecAluOpRRR::VfaddVV
|
348
|
+
| VecAluOpRRR::VfsubVV
|
349
|
+
| VecAluOpRRR::VfmulVV
|
350
|
+
| VecAluOpRRR::VfdivVV
|
351
|
+
| VecAluOpRRR::VfsgnjnVV => VecOpCategory::OPFVV,
|
352
|
+
VecAluOpRRR::VfaddVF
|
353
|
+
| VecAluOpRRR::VfsubVF
|
354
|
+
| VecAluOpRRR::VfrsubVF
|
355
|
+
| VecAluOpRRR::VfmulVF
|
356
|
+
| VecAluOpRRR::VfdivVF
|
357
|
+
| VecAluOpRRR::VfrdivVF
|
358
|
+
| VecAluOpRRR::VfmergeVFM => VecOpCategory::OPFVF,
|
359
|
+
}
|
360
|
+
}
|
361
|
+
|
362
|
+
// vs1 is the only variable source, vs2 is fixed.
|
363
|
+
pub fn vs1_regclass(&self) -> RegClass {
|
364
|
+
match self.category() {
|
365
|
+
VecOpCategory::OPIVV | VecOpCategory::OPFVV | VecOpCategory::OPMVV => RegClass::Vector,
|
366
|
+
VecOpCategory::OPIVX | VecOpCategory::OPMVX => RegClass::Int,
|
367
|
+
VecOpCategory::OPFVF => RegClass::Float,
|
368
|
+
_ => unreachable!(),
|
369
|
+
}
|
370
|
+
}
|
371
|
+
}
|
372
|
+
|
373
|
+
impl fmt::Display for VecAluOpRRR {
|
374
|
+
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
375
|
+
let suffix_length = match self {
|
376
|
+
VecAluOpRRR::VmergeVVM | VecAluOpRRR::VmergeVXM | VecAluOpRRR::VfmergeVFM => 3,
|
377
|
+
_ => 2,
|
378
|
+
};
|
379
|
+
|
380
|
+
let mut s = format!("{self:?}");
|
381
|
+
s.make_ascii_lowercase();
|
382
|
+
let (opcode, category) = s.split_at(s.len() - suffix_length);
|
383
|
+
f.write_str(&format!("{opcode}.{category}"))
|
384
|
+
}
|
385
|
+
}
|
386
|
+
|
387
|
+
impl VecAluOpRRImm5 {
|
388
|
+
pub fn opcode(&self) -> u32 {
|
389
|
+
// Vector Opcode
|
390
|
+
0x57
|
391
|
+
}
|
392
|
+
pub fn funct3(&self) -> u32 {
|
393
|
+
self.category().encode()
|
394
|
+
}
|
395
|
+
|
396
|
+
pub fn funct6(&self) -> u32 {
|
397
|
+
// See: https://github.com/riscv/riscv-v-spec/blob/master/inst-table.adoc
|
398
|
+
match self {
|
399
|
+
VecAluOpRRImm5::VaddVI => 0b000000,
|
400
|
+
VecAluOpRRImm5::VrsubVI => 0b000011,
|
401
|
+
VecAluOpRRImm5::VsllVI => 0b100101,
|
402
|
+
VecAluOpRRImm5::VsrlVI => 0b101000,
|
403
|
+
VecAluOpRRImm5::VsraVI => 0b101001,
|
404
|
+
VecAluOpRRImm5::VandVI => 0b001001,
|
405
|
+
VecAluOpRRImm5::VorVI => 0b001010,
|
406
|
+
VecAluOpRRImm5::VxorVI => 0b001011,
|
407
|
+
VecAluOpRRImm5::VslidedownVI => 0b001111,
|
408
|
+
VecAluOpRRImm5::VmergeVIM => 0b010111,
|
409
|
+
VecAluOpRRImm5::VsadduVI => 0b100000,
|
410
|
+
VecAluOpRRImm5::VsaddVI => 0b100001,
|
411
|
+
}
|
412
|
+
}
|
413
|
+
|
414
|
+
pub fn category(&self) -> VecOpCategory {
|
415
|
+
match self {
|
416
|
+
VecAluOpRRImm5::VaddVI
|
417
|
+
| VecAluOpRRImm5::VrsubVI
|
418
|
+
| VecAluOpRRImm5::VsllVI
|
419
|
+
| VecAluOpRRImm5::VsrlVI
|
420
|
+
| VecAluOpRRImm5::VsraVI
|
421
|
+
| VecAluOpRRImm5::VandVI
|
422
|
+
| VecAluOpRRImm5::VorVI
|
423
|
+
| VecAluOpRRImm5::VxorVI
|
424
|
+
| VecAluOpRRImm5::VslidedownVI
|
425
|
+
| VecAluOpRRImm5::VmergeVIM
|
426
|
+
| VecAluOpRRImm5::VsadduVI
|
427
|
+
| VecAluOpRRImm5::VsaddVI => VecOpCategory::OPIVI,
|
428
|
+
}
|
429
|
+
}
|
430
|
+
|
431
|
+
pub fn imm_is_unsigned(&self) -> bool {
|
432
|
+
match self {
|
433
|
+
VecAluOpRRImm5::VsllVI
|
434
|
+
| VecAluOpRRImm5::VsrlVI
|
435
|
+
| VecAluOpRRImm5::VsraVI
|
436
|
+
| VecAluOpRRImm5::VslidedownVI => true,
|
437
|
+
VecAluOpRRImm5::VaddVI
|
438
|
+
| VecAluOpRRImm5::VrsubVI
|
439
|
+
| VecAluOpRRImm5::VandVI
|
440
|
+
| VecAluOpRRImm5::VorVI
|
441
|
+
| VecAluOpRRImm5::VxorVI
|
442
|
+
| VecAluOpRRImm5::VmergeVIM
|
443
|
+
| VecAluOpRRImm5::VsadduVI
|
444
|
+
| VecAluOpRRImm5::VsaddVI => false,
|
445
|
+
}
|
446
|
+
}
|
447
|
+
}
|
448
|
+
|
449
|
+
impl fmt::Display for VecAluOpRRImm5 {
|
450
|
+
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
451
|
+
let suffix_length = match self {
|
452
|
+
VecAluOpRRImm5::VmergeVIM => 3,
|
453
|
+
_ => 2,
|
454
|
+
};
|
455
|
+
|
456
|
+
let mut s = format!("{self:?}");
|
457
|
+
s.make_ascii_lowercase();
|
458
|
+
let (opcode, category) = s.split_at(s.len() - suffix_length);
|
459
|
+
f.write_str(&format!("{opcode}.{category}"))
|
460
|
+
}
|
461
|
+
}
|
462
|
+
|
463
|
+
impl VecAluOpRR {
|
464
|
+
pub fn opcode(&self) -> u32 {
|
465
|
+
// Vector Opcode
|
466
|
+
0x57
|
467
|
+
}
|
468
|
+
|
469
|
+
pub fn funct3(&self) -> u32 {
|
470
|
+
self.category().encode()
|
471
|
+
}
|
472
|
+
|
473
|
+
pub fn funct6(&self) -> u32 {
|
474
|
+
// See: https://github.com/riscv/riscv-v-spec/blob/master/inst-table.adoc
|
475
|
+
match self {
|
476
|
+
VecAluOpRR::VmvSX | VecAluOpRR::VmvXS | VecAluOpRR::VfmvSF | VecAluOpRR::VfmvFS => {
|
477
|
+
0b010000
|
478
|
+
}
|
479
|
+
VecAluOpRR::VfsqrtV => 0b010011,
|
480
|
+
VecAluOpRR::VmvVV | VecAluOpRR::VmvVX | VecAluOpRR::VfmvVF => 0b010111,
|
481
|
+
}
|
482
|
+
}
|
483
|
+
|
484
|
+
pub fn category(&self) -> VecOpCategory {
|
485
|
+
match self {
|
486
|
+
VecAluOpRR::VmvSX => VecOpCategory::OPMVX,
|
487
|
+
VecAluOpRR::VmvXS => VecOpCategory::OPMVV,
|
488
|
+
VecAluOpRR::VfmvSF | VecAluOpRR::VfmvVF => VecOpCategory::OPFVF,
|
489
|
+
VecAluOpRR::VfmvFS | VecAluOpRR::VfsqrtV => VecOpCategory::OPFVV,
|
490
|
+
VecAluOpRR::VmvVV => VecOpCategory::OPIVV,
|
491
|
+
VecAluOpRR::VmvVX => VecOpCategory::OPIVX,
|
492
|
+
}
|
493
|
+
}
|
494
|
+
|
495
|
+
/// Returns the auxiliary encoding field for the instruction, if any.
|
496
|
+
pub fn aux_encoding(&self) -> u32 {
|
497
|
+
match self {
|
498
|
+
// VRXUNARY0
|
499
|
+
VecAluOpRR::VmvSX => 0b00000,
|
500
|
+
// VWXUNARY0
|
501
|
+
VecAluOpRR::VmvXS => 0b00000,
|
502
|
+
// VRFUNARY0
|
503
|
+
VecAluOpRR::VfmvSF => 0b00000,
|
504
|
+
// VWFUNARY0
|
505
|
+
VecAluOpRR::VfmvFS => 0b00000,
|
506
|
+
// VFUNARY1
|
507
|
+
VecAluOpRR::VfsqrtV => 0b00000,
|
508
|
+
// These don't have a explicit encoding table, but Section 11.16 Vector Integer Move Instruction states:
|
509
|
+
// > The first operand specifier (vs2) must contain v0, and any other vector register number in vs2 is reserved.
|
510
|
+
VecAluOpRR::VmvVV | VecAluOpRR::VmvVX | VecAluOpRR::VfmvVF => 0,
|
511
|
+
}
|
512
|
+
}
|
513
|
+
|
514
|
+
/// Most of these opcodes have the source register encoded in the VS2 field and
|
515
|
+
/// the `aux_encoding` field in VS1. However some special snowflakes have it the
|
516
|
+
/// other way around. As far as I can tell only vmv.v.* are backwards.
|
517
|
+
pub fn vs_is_vs2_encoded(&self) -> bool {
|
518
|
+
match self {
|
519
|
+
VecAluOpRR::VmvXS | VecAluOpRR::VfmvFS | VecAluOpRR::VfsqrtV => true,
|
520
|
+
VecAluOpRR::VmvSX
|
521
|
+
| VecAluOpRR::VfmvSF
|
522
|
+
| VecAluOpRR::VmvVV
|
523
|
+
| VecAluOpRR::VmvVX
|
524
|
+
| VecAluOpRR::VfmvVF => false,
|
525
|
+
}
|
526
|
+
}
|
527
|
+
|
528
|
+
pub fn dst_regclass(&self) -> RegClass {
|
529
|
+
match self {
|
530
|
+
VecAluOpRR::VfmvSF
|
531
|
+
| VecAluOpRR::VmvSX
|
532
|
+
| VecAluOpRR::VmvVV
|
533
|
+
| VecAluOpRR::VmvVX
|
534
|
+
| VecAluOpRR::VfmvVF
|
535
|
+
| VecAluOpRR::VfsqrtV => RegClass::Vector,
|
536
|
+
VecAluOpRR::VmvXS => RegClass::Int,
|
537
|
+
VecAluOpRR::VfmvFS => RegClass::Float,
|
538
|
+
}
|
539
|
+
}
|
540
|
+
|
541
|
+
pub fn src_regclass(&self) -> RegClass {
|
542
|
+
match self {
|
543
|
+
VecAluOpRR::VmvXS | VecAluOpRR::VfmvFS | VecAluOpRR::VmvVV | VecAluOpRR::VfsqrtV => {
|
544
|
+
RegClass::Vector
|
545
|
+
}
|
546
|
+
VecAluOpRR::VfmvSF | VecAluOpRR::VfmvVF => RegClass::Float,
|
547
|
+
VecAluOpRR::VmvSX | VecAluOpRR::VmvVX => RegClass::Int,
|
548
|
+
}
|
549
|
+
}
|
550
|
+
}
|
551
|
+
|
552
|
+
impl fmt::Display for VecAluOpRR {
|
553
|
+
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
554
|
+
f.write_str(match self {
|
555
|
+
VecAluOpRR::VmvSX => "vmv.s.x",
|
556
|
+
VecAluOpRR::VmvXS => "vmv.x.s",
|
557
|
+
VecAluOpRR::VfmvSF => "vfmv.s.f",
|
558
|
+
VecAluOpRR::VfmvFS => "vfmv.f.s",
|
559
|
+
VecAluOpRR::VfsqrtV => "vfsqrt.v",
|
560
|
+
VecAluOpRR::VmvVV => "vmv.v.v",
|
561
|
+
VecAluOpRR::VmvVX => "vmv.v.x",
|
562
|
+
VecAluOpRR::VfmvVF => "vfmv.v.f",
|
563
|
+
})
|
564
|
+
}
|
565
|
+
}
|
566
|
+
|
567
|
+
impl VecAluOpRImm5 {
|
568
|
+
pub fn opcode(&self) -> u32 {
|
569
|
+
// Vector Opcode
|
570
|
+
0x57
|
571
|
+
}
|
572
|
+
pub fn funct3(&self) -> u32 {
|
573
|
+
self.category().encode()
|
574
|
+
}
|
575
|
+
|
576
|
+
pub fn funct6(&self) -> u32 {
|
577
|
+
// See: https://github.com/riscv/riscv-v-spec/blob/master/inst-table.adoc
|
578
|
+
match self {
|
579
|
+
VecAluOpRImm5::VmvVI => 0b010111,
|
580
|
+
}
|
581
|
+
}
|
582
|
+
|
583
|
+
pub fn category(&self) -> VecOpCategory {
|
584
|
+
match self {
|
585
|
+
VecAluOpRImm5::VmvVI => VecOpCategory::OPIVI,
|
586
|
+
}
|
587
|
+
}
|
588
|
+
|
589
|
+
/// Returns the auxiliary encoding field for the instruction, if any.
|
590
|
+
pub fn aux_encoding(&self) -> u32 {
|
591
|
+
match self {
|
592
|
+
// These don't have a explicit encoding table, but Section 11.16 Vector Integer Move Instruction states:
|
593
|
+
// > The first operand specifier (vs2) must contain v0, and any other vector register number in vs2 is reserved.
|
594
|
+
VecAluOpRImm5::VmvVI => 0,
|
595
|
+
}
|
596
|
+
}
|
597
|
+
}
|
598
|
+
|
599
|
+
impl fmt::Display for VecAluOpRImm5 {
|
600
|
+
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
601
|
+
f.write_str(match self {
|
602
|
+
VecAluOpRImm5::VmvVI => "vmv.v.i",
|
603
|
+
})
|
604
|
+
}
|
605
|
+
}
|
606
|
+
|
607
|
+
impl VecAMode {
|
608
|
+
pub fn get_base_register(&self) -> Option<Reg> {
|
609
|
+
match self {
|
610
|
+
VecAMode::UnitStride { base, .. } => base.get_base_register(),
|
611
|
+
}
|
612
|
+
}
|
613
|
+
|
614
|
+
pub fn get_allocatable_register(&self) -> Option<Reg> {
|
615
|
+
match self {
|
616
|
+
VecAMode::UnitStride { base, .. } => base.get_allocatable_register(),
|
617
|
+
}
|
618
|
+
}
|
619
|
+
|
620
|
+
pub(crate) fn with_allocs(self, allocs: &mut AllocationConsumer<'_>) -> Self {
|
621
|
+
match self {
|
622
|
+
VecAMode::UnitStride { base } => VecAMode::UnitStride {
|
623
|
+
base: base.with_allocs(allocs),
|
624
|
+
},
|
625
|
+
}
|
626
|
+
}
|
627
|
+
|
628
|
+
pub(crate) fn get_offset_with_state(&self, state: &EmitState) -> i64 {
|
629
|
+
match self {
|
630
|
+
VecAMode::UnitStride { base, .. } => base.get_offset_with_state(state),
|
631
|
+
}
|
632
|
+
}
|
633
|
+
|
634
|
+
/// `mop` field, described in Table 7 of Section 7.2. Vector Load/Store Addressing Modes
|
635
|
+
/// https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#72-vector-loadstore-addressing-modes
|
636
|
+
pub fn mop(&self) -> u32 {
|
637
|
+
match self {
|
638
|
+
VecAMode::UnitStride { .. } => 0b00,
|
639
|
+
}
|
640
|
+
}
|
641
|
+
|
642
|
+
/// `lumop` field, described in Table 9 of Section 7.2. Vector Load/Store Addressing Modes
|
643
|
+
/// https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#72-vector-loadstore-addressing-modes
|
644
|
+
pub fn lumop(&self) -> u32 {
|
645
|
+
match self {
|
646
|
+
VecAMode::UnitStride { .. } => 0b00000,
|
647
|
+
}
|
648
|
+
}
|
649
|
+
|
650
|
+
/// `sumop` field, described in Table 10 of Section 7.2. Vector Load/Store Addressing Modes
|
651
|
+
/// https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#72-vector-loadstore-addressing-modes
|
652
|
+
pub fn sumop(&self) -> u32 {
|
653
|
+
match self {
|
654
|
+
VecAMode::UnitStride { .. } => 0b00000,
|
655
|
+
}
|
656
|
+
}
|
657
|
+
|
658
|
+
/// The `nf[2:0]` field encodes the number of fields in each segment. For regular vector loads and
|
659
|
+
/// stores, nf=0, indicating that a single value is moved between a vector register group and memory
|
660
|
+
/// at each element position. Larger values in the nf field are used to access multiple contiguous
|
661
|
+
/// fields within a segment as described in Section 7.8 Vector Load/Store Segment Instructions.
|
662
|
+
///
|
663
|
+
/// https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#72-vector-loadstore-addressing-modes
|
664
|
+
pub fn nf(&self) -> u32 {
|
665
|
+
match self {
|
666
|
+
VecAMode::UnitStride { .. } => 0b000,
|
667
|
+
}
|
668
|
+
}
|
669
|
+
}
|